5e641acc90
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;
..etc..
25 lines
648 B
Verilog
25 lines
648 B
Verilog
|
|
// test_simulation_nand_1_test.v
|
|
module f1_test(input [1:0] in, output out);
|
|
assign out = ~(in[0] & in[1]);
|
|
endmodule
|
|
|
|
// test_simulation_nand_3_test.v
|
|
module f2_test(input [2:0] in, output out);
|
|
assign out = !(in[0] & in[1] & in[2]);
|
|
endmodule
|
|
|
|
// test_simulation_nand_4_test.v
|
|
module f3_test(input [2:0] in, output out);
|
|
assign out = ~(in[0] && in[1] && in[2]);
|
|
endmodule
|
|
|
|
// test_simulation_nand_5_test.v
|
|
module f4_test(input [3:0] in, output out);
|
|
assign out = !(in[0] & in[1] & in[2] & in[3]);
|
|
endmodule
|
|
|
|
// test_simulation_nand_6_test.v
|
|
module f5_test(input [3:0] in, output out);
|
|
assign out = !(in[0] && in[1] && in[2] && in[3]);
|
|
endmodule
|