d3c67ad9b6
added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc
37 lines
609 B
Bash
Executable file
37 lines
609 B
Bash
Executable file
#!/bin/sh
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#
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# Script to writing btor from verilog design
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#
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if [ "$#" -ne 3 ]; then
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echo "Usage: $0 input.v output.btor top-module-name" >&2
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exit 1
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fi
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if ! [ -e "$1" ]; then
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echo "$1 not found" >&2
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exit 1
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fi
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FULL_PATH=$(readlink -f $1)
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DIR=$(dirname $FULL_PATH)
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./yosys -q -p "
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read_verilog -sv $1;
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hierarchy -top $3;
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hierarchy -libdir $DIR;
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hierarchy -check;
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proc;
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opt; opt_const -mux_undef; opt;
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rename -hide;;;
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#techmap -share_map pmux2mux.v;;
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splice; opt;
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memory_dff -wr_only;
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memory_collect;;
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flatten;;
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memory_unpack;
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splitnets -driver;
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setundef -zero -undriven;
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opt;;;
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write_btor $2;"
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