Clifford Wolf 91dd87e60b Improved scope resolution of local regs in Verilog+AST frontend		2014-08-05 12:15:53 +02:00
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asicworld	Added "make -j{N}" support to "make test"	2014-07-30 19:23:26 +02:00
hana	Consolidated hana test benches into fewer files	2014-08-01 03:57:37 +02:00
memories	Added SAT-based write-port sharing to memory_share	2014-07-19 15:33:55 +02:00
realmath	Added note to "make test": use git checkout of iverilog	2014-07-16 10:03:07 +02:00
sat	Added yet another resource sharing test case	2014-07-20 21:15:01 +02:00
share	Added "wreduce" to some of the standard test benches	2014-08-03 20:22:33 +02:00
simple	Improved scope resolution of local regs in Verilog+AST frontend	2014-08-05 12:15:53 +02:00
techmap	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	2014-07-16 14:08:51 +02:00
tools	Added "wreduce" to some of the standard test benches	2014-08-03 20:22:33 +02:00
various	Added tests/various/.gitignore	2014-07-26 17:43:41 +02:00
vloghtb	Added "wreduce" to some of the standard test benches	2014-08-03 20:22:33 +02:00