13 lines
134 B
Verilog
13 lines
134 B
Verilog
module reg_combo_example( a, b, y);
|
|
input a, b;
|
|
output y;
|
|
|
|
reg y;
|
|
wire a, b;
|
|
|
|
always @ ( a or b)
|
|
begin
|
|
y = a & b;
|
|
end
|
|
|
|
endmodule
|