yosys/tests/asicworld/code_verilog_tutorial_multiply.v
2013-01-05 11:13:26 +01:00

8 lines
161 B
Verilog

module muliply (a,product);
input [3:0] a;
output [4:0] product;
wire [4:0] product;
assign product = a << 1;
endmodule