This website requires JavaScript.
Explore
Help
Sign in
stv0g
/
yosys
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Pull requests
Releases
Wiki
Activity
5a592b3739
yosys
/
techlibs
History
Clifford Wolf
29d6ebd961
Implemented technology mapping for multipliers (using array multiplier)
2013-06-03 12:48:44 +02:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
blackbox.sed
initial import
2013-01-05 11:13:26 +01:00
Makefile.inc
Added EXTRA_TARGETS Makefile variable
2013-03-28 16:53:40 +01:00
simlib.v
Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v
2013-04-07 16:42:29 +02:00
stdcells.v
Implemented technology mapping for multipliers (using array multiplier)
2013-06-03 12:48:44 +02:00
stdcells_sim.v
initial import
2013-01-05 11:13:26 +01:00