yosys/techlibs
2014-01-18 15:35:15 +01:00
..
cmos Updated abc 2013-11-21 22:39:10 +01:00
common Added $bu0 cell to simlib.v 2014-01-18 15:35:15 +01:00
xilinx Added "techmap -share_map" option 2013-11-24 19:50:25 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00