yosys/manual/PRESENTATION_ExAdv/sym_mul_cells.v
2014-02-16 14:32:56 +01:00

6 lines
134 B
Verilog

module MYMUL(A, B, Y);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output [WIDTH-1:0] Y;
assign Y = A * B;
endmodule