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yosys
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techlibs
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common
History
Clifford Wolf
a92a68ce52
Using "via_celltype" in $mul carry-save-acc implementation
2014-08-18 14:30:20 +02:00
..
adff2dff.v
Added adff2dff.v (for techmap -share_map)
2014-08-07 16:14:38 +02:00
blackbox.sed
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
Makefile.inc
Added adff2dff.v (for techmap -share_map)
2014-08-07 16:14:38 +02:00
pmux2mux.v
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
simcells.v
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
simlib.v
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
techmap.v
Using "via_celltype" in $mul carry-save-acc implementation
2014-08-18 14:30:20 +02:00