Clifford Wolf 7d9a90396d Added verilog frontend -ignore_redef option		2013-11-24 19:57:42 +01:00
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ast.cc	Added verilog frontend -ignore_redef option	2013-11-24 19:57:42 +01:00
ast.h	Added verilog frontend -ignore_redef option	2013-11-24 19:57:42 +01:00
genrtlil.cc	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
simplify.cc	Early wire/reg/parameter width calculation in ast/simplify	2013-11-24 19:40:23 +01:00