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yosys/techlibs
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Clifford Wolf 881dcd8af9 Added final checks to "synth" and "synth_xilinx"
2015-02-15 13:00:00 +01:00
..
cmos Added test comments to techlibs/cmos/cmos_cells.lib 2014-01-29 10:51:02 +01:00
common Added final checks to "synth" and "synth_xilinx" 2015-02-15 13:00:00 +01:00
xilinx Added final checks to "synth" and "synth_xilinx" 2015-02-15 13:00:00 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00