9 lines
188 B
Verilog
9 lines
188 B
Verilog
module test(in, out, en, vin1, vout1, en1);
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input in, en, en1;
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output out;
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input [1:0] vin1;
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output [1:0] vout1;
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assign out = en ? in : 1'bz;
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assign vout1 = en1 ? vin1 : 2'bzz;
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endmodule
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