10 lines
186 B
Verilog
10 lines
186 B
Verilog
module test(vin0, vout0);
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input [2:0] vin0;
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output reg [7:0] vout0;
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wire [7:0] myreg0, myreg1, myreg2;
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integer i;
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assign myreg0 = vout0 << vin0;
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assign myreg1 = myreg2 >> i;
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endmodule
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