yosys/tests/hana/test_parser_directives_define_simpledef_test.v
2013-01-05 11:13:26 +01:00

9 lines
134 B
Verilog

`define parvez ahmad
`define WIRE wire
`define TEN 10
module `parvez();
parameter param = `TEN;
`WIRE w;
assign w = `TEN;
endmodule