11 lines
179 B
Verilog
11 lines
179 B
Verilog
module test(ctrl, in1, in2, out);
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input ctrl;
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input in1, in2;
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output reg out;
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always @ (ctrl or in1 or in2)
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if(ctrl)
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out = in1 & in2;
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else
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out = in1 | in2;
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endmodule
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