9 lines
134 B
Verilog
9 lines
134 B
Verilog
module test(input in, output reg [1:0] out);
|
|
|
|
always @(in)
|
|
begin
|
|
out = in;
|
|
out = out + in;
|
|
end
|
|
|
|
endmodule
|