yosys/tests/hana/test_simulation_techmap_nand_5_tech.v
2013-01-05 11:13:26 +01:00

11 lines
238 B
Verilog

module TECH_NAND18(input [17:0] in, output out);
assign out = ~(&in);
endmodule
module TECH_NAND4(input [3:0] in, output out);
assign out = ~(&in);
endmodule
module TECH_NAND2(input [1:0] in, output out);
assign out = ~(&in);
endmodule