yosys/tests/hana/test_simulation_techmap_nor_2_tech.v
2013-01-05 11:13:26 +01:00

11 lines
235 B
Verilog

module TECH_NOR18(input [17:0] in, output out);
assign out = ~(|in);
endmodule
module TECH_NOR4(input [3:0] in, output out);
assign out = ~(|in);
endmodule
module TECH_NOR2(input [1:0] in, output out);
assign out = ~(|in);
endmodule