Andrew Zonenberg a0c19aae55 Added simulation timescale declaration		2016-05-07 21:13:47 -07:00
..
common	Added "prep -flatten" and "synth -flatten"	2016-04-24 00:48:33 +02:00
greenpak4	Added simulation timescale declaration	2016-05-07 21:13:47 -07:00
ice40	Added synth_ice40 support for latches via logic loops	2016-05-06 23:02:37 +02:00
xilinx	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00