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a233762a81
yosys
/
passes
/
proc
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Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
..
Makefile.inc
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
proc.cc
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
proc_arst.cc
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
proc_clean.cc
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
proc_dff.cc
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
proc_init.cc
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
proc_mux.cc
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
proc_rmdead.cc
Added help messages to proc_* passes
2013-03-01 09:26:29 +01:00