stv0g/yosys
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity
yosys/tests/hana/test_parse2synthtrans_module_basic0_test.v
Clifford Wolf 7764d0ba1d initial import
2013-01-05 11:13:26 +01:00

2 lines
23 B
Verilog
Raw Blame History

module test;
endmodule
Reference in a new issue View git blame Copy permalink