yosys/tests/hana/test_parser_constructs_port_basic0_test.v
2013-01-05 11:13:26 +01:00

8 lines
137 B
Verilog

module test(in, out, io, vin, vout, vio);
input in;
output out;
inout io;
input [3:0] vin;
output [3:0] vout;
inout [0:3] vio;
endmodule