yosys/tests/hana/test_simulation_techmap_or_19_tech.v
2013-01-05 11:13:26 +01:00

7 lines
149 B
Verilog

module TECH_OR18(input [17:0] in, output out);
assign out = |in;
endmodule
module TECH_OR4(input [3:0] in, output out);
assign out = |in;
endmodule