This website requires JavaScript.
Explore
Help
Sign in
stv0g
/
yosys
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Pull requests
Releases
Wiki
Activity
b1b96d199f
Branches
Tags
No results found.
yosys
/
techlibs
/
common
History
Clifford Wolf
7370ae01e9
Added SIMLIB_NOLUT to simlib.v
2014-04-02 21:28:33 +02:00
..
blackbox.sed
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
Makefile.inc
Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
2014-03-11 14:42:58 +01:00
pmux2mux.v
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
simcells.v
Added support for dlatchsr cells
2014-03-31 14:14:40 +02:00
simlib.v
Added SIMLIB_NOLUT to simlib.v
2014-04-02 21:28:33 +02:00
stdcells.v
Fixes for improved techmap of shifts with large B inputs
2014-03-06 13:33:12 +01:00