Clifford Wolf 7815f81c32 Added "synth" command		2014-09-14 16:09:06 +02:00
..
asicworld	Added autotest -e (do not use -noexpr on write_verilog)	2014-08-30 18:34:07 +02:00
fsm	Cosmetic changes to FSM tests	2014-08-21 17:40:49 +02:00
hana	Added autotest -e (do not use -noexpr on write_verilog)	2014-08-30 18:34:07 +02:00
memories	Added SAT-based write-port sharing to memory_share	2014-07-19 15:33:55 +02:00
realmath	Added note to "make test": use git checkout of iverilog	2014-07-16 10:03:07 +02:00
sat	Added yet another resource sharing test case	2014-07-20 21:15:01 +02:00
share	Added "wreduce" to some of the standard test benches	2014-08-03 20:22:33 +02:00
simple	Added multi-dim memory test (requires iverilog git head)	2014-08-12 10:37:47 +02:00
techmap	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	2014-07-16 14:08:51 +02:00
tools	Added "synth" command	2014-09-14 16:09:06 +02:00
various	Added tests/various/constmsk_test.ys	2014-09-04 15:07:30 +02:00
vloghtb	Added "wreduce" to some of the standard test benches	2014-08-03 20:22:33 +02:00