Clifford Wolf 91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys ... (see https://github.com/cliffordwolf/yosys/pull/28)		2014-03-11 14:24:24 +01:00
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Makefile.inc	Added vhdl2verilog	2014-02-21 18:59:49 +01:00
vhdl2verilog.cc	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	2014-03-11 14:24:24 +01:00