yosys/tests/asicworld/code_verilog_tutorial_simple_function.v
2013-01-05 11:13:26 +01:00

10 lines
132 B
Verilog

module simple_function();
function myfunction;
input a, b, c, d;
begin
myfunction = ((a+b) + (c-d));
end
endfunction
endmodule