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yosys
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e7bec9bbb8
yosys
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techlibs
History
Clifford Wolf
d69395ca08
Added dffsr2dff
2016-02-02 17:19:01 +01:00
..
common
Progress in cell library documentation
2016-02-01 13:58:10 +01:00
greenpak4
Added nlutmap
2015-09-18 21:57:34 +02:00
ice40
Added dffsr2dff
2016-02-02 17:19:01 +01:00
xilinx
Added "abc -luts" option, Improved Xilinx logic mapping
2016-02-01 12:40:32 +01:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00