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ee65dea738
yosys
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frontends
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verilog
History
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
const2ast.cc
Improved parsing of large integer constants
2014-06-15 08:48:17 +02:00
lexer.l
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
Makefile.inc
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
parser.y
fixed parsing of constant with comment between size and value
2014-07-02 06:27:04 +02:00
preproc.cc
Added Verilog support for "`default_nettype none"
2014-02-17 14:28:52 +01:00
verilog_frontend.cc
Added read_verilog -sv options, added support for bit, logic,
2014-06-12 11:54:20 +02:00
verilog_frontend.h
Added read_verilog -sv options, added support for bit, logic,
2014-06-12 11:54:20 +02:00