Initial commit

2015-03-23 20:17:40 +01:00 · 2015-03-23 20:17:40 +01:00 · 6e22380d37
commit 6e22380d37
5 changed files with 531 additions and 0 deletions
--- a/README.md
+++ b/README.md
@ -0,0 +1,25 @@
+Various Files for MYiR ZTurn Board
+==================================
+
+Information
+-----------
+
+Contents:
+
+ - I/O constraints file (`constraints/`)
+ - board definitions and autmation (`board-definition/`), drop in `Xilinx/Vivado/2014.4`
+
+License
+-------
+
+Copyright (c) 2015, Sergiusz 'q3k' Bazański <q3k@q3k.org>
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- a/board-definition/data/boards/board_parts/zynq/zturn/1.0/.ps7.tcl.swp
+++ b/board-definition/data/boards/board_parts/zynq/zturn/1.0/.ps7.tcl.swp
--- a/board-definition/data/boards/board_parts/zynq/zturn/1.0/board_part.xml
+++ b/board-definition/data/boards/board_parts/zynq/zturn/1.0/board_part.xml
@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<board_part board_name="ZTurn_7010" board_revision="a" board_part="part0" schema_version="1.0" vendor="myir.com" version="1.0">
+
+  <part_info part_name="xc7z010clg400-1" device="xc7z010" family="zynq" jtag_position="1" package="clg400" silicon_version="1.0" speed_grade="-1"/>
+
+  <board_info description="ZTurn 7010 Board" display_name="ZTurn 7010 Board" url="http://www.myir.com"/>
+
+  <interfaces>
+    <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0">
+      <preset_file name="ps7.tcl"/>
+    </interface>
+  </interfaces>
+
+  <ports/>
+
+</board_part>
--- a/board-definition/data/boards/board_parts/zynq/zturn/1.0/ps7.tcl
+++ b/board-definition/data/boards/board_parts/zynq/zturn/1.0/ps7.tcl
@ -0,0 +1,287 @@
+# ----------------------------------------------------------------------------
+# 
+#  MYiR ZTurn Zynq 7010 Board Definition File
+#
+#  Sergiusz 'q3k' Bazański <q3k@q3k.org>
+# 
+# ----------------------------------------------------------------------------
+ 
+############################################################################
+# PS Bank Voltage, Busses, Clocks 
+############################################################################
+proc apply_ps7_board_setting { ps7_ip } {
+set_property -dict [ list \
+	CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
+	CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+	CONFIG.PCW_PACKAGE_NAME {clg400} \
+	CONFIG.PCW_USE_M_AXI_GP0 {1} \
+	CONFIG.PCW_USE_M_AXI_GP1 {0} \
+	CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
+	CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+	CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
+	CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
+	CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
+	CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
+	CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {ARM PLL} \
+	CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
+	CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
+	CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+	CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+	CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+	CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \
+	CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333333} \
+	CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+	CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {125} \
+	CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
+	CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+	CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
+	CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+	CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+	CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+] [get_bd_cells $ps7_ip]
+
+############################################################################
+# Fabric Clocks - CLK0 enabled, CLK[3:1] disabled by default
+############################################################################
+
+set_property -dict [ list \
+	CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
+	CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
+	CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
+	CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
+	CONFIG.PCW_FCLK_CLK0_BUF {true} \
+	CONFIG.PCW_FCLK_CLK1_BUF {true} \
+	CONFIG.PCW_FCLK_CLK2_BUF {false} \
+	CONFIG.PCW_FCLK_CLK3_BUF {false} \
+	CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
+	CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
+	CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
+	CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
+	CONFIG.PCW_EN_CLK0_PORT {1} \
+	CONFIG.PCW_EN_CLK1_PORT {1} \
+	CONFIG.PCW_EN_CLK2_PORT {0} \
+	CONFIG.PCW_EN_CLK3_PORT {0} \
+	CONFIG.PCW_EN_RST0_PORT {1} \
+	CONFIG.PCW_EN_RST1_PORT {0} \
+	CONFIG.PCW_EN_RST2_PORT {0} \
+	CONFIG.PCW_EN_RST3_PORT {0} \
+] [get_bd_cells ]
+
+############################################################################
+# DDR3 
+############################################################################
+set_property -dict [ list \
+	CONFIG.PCW_EN_DDR {1} \
+	CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
+	CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+	CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
+	CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
+	CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+	CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+	CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
+	CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+	CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
+	CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
+	CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
+	CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
+	CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.229} \
+	CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.250} \
+	CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.121} \
+	CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.146} \
+	CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.271} \
+	CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.259} \
+	CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.219} \
+	CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.207} \
+	CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
+] [get_bd_cells processing_system7_0]
+
+############################################################################
+# Peripheral assignments
+############################################################################
+set_property -dict [ list \
+	CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+	CONFIG.PCW_USB0_RESET_IO {MIO 7} \
+	CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
+	CONFIG.PCW_UART0_UART0_IO {MIO 10 .. 11} \
+    CONFIG.PCW_I2C0_I2C0_IO EMIO \
+    CONFIG.PCW_I2C1_I2C1_IO {MIO 12 .. 13} \
+    CONFIG.PCW_CAN0_CAN0_IO {MIO 14 .. 15} \
+	CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+	CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
+	CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
+	CONFIG.PCW_SD0_GRP_CD_IO {MIO 46} \
+	CONFIG.PCW_SD0_GRP_WP_IO {MIO 47} \
+	CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
+	CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
+	CONFIG.PCW_TTC0_TTC0_IO {EMIO} \
+] [get_bd_cells processing_system7_0]
+
+############################################################################
+# Enable Peripherals 
+############################################################################
+set_property -dict [ list \
+	CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+	CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
+	CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+	CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
+	CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+	CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+	CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+	CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
+	CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \
+	CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {1} \
+	CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
+	CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \
+	CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+	CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
+	CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {1} \
+	CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+	CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
+	CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \
+] [get_bd_cells processing_system7_0]
+
+############################################################################
+# Configure MIOs
+############################################################################
+set_property -dict [ list \
+	CONFIG.PCW_MIO_0_PULLUP {enabled} \
+	CONFIG.PCW_MIO_1_PULLUP {disabled} \
+	CONFIG.PCW_MIO_2_PULLUP {disabled} \
+	CONFIG.PCW_MIO_3_PULLUP {disabled} \
+	CONFIG.PCW_MIO_4_PULLUP {disabled} \
+	CONFIG.PCW_MIO_5_PULLUP {disabled} \
+	CONFIG.PCW_MIO_6_PULLUP {disabled} \
+	CONFIG.PCW_MIO_7_PULLUP {disabled} \
+	CONFIG.PCW_MIO_8_PULLUP {disabled} \
+	CONFIG.PCW_MIO_9_PULLUP {disabled} \
+	CONFIG.PCW_MIO_10_PULLUP {enabled} \
+	CONFIG.PCW_MIO_11_PULLUP {enabled} \
+	CONFIG.PCW_MIO_12_PULLUP {enabled} \
+	CONFIG.PCW_MIO_13_PULLUP {enabled} \
+	CONFIG.PCW_MIO_14_PULLUP {enabled} \
+	CONFIG.PCW_MIO_15_PULLUP {enabled} \
+	CONFIG.PCW_MIO_16_PULLUP {enabled} \
+	CONFIG.PCW_MIO_17_PULLUP {enabled} \
+	CONFIG.PCW_MIO_18_PULLUP {enabled} \
+	CONFIG.PCW_MIO_19_PULLUP {enabled} \
+	CONFIG.PCW_MIO_20_PULLUP {enabled} \
+	CONFIG.PCW_MIO_21_PULLUP {enabled} \
+	CONFIG.PCW_MIO_22_PULLUP {enabled} \
+	CONFIG.PCW_MIO_23_PULLUP {enabled} \
+	CONFIG.PCW_MIO_24_PULLUP {enabled} \
+	CONFIG.PCW_MIO_25_PULLUP {enabled} \
+	CONFIG.PCW_MIO_26_PULLUP {enabled} \
+	CONFIG.PCW_MIO_27_PULLUP {enabled} \
+	CONFIG.PCW_MIO_28_PULLUP {enabled} \
+	CONFIG.PCW_MIO_29_PULLUP {enabled} \
+	CONFIG.PCW_MIO_30_PULLUP {enabled} \
+	CONFIG.PCW_MIO_31_PULLUP {enabled} \
+	CONFIG.PCW_MIO_32_PULLUP {enabled} \
+	CONFIG.PCW_MIO_33_PULLUP {enabled} \
+	CONFIG.PCW_MIO_34_PULLUP {enabled} \
+	CONFIG.PCW_MIO_35_PULLUP {enabled} \
+	CONFIG.PCW_MIO_36_PULLUP {enabled} \
+	CONFIG.PCW_MIO_37_PULLUP {enabled} \
+	CONFIG.PCW_MIO_38_PULLUP {enabled} \
+	CONFIG.PCW_MIO_39_PULLUP {enabled} \
+	CONFIG.PCW_MIO_40_PULLUP {enabled} \
+	CONFIG.PCW_MIO_41_PULLUP {enabled} \
+	CONFIG.PCW_MIO_42_PULLUP {enabled} \
+	CONFIG.PCW_MIO_43_PULLUP {enabled} \
+	CONFIG.PCW_MIO_44_PULLUP {enabled} \
+	CONFIG.PCW_MIO_45_PULLUP {enabled} \
+	CONFIG.PCW_MIO_46_PULLUP {disabled} \
+	CONFIG.PCW_MIO_47_PULLUP {disabled} \
+	CONFIG.PCW_MIO_48_PULLUP {enabled} \
+	CONFIG.PCW_MIO_49_PULLUP {enabled} \
+	CONFIG.PCW_MIO_50_PULLUP {disabled} \
+	CONFIG.PCW_MIO_51_PULLUP {disabled} \
+	CONFIG.PCW_MIO_52_PULLUP {enabled} \
+	CONFIG.PCW_MIO_53_PULLUP {enabled} \
+	CONFIG.PCW_MIO_0_SLEW {slow} \
+	CONFIG.PCW_MIO_1_SLEW {slow} \
+	CONFIG.PCW_MIO_2_SLEW {slow} \
+	CONFIG.PCW_MIO_3_SLEW {slow} \
+	CONFIG.PCW_MIO_4_SLEW {slow} \
+	CONFIG.PCW_MIO_5_SLEW {slow} \
+	CONFIG.PCW_MIO_6_SLEW {slow} \
+	CONFIG.PCW_MIO_7_SLEW {slow} \
+	CONFIG.PCW_MIO_8_SLEW {slow} \
+	CONFIG.PCW_MIO_9_SLEW {slow} \
+	CONFIG.PCW_MIO_10_SLEW {slow} \
+	CONFIG.PCW_MIO_11_SLEW {slow} \
+	CONFIG.PCW_MIO_12_SLEW {slow} \
+	CONFIG.PCW_MIO_13_SLEW {slow} \
+	CONFIG.PCW_MIO_14_SLEW {slow} \
+	CONFIG.PCW_MIO_15_SLEW {slow} \
+	CONFIG.PCW_MIO_16_SLEW {slow} \
+	CONFIG.PCW_MIO_17_SLEW {slow} \
+	CONFIG.PCW_MIO_18_SLEW {slow} \
+	CONFIG.PCW_MIO_19_SLEW {slow} \
+	CONFIG.PCW_MIO_20_SLEW {slow} \
+	CONFIG.PCW_MIO_21_SLEW {slow} \
+	CONFIG.PCW_MIO_22_SLEW {slow} \
+	CONFIG.PCW_MIO_23_SLEW {slow} \
+	CONFIG.PCW_MIO_24_SLEW {slow} \
+	CONFIG.PCW_MIO_25_SLEW {slow} \
+	CONFIG.PCW_MIO_26_SLEW {slow} \
+	CONFIG.PCW_MIO_27_SLEW {slow} \
+	CONFIG.PCW_MIO_28_SLEW {slow} \
+	CONFIG.PCW_MIO_29_SLEW {slow} \
+	CONFIG.PCW_MIO_30_SLEW {slow} \
+	CONFIG.PCW_MIO_31_SLEW {slow} \
+	CONFIG.PCW_MIO_32_SLEW {slow} \
+	CONFIG.PCW_MIO_33_SLEW {slow} \
+	CONFIG.PCW_MIO_34_SLEW {slow} \
+	CONFIG.PCW_MIO_35_SLEW {slow} \
+	CONFIG.PCW_MIO_36_SLEW {slow} \
+	CONFIG.PCW_MIO_37_SLEW {slow} \
+	CONFIG.PCW_MIO_38_SLEW {slow} \
+	CONFIG.PCW_MIO_39_SLEW {slow} \
+	CONFIG.PCW_MIO_40_SLEW {slow} \
+	CONFIG.PCW_MIO_41_SLEW {slow} \
+	CONFIG.PCW_MIO_42_SLEW {slow} \
+	CONFIG.PCW_MIO_43_SLEW {slow} \
+	CONFIG.PCW_MIO_44_SLEW {slow} \
+	CONFIG.PCW_MIO_45_SLEW {slow} \
+	CONFIG.PCW_MIO_46_SLEW {slow} \
+	CONFIG.PCW_MIO_47_SLEW {slow} \
+	CONFIG.PCW_MIO_48_SLEW {slow} \
+	CONFIG.PCW_MIO_49_SLEW {slow} \
+	CONFIG.PCW_MIO_50_SLEW {slow} \
+	CONFIG.PCW_MIO_51_SLEW {slow} \
+	CONFIG.PCW_MIO_52_SLEW {slow} \
+	CONFIG.PCW_MIO_53_SLEW {slow} \
+] [get_bd_cells processing_system7_0]
+
+############################################################################
+# Enable USB Reset last
+############################################################################
+set_property -dict [ list \
+	CONFIG.PCW_USB0_RESET_ENABLE {1} \
+] [get_bd_cells processing_system7_0]
+
+############################################################################
+# Extra stuff?
+############################################################################
+
+set_property -dict [ list \
+	CONFIG.PCW_USE_S_AXI_HP0 {1} \
+	CONFIG.PCW_IRQ_F2P_INTR {1} \
+] [get_bd_cells processing_system7_0]
+
+############################################################################
+# End ZTurn Presets 
+############################################################################
+}
--- a/constraints/system.xdc
+++ b/constraints/system.xdc
@ -0,0 +1,203 @@
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[24]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[23]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[22]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[21]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[20]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[19]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[18]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[24]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[23]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[22]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[21]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[20]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[19]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[18]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[0]}]
+set_property PACKAGE_PIN T11 [get_ports {IO_B34_LP[1]}]
+set_property PACKAGE_PIN T10 [get_ports {IO_B34_LN[1]}]
+set_property PACKAGE_PIN T12 [get_ports {IO_B34_LP[2]}]
+set_property PACKAGE_PIN U12 [get_ports {IO_B34_LN[2]}]
+set_property PACKAGE_PIN U13 [get_ports {IO_B34_LP[3]}]
+set_property PACKAGE_PIN V13 [get_ports {IO_B34_LN[3]}]
+set_property PACKAGE_PIN V12 [get_ports {IO_B34_LP[4]}]
+set_property PACKAGE_PIN W13 [get_ports {IO_B34_LN[4]}]
+set_property PACKAGE_PIN T14 [get_ports {IO_B34_LP[5]}]
+set_property PACKAGE_PIN T15 [get_ports {IO_B34_LN[5]}]
+set_property PACKAGE_PIN T16 [get_ports {LCD_DATA[0]}]
+set_property PACKAGE_PIN U17 [get_ports {LCD_DATA[1]}]
+set_property PACKAGE_PIN V15 [get_ports {LCD_DATA[2]}]
+set_property PACKAGE_PIN W15 [get_ports {LCD_DATA[3]}]
+set_property PACKAGE_PIN U18 [get_ports {LCD_DATA[4]}]
+set_property PACKAGE_PIN U19 [get_ports {LCD_DATA[5]}]
+set_property PACKAGE_PIN N18 [get_ports {LCD_DATA[6]}]
+set_property PACKAGE_PIN P19 [get_ports {LCD_DATA[7]}]
+set_property PACKAGE_PIN N20 [get_ports {LCD_DATA[8]}]
+set_property PACKAGE_PIN P20 [get_ports {LCD_DATA[9]}]
+set_property PACKAGE_PIN T20 [get_ports {LCD_DATA[10]}]
+set_property PACKAGE_PIN U20 [get_ports {LCD_DATA[11]}]
+set_property PACKAGE_PIN V20 [get_ports {LCD_DATA[12]}]
+set_property PACKAGE_PIN W20 [get_ports {LCD_DATA[13]}]
+set_property PACKAGE_PIN Y18 [get_ports {LCD_DATA[14]}]
+set_property PACKAGE_PIN Y19 [get_ports {LCD_DATA[15]}]
+set_property PACKAGE_PIN P18 [get_ports BP]
+set_property PACKAGE_PIN P15 [get_ports I2C0_SDA]
+set_property PACKAGE_PIN P16 [get_ports I2C0_SCL]
+set_property IOSTANDARD LVCMOS33 [get_ports BP]
+set_property IOSTANDARD LVCMOS33 [get_ports I2C0_SCL]
+set_property IOSTANDARD LVCMOS33 [get_ports I2C0_SDA]
+set_property PACKAGE_PIN N17 [get_ports MEMS_INTn]
+set_property IOSTANDARD LVCMOS33 [get_ports MEMS_INTn]
+set_property PACKAGE_PIN V16 [get_ports LCD_VSYNC]
+set_property PACKAGE_PIN W16 [get_ports LCD_HSYNC]
+set_property PACKAGE_PIN R16 [get_ports LCD_DE]
+set_property PACKAGE_PIN R17 [get_ports LCD_PCLK]
+set_property IOSTANDARD LVCMOS33 [get_ports LCD_PCLK]
+set_property IOSTANDARD LVCMOS33 [get_ports LCD_HSYNC]
+set_property IOSTANDARD LVCMOS33 [get_ports LCD_DE]
+set_property IOSTANDARD LVCMOS33 [get_ports LCD_VSYNC]
+set_property PACKAGE_PIN W18 [get_ports I2S_DIN]
+set_property PACKAGE_PIN V18 [get_ports I2S_FSYNC_IN]
+set_property IOSTANDARD LVCMOS33 [get_ports I2S_DIN]
+set_property IOSTANDARD LVCMOS33 [get_ports I2S_FSYNC_IN]
+set_property PACKAGE_PIN P14 [get_ports IO_B34_LP6]
+set_property PACKAGE_PIN W14 [get_ports IO_B34_LP8]
+set_property PACKAGE_PIN Y14 [get_ports IO_B34_LN8]
+set_property PACKAGE_PIN U14 [get_ports IO_B34_LP11]
+set_property PACKAGE_PIN U15 [get_ports IO_B34_LN11]
+set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LP11]
+set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LP8]
+set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LN11]
+set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LN8]
+set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LP6]
+set_property PACKAGE_PIN C20 [get_ports {IO_B35_LP[1]}]
+set_property PACKAGE_PIN B20 [get_ports {IO_B35_LN[1]}]
+set_property PACKAGE_PIN A20 [get_ports {IO_B35_LN[2]}]
+set_property PACKAGE_PIN B19 [get_ports {IO_B35_LP[2]}]
+set_property PACKAGE_PIN E17 [get_ports {IO_B35_LP[3]}]
+set_property PACKAGE_PIN D18 [get_ports {IO_B35_LN[3]}]
+set_property PACKAGE_PIN D19 [get_ports {IO_B35_LP[4]}]
+set_property PACKAGE_PIN D20 [get_ports {IO_B35_LN[4]}]
+set_property PACKAGE_PIN E18 [get_ports {IO_B35_LP[5]}]
+set_property PACKAGE_PIN E19 [get_ports {IO_B35_LN[5]}]
+set_property PACKAGE_PIN F16 [get_ports {IO_B35_LP[6]}]
+set_property PACKAGE_PIN F17 [get_ports {IO_B35_LN[6]}]
+set_property PACKAGE_PIN M19 [get_ports {IO_B35_LP[7]}]
+set_property PACKAGE_PIN M20 [get_ports {IO_B35_LN[7]}]
+set_property PACKAGE_PIN M17 [get_ports {IO_B35_LP[8]}]
+set_property PACKAGE_PIN M18 [get_ports {IO_B35_LN[8]}]
+set_property PACKAGE_PIN L19 [get_ports {IO_B35_LP[9]}]
+set_property PACKAGE_PIN L20 [get_ports {IO_B35_LN[9]}]
+set_property PACKAGE_PIN K19 [get_ports {IO_B35_LP[10]}]
+set_property PACKAGE_PIN J19 [get_ports {IO_B35_LN[10]}]
+set_property PACKAGE_PIN L16 [get_ports {IO_B35_LP[11]}]
+set_property PACKAGE_PIN L17 [get_ports {IO_B35_LN[11]}]
+set_property PACKAGE_PIN K17 [get_ports {IO_B35_LP[12]}]
+set_property PACKAGE_PIN K18 [get_ports {IO_B35_LN[12]}]
+set_property PACKAGE_PIN H16 [get_ports {IO_B35_LP[13]}]
+set_property PACKAGE_PIN H17 [get_ports {IO_B35_LN[13]}]
+set_property PACKAGE_PIN J18 [get_ports {IO_B35_LP[14]}]
+set_property PACKAGE_PIN H18 [get_ports {IO_B35_LN[14]}]
+set_property PACKAGE_PIN F19 [get_ports {IO_B35_LP[15]}]
+set_property PACKAGE_PIN F20 [get_ports {IO_B35_LN[15]}]
+set_property PACKAGE_PIN G17 [get_ports {IO_B35_LP[16]}]
+set_property PACKAGE_PIN G18 [get_ports {IO_B35_LN[16]}]
+set_property PACKAGE_PIN J20 [get_ports {IO_B35_LP[17]}]
+set_property PACKAGE_PIN H20 [get_ports {IO_B35_LN[17]}]
+set_property PACKAGE_PIN G19 [get_ports {IO_B35_LP[18]}]
+set_property PACKAGE_PIN G20 [get_ports {IO_B35_LN[18]}]
+set_property PACKAGE_PIN H15 [get_ports {IO_B35_LP[19]}]
+set_property PACKAGE_PIN G15 [get_ports {IO_B35_LN[19]}]
+set_property PACKAGE_PIN K14 [get_ports {IO_B35_LP[20]}]
+set_property PACKAGE_PIN J14 [get_ports {IO_B35_LN[20]}]
+set_property PACKAGE_PIN N15 [get_ports {IO_B35_LP[21]}]
+set_property PACKAGE_PIN N16 [get_ports {IO_B35_LN[21]}]
+set_property PACKAGE_PIN L14 [get_ports {IO_B35_LP[22]}]
+set_property PACKAGE_PIN L15 [get_ports {IO_B35_LN[22]}]
+set_property PACKAGE_PIN M14 [get_ports {IO_B35_LP[23]}]
+set_property PACKAGE_PIN M15 [get_ports {IO_B35_LN[23]}]
+set_property PACKAGE_PIN K16 [get_ports {IO_B35_LP[24]}]
+set_property PACKAGE_PIN J16 [get_ports {IO_B35_LN[24]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports HDMI_INTn]
+set_property PACKAGE_PIN W19 [get_ports HDMI_INTn]
+set_property IOSTANDARD LVCMOS33 [get_ports I2S_FSYNC_OUT]
+set_property IOSTANDARD LVCMOS33 [get_ports I2S_SCLK]
+set_property IOSTANDARD LVCMOS33 [get_ports I2S_DOUT]
+set_property PACKAGE_PIN V17 [get_ports I2S_DOUT]
+set_property PACKAGE_PIN T17 [get_ports I2S_SCLK]
+set_property PACKAGE_PIN R18 [get_ports I2S_FSYNC_OUT]
+set_property PACKAGE_PIN R19 [get_ports {SW[0]}]
+set_property PACKAGE_PIN T19 [get_ports {SW[1]}]
+set_property PACKAGE_PIN G14 [get_ports {SW[2]}]
+set_property PACKAGE_PIN J15 [get_ports {SW[3]}]
+set_property PACKAGE_PIN Y16 [get_ports {LEDS[0]}]
+set_property PACKAGE_PIN Y17 [get_ports {LEDS[1]}]
+set_property PACKAGE_PIN R14 [get_ports {LEDS[2]}]
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]