diff --git a/sdsoc-platform/zturn-7z020/arm-xilinx-eabi/lib/libxil.a b/sdsoc-platform/zturn-7z020/arm-xilinx-eabi/lib/libxil.a new file mode 100644 index 0000000..2f73a1c Binary files /dev/null and b/sdsoc-platform/zturn-7z020/arm-xilinx-eabi/lib/libxil.a differ diff --git a/sdsoc-platform/zturn-7z020/arm-xilinx-eabi/lscript.ld b/sdsoc-platform/zturn-7z020/arm-xilinx-eabi/lscript.ld new file mode 100644 index 0000000..2f20d8b --- /dev/null +++ b/sdsoc-platform/zturn-7z020/arm-xilinx-eabi/lscript.ld @@ -0,0 +1,285 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: Xilinx EDK 2013.4 EDK_2013.4.20131205 */ +/* */ +/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : Cortex-A9 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x40000; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x8000000; + +_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024; +_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048; +_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024; +_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024; +_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x00100000, LENGTH = 0x3FF00000 + ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000 + ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00 +} + +/* Specify the default entry point to the program */ + +ENTRY(_vector_table) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + *(.vectors) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.vfp11_veneer) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) +} > ps7_ddr_0_S_AXI_BASEADDR + +.init : { + KEEP (*(.init)) +} > ps7_ddr_0_S_AXI_BASEADDR + +.fini : { + KEEP (*(.fini)) +} > ps7_ddr_0_S_AXI_BASEADDR + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.rodata1 : { + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.sdata2 : { + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.data : { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + __data_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.data1 : { + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.got : { + *(.got) +} > ps7_ddr_0_S_AXI_BASEADDR + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.eh_frame : { + *(.eh_frame) +} > ps7_ddr_0_S_AXI_BASEADDR + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.gcc_except_table : { + *(.gcc_except_table) +} > ps7_ddr_0_S_AXI_BASEADDR + +.mmu_tbl (ALIGN(16384)) : { + __mmu_tbl_start = .; + *(.mmu_tbl) + __mmu_tbl_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidix.*.*) + __exidx_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.preinit_array : { + __preinit_array_start = .; + KEEP (*(SORT(.preinit_array.*))) + KEEP (*(.preinit_array)) + __preinit_array_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.init_array : { + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.fini_array : { + __fini_array_start = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + __fini_array_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.ARM.attributes : { + __ARM.attributes_start = .; + *(.ARM.attributes) + __ARM.attributes_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.sdata : { + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.sbss (NOLOAD) : { + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + __sbss_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.bss (NOLOAD) : { + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); + +_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); + +/* Generate Stack and Heap definitions */ + +.heap (NOLOAD) : { + . = ALIGN(16); + _heap = .; + HeapBase = .; + _heap_start = .; + . += _HEAP_SIZE; + _heap_end = .; + HeapLimit = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.stack (NOLOAD) : { + . = ALIGN(16); + _stack_end = .; + . += _STACK_SIZE; + _stack = .; + __stack = _stack; + . = ALIGN(16); + _irq_stack_end = .; + . += _IRQ_STACK_SIZE; + __irq_stack = .; + _supervisor_stack_end = .; + . += _SUPERVISOR_STACK_SIZE; + . = ALIGN(16); + __supervisor_stack = .; + _abort_stack_end = .; + . += _ABORT_STACK_SIZE; + . = ALIGN(16); + __abort_stack = .; + _fiq_stack_end = .; + . += _FIQ_STACK_SIZE; + . = ALIGN(16); + __fiq_stack = .; + _undef_stack_end = .; + . += _UNDEF_STACK_SIZE; + . = ALIGN(16); + __undef_stack = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +_end = .; +} + diff --git a/sdsoc-platform/zturn-7z020/boot/fsbl.elf b/sdsoc-platform/zturn-7z020/boot/fsbl.elf new file mode 100644 index 0000000..2cfcc4d Binary files /dev/null and b/sdsoc-platform/zturn-7z020/boot/fsbl.elf differ diff --git a/sdsoc-platform/zturn-7z020/boot/generic.readme b/sdsoc-platform/zturn-7z020/boot/generic.readme new file mode 100644 index 0000000..25a2876 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/boot/generic.readme @@ -0,0 +1,10 @@ +-= SD card boot image =- + +Platform: +Application: + +1. Copy the contents of this directory to an SD card +2. Set boot mode to SD + Jumper J1 NC + Jumper J2 1-2 +3. Insert SD card and turn board on diff --git a/sdsoc-platform/zturn-7z020/boot/standalone.bif b/sdsoc-platform/zturn-7z020/boot/standalone.bif new file mode 100644 index 0000000..32a161e --- /dev/null +++ b/sdsoc-platform/zturn-7z020/boot/standalone.bif @@ -0,0 +1,7 @@ +/* standalone */ +the_ROM_image: +{ + [bootloader] + + +} diff --git a/sdsoc-platform/zturn-7z020/hardware/prebuilt/bitstream.bit b/sdsoc-platform/zturn-7z020/hardware/prebuilt/bitstream.bit new file mode 100644 index 0000000..794afee Binary files /dev/null and b/sdsoc-platform/zturn-7z020/hardware/prebuilt/bitstream.bit differ diff --git a/sdsoc-platform/zturn-7z020/hardware/prebuilt/export/z_turn20.hdf b/sdsoc-platform/zturn-7z020/hardware/prebuilt/export/z_turn20.hdf new file mode 100644 index 0000000..311ec3e Binary files /dev/null and b/sdsoc-platform/zturn-7z020/hardware/prebuilt/export/z_turn20.hdf differ diff --git a/sdsoc-platform/zturn-7z020/hardware/prebuilt/hwcf/apsys_0.xml b/sdsoc-platform/zturn-7z020/hardware/prebuilt/hwcf/apsys_0.xml new file mode 100644 index 0000000..cf74959 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/hardware/prebuilt/hwcf/apsys_0.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/hardware/prebuilt/hwcf/partitions.xml b/sdsoc-platform/zturn-7z020/hardware/prebuilt/hwcf/partitions.xml new file mode 100644 index 0000000..8eebba3 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/hardware/prebuilt/hwcf/partitions.xml @@ -0,0 +1,4 @@ + + + + diff --git a/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/devreg.c b/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/devreg.c new file mode 100644 index 0000000..0820d34 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/devreg.c @@ -0,0 +1,65 @@ +/* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/devreg.c */ +#include "cf_lib.h" +#include "cf_request.h" +#include "devreg.h" + +#include "stdio.h" // for getting printf +#include "xlnk_core_cf.h" +#include "accel_info.h" +#include "axi_dma_simple_dm.h" +#include "axi_lite_dm.h" + +axi_dma_simple_info_t _p0_datamover_0 = { + .device_id = 0, + .phys_base_addr = 0x80400000, + .addr_range = 0x10000, + .dir = XLNK_DMA_TO_DEV, +}; + +axi_dma_simple_info_t _p0_datamover_1 = { + .device_id = 1, + .phys_base_addr = 0x80410000, + .addr_range = 0x10000, + .dir = XLNK_DMA_TO_DEV, +}; + +axi_dma_simple_info_t _p0_datamover_2 = { + .device_id = 2, + .phys_base_addr = 0x80420000, + .addr_range = 0x10000, + .dir = XLNK_DMA_FROM_DEV, +}; + +accel_info_t _sds__p0_mmult_0 = { + .device_id = 3, + .phys_base_addr = 0x83c00000, + .addr_range = 0x10000, + .ip_type = "axis_acc_adapter" +}; + +void _p0_cf_register(int first) +{ + int xlnk_init_done = cf_xlnk_open(first); + if (xlnk_init_done == 0) { + axi_dma_simple_register(&_p0_datamover_0); + axi_dma_simple_register(&_p0_datamover_1); + axi_dma_simple_register(&_p0_datamover_2); + accel_register(&_sds__p0_mmult_0); + cf_xlnk_init(first); + } + else if (xlnk_init_done <0) { + fprintf(stderr, "ERROR: unable to open xlnk %d\n", xlnk_init_done); + } + else { + } +} + +void _p0_cf_unregister(int last) +{ + axi_dma_simple_unregister(&_p0_datamover_0); + axi_dma_simple_unregister(&_p0_datamover_1); + axi_dma_simple_unregister(&_p0_datamover_2); + accel_unregister(&_sds__p0_mmult_0); + xlnkClose(last,NULL); +} + diff --git a/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/devreg.h b/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/devreg.h new file mode 100644 index 0000000..f965ad9 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/devreg.h @@ -0,0 +1,13 @@ +#ifndef _SDI_DEVREG_H +#define _SDI_DEVREG_H +/* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/devreg.h */ +#ifdef __cplusplus +extern "C" { +#endif + +void _p0_cf_register(int); +void _p0_cf_unregister(int); +#ifdef __cplusplus +}; +#endif +#endif /* _SDI_DEVREG_H_ */ diff --git a/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/portinfo.c b/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/portinfo.c new file mode 100644 index 0000000..1dc7ad5 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/portinfo.c @@ -0,0 +1,137 @@ +/* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/portinfo.c */ +#include "cf_lib.h" +#include "cf_request.h" +#include "devreg.h" + +#include "portinfo.h" + +#include "stdio.h" // for printf + +#include "xlnk_core_cf.h" +#include "accel_info.h" +#include "axi_dma_simple_dm.h" +#include "axi_lite_dm.h" + +extern axi_dma_simple_info_t _p0_datamover_0; +extern axi_dma_simple_info_t _p0_datamover_1; +extern axi_dma_simple_info_t _p0_datamover_2; +extern accel_info_t _sds__p0_mmult_0; + +axi_lite_info_t _p0_swinst_mmult_0_cmd_mmult_info = { + .accel_info = &_sds__p0_mmult_0, + .reg_name = "0x28" +}; + +axi_dma_simple_channel_info_t _p0_swinst_mmult_0_A_info = { + .dma_info = &_p0_datamover_1, + .in_use = 0, + .needs_cache_flush_invalidate = 0 +}; + +axi_dma_simple_channel_info_t _p0_swinst_mmult_0_B_info = { + .dma_info = &_p0_datamover_0, + .in_use = 0, + .needs_cache_flush_invalidate = 0 +}; + +axi_dma_simple_channel_info_t _p0_swinst_mmult_0_C_info = { + .dma_info = &_p0_datamover_2, + .in_use = 0, + .needs_cache_flush_invalidate = 0 +}; + +struct _p0_swblk_mmult _p0_swinst_mmult_0 = { + .cmd_mmult = { .base = { + .channel_info = &_p0_swinst_mmult_0_cmd_mmult_info, + .open_i = &axi_lite_open, + .close_i = &axi_lite_close }, + .send_i = &axi_lite_send }, + .A = { .base = { + .channel_info = &_p0_swinst_mmult_0_A_info, + .open_i = &axi_dma_simple_open, + .close_i = &axi_dma_simple_close }, + .send_i = &axi_dma_simple_send_i }, + .B = { .base = { + .channel_info = &_p0_swinst_mmult_0_B_info, + .open_i = &axi_dma_simple_open, + .close_i = &axi_dma_simple_close }, + .send_i = &axi_dma_simple_send_i }, + .C = { .base = { + .channel_info = &_p0_swinst_mmult_0_C_info, + .open_i = &axi_dma_simple_open, + .close_i = &axi_dma_simple_close }, + .receive_ref_i = 0, + .receive_i = &axi_dma_simple_recv_i }, +}; + +void _p0_cf_open_port (cf_port_base_t *port) +{ + port->open_i(port, NULL); +} + +void _p0_cf_framework_open(int first) +{ + cf_context_init(); + xlnkCounterMap(); + _p0_cf_register(first); + cf_get_current_context(); + accel_open(&_sds__p0_mmult_0); + _p0_cf_open_port( &_p0_swinst_mmult_0.cmd_mmult.base ); + _p0_cf_open_port( &_p0_swinst_mmult_0.A.base ); + _p0_cf_open_port( &_p0_swinst_mmult_0.B.base ); + _p0_cf_open_port( &_p0_swinst_mmult_0.C.base ); +} + +void _p0_cf_framework_close(int last) +{ + cf_close_i( &_p0_swinst_mmult_0.cmd_mmult, NULL); + cf_close_i( &_p0_swinst_mmult_0.A, NULL); + cf_close_i( &_p0_swinst_mmult_0.B, NULL); + cf_close_i( &_p0_swinst_mmult_0.C, NULL); + accel_close(&_sds__p0_mmult_0); + _p0_cf_unregister(last); +} + +#define TOTAL_PARTITIONS 1 +int current_partition_num = 0; +struct { + void (*open)(int); + void (*close)(int); +} + +_ptable[TOTAL_PARTITIONS] = { + {.open = &_p0_cf_framework_open, .close= &_p0_cf_framework_close}, +}; + +void switch_to_next_partition(int partition_num) +{ +#ifdef __linux__ + if (current_partition_num != partition_num) { + _ptable[current_partition_num].close(0); + char buf[128]; + sprintf(buf, "cat /mnt/_sds/_p%d_.bin > /dev/xdevcfg", partition_num); + system(buf); + _ptable[partition_num].open(0); + current_partition_num = partition_num; + } +#endif +} + +void init_first_partition() __attribute__ ((constructor)); +void close_last_partition() __attribute__ ((destructor)); +void init_first_partition() +{ + current_partition_num = 0; + _ptable[current_partition_num].open(1); +} + + +void close_last_partition() +{ +#ifdef PERF_EST + apf_perf_estimation_exit(); +#endif + _ptable[current_partition_num].close(1); + current_partition_num = 0; +} + diff --git a/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/portinfo.h b/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/portinfo.h new file mode 100644 index 0000000..cf979e4 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/hardware/prebuilt/swcf/portinfo.h @@ -0,0 +1,31 @@ +#ifndef _SDI_PORTINFO_H +#define _SDI_PORTINFO_H +/* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/portinfo.h */ +#ifdef __cplusplus +extern "C" { +#endif + +struct _p0_swblk_mmult { + cf_port_send_t cmd_mmult; + cf_port_send_t A; + cf_port_send_t B; + cf_port_receive_t C; +}; + +extern struct _p0_swblk_mmult _p0_swinst_mmult_0; +void _p0_cf_framework_open(int); +void _p0_cf_framework_close(int); + +#ifdef __cplusplus +}; +#endif +#ifdef __cplusplus +extern "C" { +#endif +void switch_to_next_partition(int); +void init_first_partition(); +void close_last_partition(); +#ifdef __cplusplus +}; +#endif /* extern "C" */ +#endif /* _SDI_PORTINFO_H_ */ diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/constrs_1/new/system.xdc b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/constrs_1/new/system.xdc new file mode 100644 index 0000000..3ca434f --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/constrs_1/new/system.xdc @@ -0,0 +1,203 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LN[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B34_LP[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[24]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[23]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[22]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[21]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[20]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[19]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[18]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[17]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[16]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LP[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[24]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[23]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[22]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[21]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[20]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[19]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[18]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[17]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[16]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {IO_B35_LN[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LCD_DATA[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[0]}] +set_property PACKAGE_PIN T11 [get_ports {IO_B34_LP[1]}] +set_property PACKAGE_PIN T10 [get_ports {IO_B34_LN[1]}] +set_property PACKAGE_PIN T12 [get_ports {IO_B34_LP[2]}] +set_property PACKAGE_PIN U12 [get_ports {IO_B34_LN[2]}] +set_property PACKAGE_PIN U13 [get_ports {IO_B34_LP[3]}] +set_property PACKAGE_PIN V13 [get_ports {IO_B34_LN[3]}] +set_property PACKAGE_PIN V12 [get_ports {IO_B34_LP[4]}] +set_property PACKAGE_PIN W13 [get_ports {IO_B34_LN[4]}] +set_property PACKAGE_PIN T14 [get_ports {IO_B34_LP[5]}] +set_property PACKAGE_PIN T15 [get_ports {IO_B34_LN[5]}] +set_property PACKAGE_PIN T16 [get_ports {LCD_DATA[0]}] +set_property PACKAGE_PIN U17 [get_ports {LCD_DATA[1]}] +set_property PACKAGE_PIN V15 [get_ports {LCD_DATA[2]}] +set_property PACKAGE_PIN W15 [get_ports {LCD_DATA[3]}] +set_property PACKAGE_PIN U18 [get_ports {LCD_DATA[4]}] +set_property PACKAGE_PIN U19 [get_ports {LCD_DATA[5]}] +set_property PACKAGE_PIN N18 [get_ports {LCD_DATA[6]}] +set_property PACKAGE_PIN P19 [get_ports {LCD_DATA[7]}] +set_property PACKAGE_PIN N20 [get_ports {LCD_DATA[8]}] +set_property PACKAGE_PIN P20 [get_ports {LCD_DATA[9]}] +set_property PACKAGE_PIN T20 [get_ports {LCD_DATA[10]}] +set_property PACKAGE_PIN U20 [get_ports {LCD_DATA[11]}] +set_property PACKAGE_PIN V20 [get_ports {LCD_DATA[12]}] +set_property PACKAGE_PIN W20 [get_ports {LCD_DATA[13]}] +set_property PACKAGE_PIN Y18 [get_ports {LCD_DATA[14]}] +set_property PACKAGE_PIN Y19 [get_ports {LCD_DATA[15]}] +set_property PACKAGE_PIN P18 [get_ports BP] +set_property PACKAGE_PIN P15 [get_ports iic_0_sda_io] +set_property PACKAGE_PIN P16 [get_ports iic_0_scl_io] +set_property IOSTANDARD LVCMOS33 [get_ports BP] +set_property IOSTANDARD LVCMOS33 [get_ports iic_0_scl_io] +set_property IOSTANDARD LVCMOS33 [get_ports iic_0_sda_io] +set_property PACKAGE_PIN N17 [get_ports MEMS_INTn] +set_property IOSTANDARD LVCMOS33 [get_ports MEMS_INTn] +set_property PACKAGE_PIN V16 [get_ports LCD_VSYNC] +set_property PACKAGE_PIN W16 [get_ports LCD_HSYNC] +set_property PACKAGE_PIN R16 [get_ports LCD_DE] +set_property PACKAGE_PIN R17 [get_ports LCD_PCLK] +set_property IOSTANDARD LVCMOS33 [get_ports LCD_PCLK] +set_property IOSTANDARD LVCMOS33 [get_ports LCD_HSYNC] +set_property IOSTANDARD LVCMOS33 [get_ports LCD_DE] +set_property IOSTANDARD LVCMOS33 [get_ports LCD_VSYNC] +set_property PACKAGE_PIN W18 [get_ports I2S_DIN] +set_property PACKAGE_PIN V18 [get_ports I2S_FSYNC_IN] +set_property IOSTANDARD LVCMOS33 [get_ports I2S_DIN] +set_property IOSTANDARD LVCMOS33 [get_ports I2S_FSYNC_IN] +set_property PACKAGE_PIN P14 [get_ports IO_B34_LP6] +set_property PACKAGE_PIN W14 [get_ports IO_B34_LP8] +set_property PACKAGE_PIN Y14 [get_ports IO_B34_LN8] +set_property PACKAGE_PIN U14 [get_ports IO_B34_LP11] +set_property PACKAGE_PIN U15 [get_ports IO_B34_LN11] +set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LP11] +set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LP8] +set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LN11] +set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LN8] +set_property IOSTANDARD LVCMOS33 [get_ports IO_B34_LP6] +set_property PACKAGE_PIN C20 [get_ports {IO_B35_LP[1]}] +set_property PACKAGE_PIN B20 [get_ports {IO_B35_LN[1]}] +set_property PACKAGE_PIN A20 [get_ports {IO_B35_LN[2]}] +set_property PACKAGE_PIN B19 [get_ports {IO_B35_LP[2]}] +set_property PACKAGE_PIN E17 [get_ports {IO_B35_LP[3]}] +set_property PACKAGE_PIN D18 [get_ports {IO_B35_LN[3]}] +set_property PACKAGE_PIN D19 [get_ports {IO_B35_LP[4]}] +set_property PACKAGE_PIN D20 [get_ports {IO_B35_LN[4]}] +set_property PACKAGE_PIN E18 [get_ports {IO_B35_LP[5]}] +set_property PACKAGE_PIN E19 [get_ports {IO_B35_LN[5]}] +set_property PACKAGE_PIN F16 [get_ports {IO_B35_LP[6]}] +set_property PACKAGE_PIN F17 [get_ports {IO_B35_LN[6]}] +set_property PACKAGE_PIN M19 [get_ports {IO_B35_LP[7]}] +set_property PACKAGE_PIN M20 [get_ports {IO_B35_LN[7]}] +set_property PACKAGE_PIN M17 [get_ports {IO_B35_LP[8]}] +set_property PACKAGE_PIN M18 [get_ports {IO_B35_LN[8]}] +set_property PACKAGE_PIN L19 [get_ports {IO_B35_LP[9]}] +set_property PACKAGE_PIN L20 [get_ports {IO_B35_LN[9]}] +set_property PACKAGE_PIN K19 [get_ports {IO_B35_LP[10]}] +set_property PACKAGE_PIN J19 [get_ports {IO_B35_LN[10]}] +set_property PACKAGE_PIN L16 [get_ports {IO_B35_LP[11]}] +set_property PACKAGE_PIN L17 [get_ports {IO_B35_LN[11]}] +set_property PACKAGE_PIN K17 [get_ports {IO_B35_LP[12]}] +set_property PACKAGE_PIN K18 [get_ports {IO_B35_LN[12]}] +set_property PACKAGE_PIN H16 [get_ports {IO_B35_LP[13]}] +set_property PACKAGE_PIN H17 [get_ports {IO_B35_LN[13]}] +set_property PACKAGE_PIN J18 [get_ports {IO_B35_LP[14]}] +set_property PACKAGE_PIN H18 [get_ports {IO_B35_LN[14]}] +set_property PACKAGE_PIN F19 [get_ports {IO_B35_LP[15]}] +set_property PACKAGE_PIN F20 [get_ports {IO_B35_LN[15]}] +set_property PACKAGE_PIN G17 [get_ports {IO_B35_LP[16]}] +set_property PACKAGE_PIN G18 [get_ports {IO_B35_LN[16]}] +set_property PACKAGE_PIN J20 [get_ports {IO_B35_LP[17]}] +set_property PACKAGE_PIN H20 [get_ports {IO_B35_LN[17]}] +set_property PACKAGE_PIN G19 [get_ports {IO_B35_LP[18]}] +set_property PACKAGE_PIN G20 [get_ports {IO_B35_LN[18]}] +set_property PACKAGE_PIN H15 [get_ports {IO_B35_LP[19]}] +set_property PACKAGE_PIN G15 [get_ports {IO_B35_LN[19]}] +set_property PACKAGE_PIN K14 [get_ports {IO_B35_LP[20]}] +set_property PACKAGE_PIN J14 [get_ports {IO_B35_LN[20]}] +set_property PACKAGE_PIN N15 [get_ports {IO_B35_LP[21]}] +set_property PACKAGE_PIN N16 [get_ports {IO_B35_LN[21]}] +set_property PACKAGE_PIN L14 [get_ports {IO_B35_LP[22]}] +set_property PACKAGE_PIN L15 [get_ports {IO_B35_LN[22]}] +set_property PACKAGE_PIN M14 [get_ports {IO_B35_LP[23]}] +set_property PACKAGE_PIN M15 [get_ports {IO_B35_LN[23]}] +set_property PACKAGE_PIN K16 [get_ports {IO_B35_LP[24]}] +set_property PACKAGE_PIN J16 [get_ports {IO_B35_LN[24]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports HDMI_INTn] +set_property PACKAGE_PIN W19 [get_ports HDMI_INTn] +set_property IOSTANDARD LVCMOS33 [get_ports I2S_FSYNC_OUT] +set_property IOSTANDARD LVCMOS33 [get_ports I2S_SCLK] +set_property IOSTANDARD LVCMOS33 [get_ports I2S_DOUT] +set_property PACKAGE_PIN V17 [get_ports I2S_DOUT] +set_property PACKAGE_PIN T17 [get_ports I2S_SCLK] +set_property PACKAGE_PIN R18 [get_ports I2S_FSYNC_OUT] +set_property PACKAGE_PIN R19 [get_ports {SW[0]}] +set_property PACKAGE_PIN T19 [get_ports {SW[1]}] +set_property PACKAGE_PIN G14 [get_ports {SW[2]}] +set_property PACKAGE_PIN J15 [get_ports {SW[3]}] +set_property PACKAGE_PIN Y16 [get_ports {LEDS[0]}] +set_property PACKAGE_PIN Y17 [get_ports {LEDS[1]}] +set_property PACKAGE_PIN R14 [get_ports {LEDS[2]}] + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn.hwdef b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn.hwdef new file mode 100644 index 0000000..bf6aff7 Binary files /dev/null and b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn.hwdef differ diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn.v new file mode 100644 index 0000000..d14a506 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn.v @@ -0,0 +1,2007 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +//Date : Wed Jul 15 11:10:09 2015 +//Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +//Command : generate_target z_turn.bd +//Design : z_turn +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module s00_couplers_imp_1N0XG9 + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arid, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arqos, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awid, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awqos, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rid, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wid, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arqos, + S_AXI_arready, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awqos, + S_AXI_awready, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wid, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input [0:0]M_ARESETN; + output M_AXI_araddr; + output M_AXI_arburst; + output M_AXI_arcache; + output M_AXI_arid; + output M_AXI_arlen; + output M_AXI_arlock; + output M_AXI_arprot; + output M_AXI_arqos; + input M_AXI_arready; + output M_AXI_arsize; + output M_AXI_arvalid; + output M_AXI_awaddr; + output M_AXI_awburst; + output M_AXI_awcache; + output M_AXI_awid; + output M_AXI_awlen; + output M_AXI_awlock; + output M_AXI_awprot; + output M_AXI_awqos; + input M_AXI_awready; + output M_AXI_awsize; + output M_AXI_awvalid; + input M_AXI_bid; + output M_AXI_bready; + input M_AXI_bresp; + input M_AXI_bvalid; + input M_AXI_rdata; + input M_AXI_rid; + input M_AXI_rlast; + output M_AXI_rready; + input M_AXI_rresp; + input M_AXI_rvalid; + output M_AXI_wdata; + output M_AXI_wid; + output M_AXI_wlast; + input M_AXI_wready; + output M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input [0:0]S_ARESETN; + input S_AXI_araddr; + input S_AXI_arburst; + input S_AXI_arcache; + input S_AXI_arid; + input S_AXI_arlen; + input S_AXI_arlock; + input S_AXI_arprot; + input S_AXI_arqos; + output S_AXI_arready; + input S_AXI_arsize; + input S_AXI_arvalid; + input S_AXI_awaddr; + input S_AXI_awburst; + input S_AXI_awcache; + input S_AXI_awid; + input S_AXI_awlen; + input S_AXI_awlock; + input S_AXI_awprot; + input S_AXI_awqos; + output S_AXI_awready; + input S_AXI_awsize; + input S_AXI_awvalid; + output S_AXI_bid; + input S_AXI_bready; + output S_AXI_bresp; + output S_AXI_bvalid; + output S_AXI_rdata; + output S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output S_AXI_rresp; + output S_AXI_rvalid; + input S_AXI_wdata; + input S_AXI_wid; + input S_AXI_wlast; + output S_AXI_wready; + input S_AXI_wstrb; + input S_AXI_wvalid; + + wire s00_couplers_to_s00_couplers_ARADDR; + wire s00_couplers_to_s00_couplers_ARBURST; + wire s00_couplers_to_s00_couplers_ARCACHE; + wire s00_couplers_to_s00_couplers_ARID; + wire s00_couplers_to_s00_couplers_ARLEN; + wire s00_couplers_to_s00_couplers_ARLOCK; + wire s00_couplers_to_s00_couplers_ARPROT; + wire s00_couplers_to_s00_couplers_ARQOS; + wire s00_couplers_to_s00_couplers_ARREADY; + wire s00_couplers_to_s00_couplers_ARSIZE; + wire s00_couplers_to_s00_couplers_ARVALID; + wire s00_couplers_to_s00_couplers_AWADDR; + wire s00_couplers_to_s00_couplers_AWBURST; + wire s00_couplers_to_s00_couplers_AWCACHE; + wire s00_couplers_to_s00_couplers_AWID; + wire s00_couplers_to_s00_couplers_AWLEN; + wire s00_couplers_to_s00_couplers_AWLOCK; + wire s00_couplers_to_s00_couplers_AWPROT; + wire s00_couplers_to_s00_couplers_AWQOS; + wire s00_couplers_to_s00_couplers_AWREADY; + wire s00_couplers_to_s00_couplers_AWSIZE; + wire s00_couplers_to_s00_couplers_AWVALID; + wire s00_couplers_to_s00_couplers_BID; + wire s00_couplers_to_s00_couplers_BREADY; + wire s00_couplers_to_s00_couplers_BRESP; + wire s00_couplers_to_s00_couplers_BVALID; + wire s00_couplers_to_s00_couplers_RDATA; + wire s00_couplers_to_s00_couplers_RID; + wire s00_couplers_to_s00_couplers_RLAST; + wire s00_couplers_to_s00_couplers_RREADY; + wire s00_couplers_to_s00_couplers_RRESP; + wire s00_couplers_to_s00_couplers_RVALID; + wire s00_couplers_to_s00_couplers_WDATA; + wire s00_couplers_to_s00_couplers_WID; + wire s00_couplers_to_s00_couplers_WLAST; + wire s00_couplers_to_s00_couplers_WREADY; + wire s00_couplers_to_s00_couplers_WSTRB; + wire s00_couplers_to_s00_couplers_WVALID; + + assign M_AXI_araddr = s00_couplers_to_s00_couplers_ARADDR; + assign M_AXI_arburst = s00_couplers_to_s00_couplers_ARBURST; + assign M_AXI_arcache = s00_couplers_to_s00_couplers_ARCACHE; + assign M_AXI_arid = s00_couplers_to_s00_couplers_ARID; + assign M_AXI_arlen = s00_couplers_to_s00_couplers_ARLEN; + assign M_AXI_arlock = s00_couplers_to_s00_couplers_ARLOCK; + assign M_AXI_arprot = s00_couplers_to_s00_couplers_ARPROT; + assign M_AXI_arqos = s00_couplers_to_s00_couplers_ARQOS; + assign M_AXI_arsize = s00_couplers_to_s00_couplers_ARSIZE; + assign M_AXI_arvalid = s00_couplers_to_s00_couplers_ARVALID; + assign M_AXI_awaddr = s00_couplers_to_s00_couplers_AWADDR; + assign M_AXI_awburst = s00_couplers_to_s00_couplers_AWBURST; + assign M_AXI_awcache = s00_couplers_to_s00_couplers_AWCACHE; + assign M_AXI_awid = s00_couplers_to_s00_couplers_AWID; + assign M_AXI_awlen = s00_couplers_to_s00_couplers_AWLEN; + assign M_AXI_awlock = s00_couplers_to_s00_couplers_AWLOCK; + assign M_AXI_awprot = s00_couplers_to_s00_couplers_AWPROT; + assign M_AXI_awqos = s00_couplers_to_s00_couplers_AWQOS; + assign M_AXI_awsize = s00_couplers_to_s00_couplers_AWSIZE; + assign M_AXI_awvalid = s00_couplers_to_s00_couplers_AWVALID; + assign M_AXI_bready = s00_couplers_to_s00_couplers_BREADY; + assign M_AXI_rready = s00_couplers_to_s00_couplers_RREADY; + assign M_AXI_wdata = s00_couplers_to_s00_couplers_WDATA; + assign M_AXI_wid = s00_couplers_to_s00_couplers_WID; + assign M_AXI_wlast = s00_couplers_to_s00_couplers_WLAST; + assign M_AXI_wstrb = s00_couplers_to_s00_couplers_WSTRB; + assign M_AXI_wvalid = s00_couplers_to_s00_couplers_WVALID; + assign S_AXI_arready = s00_couplers_to_s00_couplers_ARREADY; + assign S_AXI_awready = s00_couplers_to_s00_couplers_AWREADY; + assign S_AXI_bid = s00_couplers_to_s00_couplers_BID; + assign S_AXI_bresp = s00_couplers_to_s00_couplers_BRESP; + assign S_AXI_bvalid = s00_couplers_to_s00_couplers_BVALID; + assign S_AXI_rdata = s00_couplers_to_s00_couplers_RDATA; + assign S_AXI_rid = s00_couplers_to_s00_couplers_RID; + assign S_AXI_rlast = s00_couplers_to_s00_couplers_RLAST; + assign S_AXI_rresp = s00_couplers_to_s00_couplers_RRESP; + assign S_AXI_rvalid = s00_couplers_to_s00_couplers_RVALID; + assign S_AXI_wready = s00_couplers_to_s00_couplers_WREADY; + assign s00_couplers_to_s00_couplers_ARADDR = S_AXI_araddr; + assign s00_couplers_to_s00_couplers_ARBURST = S_AXI_arburst; + assign s00_couplers_to_s00_couplers_ARCACHE = S_AXI_arcache; + assign s00_couplers_to_s00_couplers_ARID = S_AXI_arid; + assign s00_couplers_to_s00_couplers_ARLEN = S_AXI_arlen; + assign s00_couplers_to_s00_couplers_ARLOCK = S_AXI_arlock; + assign s00_couplers_to_s00_couplers_ARPROT = S_AXI_arprot; + assign s00_couplers_to_s00_couplers_ARQOS = S_AXI_arqos; + assign s00_couplers_to_s00_couplers_ARREADY = M_AXI_arready; + assign s00_couplers_to_s00_couplers_ARSIZE = S_AXI_arsize; + assign s00_couplers_to_s00_couplers_ARVALID = S_AXI_arvalid; + assign s00_couplers_to_s00_couplers_AWADDR = S_AXI_awaddr; + assign s00_couplers_to_s00_couplers_AWBURST = S_AXI_awburst; + assign s00_couplers_to_s00_couplers_AWCACHE = S_AXI_awcache; + assign s00_couplers_to_s00_couplers_AWID = S_AXI_awid; + assign s00_couplers_to_s00_couplers_AWLEN = S_AXI_awlen; + assign s00_couplers_to_s00_couplers_AWLOCK = S_AXI_awlock; + assign s00_couplers_to_s00_couplers_AWPROT = S_AXI_awprot; + assign s00_couplers_to_s00_couplers_AWQOS = S_AXI_awqos; + assign s00_couplers_to_s00_couplers_AWREADY = M_AXI_awready; + assign s00_couplers_to_s00_couplers_AWSIZE = S_AXI_awsize; + assign s00_couplers_to_s00_couplers_AWVALID = S_AXI_awvalid; + assign s00_couplers_to_s00_couplers_BID = M_AXI_bid; + assign s00_couplers_to_s00_couplers_BREADY = S_AXI_bready; + assign s00_couplers_to_s00_couplers_BRESP = M_AXI_bresp; + assign s00_couplers_to_s00_couplers_BVALID = M_AXI_bvalid; + assign s00_couplers_to_s00_couplers_RDATA = M_AXI_rdata; + assign s00_couplers_to_s00_couplers_RID = M_AXI_rid; + assign s00_couplers_to_s00_couplers_RLAST = M_AXI_rlast; + assign s00_couplers_to_s00_couplers_RREADY = S_AXI_rready; + assign s00_couplers_to_s00_couplers_RRESP = M_AXI_rresp; + assign s00_couplers_to_s00_couplers_RVALID = M_AXI_rvalid; + assign s00_couplers_to_s00_couplers_WDATA = S_AXI_wdata; + assign s00_couplers_to_s00_couplers_WID = S_AXI_wid; + assign s00_couplers_to_s00_couplers_WLAST = S_AXI_wlast; + assign s00_couplers_to_s00_couplers_WREADY = M_AXI_wready; + assign s00_couplers_to_s00_couplers_WSTRB = S_AXI_wstrb; + assign s00_couplers_to_s00_couplers_WVALID = S_AXI_wvalid; +endmodule + +module s00_couplers_imp_QSJACF + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arid, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arqos, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awid, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awqos, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rid, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wid, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arqos, + S_AXI_arready, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awqos, + S_AXI_awready, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wid, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input [0:0]M_ARESETN; + output M_AXI_araddr; + output M_AXI_arburst; + output M_AXI_arcache; + output M_AXI_arid; + output M_AXI_arlen; + output M_AXI_arlock; + output M_AXI_arprot; + output M_AXI_arqos; + input M_AXI_arready; + output M_AXI_arsize; + output M_AXI_arvalid; + output M_AXI_awaddr; + output M_AXI_awburst; + output M_AXI_awcache; + output M_AXI_awid; + output M_AXI_awlen; + output M_AXI_awlock; + output M_AXI_awprot; + output M_AXI_awqos; + input M_AXI_awready; + output M_AXI_awsize; + output M_AXI_awvalid; + input M_AXI_bid; + output M_AXI_bready; + input M_AXI_bresp; + input M_AXI_bvalid; + input M_AXI_rdata; + input M_AXI_rid; + input M_AXI_rlast; + output M_AXI_rready; + input M_AXI_rresp; + input M_AXI_rvalid; + output M_AXI_wdata; + output M_AXI_wid; + output M_AXI_wlast; + input M_AXI_wready; + output M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input [0:0]S_ARESETN; + input S_AXI_araddr; + input S_AXI_arburst; + input S_AXI_arcache; + input S_AXI_arid; + input S_AXI_arlen; + input S_AXI_arlock; + input S_AXI_arprot; + input S_AXI_arqos; + output S_AXI_arready; + input S_AXI_arsize; + input S_AXI_arvalid; + input S_AXI_awaddr; + input S_AXI_awburst; + input S_AXI_awcache; + input S_AXI_awid; + input S_AXI_awlen; + input S_AXI_awlock; + input S_AXI_awprot; + input S_AXI_awqos; + output S_AXI_awready; + input S_AXI_awsize; + input S_AXI_awvalid; + output S_AXI_bid; + input S_AXI_bready; + output S_AXI_bresp; + output S_AXI_bvalid; + output S_AXI_rdata; + output S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output S_AXI_rresp; + output S_AXI_rvalid; + input S_AXI_wdata; + input S_AXI_wid; + input S_AXI_wlast; + output S_AXI_wready; + input S_AXI_wstrb; + input S_AXI_wvalid; + + wire s00_couplers_to_s00_couplers_ARADDR; + wire s00_couplers_to_s00_couplers_ARBURST; + wire s00_couplers_to_s00_couplers_ARCACHE; + wire s00_couplers_to_s00_couplers_ARID; + wire s00_couplers_to_s00_couplers_ARLEN; + wire s00_couplers_to_s00_couplers_ARLOCK; + wire s00_couplers_to_s00_couplers_ARPROT; + wire s00_couplers_to_s00_couplers_ARQOS; + wire s00_couplers_to_s00_couplers_ARREADY; + wire s00_couplers_to_s00_couplers_ARSIZE; + wire s00_couplers_to_s00_couplers_ARVALID; + wire s00_couplers_to_s00_couplers_AWADDR; + wire s00_couplers_to_s00_couplers_AWBURST; + wire s00_couplers_to_s00_couplers_AWCACHE; + wire s00_couplers_to_s00_couplers_AWID; + wire s00_couplers_to_s00_couplers_AWLEN; + wire s00_couplers_to_s00_couplers_AWLOCK; + wire s00_couplers_to_s00_couplers_AWPROT; + wire s00_couplers_to_s00_couplers_AWQOS; + wire s00_couplers_to_s00_couplers_AWREADY; + wire s00_couplers_to_s00_couplers_AWSIZE; + wire s00_couplers_to_s00_couplers_AWVALID; + wire s00_couplers_to_s00_couplers_BID; + wire s00_couplers_to_s00_couplers_BREADY; + wire s00_couplers_to_s00_couplers_BRESP; + wire s00_couplers_to_s00_couplers_BVALID; + wire s00_couplers_to_s00_couplers_RDATA; + wire s00_couplers_to_s00_couplers_RID; + wire s00_couplers_to_s00_couplers_RLAST; + wire s00_couplers_to_s00_couplers_RREADY; + wire s00_couplers_to_s00_couplers_RRESP; + wire s00_couplers_to_s00_couplers_RVALID; + wire s00_couplers_to_s00_couplers_WDATA; + wire s00_couplers_to_s00_couplers_WID; + wire s00_couplers_to_s00_couplers_WLAST; + wire s00_couplers_to_s00_couplers_WREADY; + wire s00_couplers_to_s00_couplers_WSTRB; + wire s00_couplers_to_s00_couplers_WVALID; + + assign M_AXI_araddr = s00_couplers_to_s00_couplers_ARADDR; + assign M_AXI_arburst = s00_couplers_to_s00_couplers_ARBURST; + assign M_AXI_arcache = s00_couplers_to_s00_couplers_ARCACHE; + assign M_AXI_arid = s00_couplers_to_s00_couplers_ARID; + assign M_AXI_arlen = s00_couplers_to_s00_couplers_ARLEN; + assign M_AXI_arlock = s00_couplers_to_s00_couplers_ARLOCK; + assign M_AXI_arprot = s00_couplers_to_s00_couplers_ARPROT; + assign M_AXI_arqos = s00_couplers_to_s00_couplers_ARQOS; + assign M_AXI_arsize = s00_couplers_to_s00_couplers_ARSIZE; + assign M_AXI_arvalid = s00_couplers_to_s00_couplers_ARVALID; + assign M_AXI_awaddr = s00_couplers_to_s00_couplers_AWADDR; + assign M_AXI_awburst = s00_couplers_to_s00_couplers_AWBURST; + assign M_AXI_awcache = s00_couplers_to_s00_couplers_AWCACHE; + assign M_AXI_awid = s00_couplers_to_s00_couplers_AWID; + assign M_AXI_awlen = s00_couplers_to_s00_couplers_AWLEN; + assign M_AXI_awlock = s00_couplers_to_s00_couplers_AWLOCK; + assign M_AXI_awprot = s00_couplers_to_s00_couplers_AWPROT; + assign M_AXI_awqos = s00_couplers_to_s00_couplers_AWQOS; + assign M_AXI_awsize = s00_couplers_to_s00_couplers_AWSIZE; + assign M_AXI_awvalid = s00_couplers_to_s00_couplers_AWVALID; + assign M_AXI_bready = s00_couplers_to_s00_couplers_BREADY; + assign M_AXI_rready = s00_couplers_to_s00_couplers_RREADY; + assign M_AXI_wdata = s00_couplers_to_s00_couplers_WDATA; + assign M_AXI_wid = s00_couplers_to_s00_couplers_WID; + assign M_AXI_wlast = s00_couplers_to_s00_couplers_WLAST; + assign M_AXI_wstrb = s00_couplers_to_s00_couplers_WSTRB; + assign M_AXI_wvalid = s00_couplers_to_s00_couplers_WVALID; + assign S_AXI_arready = s00_couplers_to_s00_couplers_ARREADY; + assign S_AXI_awready = s00_couplers_to_s00_couplers_AWREADY; + assign S_AXI_bid = s00_couplers_to_s00_couplers_BID; + assign S_AXI_bresp = s00_couplers_to_s00_couplers_BRESP; + assign S_AXI_bvalid = s00_couplers_to_s00_couplers_BVALID; + assign S_AXI_rdata = s00_couplers_to_s00_couplers_RDATA; + assign S_AXI_rid = s00_couplers_to_s00_couplers_RID; + assign S_AXI_rlast = s00_couplers_to_s00_couplers_RLAST; + assign S_AXI_rresp = s00_couplers_to_s00_couplers_RRESP; + assign S_AXI_rvalid = s00_couplers_to_s00_couplers_RVALID; + assign S_AXI_wready = s00_couplers_to_s00_couplers_WREADY; + assign s00_couplers_to_s00_couplers_ARADDR = S_AXI_araddr; + assign s00_couplers_to_s00_couplers_ARBURST = S_AXI_arburst; + assign s00_couplers_to_s00_couplers_ARCACHE = S_AXI_arcache; + assign s00_couplers_to_s00_couplers_ARID = S_AXI_arid; + assign s00_couplers_to_s00_couplers_ARLEN = S_AXI_arlen; + assign s00_couplers_to_s00_couplers_ARLOCK = S_AXI_arlock; + assign s00_couplers_to_s00_couplers_ARPROT = S_AXI_arprot; + assign s00_couplers_to_s00_couplers_ARQOS = S_AXI_arqos; + assign s00_couplers_to_s00_couplers_ARREADY = M_AXI_arready; + assign s00_couplers_to_s00_couplers_ARSIZE = S_AXI_arsize; + assign s00_couplers_to_s00_couplers_ARVALID = S_AXI_arvalid; + assign s00_couplers_to_s00_couplers_AWADDR = S_AXI_awaddr; + assign s00_couplers_to_s00_couplers_AWBURST = S_AXI_awburst; + assign s00_couplers_to_s00_couplers_AWCACHE = S_AXI_awcache; + assign s00_couplers_to_s00_couplers_AWID = S_AXI_awid; + assign s00_couplers_to_s00_couplers_AWLEN = S_AXI_awlen; + assign s00_couplers_to_s00_couplers_AWLOCK = S_AXI_awlock; + assign s00_couplers_to_s00_couplers_AWPROT = S_AXI_awprot; + assign s00_couplers_to_s00_couplers_AWQOS = S_AXI_awqos; + assign s00_couplers_to_s00_couplers_AWREADY = M_AXI_awready; + assign s00_couplers_to_s00_couplers_AWSIZE = S_AXI_awsize; + assign s00_couplers_to_s00_couplers_AWVALID = S_AXI_awvalid; + assign s00_couplers_to_s00_couplers_BID = M_AXI_bid; + assign s00_couplers_to_s00_couplers_BREADY = S_AXI_bready; + assign s00_couplers_to_s00_couplers_BRESP = M_AXI_bresp; + assign s00_couplers_to_s00_couplers_BVALID = M_AXI_bvalid; + assign s00_couplers_to_s00_couplers_RDATA = M_AXI_rdata; + assign s00_couplers_to_s00_couplers_RID = M_AXI_rid; + assign s00_couplers_to_s00_couplers_RLAST = M_AXI_rlast; + assign s00_couplers_to_s00_couplers_RREADY = S_AXI_rready; + assign s00_couplers_to_s00_couplers_RRESP = M_AXI_rresp; + assign s00_couplers_to_s00_couplers_RVALID = M_AXI_rvalid; + assign s00_couplers_to_s00_couplers_WDATA = S_AXI_wdata; + assign s00_couplers_to_s00_couplers_WID = S_AXI_wid; + assign s00_couplers_to_s00_couplers_WLAST = S_AXI_wlast; + assign s00_couplers_to_s00_couplers_WREADY = M_AXI_wready; + assign s00_couplers_to_s00_couplers_WSTRB = S_AXI_wstrb; + assign s00_couplers_to_s00_couplers_WVALID = S_AXI_wvalid; +endmodule + +(* CORE_GENERATION_INFO = "z_turn,IP_Integrator,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=z_turn,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=16,numReposBlks=12,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=0,da_axi4_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "z_turn.hwdef" *) +module z_turn + (BP, + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + HDMI_INTn, + I2S_DIN, + I2S_DOUT, + I2S_FSYNC_IN, + I2S_FSYNC_OUT, + I2S_SCLK, + IIC_0_scl_i, + IIC_0_scl_o, + IIC_0_scl_t, + IIC_0_sda_i, + IIC_0_sda_o, + IIC_0_sda_t, + IO_B34_LN, + IO_B34_LN11, + IO_B34_LN8, + IO_B34_LP, + IO_B34_LP11, + IO_B34_LP6, + IO_B34_LP8, + IO_B35_LN, + IO_B35_LP, + LCD_DATA, + LCD_DE, + LCD_HSYNC, + LCD_PCLK, + LCD_VSYNC, + LEDS, + MEMS_INTn, + SW); + output BP; + inout [14:0]DDR_addr; + inout [2:0]DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [3:0]DDR_dm; + inout [31:0]DDR_dq; + inout [3:0]DDR_dqs_n; + inout [3:0]DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0]FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + input HDMI_INTn; + input I2S_DIN; + output I2S_DOUT; + input I2S_FSYNC_IN; + output I2S_FSYNC_OUT; + output I2S_SCLK; + input IIC_0_scl_i; + output IIC_0_scl_o; + output IIC_0_scl_t; + input IIC_0_sda_i; + output IIC_0_sda_o; + output IIC_0_sda_t; + input [5:1]IO_B34_LN; + input IO_B34_LN11; + input IO_B34_LN8; + input [5:1]IO_B34_LP; + input IO_B34_LP11; + input IO_B34_LP6; + input IO_B34_LP8; + input [24:1]IO_B35_LN; + input [24:1]IO_B35_LP; + output [15:0]LCD_DATA; + output LCD_DE; + output LCD_HSYNC; + output LCD_PCLK; + output LCD_VSYNC; + output [2:0]LEDS; + input MEMS_INTn; + input [3:0]SW; + + wire GND_1; + wire HDMI_INTn_1; + wire MEMS_INTn_1; + wire [3:0]SW_1; + wire VCC_1; + wire io2axis_M00_AXI_ARADDR; + wire io2axis_M00_AXI_ARBURST; + wire io2axis_M00_AXI_ARCACHE; + wire io2axis_M00_AXI_ARID; + wire io2axis_M00_AXI_ARLEN; + wire io2axis_M00_AXI_ARLOCK; + wire io2axis_M00_AXI_ARPROT; + wire io2axis_M00_AXI_ARQOS; + wire io2axis_M00_AXI_ARREADY; + wire io2axis_M00_AXI_ARSIZE; + wire io2axis_M00_AXI_ARVALID; + wire io2axis_M00_AXI_AWADDR; + wire io2axis_M00_AXI_AWBURST; + wire io2axis_M00_AXI_AWCACHE; + wire io2axis_M00_AXI_AWID; + wire io2axis_M00_AXI_AWLEN; + wire io2axis_M00_AXI_AWLOCK; + wire io2axis_M00_AXI_AWPROT; + wire io2axis_M00_AXI_AWQOS; + wire io2axis_M00_AXI_AWREADY; + wire io2axis_M00_AXI_AWSIZE; + wire io2axis_M00_AXI_AWVALID; + wire [5:0]io2axis_M00_AXI_BID; + wire io2axis_M00_AXI_BREADY; + wire [1:0]io2axis_M00_AXI_BRESP; + wire io2axis_M00_AXI_BVALID; + wire [63:0]io2axis_M00_AXI_RDATA; + wire [5:0]io2axis_M00_AXI_RID; + wire io2axis_M00_AXI_RLAST; + wire io2axis_M00_AXI_RREADY; + wire [1:0]io2axis_M00_AXI_RRESP; + wire io2axis_M00_AXI_RVALID; + wire io2axis_M00_AXI_WDATA; + wire io2axis_M00_AXI_WID; + wire io2axis_M00_AXI_WLAST; + wire io2axis_M00_AXI_WREADY; + wire io2axis_M00_AXI_WSTRB; + wire io2axis_M00_AXI_WVALID; + wire [0:0]proc_sys_reset2_interconnect_aresetn; + wire [0:0]proc_sys_reset2_peripheral_aresetn; + wire ps7_IIC_0_SCL_I; + wire ps7_IIC_0_SCL_O; + wire ps7_IIC_0_SCL_T; + wire ps7_IIC_0_SDA_I; + wire ps7_IIC_0_SDA_O; + wire ps7_IIC_0_SDA_T; + wire [14:0]ps_7_DDR_ADDR; + wire [2:0]ps_7_DDR_BA; + wire ps_7_DDR_CAS_N; + wire ps_7_DDR_CKE; + wire ps_7_DDR_CK_N; + wire ps_7_DDR_CK_P; + wire ps_7_DDR_CS_N; + wire [3:0]ps_7_DDR_DM; + wire [31:0]ps_7_DDR_DQ; + wire [3:0]ps_7_DDR_DQS_N; + wire [3:0]ps_7_DDR_DQS_P; + wire ps_7_DDR_ODT; + wire ps_7_DDR_RAS_N; + wire ps_7_DDR_RESET_N; + wire ps_7_DDR_WE_N; + wire ps_7_FCLK_CLK0; + wire ps_7_FCLK_CLK1; + wire ps_7_FCLK_CLK2; + wire ps_7_FCLK_CLK3; + wire ps_7_FCLK_RESET0_N; + wire ps_7_FCLK_RESET1_N; + wire ps_7_FCLK_RESET2_N; + wire ps_7_FCLK_RESET3_N; + wire ps_7_FIXED_IO_DDR_VRN; + wire ps_7_FIXED_IO_DDR_VRP; + wire [53:0]ps_7_FIXED_IO_MIO; + wire ps_7_FIXED_IO_PS_CLK; + wire ps_7_FIXED_IO_PS_PORB; + wire ps_7_FIXED_IO_PS_SRSTB; + wire [31:0]ps_7_M_AXI_GP0_ARADDR; + wire [1:0]ps_7_M_AXI_GP0_ARBURST; + wire [3:0]ps_7_M_AXI_GP0_ARCACHE; + wire [11:0]ps_7_M_AXI_GP0_ARID; + wire [3:0]ps_7_M_AXI_GP0_ARLEN; + wire [1:0]ps_7_M_AXI_GP0_ARLOCK; + wire [2:0]ps_7_M_AXI_GP0_ARPROT; + wire [3:0]ps_7_M_AXI_GP0_ARQOS; + wire ps_7_M_AXI_GP0_ARREADY; + wire [2:0]ps_7_M_AXI_GP0_ARSIZE; + wire ps_7_M_AXI_GP0_ARVALID; + wire [31:0]ps_7_M_AXI_GP0_AWADDR; + wire [1:0]ps_7_M_AXI_GP0_AWBURST; + wire [3:0]ps_7_M_AXI_GP0_AWCACHE; + wire [11:0]ps_7_M_AXI_GP0_AWID; + wire [3:0]ps_7_M_AXI_GP0_AWLEN; + wire [1:0]ps_7_M_AXI_GP0_AWLOCK; + wire [2:0]ps_7_M_AXI_GP0_AWPROT; + wire [3:0]ps_7_M_AXI_GP0_AWQOS; + wire ps_7_M_AXI_GP0_AWREADY; + wire [2:0]ps_7_M_AXI_GP0_AWSIZE; + wire ps_7_M_AXI_GP0_AWVALID; + wire ps_7_M_AXI_GP0_BID; + wire ps_7_M_AXI_GP0_BREADY; + wire ps_7_M_AXI_GP0_BRESP; + wire ps_7_M_AXI_GP0_BVALID; + wire ps_7_M_AXI_GP0_RDATA; + wire ps_7_M_AXI_GP0_RID; + wire ps_7_M_AXI_GP0_RLAST; + wire ps_7_M_AXI_GP0_RREADY; + wire ps_7_M_AXI_GP0_RRESP; + wire ps_7_M_AXI_GP0_RVALID; + wire [31:0]ps_7_M_AXI_GP0_WDATA; + wire [11:0]ps_7_M_AXI_GP0_WID; + wire ps_7_M_AXI_GP0_WLAST; + wire ps_7_M_AXI_GP0_WREADY; + wire [3:0]ps_7_M_AXI_GP0_WSTRB; + wire ps_7_M_AXI_GP0_WVALID; + wire [0:0]rst_ps_7_166M_interconnect_aresetn; + wire [0:0]rst_ps_7_166M_peripheral_aresetn; + wire [0:0]util_vector_logic_0_Res; + wire [0:0]util_vector_logic_1_Res; + wire [0:0]util_vector_logic_2_Res; + wire [15:0]xlconcat_0_dout; + wire [63:0]xlconcat_0_dout1; + wire [31:0]xlconcat_1_dout; + wire [31:0]xlconcat_2_dout; + + assign HDMI_INTn_1 = HDMI_INTn; + assign IIC_0_scl_o = ps7_IIC_0_SCL_O; + assign IIC_0_scl_t = ps7_IIC_0_SCL_T; + assign IIC_0_sda_o = ps7_IIC_0_SDA_O; + assign IIC_0_sda_t = ps7_IIC_0_SDA_T; + assign MEMS_INTn_1 = MEMS_INTn; + assign SW_1 = SW[3:0]; + assign ps7_IIC_0_SCL_I = IIC_0_scl_i; + assign ps7_IIC_0_SDA_I = IIC_0_sda_i; + GND GND + (.G(GND_1)); + VCC VCC + (.P(VCC_1)); + z_turn_proc_sys_reset_3_0 proc_sys_reset_0 + (.aux_reset_in(VCC_1), + .dcm_locked(VCC_1), + .ext_reset_in(ps_7_FCLK_RESET0_N), + .mb_debug_sys_rst(GND_1), + .slowest_sync_clk(ps_7_FCLK_CLK1)); + z_turn_rst_ps_7_166M_0 proc_sys_reset_1 + (.aux_reset_in(VCC_1), + .dcm_locked(VCC_1), + .ext_reset_in(ps_7_FCLK_RESET1_N), + .interconnect_aresetn(rst_ps_7_166M_interconnect_aresetn), + .mb_debug_sys_rst(GND_1), + .peripheral_aresetn(rst_ps_7_166M_peripheral_aresetn), + .slowest_sync_clk(ps_7_FCLK_CLK0)); + z_turn_proc_sys_reset1_0 proc_sys_reset_2 + (.aux_reset_in(VCC_1), + .dcm_locked(VCC_1), + .ext_reset_in(ps_7_FCLK_RESET2_N), + .interconnect_aresetn(proc_sys_reset2_interconnect_aresetn), + .mb_debug_sys_rst(GND_1), + .peripheral_aresetn(proc_sys_reset2_peripheral_aresetn), + .slowest_sync_clk(ps_7_FCLK_CLK2)); + z_turn_proc_sys_reset_1_0 proc_sys_reset_3 + (.aux_reset_in(VCC_1), + .dcm_locked(VCC_1), + .ext_reset_in(ps_7_FCLK_RESET3_N), + .mb_debug_sys_rst(GND_1), + .slowest_sync_clk(ps_7_FCLK_CLK3)); + z_turn_processing_system7_0_0 ps7 + (.DDR_Addr(DDR_addr[14:0]), + .DDR_BankAddr(DDR_ba[2:0]), + .DDR_CAS_n(DDR_cas_n), + .DDR_CKE(DDR_cke), + .DDR_CS_n(DDR_cs_n), + .DDR_Clk(DDR_ck_p), + .DDR_Clk_n(DDR_ck_n), + .DDR_DM(DDR_dm[3:0]), + .DDR_DQ(DDR_dq[31:0]), + .DDR_DQS(DDR_dqs_p[3:0]), + .DDR_DQS_n(DDR_dqs_n[3:0]), + .DDR_DRSTB(DDR_reset_n), + .DDR_ODT(DDR_odt), + .DDR_RAS_n(DDR_ras_n), + .DDR_VRN(FIXED_IO_ddr_vrn), + .DDR_VRP(FIXED_IO_ddr_vrp), + .DDR_WEB(DDR_we_n), + .FCLK_CLK0(ps_7_FCLK_CLK1), + .FCLK_CLK1(ps_7_FCLK_CLK0), + .FCLK_CLK2(ps_7_FCLK_CLK2), + .FCLK_CLK3(ps_7_FCLK_CLK3), + .FCLK_RESET0_N(ps_7_FCLK_RESET0_N), + .FCLK_RESET1_N(ps_7_FCLK_RESET1_N), + .FCLK_RESET2_N(ps_7_FCLK_RESET2_N), + .FCLK_RESET3_N(ps_7_FCLK_RESET3_N), + .GPIO_I(xlconcat_0_dout1), + .I2C0_SCL_I(ps7_IIC_0_SCL_I), + .I2C0_SCL_O(ps7_IIC_0_SCL_O), + .I2C0_SCL_T(ps7_IIC_0_SCL_T), + .I2C0_SDA_I(ps7_IIC_0_SDA_I), + .I2C0_SDA_O(ps7_IIC_0_SDA_O), + .I2C0_SDA_T(ps7_IIC_0_SDA_T), + .IRQ_F2P(xlconcat_0_dout), + .MIO(FIXED_IO_mio[53:0]), + .M_AXI_GP0_ACLK(ps_7_FCLK_CLK0), + .M_AXI_GP0_ARADDR(ps_7_M_AXI_GP0_ARADDR), + .M_AXI_GP0_ARBURST(ps_7_M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARCACHE(ps_7_M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARID(ps_7_M_AXI_GP0_ARID), + .M_AXI_GP0_ARLEN(ps_7_M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARLOCK(ps_7_M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARPROT(ps_7_M_AXI_GP0_ARPROT), + .M_AXI_GP0_ARQOS(ps_7_M_AXI_GP0_ARQOS), + .M_AXI_GP0_ARREADY(ps_7_M_AXI_GP0_ARREADY), + .M_AXI_GP0_ARSIZE(ps_7_M_AXI_GP0_ARSIZE), + .M_AXI_GP0_ARVALID(ps_7_M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWADDR(ps_7_M_AXI_GP0_AWADDR), + .M_AXI_GP0_AWBURST(ps_7_M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWCACHE(ps_7_M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWID(ps_7_M_AXI_GP0_AWID), + .M_AXI_GP0_AWLEN(ps_7_M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWLOCK(ps_7_M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWPROT(ps_7_M_AXI_GP0_AWPROT), + .M_AXI_GP0_AWQOS(ps_7_M_AXI_GP0_AWQOS), + .M_AXI_GP0_AWREADY(ps_7_M_AXI_GP0_AWREADY), + .M_AXI_GP0_AWSIZE(ps_7_M_AXI_GP0_AWSIZE), + .M_AXI_GP0_AWVALID(ps_7_M_AXI_GP0_AWVALID), + .M_AXI_GP0_BID({ps_7_M_AXI_GP0_BID,ps_7_M_AXI_GP0_BID,ps_7_M_AXI_GP0_BID,ps_7_M_AXI_GP0_BID,ps_7_M_AXI_GP0_BID,ps_7_M_AXI_GP0_BID,ps_7_M_AXI_GP0_BID,ps_7_M_AXI_GP0_BID,ps_7_M_AXI_GP0_BID,ps_7_M_AXI_GP0_BID,ps_7_M_AXI_GP0_BID,ps_7_M_AXI_GP0_BID}), + .M_AXI_GP0_BREADY(ps_7_M_AXI_GP0_BREADY), + .M_AXI_GP0_BRESP({ps_7_M_AXI_GP0_BRESP,ps_7_M_AXI_GP0_BRESP}), + .M_AXI_GP0_BVALID(ps_7_M_AXI_GP0_BVALID), + .M_AXI_GP0_RDATA({ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA,ps_7_M_AXI_GP0_RDATA}), + .M_AXI_GP0_RID({ps_7_M_AXI_GP0_RID,ps_7_M_AXI_GP0_RID,ps_7_M_AXI_GP0_RID,ps_7_M_AXI_GP0_RID,ps_7_M_AXI_GP0_RID,ps_7_M_AXI_GP0_RID,ps_7_M_AXI_GP0_RID,ps_7_M_AXI_GP0_RID,ps_7_M_AXI_GP0_RID,ps_7_M_AXI_GP0_RID,ps_7_M_AXI_GP0_RID,ps_7_M_AXI_GP0_RID}), + .M_AXI_GP0_RLAST(ps_7_M_AXI_GP0_RLAST), + .M_AXI_GP0_RREADY(ps_7_M_AXI_GP0_RREADY), + .M_AXI_GP0_RRESP({ps_7_M_AXI_GP0_RRESP,ps_7_M_AXI_GP0_RRESP}), + .M_AXI_GP0_RVALID(ps_7_M_AXI_GP0_RVALID), + .M_AXI_GP0_WDATA(ps_7_M_AXI_GP0_WDATA), + .M_AXI_GP0_WID(ps_7_M_AXI_GP0_WID), + .M_AXI_GP0_WLAST(ps_7_M_AXI_GP0_WLAST), + .M_AXI_GP0_WREADY(ps_7_M_AXI_GP0_WREADY), + .M_AXI_GP0_WSTRB(ps_7_M_AXI_GP0_WSTRB), + .M_AXI_GP0_WVALID(ps_7_M_AXI_GP0_WVALID), + .PS_CLK(FIXED_IO_ps_clk), + .PS_PORB(FIXED_IO_ps_porb), + .PS_SRSTB(FIXED_IO_ps_srstb), + .S_AXI_HP0_ACLK(ps_7_FCLK_CLK2), + .S_AXI_HP0_ARADDR({io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR,io2axis_M00_AXI_ARADDR}), + .S_AXI_HP0_ARBURST({io2axis_M00_AXI_ARBURST,io2axis_M00_AXI_ARBURST}), + .S_AXI_HP0_ARCACHE({io2axis_M00_AXI_ARCACHE,io2axis_M00_AXI_ARCACHE,io2axis_M00_AXI_ARCACHE,io2axis_M00_AXI_ARCACHE}), + .S_AXI_HP0_ARID({io2axis_M00_AXI_ARID,io2axis_M00_AXI_ARID,io2axis_M00_AXI_ARID,io2axis_M00_AXI_ARID,io2axis_M00_AXI_ARID,io2axis_M00_AXI_ARID}), + .S_AXI_HP0_ARLEN({io2axis_M00_AXI_ARLEN,io2axis_M00_AXI_ARLEN,io2axis_M00_AXI_ARLEN,io2axis_M00_AXI_ARLEN}), + .S_AXI_HP0_ARLOCK({io2axis_M00_AXI_ARLOCK,io2axis_M00_AXI_ARLOCK}), + .S_AXI_HP0_ARPROT({io2axis_M00_AXI_ARPROT,io2axis_M00_AXI_ARPROT,io2axis_M00_AXI_ARPROT}), + .S_AXI_HP0_ARQOS({io2axis_M00_AXI_ARQOS,io2axis_M00_AXI_ARQOS,io2axis_M00_AXI_ARQOS,io2axis_M00_AXI_ARQOS}), + .S_AXI_HP0_ARREADY(io2axis_M00_AXI_ARREADY), + .S_AXI_HP0_ARSIZE({io2axis_M00_AXI_ARSIZE,io2axis_M00_AXI_ARSIZE,io2axis_M00_AXI_ARSIZE}), + .S_AXI_HP0_ARVALID(io2axis_M00_AXI_ARVALID), + .S_AXI_HP0_AWADDR({io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR,io2axis_M00_AXI_AWADDR}), + .S_AXI_HP0_AWBURST({io2axis_M00_AXI_AWBURST,io2axis_M00_AXI_AWBURST}), + .S_AXI_HP0_AWCACHE({io2axis_M00_AXI_AWCACHE,io2axis_M00_AXI_AWCACHE,io2axis_M00_AXI_AWCACHE,io2axis_M00_AXI_AWCACHE}), + .S_AXI_HP0_AWID({io2axis_M00_AXI_AWID,io2axis_M00_AXI_AWID,io2axis_M00_AXI_AWID,io2axis_M00_AXI_AWID,io2axis_M00_AXI_AWID,io2axis_M00_AXI_AWID}), + .S_AXI_HP0_AWLEN({io2axis_M00_AXI_AWLEN,io2axis_M00_AXI_AWLEN,io2axis_M00_AXI_AWLEN,io2axis_M00_AXI_AWLEN}), + .S_AXI_HP0_AWLOCK({io2axis_M00_AXI_AWLOCK,io2axis_M00_AXI_AWLOCK}), + .S_AXI_HP0_AWPROT({io2axis_M00_AXI_AWPROT,io2axis_M00_AXI_AWPROT,io2axis_M00_AXI_AWPROT}), + .S_AXI_HP0_AWQOS({io2axis_M00_AXI_AWQOS,io2axis_M00_AXI_AWQOS,io2axis_M00_AXI_AWQOS,io2axis_M00_AXI_AWQOS}), + .S_AXI_HP0_AWREADY(io2axis_M00_AXI_AWREADY), + .S_AXI_HP0_AWSIZE({io2axis_M00_AXI_AWSIZE,io2axis_M00_AXI_AWSIZE,io2axis_M00_AXI_AWSIZE}), + .S_AXI_HP0_AWVALID(io2axis_M00_AXI_AWVALID), + .S_AXI_HP0_BID(io2axis_M00_AXI_BID), + .S_AXI_HP0_BREADY(io2axis_M00_AXI_BREADY), + .S_AXI_HP0_BRESP(io2axis_M00_AXI_BRESP), + .S_AXI_HP0_BVALID(io2axis_M00_AXI_BVALID), + .S_AXI_HP0_RDATA(io2axis_M00_AXI_RDATA), + .S_AXI_HP0_RDISSUECAP1_EN(GND_1), + .S_AXI_HP0_RID(io2axis_M00_AXI_RID), + .S_AXI_HP0_RLAST(io2axis_M00_AXI_RLAST), + .S_AXI_HP0_RREADY(io2axis_M00_AXI_RREADY), + .S_AXI_HP0_RRESP(io2axis_M00_AXI_RRESP), + .S_AXI_HP0_RVALID(io2axis_M00_AXI_RVALID), + .S_AXI_HP0_WDATA({io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA,io2axis_M00_AXI_WDATA}), + .S_AXI_HP0_WID({io2axis_M00_AXI_WID,io2axis_M00_AXI_WID,io2axis_M00_AXI_WID,io2axis_M00_AXI_WID,io2axis_M00_AXI_WID,io2axis_M00_AXI_WID}), + .S_AXI_HP0_WLAST(io2axis_M00_AXI_WLAST), + .S_AXI_HP0_WREADY(io2axis_M00_AXI_WREADY), + .S_AXI_HP0_WRISSUECAP1_EN(GND_1), + .S_AXI_HP0_WSTRB({io2axis_M00_AXI_WSTRB,io2axis_M00_AXI_WSTRB,io2axis_M00_AXI_WSTRB,io2axis_M00_AXI_WSTRB,io2axis_M00_AXI_WSTRB,io2axis_M00_AXI_WSTRB,io2axis_M00_AXI_WSTRB,io2axis_M00_AXI_WSTRB}), + .S_AXI_HP0_WVALID(io2axis_M00_AXI_WVALID), + .USB0_VBUS_PWRFAULT(GND_1)); + z_turn_util_vector_logic_0_0 util_vector_logic_0 + (.Op1(HDMI_INTn_1), + .Res(util_vector_logic_0_Res)); + z_turn_util_vector_logic_0_1 util_vector_logic_1 + (.Op1(MEMS_INTn_1), + .Res(util_vector_logic_1_Res)); + z_turn_util_vector_logic_1_0 util_vector_logic_2 + (.Op1(MEMS_INTn_1), + .Res(util_vector_logic_2_Res)); + z_turn_xlconcat_0_0 xlconcat + (.In0(util_vector_logic_0_Res), + .In1(GND_1), + .In10(GND_1), + .In11(GND_1), + .In12(GND_1), + .In13(GND_1), + .In14(GND_1), + .In15(GND_1), + .In2(util_vector_logic_1_Res), + .In3(util_vector_logic_2_Res), + .In4(GND_1), + .In5(GND_1), + .In6(GND_1), + .In7(GND_1), + .In8(GND_1), + .In9(GND_1), + .dout(xlconcat_0_dout)); + z_turn_xlconcat_0_1 xlconcat_0 + (.In0(xlconcat_1_dout), + .In1(xlconcat_2_dout), + .dout(xlconcat_0_dout1)); + z_turn_xlconcat_0_2 xlconcat_1 + (.In0(GND_1), + .In1(GND_1), + .In10(GND_1), + .In11(GND_1), + .In12(GND_1), + .In13(GND_1), + .In14(GND_1), + .In15(GND_1), + .In16(GND_1), + .In17(GND_1), + .In18(GND_1), + .In19(GND_1), + .In2(GND_1), + .In20(GND_1), + .In21(GND_1), + .In22(GND_1), + .In23(GND_1), + .In24(GND_1), + .In25(GND_1), + .In26(GND_1), + .In27(GND_1), + .In28(GND_1), + .In29(GND_1), + .In3(GND_1), + .In30(GND_1), + .In31(GND_1), + .In4(GND_1), + .In5(GND_1), + .In6(GND_1), + .In7(GND_1), + .In8(GND_1), + .In9(GND_1), + .dout(xlconcat_1_dout)); + z_turn_xlconcat_1_0 xlconcat_2 + (.In0(GND_1), + .In1(GND_1), + .In10(GND_1), + .In11(GND_1), + .In12(GND_1), + .In13(GND_1), + .In14(GND_1), + .In15(GND_1), + .In16(GND_1), + .In17(GND_1), + .In18(GND_1), + .In19(GND_1), + .In2(GND_1), + .In20(GND_1), + .In21(GND_1), + .In22(GND_1), + .In23(GND_1), + .In24(SW_1), + .In25(GND_1), + .In26(GND_1), + .In27(GND_1), + .In28(GND_1), + .In3(GND_1), + .In4(GND_1), + .In5(GND_1), + .In6(GND_1), + .In7(GND_1), + .In8(GND_1), + .In9(GND_1), + .dout(xlconcat_2_dout)); + z_turn_ps_7_axi_periph_0 z_turn_ps_7_axi_periph_0 + (.ACLK(ps_7_FCLK_CLK0), + .ARESETN(rst_ps_7_166M_interconnect_aresetn), + .M00_ACLK(ps_7_FCLK_CLK0), + .M00_ARESETN(rst_ps_7_166M_peripheral_aresetn), + .M00_AXI_arready(GND_1), + .M00_AXI_awready(GND_1), + .M00_AXI_bid(GND_1), + .M00_AXI_bresp(GND_1), + .M00_AXI_bvalid(GND_1), + .M00_AXI_rdata(GND_1), + .M00_AXI_rid(GND_1), + .M00_AXI_rlast(GND_1), + .M00_AXI_rresp(GND_1), + .M00_AXI_rvalid(GND_1), + .M00_AXI_wready(GND_1), + .S00_ACLK(ps_7_FCLK_CLK0), + .S00_ARESETN(rst_ps_7_166M_peripheral_aresetn), + .S00_AXI_araddr(ps_7_M_AXI_GP0_ARADDR[0]), + .S00_AXI_arburst(ps_7_M_AXI_GP0_ARBURST[0]), + .S00_AXI_arcache(ps_7_M_AXI_GP0_ARCACHE[0]), + .S00_AXI_arid(ps_7_M_AXI_GP0_ARID[0]), + .S00_AXI_arlen(ps_7_M_AXI_GP0_ARLEN[0]), + .S00_AXI_arlock(ps_7_M_AXI_GP0_ARLOCK[0]), + .S00_AXI_arprot(ps_7_M_AXI_GP0_ARPROT[0]), + .S00_AXI_arqos(ps_7_M_AXI_GP0_ARQOS[0]), + .S00_AXI_arready(ps_7_M_AXI_GP0_ARREADY), + .S00_AXI_arsize(ps_7_M_AXI_GP0_ARSIZE[0]), + .S00_AXI_arvalid(ps_7_M_AXI_GP0_ARVALID), + .S00_AXI_awaddr(ps_7_M_AXI_GP0_AWADDR[0]), + .S00_AXI_awburst(ps_7_M_AXI_GP0_AWBURST[0]), + .S00_AXI_awcache(ps_7_M_AXI_GP0_AWCACHE[0]), + .S00_AXI_awid(ps_7_M_AXI_GP0_AWID[0]), + .S00_AXI_awlen(ps_7_M_AXI_GP0_AWLEN[0]), + .S00_AXI_awlock(ps_7_M_AXI_GP0_AWLOCK[0]), + .S00_AXI_awprot(ps_7_M_AXI_GP0_AWPROT[0]), + .S00_AXI_awqos(ps_7_M_AXI_GP0_AWQOS[0]), + .S00_AXI_awready(ps_7_M_AXI_GP0_AWREADY), + .S00_AXI_awsize(ps_7_M_AXI_GP0_AWSIZE[0]), + .S00_AXI_awvalid(ps_7_M_AXI_GP0_AWVALID), + .S00_AXI_bid(ps_7_M_AXI_GP0_BID), + .S00_AXI_bready(ps_7_M_AXI_GP0_BREADY), + .S00_AXI_bresp(ps_7_M_AXI_GP0_BRESP), + .S00_AXI_bvalid(ps_7_M_AXI_GP0_BVALID), + .S00_AXI_rdata(ps_7_M_AXI_GP0_RDATA), + .S00_AXI_rid(ps_7_M_AXI_GP0_RID), + .S00_AXI_rlast(ps_7_M_AXI_GP0_RLAST), + .S00_AXI_rready(ps_7_M_AXI_GP0_RREADY), + .S00_AXI_rresp(ps_7_M_AXI_GP0_RRESP), + .S00_AXI_rvalid(ps_7_M_AXI_GP0_RVALID), + .S00_AXI_wdata(ps_7_M_AXI_GP0_WDATA[0]), + .S00_AXI_wid(ps_7_M_AXI_GP0_WID[0]), + .S00_AXI_wlast(ps_7_M_AXI_GP0_WLAST), + .S00_AXI_wready(ps_7_M_AXI_GP0_WREADY), + .S00_AXI_wstrb(ps_7_M_AXI_GP0_WSTRB[0]), + .S00_AXI_wvalid(ps_7_M_AXI_GP0_WVALID)); + z_turn_ps_7_axi_periph_1 z_turn_ps_7_axi_periph_1 + (.ACLK(ps_7_FCLK_CLK2), + .ARESETN(proc_sys_reset2_interconnect_aresetn), + .M00_ACLK(ps_7_FCLK_CLK2), + .M00_ARESETN(proc_sys_reset2_peripheral_aresetn), + .M00_AXI_araddr(io2axis_M00_AXI_ARADDR), + .M00_AXI_arburst(io2axis_M00_AXI_ARBURST), + .M00_AXI_arcache(io2axis_M00_AXI_ARCACHE), + .M00_AXI_arid(io2axis_M00_AXI_ARID), + .M00_AXI_arlen(io2axis_M00_AXI_ARLEN), + .M00_AXI_arlock(io2axis_M00_AXI_ARLOCK), + .M00_AXI_arprot(io2axis_M00_AXI_ARPROT), + .M00_AXI_arqos(io2axis_M00_AXI_ARQOS), + .M00_AXI_arready(io2axis_M00_AXI_ARREADY), + .M00_AXI_arsize(io2axis_M00_AXI_ARSIZE), + .M00_AXI_arvalid(io2axis_M00_AXI_ARVALID), + .M00_AXI_awaddr(io2axis_M00_AXI_AWADDR), + .M00_AXI_awburst(io2axis_M00_AXI_AWBURST), + .M00_AXI_awcache(io2axis_M00_AXI_AWCACHE), + .M00_AXI_awid(io2axis_M00_AXI_AWID), + .M00_AXI_awlen(io2axis_M00_AXI_AWLEN), + .M00_AXI_awlock(io2axis_M00_AXI_AWLOCK), + .M00_AXI_awprot(io2axis_M00_AXI_AWPROT), + .M00_AXI_awqos(io2axis_M00_AXI_AWQOS), + .M00_AXI_awready(io2axis_M00_AXI_AWREADY), + .M00_AXI_awsize(io2axis_M00_AXI_AWSIZE), + .M00_AXI_awvalid(io2axis_M00_AXI_AWVALID), + .M00_AXI_bid(io2axis_M00_AXI_BID[0]), + .M00_AXI_bready(io2axis_M00_AXI_BREADY), + .M00_AXI_bresp(io2axis_M00_AXI_BRESP[0]), + .M00_AXI_bvalid(io2axis_M00_AXI_BVALID), + .M00_AXI_rdata(io2axis_M00_AXI_RDATA[0]), + .M00_AXI_rid(io2axis_M00_AXI_RID[0]), + .M00_AXI_rlast(io2axis_M00_AXI_RLAST), + .M00_AXI_rready(io2axis_M00_AXI_RREADY), + .M00_AXI_rresp(io2axis_M00_AXI_RRESP[0]), + .M00_AXI_rvalid(io2axis_M00_AXI_RVALID), + .M00_AXI_wdata(io2axis_M00_AXI_WDATA), + .M00_AXI_wid(io2axis_M00_AXI_WID), + .M00_AXI_wlast(io2axis_M00_AXI_WLAST), + .M00_AXI_wready(io2axis_M00_AXI_WREADY), + .M00_AXI_wstrb(io2axis_M00_AXI_WSTRB), + .M00_AXI_wvalid(io2axis_M00_AXI_WVALID), + .S00_ACLK(ps_7_FCLK_CLK2), + .S00_ARESETN(proc_sys_reset2_peripheral_aresetn), + .S00_AXI_araddr(GND_1), + .S00_AXI_arburst(GND_1), + .S00_AXI_arcache(GND_1), + .S00_AXI_arid(GND_1), + .S00_AXI_arlen(GND_1), + .S00_AXI_arlock(GND_1), + .S00_AXI_arprot(GND_1), + .S00_AXI_arqos(GND_1), + .S00_AXI_arsize(GND_1), + .S00_AXI_arvalid(GND_1), + .S00_AXI_awaddr(GND_1), + .S00_AXI_awburst(GND_1), + .S00_AXI_awcache(GND_1), + .S00_AXI_awid(GND_1), + .S00_AXI_awlen(GND_1), + .S00_AXI_awlock(GND_1), + .S00_AXI_awprot(GND_1), + .S00_AXI_awqos(GND_1), + .S00_AXI_awsize(GND_1), + .S00_AXI_awvalid(GND_1), + .S00_AXI_bready(GND_1), + .S00_AXI_rready(GND_1), + .S00_AXI_wdata(GND_1), + .S00_AXI_wid(GND_1), + .S00_AXI_wlast(GND_1), + .S00_AXI_wstrb(GND_1), + .S00_AXI_wvalid(GND_1)); +endmodule + +module z_turn_ps_7_axi_periph_0 + (ACLK, + ARESETN, + M00_ACLK, + M00_ARESETN, + M00_AXI_araddr, + M00_AXI_arburst, + M00_AXI_arcache, + M00_AXI_arid, + M00_AXI_arlen, + M00_AXI_arlock, + M00_AXI_arprot, + M00_AXI_arqos, + M00_AXI_arready, + M00_AXI_arsize, + M00_AXI_arvalid, + M00_AXI_awaddr, + M00_AXI_awburst, + M00_AXI_awcache, + M00_AXI_awid, + M00_AXI_awlen, + M00_AXI_awlock, + M00_AXI_awprot, + M00_AXI_awqos, + M00_AXI_awready, + M00_AXI_awsize, + M00_AXI_awvalid, + M00_AXI_bid, + M00_AXI_bready, + M00_AXI_bresp, + M00_AXI_bvalid, + M00_AXI_rdata, + M00_AXI_rid, + M00_AXI_rlast, + M00_AXI_rready, + M00_AXI_rresp, + M00_AXI_rvalid, + M00_AXI_wdata, + M00_AXI_wid, + M00_AXI_wlast, + M00_AXI_wready, + M00_AXI_wstrb, + M00_AXI_wvalid, + S00_ACLK, + S00_ARESETN, + S00_AXI_araddr, + S00_AXI_arburst, + S00_AXI_arcache, + S00_AXI_arid, + S00_AXI_arlen, + S00_AXI_arlock, + S00_AXI_arprot, + S00_AXI_arqos, + S00_AXI_arready, + S00_AXI_arsize, + S00_AXI_arvalid, + S00_AXI_awaddr, + S00_AXI_awburst, + S00_AXI_awcache, + S00_AXI_awid, + S00_AXI_awlen, + S00_AXI_awlock, + S00_AXI_awprot, + S00_AXI_awqos, + S00_AXI_awready, + S00_AXI_awsize, + S00_AXI_awvalid, + S00_AXI_bid, + S00_AXI_bready, + S00_AXI_bresp, + S00_AXI_bvalid, + S00_AXI_rdata, + S00_AXI_rid, + S00_AXI_rlast, + S00_AXI_rready, + S00_AXI_rresp, + S00_AXI_rvalid, + S00_AXI_wdata, + S00_AXI_wid, + S00_AXI_wlast, + S00_AXI_wready, + S00_AXI_wstrb, + S00_AXI_wvalid); + input ACLK; + input [0:0]ARESETN; + input M00_ACLK; + input [0:0]M00_ARESETN; + output M00_AXI_araddr; + output M00_AXI_arburst; + output M00_AXI_arcache; + output M00_AXI_arid; + output M00_AXI_arlen; + output M00_AXI_arlock; + output M00_AXI_arprot; + output M00_AXI_arqos; + input M00_AXI_arready; + output M00_AXI_arsize; + output M00_AXI_arvalid; + output M00_AXI_awaddr; + output M00_AXI_awburst; + output M00_AXI_awcache; + output M00_AXI_awid; + output M00_AXI_awlen; + output M00_AXI_awlock; + output M00_AXI_awprot; + output M00_AXI_awqos; + input M00_AXI_awready; + output M00_AXI_awsize; + output M00_AXI_awvalid; + input M00_AXI_bid; + output M00_AXI_bready; + input M00_AXI_bresp; + input M00_AXI_bvalid; + input M00_AXI_rdata; + input M00_AXI_rid; + input M00_AXI_rlast; + output M00_AXI_rready; + input M00_AXI_rresp; + input M00_AXI_rvalid; + output M00_AXI_wdata; + output M00_AXI_wid; + output M00_AXI_wlast; + input M00_AXI_wready; + output M00_AXI_wstrb; + output M00_AXI_wvalid; + input S00_ACLK; + input [0:0]S00_ARESETN; + input S00_AXI_araddr; + input S00_AXI_arburst; + input S00_AXI_arcache; + input S00_AXI_arid; + input S00_AXI_arlen; + input S00_AXI_arlock; + input S00_AXI_arprot; + input S00_AXI_arqos; + output S00_AXI_arready; + input S00_AXI_arsize; + input S00_AXI_arvalid; + input S00_AXI_awaddr; + input S00_AXI_awburst; + input S00_AXI_awcache; + input S00_AXI_awid; + input S00_AXI_awlen; + input S00_AXI_awlock; + input S00_AXI_awprot; + input S00_AXI_awqos; + output S00_AXI_awready; + input S00_AXI_awsize; + input S00_AXI_awvalid; + output S00_AXI_bid; + input S00_AXI_bready; + output S00_AXI_bresp; + output S00_AXI_bvalid; + output S00_AXI_rdata; + output S00_AXI_rid; + output S00_AXI_rlast; + input S00_AXI_rready; + output S00_AXI_rresp; + output S00_AXI_rvalid; + input S00_AXI_wdata; + input S00_AXI_wid; + input S00_AXI_wlast; + output S00_AXI_wready; + input S00_AXI_wstrb; + input S00_AXI_wvalid; + + wire S00_ACLK_1; + wire [0:0]S00_ARESETN_1; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_ARADDR; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_ARBURST; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_ARCACHE; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_ARID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_ARLEN; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_ARLOCK; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_ARPROT; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_ARQOS; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_ARREADY; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_ARSIZE; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_ARVALID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_AWADDR; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_AWBURST; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_AWCACHE; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_AWID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_AWLEN; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_AWLOCK; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_AWPROT; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_AWQOS; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_AWREADY; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_AWSIZE; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_AWVALID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_BID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_BREADY; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_BRESP; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_BVALID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_RDATA; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_RID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_RLAST; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_RREADY; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_RRESP; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_RVALID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_WDATA; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_WID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_WLAST; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_WREADY; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_WSTRB; + wire s00_couplers_to_z_turn_ps_7_axi_periph_0_WVALID; + wire z_turn_ps_7_axi_periph_0_ACLK_net; + wire [0:0]z_turn_ps_7_axi_periph_0_ARESETN_net; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_ARADDR; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_ARBURST; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_ARCACHE; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_ARID; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_ARLEN; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_ARLOCK; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_ARPROT; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_ARQOS; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_ARREADY; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_ARSIZE; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_ARVALID; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_AWADDR; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_AWBURST; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_AWCACHE; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_AWID; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_AWLEN; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_AWLOCK; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_AWPROT; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_AWQOS; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_AWREADY; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_AWSIZE; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_AWVALID; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_BID; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_BREADY; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_BRESP; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_BVALID; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_RDATA; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_RID; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_RLAST; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_RREADY; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_RRESP; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_RVALID; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_WDATA; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_WID; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_WLAST; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_WREADY; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_WSTRB; + wire z_turn_ps_7_axi_periph_0_to_s00_couplers_WVALID; + + assign M00_AXI_araddr = s00_couplers_to_z_turn_ps_7_axi_periph_0_ARADDR; + assign M00_AXI_arburst = s00_couplers_to_z_turn_ps_7_axi_periph_0_ARBURST; + assign M00_AXI_arcache = s00_couplers_to_z_turn_ps_7_axi_periph_0_ARCACHE; + assign M00_AXI_arid = s00_couplers_to_z_turn_ps_7_axi_periph_0_ARID; + assign M00_AXI_arlen = s00_couplers_to_z_turn_ps_7_axi_periph_0_ARLEN; + assign M00_AXI_arlock = s00_couplers_to_z_turn_ps_7_axi_periph_0_ARLOCK; + assign M00_AXI_arprot = s00_couplers_to_z_turn_ps_7_axi_periph_0_ARPROT; + assign M00_AXI_arqos = s00_couplers_to_z_turn_ps_7_axi_periph_0_ARQOS; + assign M00_AXI_arsize = s00_couplers_to_z_turn_ps_7_axi_periph_0_ARSIZE; + assign M00_AXI_arvalid = s00_couplers_to_z_turn_ps_7_axi_periph_0_ARVALID; + assign M00_AXI_awaddr = s00_couplers_to_z_turn_ps_7_axi_periph_0_AWADDR; + assign M00_AXI_awburst = s00_couplers_to_z_turn_ps_7_axi_periph_0_AWBURST; + assign M00_AXI_awcache = s00_couplers_to_z_turn_ps_7_axi_periph_0_AWCACHE; + assign M00_AXI_awid = s00_couplers_to_z_turn_ps_7_axi_periph_0_AWID; + assign M00_AXI_awlen = s00_couplers_to_z_turn_ps_7_axi_periph_0_AWLEN; + assign M00_AXI_awlock = s00_couplers_to_z_turn_ps_7_axi_periph_0_AWLOCK; + assign M00_AXI_awprot = s00_couplers_to_z_turn_ps_7_axi_periph_0_AWPROT; + assign M00_AXI_awqos = s00_couplers_to_z_turn_ps_7_axi_periph_0_AWQOS; + assign M00_AXI_awsize = s00_couplers_to_z_turn_ps_7_axi_periph_0_AWSIZE; + assign M00_AXI_awvalid = s00_couplers_to_z_turn_ps_7_axi_periph_0_AWVALID; + assign M00_AXI_bready = s00_couplers_to_z_turn_ps_7_axi_periph_0_BREADY; + assign M00_AXI_rready = s00_couplers_to_z_turn_ps_7_axi_periph_0_RREADY; + assign M00_AXI_wdata = s00_couplers_to_z_turn_ps_7_axi_periph_0_WDATA; + assign M00_AXI_wid = s00_couplers_to_z_turn_ps_7_axi_periph_0_WID; + assign M00_AXI_wlast = s00_couplers_to_z_turn_ps_7_axi_periph_0_WLAST; + assign M00_AXI_wstrb = s00_couplers_to_z_turn_ps_7_axi_periph_0_WSTRB; + assign M00_AXI_wvalid = s00_couplers_to_z_turn_ps_7_axi_periph_0_WVALID; + assign S00_ACLK_1 = S00_ACLK; + assign S00_ARESETN_1 = S00_ARESETN[0]; + assign S00_AXI_arready = z_turn_ps_7_axi_periph_0_to_s00_couplers_ARREADY; + assign S00_AXI_awready = z_turn_ps_7_axi_periph_0_to_s00_couplers_AWREADY; + assign S00_AXI_bid = z_turn_ps_7_axi_periph_0_to_s00_couplers_BID; + assign S00_AXI_bresp = z_turn_ps_7_axi_periph_0_to_s00_couplers_BRESP; + assign S00_AXI_bvalid = z_turn_ps_7_axi_periph_0_to_s00_couplers_BVALID; + assign S00_AXI_rdata = z_turn_ps_7_axi_periph_0_to_s00_couplers_RDATA; + assign S00_AXI_rid = z_turn_ps_7_axi_periph_0_to_s00_couplers_RID; + assign S00_AXI_rlast = z_turn_ps_7_axi_periph_0_to_s00_couplers_RLAST; + assign S00_AXI_rresp = z_turn_ps_7_axi_periph_0_to_s00_couplers_RRESP; + assign S00_AXI_rvalid = z_turn_ps_7_axi_periph_0_to_s00_couplers_RVALID; + assign S00_AXI_wready = z_turn_ps_7_axi_periph_0_to_s00_couplers_WREADY; + assign s00_couplers_to_z_turn_ps_7_axi_periph_0_ARREADY = M00_AXI_arready; + assign s00_couplers_to_z_turn_ps_7_axi_periph_0_AWREADY = M00_AXI_awready; + assign s00_couplers_to_z_turn_ps_7_axi_periph_0_BID = M00_AXI_bid; + assign s00_couplers_to_z_turn_ps_7_axi_periph_0_BRESP = M00_AXI_bresp; + assign s00_couplers_to_z_turn_ps_7_axi_periph_0_BVALID = M00_AXI_bvalid; + assign s00_couplers_to_z_turn_ps_7_axi_periph_0_RDATA = M00_AXI_rdata; + assign s00_couplers_to_z_turn_ps_7_axi_periph_0_RID = M00_AXI_rid; + assign s00_couplers_to_z_turn_ps_7_axi_periph_0_RLAST = M00_AXI_rlast; + assign s00_couplers_to_z_turn_ps_7_axi_periph_0_RRESP = M00_AXI_rresp; + assign s00_couplers_to_z_turn_ps_7_axi_periph_0_RVALID = M00_AXI_rvalid; + assign s00_couplers_to_z_turn_ps_7_axi_periph_0_WREADY = M00_AXI_wready; + assign z_turn_ps_7_axi_periph_0_ACLK_net = M00_ACLK; + assign z_turn_ps_7_axi_periph_0_ARESETN_net = M00_ARESETN[0]; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_ARADDR = S00_AXI_araddr; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_ARBURST = S00_AXI_arburst; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_ARCACHE = S00_AXI_arcache; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_ARID = S00_AXI_arid; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_ARLEN = S00_AXI_arlen; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_ARLOCK = S00_AXI_arlock; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_ARPROT = S00_AXI_arprot; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_ARQOS = S00_AXI_arqos; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_ARSIZE = S00_AXI_arsize; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_ARVALID = S00_AXI_arvalid; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_AWADDR = S00_AXI_awaddr; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_AWBURST = S00_AXI_awburst; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_AWCACHE = S00_AXI_awcache; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_AWID = S00_AXI_awid; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_AWLEN = S00_AXI_awlen; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_AWLOCK = S00_AXI_awlock; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_AWPROT = S00_AXI_awprot; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_AWQOS = S00_AXI_awqos; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_AWSIZE = S00_AXI_awsize; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_AWVALID = S00_AXI_awvalid; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_BREADY = S00_AXI_bready; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_RREADY = S00_AXI_rready; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_WDATA = S00_AXI_wdata; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_WID = S00_AXI_wid; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_WLAST = S00_AXI_wlast; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_WSTRB = S00_AXI_wstrb; + assign z_turn_ps_7_axi_periph_0_to_s00_couplers_WVALID = S00_AXI_wvalid; + s00_couplers_imp_QSJACF s00_couplers + (.M_ACLK(z_turn_ps_7_axi_periph_0_ACLK_net), + .M_ARESETN(z_turn_ps_7_axi_periph_0_ARESETN_net), + .M_AXI_araddr(s00_couplers_to_z_turn_ps_7_axi_periph_0_ARADDR), + .M_AXI_arburst(s00_couplers_to_z_turn_ps_7_axi_periph_0_ARBURST), + .M_AXI_arcache(s00_couplers_to_z_turn_ps_7_axi_periph_0_ARCACHE), + .M_AXI_arid(s00_couplers_to_z_turn_ps_7_axi_periph_0_ARID), + .M_AXI_arlen(s00_couplers_to_z_turn_ps_7_axi_periph_0_ARLEN), + .M_AXI_arlock(s00_couplers_to_z_turn_ps_7_axi_periph_0_ARLOCK), + .M_AXI_arprot(s00_couplers_to_z_turn_ps_7_axi_periph_0_ARPROT), + .M_AXI_arqos(s00_couplers_to_z_turn_ps_7_axi_periph_0_ARQOS), + .M_AXI_arready(s00_couplers_to_z_turn_ps_7_axi_periph_0_ARREADY), + .M_AXI_arsize(s00_couplers_to_z_turn_ps_7_axi_periph_0_ARSIZE), + .M_AXI_arvalid(s00_couplers_to_z_turn_ps_7_axi_periph_0_ARVALID), + .M_AXI_awaddr(s00_couplers_to_z_turn_ps_7_axi_periph_0_AWADDR), + .M_AXI_awburst(s00_couplers_to_z_turn_ps_7_axi_periph_0_AWBURST), + .M_AXI_awcache(s00_couplers_to_z_turn_ps_7_axi_periph_0_AWCACHE), + .M_AXI_awid(s00_couplers_to_z_turn_ps_7_axi_periph_0_AWID), + .M_AXI_awlen(s00_couplers_to_z_turn_ps_7_axi_periph_0_AWLEN), + .M_AXI_awlock(s00_couplers_to_z_turn_ps_7_axi_periph_0_AWLOCK), + .M_AXI_awprot(s00_couplers_to_z_turn_ps_7_axi_periph_0_AWPROT), + .M_AXI_awqos(s00_couplers_to_z_turn_ps_7_axi_periph_0_AWQOS), + .M_AXI_awready(s00_couplers_to_z_turn_ps_7_axi_periph_0_AWREADY), + .M_AXI_awsize(s00_couplers_to_z_turn_ps_7_axi_periph_0_AWSIZE), + .M_AXI_awvalid(s00_couplers_to_z_turn_ps_7_axi_periph_0_AWVALID), + .M_AXI_bid(s00_couplers_to_z_turn_ps_7_axi_periph_0_BID), + .M_AXI_bready(s00_couplers_to_z_turn_ps_7_axi_periph_0_BREADY), + .M_AXI_bresp(s00_couplers_to_z_turn_ps_7_axi_periph_0_BRESP), + .M_AXI_bvalid(s00_couplers_to_z_turn_ps_7_axi_periph_0_BVALID), + .M_AXI_rdata(s00_couplers_to_z_turn_ps_7_axi_periph_0_RDATA), + .M_AXI_rid(s00_couplers_to_z_turn_ps_7_axi_periph_0_RID), + .M_AXI_rlast(s00_couplers_to_z_turn_ps_7_axi_periph_0_RLAST), + .M_AXI_rready(s00_couplers_to_z_turn_ps_7_axi_periph_0_RREADY), + .M_AXI_rresp(s00_couplers_to_z_turn_ps_7_axi_periph_0_RRESP), + .M_AXI_rvalid(s00_couplers_to_z_turn_ps_7_axi_periph_0_RVALID), + .M_AXI_wdata(s00_couplers_to_z_turn_ps_7_axi_periph_0_WDATA), + .M_AXI_wid(s00_couplers_to_z_turn_ps_7_axi_periph_0_WID), + .M_AXI_wlast(s00_couplers_to_z_turn_ps_7_axi_periph_0_WLAST), + .M_AXI_wready(s00_couplers_to_z_turn_ps_7_axi_periph_0_WREADY), + .M_AXI_wstrb(s00_couplers_to_z_turn_ps_7_axi_periph_0_WSTRB), + .M_AXI_wvalid(s00_couplers_to_z_turn_ps_7_axi_periph_0_WVALID), + .S_ACLK(S00_ACLK_1), + .S_ARESETN(S00_ARESETN_1), + .S_AXI_araddr(z_turn_ps_7_axi_periph_0_to_s00_couplers_ARADDR), + .S_AXI_arburst(z_turn_ps_7_axi_periph_0_to_s00_couplers_ARBURST), + .S_AXI_arcache(z_turn_ps_7_axi_periph_0_to_s00_couplers_ARCACHE), + .S_AXI_arid(z_turn_ps_7_axi_periph_0_to_s00_couplers_ARID), + .S_AXI_arlen(z_turn_ps_7_axi_periph_0_to_s00_couplers_ARLEN), + .S_AXI_arlock(z_turn_ps_7_axi_periph_0_to_s00_couplers_ARLOCK), + .S_AXI_arprot(z_turn_ps_7_axi_periph_0_to_s00_couplers_ARPROT), + .S_AXI_arqos(z_turn_ps_7_axi_periph_0_to_s00_couplers_ARQOS), + .S_AXI_arready(z_turn_ps_7_axi_periph_0_to_s00_couplers_ARREADY), + .S_AXI_arsize(z_turn_ps_7_axi_periph_0_to_s00_couplers_ARSIZE), + .S_AXI_arvalid(z_turn_ps_7_axi_periph_0_to_s00_couplers_ARVALID), + .S_AXI_awaddr(z_turn_ps_7_axi_periph_0_to_s00_couplers_AWADDR), + .S_AXI_awburst(z_turn_ps_7_axi_periph_0_to_s00_couplers_AWBURST), + .S_AXI_awcache(z_turn_ps_7_axi_periph_0_to_s00_couplers_AWCACHE), + .S_AXI_awid(z_turn_ps_7_axi_periph_0_to_s00_couplers_AWID), + .S_AXI_awlen(z_turn_ps_7_axi_periph_0_to_s00_couplers_AWLEN), + .S_AXI_awlock(z_turn_ps_7_axi_periph_0_to_s00_couplers_AWLOCK), + .S_AXI_awprot(z_turn_ps_7_axi_periph_0_to_s00_couplers_AWPROT), + .S_AXI_awqos(z_turn_ps_7_axi_periph_0_to_s00_couplers_AWQOS), + .S_AXI_awready(z_turn_ps_7_axi_periph_0_to_s00_couplers_AWREADY), + .S_AXI_awsize(z_turn_ps_7_axi_periph_0_to_s00_couplers_AWSIZE), + .S_AXI_awvalid(z_turn_ps_7_axi_periph_0_to_s00_couplers_AWVALID), + .S_AXI_bid(z_turn_ps_7_axi_periph_0_to_s00_couplers_BID), + .S_AXI_bready(z_turn_ps_7_axi_periph_0_to_s00_couplers_BREADY), + .S_AXI_bresp(z_turn_ps_7_axi_periph_0_to_s00_couplers_BRESP), + .S_AXI_bvalid(z_turn_ps_7_axi_periph_0_to_s00_couplers_BVALID), + .S_AXI_rdata(z_turn_ps_7_axi_periph_0_to_s00_couplers_RDATA), + .S_AXI_rid(z_turn_ps_7_axi_periph_0_to_s00_couplers_RID), + .S_AXI_rlast(z_turn_ps_7_axi_periph_0_to_s00_couplers_RLAST), + .S_AXI_rready(z_turn_ps_7_axi_periph_0_to_s00_couplers_RREADY), + .S_AXI_rresp(z_turn_ps_7_axi_periph_0_to_s00_couplers_RRESP), + .S_AXI_rvalid(z_turn_ps_7_axi_periph_0_to_s00_couplers_RVALID), + .S_AXI_wdata(z_turn_ps_7_axi_periph_0_to_s00_couplers_WDATA), + .S_AXI_wid(z_turn_ps_7_axi_periph_0_to_s00_couplers_WID), + .S_AXI_wlast(z_turn_ps_7_axi_periph_0_to_s00_couplers_WLAST), + .S_AXI_wready(z_turn_ps_7_axi_periph_0_to_s00_couplers_WREADY), + .S_AXI_wstrb(z_turn_ps_7_axi_periph_0_to_s00_couplers_WSTRB), + .S_AXI_wvalid(z_turn_ps_7_axi_periph_0_to_s00_couplers_WVALID)); +endmodule + +module z_turn_ps_7_axi_periph_1 + (ACLK, + ARESETN, + M00_ACLK, + M00_ARESETN, + M00_AXI_araddr, + M00_AXI_arburst, + M00_AXI_arcache, + M00_AXI_arid, + M00_AXI_arlen, + M00_AXI_arlock, + M00_AXI_arprot, + M00_AXI_arqos, + M00_AXI_arready, + M00_AXI_arsize, + M00_AXI_arvalid, + M00_AXI_awaddr, + M00_AXI_awburst, + M00_AXI_awcache, + M00_AXI_awid, + M00_AXI_awlen, + M00_AXI_awlock, + M00_AXI_awprot, + M00_AXI_awqos, + M00_AXI_awready, + M00_AXI_awsize, + M00_AXI_awvalid, + M00_AXI_bid, + M00_AXI_bready, + M00_AXI_bresp, + M00_AXI_bvalid, + M00_AXI_rdata, + M00_AXI_rid, + M00_AXI_rlast, + M00_AXI_rready, + M00_AXI_rresp, + M00_AXI_rvalid, + M00_AXI_wdata, + M00_AXI_wid, + M00_AXI_wlast, + M00_AXI_wready, + M00_AXI_wstrb, + M00_AXI_wvalid, + S00_ACLK, + S00_ARESETN, + S00_AXI_araddr, + S00_AXI_arburst, + S00_AXI_arcache, + S00_AXI_arid, + S00_AXI_arlen, + S00_AXI_arlock, + S00_AXI_arprot, + S00_AXI_arqos, + S00_AXI_arready, + S00_AXI_arsize, + S00_AXI_arvalid, + S00_AXI_awaddr, + S00_AXI_awburst, + S00_AXI_awcache, + S00_AXI_awid, + S00_AXI_awlen, + S00_AXI_awlock, + S00_AXI_awprot, + S00_AXI_awqos, + S00_AXI_awready, + S00_AXI_awsize, + S00_AXI_awvalid, + S00_AXI_bid, + S00_AXI_bready, + S00_AXI_bresp, + S00_AXI_bvalid, + S00_AXI_rdata, + S00_AXI_rid, + S00_AXI_rlast, + S00_AXI_rready, + S00_AXI_rresp, + S00_AXI_rvalid, + S00_AXI_wdata, + S00_AXI_wid, + S00_AXI_wlast, + S00_AXI_wready, + S00_AXI_wstrb, + S00_AXI_wvalid); + input ACLK; + input [0:0]ARESETN; + input M00_ACLK; + input [0:0]M00_ARESETN; + output M00_AXI_araddr; + output M00_AXI_arburst; + output M00_AXI_arcache; + output M00_AXI_arid; + output M00_AXI_arlen; + output M00_AXI_arlock; + output M00_AXI_arprot; + output M00_AXI_arqos; + input M00_AXI_arready; + output M00_AXI_arsize; + output M00_AXI_arvalid; + output M00_AXI_awaddr; + output M00_AXI_awburst; + output M00_AXI_awcache; + output M00_AXI_awid; + output M00_AXI_awlen; + output M00_AXI_awlock; + output M00_AXI_awprot; + output M00_AXI_awqos; + input M00_AXI_awready; + output M00_AXI_awsize; + output M00_AXI_awvalid; + input M00_AXI_bid; + output M00_AXI_bready; + input M00_AXI_bresp; + input M00_AXI_bvalid; + input M00_AXI_rdata; + input M00_AXI_rid; + input M00_AXI_rlast; + output M00_AXI_rready; + input M00_AXI_rresp; + input M00_AXI_rvalid; + output M00_AXI_wdata; + output M00_AXI_wid; + output M00_AXI_wlast; + input M00_AXI_wready; + output M00_AXI_wstrb; + output M00_AXI_wvalid; + input S00_ACLK; + input [0:0]S00_ARESETN; + input S00_AXI_araddr; + input S00_AXI_arburst; + input S00_AXI_arcache; + input S00_AXI_arid; + input S00_AXI_arlen; + input S00_AXI_arlock; + input S00_AXI_arprot; + input S00_AXI_arqos; + output S00_AXI_arready; + input S00_AXI_arsize; + input S00_AXI_arvalid; + input S00_AXI_awaddr; + input S00_AXI_awburst; + input S00_AXI_awcache; + input S00_AXI_awid; + input S00_AXI_awlen; + input S00_AXI_awlock; + input S00_AXI_awprot; + input S00_AXI_awqos; + output S00_AXI_awready; + input S00_AXI_awsize; + input S00_AXI_awvalid; + output S00_AXI_bid; + input S00_AXI_bready; + output S00_AXI_bresp; + output S00_AXI_bvalid; + output S00_AXI_rdata; + output S00_AXI_rid; + output S00_AXI_rlast; + input S00_AXI_rready; + output S00_AXI_rresp; + output S00_AXI_rvalid; + input S00_AXI_wdata; + input S00_AXI_wid; + input S00_AXI_wlast; + output S00_AXI_wready; + input S00_AXI_wstrb; + input S00_AXI_wvalid; + + wire S00_ACLK_1; + wire [0:0]S00_ARESETN_1; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_ARADDR; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_ARBURST; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_ARCACHE; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_ARID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_ARLEN; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_ARLOCK; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_ARPROT; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_ARQOS; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_ARREADY; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_ARSIZE; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_ARVALID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_AWADDR; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_AWBURST; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_AWCACHE; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_AWID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_AWLEN; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_AWLOCK; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_AWPROT; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_AWQOS; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_AWREADY; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_AWSIZE; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_AWVALID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_BID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_BREADY; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_BRESP; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_BVALID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_RDATA; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_RID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_RLAST; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_RREADY; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_RRESP; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_RVALID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_WDATA; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_WID; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_WLAST; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_WREADY; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_WSTRB; + wire s00_couplers_to_z_turn_ps_7_axi_periph_1_WVALID; + wire z_turn_ps_7_axi_periph_1_ACLK_net; + wire [0:0]z_turn_ps_7_axi_periph_1_ARESETN_net; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_ARADDR; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_ARBURST; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_ARCACHE; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_ARID; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_ARLEN; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_ARLOCK; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_ARPROT; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_ARQOS; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_ARREADY; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_ARSIZE; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_ARVALID; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_AWADDR; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_AWBURST; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_AWCACHE; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_AWID; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_AWLEN; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_AWLOCK; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_AWPROT; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_AWQOS; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_AWREADY; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_AWSIZE; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_AWVALID; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_BID; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_BREADY; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_BRESP; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_BVALID; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_RDATA; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_RID; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_RLAST; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_RREADY; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_RRESP; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_RVALID; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_WDATA; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_WID; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_WLAST; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_WREADY; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_WSTRB; + wire z_turn_ps_7_axi_periph_1_to_s00_couplers_WVALID; + + assign M00_AXI_araddr = s00_couplers_to_z_turn_ps_7_axi_periph_1_ARADDR; + assign M00_AXI_arburst = s00_couplers_to_z_turn_ps_7_axi_periph_1_ARBURST; + assign M00_AXI_arcache = s00_couplers_to_z_turn_ps_7_axi_periph_1_ARCACHE; + assign M00_AXI_arid = s00_couplers_to_z_turn_ps_7_axi_periph_1_ARID; + assign M00_AXI_arlen = s00_couplers_to_z_turn_ps_7_axi_periph_1_ARLEN; + assign M00_AXI_arlock = s00_couplers_to_z_turn_ps_7_axi_periph_1_ARLOCK; + assign M00_AXI_arprot = s00_couplers_to_z_turn_ps_7_axi_periph_1_ARPROT; + assign M00_AXI_arqos = s00_couplers_to_z_turn_ps_7_axi_periph_1_ARQOS; + assign M00_AXI_arsize = s00_couplers_to_z_turn_ps_7_axi_periph_1_ARSIZE; + assign M00_AXI_arvalid = s00_couplers_to_z_turn_ps_7_axi_periph_1_ARVALID; + assign M00_AXI_awaddr = s00_couplers_to_z_turn_ps_7_axi_periph_1_AWADDR; + assign M00_AXI_awburst = s00_couplers_to_z_turn_ps_7_axi_periph_1_AWBURST; + assign M00_AXI_awcache = s00_couplers_to_z_turn_ps_7_axi_periph_1_AWCACHE; + assign M00_AXI_awid = s00_couplers_to_z_turn_ps_7_axi_periph_1_AWID; + assign M00_AXI_awlen = s00_couplers_to_z_turn_ps_7_axi_periph_1_AWLEN; + assign M00_AXI_awlock = s00_couplers_to_z_turn_ps_7_axi_periph_1_AWLOCK; + assign M00_AXI_awprot = s00_couplers_to_z_turn_ps_7_axi_periph_1_AWPROT; + assign M00_AXI_awqos = s00_couplers_to_z_turn_ps_7_axi_periph_1_AWQOS; + assign M00_AXI_awsize = s00_couplers_to_z_turn_ps_7_axi_periph_1_AWSIZE; + assign M00_AXI_awvalid = s00_couplers_to_z_turn_ps_7_axi_periph_1_AWVALID; + assign M00_AXI_bready = s00_couplers_to_z_turn_ps_7_axi_periph_1_BREADY; + assign M00_AXI_rready = s00_couplers_to_z_turn_ps_7_axi_periph_1_RREADY; + assign M00_AXI_wdata = s00_couplers_to_z_turn_ps_7_axi_periph_1_WDATA; + assign M00_AXI_wid = s00_couplers_to_z_turn_ps_7_axi_periph_1_WID; + assign M00_AXI_wlast = s00_couplers_to_z_turn_ps_7_axi_periph_1_WLAST; + assign M00_AXI_wstrb = s00_couplers_to_z_turn_ps_7_axi_periph_1_WSTRB; + assign M00_AXI_wvalid = s00_couplers_to_z_turn_ps_7_axi_periph_1_WVALID; + assign S00_ACLK_1 = S00_ACLK; + assign S00_ARESETN_1 = S00_ARESETN[0]; + assign S00_AXI_arready = z_turn_ps_7_axi_periph_1_to_s00_couplers_ARREADY; + assign S00_AXI_awready = z_turn_ps_7_axi_periph_1_to_s00_couplers_AWREADY; + assign S00_AXI_bid = z_turn_ps_7_axi_periph_1_to_s00_couplers_BID; + assign S00_AXI_bresp = z_turn_ps_7_axi_periph_1_to_s00_couplers_BRESP; + assign S00_AXI_bvalid = z_turn_ps_7_axi_periph_1_to_s00_couplers_BVALID; + assign S00_AXI_rdata = z_turn_ps_7_axi_periph_1_to_s00_couplers_RDATA; + assign S00_AXI_rid = z_turn_ps_7_axi_periph_1_to_s00_couplers_RID; + assign S00_AXI_rlast = z_turn_ps_7_axi_periph_1_to_s00_couplers_RLAST; + assign S00_AXI_rresp = z_turn_ps_7_axi_periph_1_to_s00_couplers_RRESP; + assign S00_AXI_rvalid = z_turn_ps_7_axi_periph_1_to_s00_couplers_RVALID; + assign S00_AXI_wready = z_turn_ps_7_axi_periph_1_to_s00_couplers_WREADY; + assign s00_couplers_to_z_turn_ps_7_axi_periph_1_ARREADY = M00_AXI_arready; + assign s00_couplers_to_z_turn_ps_7_axi_periph_1_AWREADY = M00_AXI_awready; + assign s00_couplers_to_z_turn_ps_7_axi_periph_1_BID = M00_AXI_bid; + assign s00_couplers_to_z_turn_ps_7_axi_periph_1_BRESP = M00_AXI_bresp; + assign s00_couplers_to_z_turn_ps_7_axi_periph_1_BVALID = M00_AXI_bvalid; + assign s00_couplers_to_z_turn_ps_7_axi_periph_1_RDATA = M00_AXI_rdata; + assign s00_couplers_to_z_turn_ps_7_axi_periph_1_RID = M00_AXI_rid; + assign s00_couplers_to_z_turn_ps_7_axi_periph_1_RLAST = M00_AXI_rlast; + assign s00_couplers_to_z_turn_ps_7_axi_periph_1_RRESP = M00_AXI_rresp; + assign s00_couplers_to_z_turn_ps_7_axi_periph_1_RVALID = M00_AXI_rvalid; + assign s00_couplers_to_z_turn_ps_7_axi_periph_1_WREADY = M00_AXI_wready; + assign z_turn_ps_7_axi_periph_1_ACLK_net = M00_ACLK; + assign z_turn_ps_7_axi_periph_1_ARESETN_net = M00_ARESETN[0]; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_ARADDR = S00_AXI_araddr; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_ARBURST = S00_AXI_arburst; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_ARCACHE = S00_AXI_arcache; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_ARID = S00_AXI_arid; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_ARLEN = S00_AXI_arlen; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_ARLOCK = S00_AXI_arlock; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_ARPROT = S00_AXI_arprot; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_ARQOS = S00_AXI_arqos; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_ARSIZE = S00_AXI_arsize; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_ARVALID = S00_AXI_arvalid; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_AWADDR = S00_AXI_awaddr; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_AWBURST = S00_AXI_awburst; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_AWCACHE = S00_AXI_awcache; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_AWID = S00_AXI_awid; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_AWLEN = S00_AXI_awlen; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_AWLOCK = S00_AXI_awlock; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_AWPROT = S00_AXI_awprot; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_AWQOS = S00_AXI_awqos; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_AWSIZE = S00_AXI_awsize; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_AWVALID = S00_AXI_awvalid; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_BREADY = S00_AXI_bready; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_RREADY = S00_AXI_rready; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_WDATA = S00_AXI_wdata; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_WID = S00_AXI_wid; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_WLAST = S00_AXI_wlast; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_WSTRB = S00_AXI_wstrb; + assign z_turn_ps_7_axi_periph_1_to_s00_couplers_WVALID = S00_AXI_wvalid; + s00_couplers_imp_1N0XG9 s00_couplers + (.M_ACLK(z_turn_ps_7_axi_periph_1_ACLK_net), + .M_ARESETN(z_turn_ps_7_axi_periph_1_ARESETN_net), + .M_AXI_araddr(s00_couplers_to_z_turn_ps_7_axi_periph_1_ARADDR), + .M_AXI_arburst(s00_couplers_to_z_turn_ps_7_axi_periph_1_ARBURST), + .M_AXI_arcache(s00_couplers_to_z_turn_ps_7_axi_periph_1_ARCACHE), + .M_AXI_arid(s00_couplers_to_z_turn_ps_7_axi_periph_1_ARID), + .M_AXI_arlen(s00_couplers_to_z_turn_ps_7_axi_periph_1_ARLEN), + .M_AXI_arlock(s00_couplers_to_z_turn_ps_7_axi_periph_1_ARLOCK), + .M_AXI_arprot(s00_couplers_to_z_turn_ps_7_axi_periph_1_ARPROT), + .M_AXI_arqos(s00_couplers_to_z_turn_ps_7_axi_periph_1_ARQOS), + .M_AXI_arready(s00_couplers_to_z_turn_ps_7_axi_periph_1_ARREADY), + .M_AXI_arsize(s00_couplers_to_z_turn_ps_7_axi_periph_1_ARSIZE), + .M_AXI_arvalid(s00_couplers_to_z_turn_ps_7_axi_periph_1_ARVALID), + .M_AXI_awaddr(s00_couplers_to_z_turn_ps_7_axi_periph_1_AWADDR), + .M_AXI_awburst(s00_couplers_to_z_turn_ps_7_axi_periph_1_AWBURST), + .M_AXI_awcache(s00_couplers_to_z_turn_ps_7_axi_periph_1_AWCACHE), + .M_AXI_awid(s00_couplers_to_z_turn_ps_7_axi_periph_1_AWID), + .M_AXI_awlen(s00_couplers_to_z_turn_ps_7_axi_periph_1_AWLEN), + .M_AXI_awlock(s00_couplers_to_z_turn_ps_7_axi_periph_1_AWLOCK), + .M_AXI_awprot(s00_couplers_to_z_turn_ps_7_axi_periph_1_AWPROT), + .M_AXI_awqos(s00_couplers_to_z_turn_ps_7_axi_periph_1_AWQOS), + .M_AXI_awready(s00_couplers_to_z_turn_ps_7_axi_periph_1_AWREADY), + .M_AXI_awsize(s00_couplers_to_z_turn_ps_7_axi_periph_1_AWSIZE), + .M_AXI_awvalid(s00_couplers_to_z_turn_ps_7_axi_periph_1_AWVALID), + .M_AXI_bid(s00_couplers_to_z_turn_ps_7_axi_periph_1_BID), + .M_AXI_bready(s00_couplers_to_z_turn_ps_7_axi_periph_1_BREADY), + .M_AXI_bresp(s00_couplers_to_z_turn_ps_7_axi_periph_1_BRESP), + .M_AXI_bvalid(s00_couplers_to_z_turn_ps_7_axi_periph_1_BVALID), + .M_AXI_rdata(s00_couplers_to_z_turn_ps_7_axi_periph_1_RDATA), + .M_AXI_rid(s00_couplers_to_z_turn_ps_7_axi_periph_1_RID), + .M_AXI_rlast(s00_couplers_to_z_turn_ps_7_axi_periph_1_RLAST), + .M_AXI_rready(s00_couplers_to_z_turn_ps_7_axi_periph_1_RREADY), + .M_AXI_rresp(s00_couplers_to_z_turn_ps_7_axi_periph_1_RRESP), + .M_AXI_rvalid(s00_couplers_to_z_turn_ps_7_axi_periph_1_RVALID), + .M_AXI_wdata(s00_couplers_to_z_turn_ps_7_axi_periph_1_WDATA), + .M_AXI_wid(s00_couplers_to_z_turn_ps_7_axi_periph_1_WID), + .M_AXI_wlast(s00_couplers_to_z_turn_ps_7_axi_periph_1_WLAST), + .M_AXI_wready(s00_couplers_to_z_turn_ps_7_axi_periph_1_WREADY), + .M_AXI_wstrb(s00_couplers_to_z_turn_ps_7_axi_periph_1_WSTRB), + .M_AXI_wvalid(s00_couplers_to_z_turn_ps_7_axi_periph_1_WVALID), + .S_ACLK(S00_ACLK_1), + .S_ARESETN(S00_ARESETN_1), + .S_AXI_araddr(z_turn_ps_7_axi_periph_1_to_s00_couplers_ARADDR), + .S_AXI_arburst(z_turn_ps_7_axi_periph_1_to_s00_couplers_ARBURST), + .S_AXI_arcache(z_turn_ps_7_axi_periph_1_to_s00_couplers_ARCACHE), + .S_AXI_arid(z_turn_ps_7_axi_periph_1_to_s00_couplers_ARID), + .S_AXI_arlen(z_turn_ps_7_axi_periph_1_to_s00_couplers_ARLEN), + .S_AXI_arlock(z_turn_ps_7_axi_periph_1_to_s00_couplers_ARLOCK), + .S_AXI_arprot(z_turn_ps_7_axi_periph_1_to_s00_couplers_ARPROT), + .S_AXI_arqos(z_turn_ps_7_axi_periph_1_to_s00_couplers_ARQOS), + .S_AXI_arready(z_turn_ps_7_axi_periph_1_to_s00_couplers_ARREADY), + .S_AXI_arsize(z_turn_ps_7_axi_periph_1_to_s00_couplers_ARSIZE), + .S_AXI_arvalid(z_turn_ps_7_axi_periph_1_to_s00_couplers_ARVALID), + .S_AXI_awaddr(z_turn_ps_7_axi_periph_1_to_s00_couplers_AWADDR), + .S_AXI_awburst(z_turn_ps_7_axi_periph_1_to_s00_couplers_AWBURST), + .S_AXI_awcache(z_turn_ps_7_axi_periph_1_to_s00_couplers_AWCACHE), + .S_AXI_awid(z_turn_ps_7_axi_periph_1_to_s00_couplers_AWID), + .S_AXI_awlen(z_turn_ps_7_axi_periph_1_to_s00_couplers_AWLEN), + .S_AXI_awlock(z_turn_ps_7_axi_periph_1_to_s00_couplers_AWLOCK), + .S_AXI_awprot(z_turn_ps_7_axi_periph_1_to_s00_couplers_AWPROT), + .S_AXI_awqos(z_turn_ps_7_axi_periph_1_to_s00_couplers_AWQOS), + .S_AXI_awready(z_turn_ps_7_axi_periph_1_to_s00_couplers_AWREADY), + .S_AXI_awsize(z_turn_ps_7_axi_periph_1_to_s00_couplers_AWSIZE), + .S_AXI_awvalid(z_turn_ps_7_axi_periph_1_to_s00_couplers_AWVALID), + .S_AXI_bid(z_turn_ps_7_axi_periph_1_to_s00_couplers_BID), + .S_AXI_bready(z_turn_ps_7_axi_periph_1_to_s00_couplers_BREADY), + .S_AXI_bresp(z_turn_ps_7_axi_periph_1_to_s00_couplers_BRESP), + .S_AXI_bvalid(z_turn_ps_7_axi_periph_1_to_s00_couplers_BVALID), + .S_AXI_rdata(z_turn_ps_7_axi_periph_1_to_s00_couplers_RDATA), + .S_AXI_rid(z_turn_ps_7_axi_periph_1_to_s00_couplers_RID), + .S_AXI_rlast(z_turn_ps_7_axi_periph_1_to_s00_couplers_RLAST), + .S_AXI_rready(z_turn_ps_7_axi_periph_1_to_s00_couplers_RREADY), + .S_AXI_rresp(z_turn_ps_7_axi_periph_1_to_s00_couplers_RRESP), + .S_AXI_rvalid(z_turn_ps_7_axi_periph_1_to_s00_couplers_RVALID), + .S_AXI_wdata(z_turn_ps_7_axi_periph_1_to_s00_couplers_WDATA), + .S_AXI_wid(z_turn_ps_7_axi_periph_1_to_s00_couplers_WID), + .S_AXI_wlast(z_turn_ps_7_axi_periph_1_to_s00_couplers_WLAST), + .S_AXI_wready(z_turn_ps_7_axi_periph_1_to_s00_couplers_WREADY), + .S_AXI_wstrb(z_turn_ps_7_axi_periph_1_to_s00_couplers_WSTRB), + .S_AXI_wvalid(z_turn_ps_7_axi_periph_1_to_s00_couplers_WVALID)); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn_wrapper.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn_wrapper.v new file mode 100644 index 0000000..94d9908 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn_wrapper.v @@ -0,0 +1,224 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +//Date : Wed Jul 15 11:10:09 2015 +//Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +//Command : generate_target z_turn_wrapper.bd +//Design : z_turn_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module z_turn_wrapper + (BP, + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + HDMI_INTn, + I2S_DIN, + I2S_DOUT, + I2S_FSYNC_IN, + I2S_FSYNC_OUT, + I2S_SCLK, + IO_B34_LN, + IO_B34_LN11, + IO_B34_LN8, + IO_B34_LP, + IO_B34_LP11, + IO_B34_LP6, + IO_B34_LP8, + IO_B35_LN, + IO_B35_LP, + LCD_DATA, + LCD_DE, + LCD_HSYNC, + LCD_PCLK, + LCD_VSYNC, + LEDS, + MEMS_INTn, + SW, + iic_0_scl_io, + iic_0_sda_io); + output BP; + inout [14:0]DDR_addr; + inout [2:0]DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [3:0]DDR_dm; + inout [31:0]DDR_dq; + inout [3:0]DDR_dqs_n; + inout [3:0]DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0]FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + input HDMI_INTn; + input I2S_DIN; + output I2S_DOUT; + input I2S_FSYNC_IN; + output I2S_FSYNC_OUT; + output I2S_SCLK; + input [5:1]IO_B34_LN; + input IO_B34_LN11; + input IO_B34_LN8; + input [5:1]IO_B34_LP; + input IO_B34_LP11; + input IO_B34_LP6; + input IO_B34_LP8; + input [24:1]IO_B35_LN; + input [24:1]IO_B35_LP; + output [15:0]LCD_DATA; + output LCD_DE; + output LCD_HSYNC; + output LCD_PCLK; + output LCD_VSYNC; + output [2:0]LEDS; + input MEMS_INTn; + input [3:0]SW; + inout iic_0_scl_io; + inout iic_0_sda_io; + + wire BP; + wire [14:0]DDR_addr; + wire [2:0]DDR_ba; + wire DDR_cas_n; + wire DDR_ck_n; + wire DDR_ck_p; + wire DDR_cke; + wire DDR_cs_n; + wire [3:0]DDR_dm; + wire [31:0]DDR_dq; + wire [3:0]DDR_dqs_n; + wire [3:0]DDR_dqs_p; + wire DDR_odt; + wire DDR_ras_n; + wire DDR_reset_n; + wire DDR_we_n; + wire FIXED_IO_ddr_vrn; + wire FIXED_IO_ddr_vrp; + wire [53:0]FIXED_IO_mio; + wire FIXED_IO_ps_clk; + wire FIXED_IO_ps_porb; + wire FIXED_IO_ps_srstb; + wire HDMI_INTn; + wire I2S_DIN; + wire I2S_DOUT; + wire I2S_FSYNC_IN; + wire I2S_FSYNC_OUT; + wire I2S_SCLK; + wire [5:1]IO_B34_LN; + wire IO_B34_LN11; + wire IO_B34_LN8; + wire [5:1]IO_B34_LP; + wire IO_B34_LP11; + wire IO_B34_LP6; + wire IO_B34_LP8; + wire [24:1]IO_B35_LN; + wire [24:1]IO_B35_LP; + wire [15:0]LCD_DATA; + wire LCD_DE; + wire LCD_HSYNC; + wire LCD_PCLK; + wire LCD_VSYNC; + wire [2:0]LEDS; + wire MEMS_INTn; + wire [3:0]SW; + wire iic_0_scl_i; + wire iic_0_scl_io; + wire iic_0_scl_o; + wire iic_0_scl_t; + wire iic_0_sda_i; + wire iic_0_sda_io; + wire iic_0_sda_o; + wire iic_0_sda_t; + + IOBUF iic_0_scl_iobuf + (.I(iic_0_scl_o), + .IO(iic_0_scl_io), + .O(iic_0_scl_i), + .T(iic_0_scl_t)); + IOBUF iic_0_sda_iobuf + (.I(iic_0_sda_o), + .IO(iic_0_sda_io), + .O(iic_0_sda_i), + .T(iic_0_sda_t)); + z_turn z_turn_i + (.BP(BP), + .DDR_addr(DDR_addr), + .DDR_ba(DDR_ba), + .DDR_cas_n(DDR_cas_n), + .DDR_ck_n(DDR_ck_n), + .DDR_ck_p(DDR_ck_p), + .DDR_cke(DDR_cke), + .DDR_cs_n(DDR_cs_n), + .DDR_dm(DDR_dm), + .DDR_dq(DDR_dq), + .DDR_dqs_n(DDR_dqs_n), + .DDR_dqs_p(DDR_dqs_p), + .DDR_odt(DDR_odt), + .DDR_ras_n(DDR_ras_n), + .DDR_reset_n(DDR_reset_n), + .DDR_we_n(DDR_we_n), + .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), + .FIXED_IO_mio(FIXED_IO_mio), + .FIXED_IO_ps_clk(FIXED_IO_ps_clk), + .FIXED_IO_ps_porb(FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), + .HDMI_INTn(HDMI_INTn), + .I2S_DIN(I2S_DIN), + .I2S_DOUT(I2S_DOUT), + .I2S_FSYNC_IN(I2S_FSYNC_IN), + .I2S_FSYNC_OUT(I2S_FSYNC_OUT), + .I2S_SCLK(I2S_SCLK), + .IIC_0_scl_i(iic_0_scl_i), + .IIC_0_scl_o(iic_0_scl_o), + .IIC_0_scl_t(iic_0_scl_t), + .IIC_0_sda_i(iic_0_sda_i), + .IIC_0_sda_o(iic_0_sda_o), + .IIC_0_sda_t(iic_0_sda_t), + .IO_B34_LN(IO_B34_LN), + .IO_B34_LN11(IO_B34_LN11), + .IO_B34_LN8(IO_B34_LN8), + .IO_B34_LP(IO_B34_LP), + .IO_B34_LP11(IO_B34_LP11), + .IO_B34_LP6(IO_B34_LP6), + .IO_B34_LP8(IO_B34_LP8), + .IO_B35_LN(IO_B35_LN), + .IO_B35_LP(IO_B35_LP), + .LCD_DATA(LCD_DATA), + .LCD_DE(LCD_DE), + .LCD_HSYNC(LCD_HSYNC), + .LCD_PCLK(LCD_PCLK), + .LCD_VSYNC(LCD_VSYNC), + .LEDS(LEDS), + .MEMS_INTn(MEMS_INTn), + .SW(SW)); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hw_handoff/z_turn.hwh b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hw_handoff/z_turn.hwh new file mode 100644 index 0000000..bdee514 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hw_handoff/z_turn.hwh @@ -0,0 +1,3298 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hw_handoff/z_turn_bd.tcl b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hw_handoff/z_turn_bd.tcl new file mode 100644 index 0000000..ddf6f60 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hw_handoff/z_turn_bd.tcl @@ -0,0 +1,300 @@ + +################################################################ +# This is a generated script based on design: z_turn +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2015.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source z_turn_script.tcl + +# If you do not already have a project created, +# you can create a project using the following command: +# create_project project_1 myproj -part xc7z020clg400-1 + +# CHECKING IF PROJECT EXISTS +if { [get_projects -quiet] eq "" } { + puts "ERROR: Please open or create a project!" + return 1 +} + + + +# CHANGE DESIGN NAME HERE +set design_name z_turn + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "ERROR: Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + puts "INFO: Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + puts "INFO: Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + puts "INFO: Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + puts "INFO: Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +puts "INFO: Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + puts $errMsg + return $nRet +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + set IIC_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_0 ] + + # Create ports + set BP [ create_bd_port -dir O BP ] + set HDMI_INTn [ create_bd_port -dir I HDMI_INTn ] + set I2S_DIN [ create_bd_port -dir I I2S_DIN ] + set I2S_DOUT [ create_bd_port -dir O I2S_DOUT ] + set I2S_FSYNC_IN [ create_bd_port -dir I I2S_FSYNC_IN ] + set I2S_FSYNC_OUT [ create_bd_port -dir O I2S_FSYNC_OUT ] + set I2S_SCLK [ create_bd_port -dir O -type clk I2S_SCLK ] + set IO_B34_LN [ create_bd_port -dir I -from 5 -to 1 IO_B34_LN ] + set IO_B34_LN8 [ create_bd_port -dir I IO_B34_LN8 ] + set IO_B34_LN11 [ create_bd_port -dir I IO_B34_LN11 ] + set IO_B34_LP [ create_bd_port -dir I -from 5 -to 1 IO_B34_LP ] + set IO_B34_LP6 [ create_bd_port -dir I IO_B34_LP6 ] + set IO_B34_LP8 [ create_bd_port -dir I IO_B34_LP8 ] + set IO_B34_LP11 [ create_bd_port -dir I -type clk IO_B34_LP11 ] + set_property -dict [ list CONFIG.FREQ_HZ {50000000} ] $IO_B34_LP11 + set IO_B35_LN [ create_bd_port -dir I -from 24 -to 1 -type data IO_B35_LN ] + set IO_B35_LP [ create_bd_port -dir I -from 24 -to 1 -type data IO_B35_LP ] + set LCD_DATA [ create_bd_port -dir O -from 15 -to 0 -type data LCD_DATA ] + set LCD_DE [ create_bd_port -dir O LCD_DE ] + set LCD_HSYNC [ create_bd_port -dir O LCD_HSYNC ] + set LCD_PCLK [ create_bd_port -dir O -type clk LCD_PCLK ] + set LCD_VSYNC [ create_bd_port -dir O LCD_VSYNC ] + set LEDS [ create_bd_port -dir O -from 2 -to 0 LEDS ] + set MEMS_INTn [ create_bd_port -dir I MEMS_INTn ] + set SW [ create_bd_port -dir I -from 3 -to 0 SW ] + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: proc_sys_reset_1, and set properties + set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] + + # Create instance: proc_sys_reset_2, and set properties + set proc_sys_reset_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_2 ] + + # Create instance: proc_sys_reset_3, and set properties + set proc_sys_reset_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_3 ] + + # Create instance: ps7, and set properties + set ps7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 ps7 ] + set_property -dict [ list CONFIG.PCW_CAN0_CAN0_IO {MIO 14 .. 15} \ +CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ +CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_ENET_RESET_ENABLE {0} CONFIG.PCW_EN_CLK1_PORT {1} \ +CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} \ +CONFIG.PCW_EN_RST1_PORT {1} CONFIG.PCW_EN_RST2_PORT {1} \ +CONFIG.PCW_EN_RST3_PORT {1} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {166.667} \ +CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100} CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ +CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} CONFIG.PCW_I2C1_I2C1_IO {MIO 12 .. 13} \ +CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} CONFIG.PCW_I2C_RESET_ENABLE {0} \ +CONFIG.PCW_IRQ_F2P_INTR {1} CONFIG.PCW_MIO_51_PULLUP {disabled} \ +CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ +CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SD0_GRP_CD_ENABLE {1} CONFIG.PCW_SD0_GRP_CD_IO {MIO 46} \ +CONFIG.PCW_SD0_GRP_WP_ENABLE {1} CONFIG.PCW_SD0_GRP_WP_IO {MIO 47} \ +CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ +CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} CONFIG.PCW_UART0_UART0_IO { + + + + + + +
Zynq Register View +
+
+ +
MIO Registers +
+ + +
PLL Registers +
+ + +
Clock Registers +
+ + +
DDR Registers +
+ + +
Peripherals Registers +
+ +
+
This design is targeted for xc7z020 board (part number: xc7z020clg400-1) + +
+

Zynq Design Summary

+ + + + + + + + + + + + + + + + + + + + + +
+Device + +xc7z020 +
+SpeedGrade + +-1 +
+Part + +xc7z020clg400-1 +
+Description + +Zynq PS Configuration Report with register details +
+Vendor + +Xilinx +
+

MIO Table View

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
+MIO 0 + +GPIO + +gpio[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
+MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
+MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
+MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
+MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
+MIO 5 + +Quad SPI Flash + +qspi0_io[3] + +LVCMOS 3.3V + +slow + +disabled + +inout +
+MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
+MIO 7 + +GPIO + +gpio[7] + +LVCMOS 3.3V + +slow + +disabled + +out +
+MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
+MIO 9 + +GPIO + +gpio[9] + +LVCMOS 3.3V + +slow + +enabled + +inout +
+MIO 10 + +GPIO + +gpio[10] + +LVCMOS 3.3V + +slow + +enabled + +inout +
+MIO 11 + +GPIO + +gpio[11] + +LVCMOS 3.3V + +slow + +enabled + +inout +
+MIO 12 + +I2C 1 + +scl + +LVCMOS 3.3V + +slow + +enabled + +inout +
+MIO 13 + +I2C 1 + +sda + +LVCMOS 3.3V + +slow + +enabled + +inout +
+MIO 14 + +CAN 0 + +rx + +LVCMOS 3.3V + +slow + +enabled + +in +
+MIO 15 + +CAN 0 + +tx + +LVCMOS 3.3V + +slow + +enabled + +out +
+MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
+MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
+MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
+MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
+MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
+MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
+MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 28 + +USB 0 + +data[4] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 29 + +USB 0 + +dir + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 30 + +USB 0 + +stp + +LVCMOS 1.8V + +slow + +enabled + +out +
+MIO 31 + +USB 0 + +nxt + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 32 + +USB 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 33 + +USB 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 34 + +USB 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 35 + +USB 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 36 + +USB 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 37 + +USB 0 + +data[5] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 38 + +USB 0 + +data[6] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 39 + +USB 0 + +data[7] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 46 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 47 + +SD 0 + +wp + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
+MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
+MIO 50 + +GPIO + +gpio[50] + +LVCMOS 1.8V + +slow + +enabled + +inout +
+MIO 51 + +USB Reset + +reset + +LVCMOS 1.8V + +slow + +disabled + +out +
+MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
+MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
+

DDR Memory information

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Parameter name + +Value + +Description +
+Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
+Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
+Memory Part + +MT41K256M16 RE-15E + + +
+DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
+ECC + +Disabled + +ECC is supported only for data width of 16-bit +
+BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
+Internal Vref + +0 + + +
+Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
+HIGH temperature + +Normal (0-85) + +Select the operating temparature +
+DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
+DRAM Device Capacity + +4096 MBits + + +
+Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
+BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
+ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
+COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
+CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
+CAS Write Latency + +6 + +Select the CAS Write Latency +
+RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
+RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
+tRC (ns ) + +49.5 + +Provide the Row cycle time tRC (ns) +
+tRASmin ( ns ) + +36.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
+tFAW + +45.0 + +It restricts the number of activates that can be done within a certain window of time +
+ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
+Write levelling + +1 + + +
+Read gate + +1 + + +
+Read gate + +1 + + +
+DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
+DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
+DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
+DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
+Board delay [0] (ns) + +0.0 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
+Board delay [1] (ns) + +0.0 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
+Board delay [2] (ns) + +0.0 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
+Board delay [3] (ns) + +0.0 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
+

PS Clocks information

+

PS Reference Clock : 33.333333

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Peripheral + +PLL source + +Frequency (MHz) +
+CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
+QSPI Flash Freq (MHz) + +IO PLL + +200.000000 +
+ENET0 Freq (MHz) + +IO PLL + +125.000000 +
+SDIO Freq (MHz) + +IO PLL + +100.000000 +
+UART Freq (MHz) + +IO PLL + +100.000000 +
+CAN Freq (MHz) + +IO PLL + +100.000000 +
+FPGA0 Freq (MHz) + +IO PLL + +166.666672 +
+FPGA1 Freq (MHz) + +IO PLL + +50.000000 +
+FPGA2 Freq (MHz) + +IO PLL + +100.000000 +
+FPGA3 Freq (MHz) + +IO PLL + +200.000000 +
+

ps7_pll_init_data_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
+ +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
+ +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_pll_init_data_3_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

PLL SLCR REGISTERS

+

ARM PLL INIT

+

Register ( slcr )ARM_PLL_CFG

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
+LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
+ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
+

+

UPDATE FB_DIV

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
+

+

BY PASS PLL

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
+

+

ASSERT RESET

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
+

+

DEASSERT RESET

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
+

+

CHECK PLL STATUS

+

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
+PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
+

+

REMOVE PLL BY PASS

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
+

+

Register ( slcr )ARM_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
+DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
+CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
+CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
+CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
+CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
+CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
+ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
+

+

DDR PLL INIT

+

Register ( slcr )DDR_PLL_CFG

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
+LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
+DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
+

+

UPDATE FB_DIV

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
+

+

BY PASS PLL

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
+

+

ASSERT RESET

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
+

+

DEASSERT RESET

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
+

+

CHECK PLL STATUS

+

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
+PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
+

+

REMOVE PLL BY PASS

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
+

+

Register ( slcr )DDR_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
+DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
+DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
+DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
+DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
+

+

IO PLL INIT

+

Register ( slcr )IO_PLL_CFG

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
+LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
+IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
+

+

UPDATE FB_DIV

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
+

+

BY PASS PLL

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
+

+

ASSERT RESET

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
+

+

DEASSERT RESET

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
+

+

CHECK PLL STATUS

+

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
+PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
+

+

REMOVE PLL BY PASS

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
+

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_clock_init_data_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
+ +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
+ +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
+ +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
+ +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
+ +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
+ +CAN_CLK_CTRL + + +0XF800015C + +32 + +RW + +0x000000 + +CAN Ref Clock Control +
+ +CAN_MIOCLK_CTRL + + +0XF8000160 + +32 + +RW + +0x000000 + +CAN MIO Clock Control +
+ +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
+ +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
+ +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
+ +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
+ +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
+ +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
+ +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_clock_init_data_3_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

CLOCK CONTROL SLCR REGISTERS

+

Register ( slcr )DCI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
+DIVISOR0 + +13:8 + +3f00 + +23 + +2300 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+DIVISOR1 + +25:20 + +3f00000 + +3 + +300000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +302301 + +DCI clock control +
+

+

Register ( slcr )GEM0_RCLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
+SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
+GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
+

+

Register ( slcr )GEM0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
+SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
+DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
+GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
+

+

Register ( slcr )LQSPI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
+LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
+

+

Register ( slcr )SDIO_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
+CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
+

+

Register ( slcr )UART_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
+CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
+DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
+UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
+

+

Register ( slcr )CAN_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CAN_CLK_CTRL + +0XF800015C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +1 + +1 + +CAN 0 Reference Clock active: 0: Clock is disabled 1: Clock is enabled +
+CLKACT1 + +1:1 + +2 + +0 + +0 + +CAN 1 Reference Clock active: 0: Clock is disabled 1: Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider. +
+CAN_CLK_CTRL@0XF800015C + +31:0 + +3f03f33 + + + +100a01 + +CAN Ref Clock Control +
+

+

Register ( slcr )CAN_MIOCLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CAN_MIOCLK_CTRL + +0XF8000160 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CAN0_MUX + +5:0 + +3f + +0 + +0 + +CAN 0 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. +
+CAN0_REF_SEL + +6:6 + +40 + +0 + +0 + +CAN 0 Reference Clock selection: 0: From internal PLL 1: From MIO based on the next field +
+CAN1_MUX + +21:16 + +3f0000 + +0 + +0 + +CAN 1 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. +
+CAN1_REF_SEL + +22:22 + +400000 + +0 + +0 + +CAN 1 Reference Clock selection: 0: From internal PLL. 1: From MIO based on the next field +
+CAN_MIOCLK_CTRL@0XF8000160 + +31:0 + +7f007f + + + +0 + +CAN MIO Clock Control +
+

+

TRACE CLOCK

+

Register ( slcr )PCAP_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
+

+

Register ( slcr )FPGA0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +6 + +600 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +100600 + +PL Clock 0 Output control +
+

+

Register ( slcr )FPGA1_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +101400 + +PL Clock 1 Output control +
+

+

Register ( slcr )FPGA2_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +100a00 + +PL Clock 2 output control +
+

+

Register ( slcr )FPGA3_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
+

+

Register ( slcr )CLK_621_TRUE

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
+CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
+

+

Register ( slcr )APER_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
+USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
+USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
+GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
+GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
+SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
+SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
+SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
+SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
+CAN0_CPU_1XCLKACT + +16:16 + +10000 + +1 + +10000 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
+CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
+I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
+I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
+UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
+UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
+GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
+LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
+SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
+APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ed044d + +AMBA Peripheral Clock Control +
+

+

THIS SHOULD BE BLANK

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_ddr_init_data_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
+ +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
+ +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
+ +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
+ +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
+ +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
+ +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
+ +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
+ +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
+ +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
+ +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
+ +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
+ +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
+ +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
+ +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
+ +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
+ +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
+ +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
+ +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
+ +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
+ +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
+ +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
+ +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
+ +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
+ +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
+ +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
+ +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
+ +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
+ +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
+ +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
+ +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
+ +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
+ +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
+ +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
+ +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
+ +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
+ +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
+ +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
+ +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
+ +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
+ +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
+ +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
+ +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
+ +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
+ +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
+ +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
+ +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
+ +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
+ +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
+ +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
+ +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
+ +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
+ +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
+ +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
+ +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
+ +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
+ +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
+ +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
+ +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
+ +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
+ +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
+ +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
+ +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
+ +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
+ +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
+ +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
+ +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
+ +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
+ +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
+ +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
+ +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
+ +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
+ +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
+ +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
+

+

ps7_ddr_init_data_3_0

+ + + + + + + + + +

DDR INITIALIZATION

+

LOCK DDR

+

Register ( slcr )ddrc_ctrl

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
+

+

Register ( slcr )Two_rank_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
+reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
+reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
+Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1081 + +Two Rank Configuration +
+

+

Register ( slcr )HPR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
+reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
+reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
+HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
+

+

Register ( slcr )LPR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
+reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
+reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
+LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
+

+

Register ( slcr )WR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
+reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
+reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
+WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
+

+

Register ( slcr )DRAM_param_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
+reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
+reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
+DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281b + +DRAM Parameters 0 +
+

+

Register ( slcr )DRAM_param_reg1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
+reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
+reg_ddrc_t_faw + +15:10 + +fc00 + +18 + +6000 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
+reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
+reg_ddrc_t_ras_min + +26:22 + +7c00000 + +14 + +5000000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
+reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
+DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +452460d2 + +DRAM Parameters 1 +
+

+

Register ( slcr )DRAM_param_reg2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
+reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
+reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
+reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
+reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
+reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
+reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
+DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
+

+

Register ( slcr )DRAM_param_reg3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
+reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
+reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
+reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
+reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
+reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
+reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
+reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
+reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
+reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
+DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
+

+

Register ( slcr )DRAM_param_reg4

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
+reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
+reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
+reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
+reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
+ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
+reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
+reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
+DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
+

+

Register ( slcr )DRAM_init_param

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
+reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
+reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
+DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
+

+

Register ( slcr )DRAM_EMR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
+reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
+DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
+

+

Register ( slcr )DRAM_EMR_MR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
+reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
+DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
+

+

Register ( slcr )DRAM_burst8_rdwr

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
+reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +105 + +1050 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
+reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
+reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
+DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +11054 + +DRAM Burst 8 read/write +
+

+

Register ( slcr )DRAM_disable_DQ

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
+reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
+DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
+

+

Register ( slcr )DRAM_addr_map_bank

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
+reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
+DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
+

+

Register ( slcr )DRAM_addr_map_col

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
+

+

Register ( slcr )DRAM_addr_map_row

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
+reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
+reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
+reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
+reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
+DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
+

+

Register ( slcr )DRAM_ODT_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
+reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
+reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
+reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
+reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
+DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
+

+

Register ( slcr )phy_cmd_timeout_rddata_cpt

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
+reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
+reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
+reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
+reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
+reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
+reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
+

+

Register ( slcr )DLL_calib

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
+DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
+

+

Register ( slcr )ODT_delay_hold

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
+reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
+reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
+reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
+ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
+

+

Register ( slcr )ctrl_reg1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
+reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
+reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
+reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
+reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
+reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
+reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
+ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
+

+

Register ( slcr )ctrl_reg2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
+reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
+ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
+

+

Register ( slcr )ctrl_reg3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
+reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
+reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
+ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
+

+

Register ( slcr )ctrl_reg4

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
+dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
+ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
+

+

Register ( slcr )ctrl_reg5

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
+reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
+reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
+ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
+

+

Register ( slcr )ctrl_reg6

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
+ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
+

+

Register ( slcr )CHE_T_ZQ

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
+reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
+reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
+reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
+reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
+CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
+

+

Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
+dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
+

+

Register ( slcr )deep_pwrdwn_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
+deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
+deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
+

+

Register ( slcr )reg_2c

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
+ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
+reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
+reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
+reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
+reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
+

+

Register ( slcr )reg_2d

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
+reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
+

+

Register ( slcr )dfi_timing

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
+reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
+reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
+dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
+

+

RESET ECC ERROR

+

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +1 + +1 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
+Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +1 + +2 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +3 + +ECC error clear +
+

+

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
+Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
+

+

Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
+ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
+

+

Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
+

+

Register ( slcr )CHE_ECC_STATS_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
+STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
+

+

Register ( slcr )ECC_scrub

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
+reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
+ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
+

+

Register ( slcr )phy_rcvr_enable

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
+reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
+phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
+

+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
+

+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
+

+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
+

+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
+

+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 0. +
+

+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 0. +
+

+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 0. +
+

+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 0. +
+

+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
+phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +b5 + +PHY FIFO write enable configuration for data slice 0. +
+

+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
+phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +b5 + +PHY FIFO write enable configuration for data slice 0. +
+

+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
+phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +b5 + +PHY FIFO write enable configuration for data slice 0. +
+

+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
+phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +b5 + +PHY FIFO write enable configuration for data slice 0. +
+

+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
+

+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
+

+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
+

+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
+

+

Register ( slcr )reg_64

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
+reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
+reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
+reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
+reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
+reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
+reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
+reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
+reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
+reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
+reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
+

+

Register ( slcr )reg_65

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
+reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
+reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
+reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
+reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
+reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
+reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
+

+

Register ( slcr )page_mask

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
+page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
+

+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
+

+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
+

+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
+

+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
+

+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

+

Register ( slcr )lpddr_ctrl0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
+reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
+reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
+lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
+

+

Register ( slcr )lpddr_ctrl1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
+lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
+

+

Register ( slcr )lpddr_ctrl2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
+reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
+reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
+lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
+

+

Register ( slcr )lpddr_ctrl3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
+reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
+lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
+

+

POLL ON DCI STATUS

+

Register ( slcr )DDRIOB_DCI_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
+DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
+

+

UNLOCK DDR

+

Register ( slcr )ddrc_ctrl

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
+

+

CHECK DDR STATUS

+

Register ( slcr )mode_sts_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
+mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
+

+ +

+

ps7_mio_init_data_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
+ +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
+ +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
+ +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
+ +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
+ +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
+ +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
+ +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
+ +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
+ +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
+ +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
+ +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
+ +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
+ +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
+ +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
+ +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
+ +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
+ +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
+ +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
+ +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
+ +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
+ +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_mio_init_data_3_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

OCM REMAPPING

+

DDRIOB SETTINGS

+

Register ( slcr )DDRIOB_ADDR0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
+

+

Register ( slcr )DDRIOB_ADDR1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
+

+

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
+

+

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
+

+

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
+

+

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
+

+

Register ( slcr )DDRIOB_CLOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
+reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
+reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
+reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
+reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
+reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
+reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
+reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
+reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
+reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
+reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
+reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
+reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
+reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
+reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
+reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
+reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
+

+

Register ( slcr )DDRIOB_DDR_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
+VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
+VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
+reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
+REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
+reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
+reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
+DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
+

+

ASSERT RESET

+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
+

+

DEASSERT RESET

+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
+reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
+

+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
+ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
+reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
+reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
+reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
+reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
+NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
+NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
+NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
+PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
+PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
+UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
+reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
+

+

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

+

Register ( slcr )MIO_PIN_12

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1640 + +MIO Pin 12 Control +
+

+

Register ( slcr )MIO_PIN_13

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1640 + +MIO Pin 13 Control +
+

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1621 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1620 + +MIO Pin 15 Control +
+

+

Register ( slcr )MIO_PIN_16

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
+

+

Register ( slcr )MIO_PIN_17

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
+

+

Register ( slcr )MIO_PIN_18

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
+

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
+

+

Register ( slcr )MIO_PIN_21

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
+

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1204 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1205 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1204 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1205 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1204 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1204 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1204 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1204 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1205 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1204 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1204 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1204 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +200 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
+

+

Register ( slcr )SD0_WP_CD_SEL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SDIO0_WP_SEL + +5:0 + +3f + +2f + +2f + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
+SDIO0_CD_SEL + +21:16 + +3f0000 + +2e + +2e0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
+SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2e002f + +SDIO 0 WP CD select +
+

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_peripherals_init_data_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
+ +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
+ +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
+ +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+ +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
+ +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
+ +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
+ +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
+ +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
+ +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+ +DIRM_1 + + +0XE000A244 + +32 + +RW + +0x000000 + +Direction mode (GPIO Bank1, MIO) +
+ +MASK_DATA_1_MSW + + +0XE000A00C + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+ +OEN_1 + + +0XE000A248 + +32 + +RW + +0x000000 + +Output enable (GPIO Bank1, MIO) +
+ +MASK_DATA_1_MSW + + +0XE000A00C + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+ +MASK_DATA_1_MSW + + +0XE000A00C + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+

+

ps7_peripherals_init_data_3_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

DDR TERM/IBUF_DISABLE_MODE SETTINGS

+

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
+

+

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
+

+

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
+

+

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
+

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+

SRAM/NOR SET OPMODE

+

UART REGISTERS

+

Register ( slcr )Baud_rate_divider_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
+Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
+

+

Register ( slcr )Baud_rate_gen_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
+Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
+

+

Register ( slcr )Control_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
+STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
+RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
+TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
+TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
+RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
+RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
+TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
+RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
+Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
+

+

Register ( slcr )mode_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
+NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
+PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
+CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
+CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
+mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
+

+

QSPI REGISTERS

+

Register ( slcr )Config_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
+Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
+

+

PL POWER ON RESET REGISTERS

+

Register ( slcr )CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
+CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+

+

SMC TIMING CALCULATION REGISTER UPDATE

+

NAND SET CYCLE

+

OPMODE

+

DIRECT COMMAND

+

SRAM/NOR CS0 SET CYCLE

+

DIRECT COMMAND

+

NOR CS0 BASE ADDRESS

+

SRAM/NOR CS1 SET CYCLE

+

DIRECT COMMAND

+

NOR CS1 BASE ADDRESS

+

USB RESET

+

USB0 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

Register ( slcr )DIRM_1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DIRM_1 + +0XE000A244 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DIRECTION_1 + +21:0 + +3fffff + +80000 + +80000 + +Operation is the same as DIRM_0[DIRECTION_0] +
+DIRM_1@0XE000A244 + +31:0 + +3fffff + + + +80000 + +Direction mode (GPIO Bank1, MIO) +
+

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

Register ( slcr )MASK_DATA_1_MSW

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MASK_DATA_1_MSW + +0XE000A00C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_1_MSW + +21:16 + +3f0000 + +37 + +370000 + +Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +
+DATA_1_MSW + +5:0 + +3f + +8 + +8 + +Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +
+MASK_DATA_1_MSW@0XE000A00C + +31:0 + +3f003f + + + +370008 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

Register ( slcr )OEN_1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+OEN_1 + +0XE000A248 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+OP_ENABLE_1 + +21:0 + +3fffff + +80000 + +80000 + +Operation is the same as OEN_0[OP_ENABLE_0] +
+OEN_1@0XE000A248 + +31:0 + +3fffff + + + +80000 + +Output enable (GPIO Bank1, MIO) +
+

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

Register ( slcr )MASK_DATA_1_MSW

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MASK_DATA_1_MSW + +0XE000A00C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_1_MSW + +21:16 + +3f0000 + +37 + +370000 + +Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +
+DATA_1_MSW + +5:0 + +3f + +0 + +0 + +Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +
+MASK_DATA_1_MSW@0XE000A00C + +31:0 + +3f003f + + + +370000 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

Register ( slcr )MASK_DATA_1_MSW

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MASK_DATA_1_MSW + +0XE000A00C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_1_MSW + +21:16 + +3f0000 + +37 + +370000 + +Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +
+DATA_1_MSW + +5:0 + +3f + +8 + +8 + +Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +
+MASK_DATA_1_MSW@0XE000A00C + +31:0 + +3f003f + + + +370008 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+

+

USB1 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

ENET RESET

+

ENET0 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

ENET1 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

I2C RESET

+

I2C0 RESET

+

DIR MODE GPIO BANK0

+

DIR MODE GPIO BANK1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE

+

OUTPUT ENABLE

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

I2C1 RESET

+

DIR MODE GPIO BANK0

+

DIR MODE GPIO BANK1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE

+

OUTPUT ENABLE

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

NOR CHIP SELECT

+

DIR MODE BANK 0

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

OUTPUT ENABLE BANK 0

+ +

+

ps7_post_config_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
+ +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_post_config_3_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

ENABLING LEVEL SHIFTER

+

Register ( slcr )LVL_SHFTR_EN

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
+USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
+USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
+USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
+LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
+

+

FPGA RESETS TO 0

+

Register ( slcr )FPGA_RST_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
+reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
+reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
+reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
+reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
+FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
+FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
+FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
+FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
+

+

AFI REGISTERS

+

AFI0 REGISTERS

+

AFI1 REGISTERS

+

AFI2 REGISTERS

+

AFI3 REGISTERS

+

AFI2 SECURE REGISTER

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_debug_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
+ +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
+ +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
+

+

ps7_debug_3_0

+ + + + + + + + + +

CROSS TRIGGER CONFIGURATIONS

+

UNLOCKING CTI REGISTERS

+

Register ( slcr )LAR

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

+

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

+

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

+

ENABLING CTI MODULES AND CHANNELS

+

MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

+ +

+ + + + +

ps7_pll_init_data_2_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
+ +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
+ +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_pll_init_data_2_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

PLL SLCR REGISTERS

+

ARM PLL INIT

+

Register ( slcr )ARM_PLL_CFG

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
+LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
+ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
+

+

UPDATE FB_DIV

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
+

+

BY PASS PLL

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
+

+

ASSERT RESET

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
+

+

DEASSERT RESET

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
+

+

CHECK PLL STATUS

+

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
+PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
+

+

REMOVE PLL BY PASS

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
+

+

Register ( slcr )ARM_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
+DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
+CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
+CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
+CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
+CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
+CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
+ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
+

+

DDR PLL INIT

+

Register ( slcr )DDR_PLL_CFG

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
+LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
+DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
+

+

UPDATE FB_DIV

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
+

+

BY PASS PLL

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
+

+

ASSERT RESET

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
+

+

DEASSERT RESET

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
+

+

CHECK PLL STATUS

+

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
+PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
+

+

REMOVE PLL BY PASS

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
+

+

Register ( slcr )DDR_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
+DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
+DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
+DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
+DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
+

+

IO PLL INIT

+

Register ( slcr )IO_PLL_CFG

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
+LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
+IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
+

+

UPDATE FB_DIV

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
+

+

BY PASS PLL

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
+

+

ASSERT RESET

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
+

+

DEASSERT RESET

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
+

+

CHECK PLL STATUS

+

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
+PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
+

+

REMOVE PLL BY PASS

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
+

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_clock_init_data_2_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
+ +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
+ +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
+ +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
+ +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
+ +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
+ +CAN_CLK_CTRL + + +0XF800015C + +32 + +RW + +0x000000 + +CAN Ref Clock Control +
+ +CAN_MIOCLK_CTRL + + +0XF8000160 + +32 + +RW + +0x000000 + +CAN MIO Clock Control +
+ +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
+ +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
+ +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +PL Clock 1 Output control +
+ +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +PL Clock 2 output control +
+ +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +PL Clock 3 output control +
+ +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
+ +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_clock_init_data_2_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

CLOCK CONTROL SLCR REGISTERS

+

Register ( slcr )DCI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
+DIVISOR0 + +13:8 + +3f00 + +23 + +2300 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+DIVISOR1 + +25:20 + +3f00000 + +3 + +300000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +302301 + +DCI clock control +
+

+

Register ( slcr )GEM0_RCLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
+SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
+GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
+

+

Register ( slcr )GEM0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
+SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
+DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
+GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
+

+

Register ( slcr )LQSPI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
+LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
+

+

Register ( slcr )SDIO_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
+CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
+

+

Register ( slcr )UART_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
+CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
+DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
+UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
+

+

Register ( slcr )CAN_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CAN_CLK_CTRL + +0XF800015C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +1 + +1 + +CAN 0 Reference Clock active: 0: Clock is disabled 1: Clock is enabled +
+CLKACT1 + +1:1 + +2 + +0 + +0 + +CAN 1 Reference Clock active: 0: Clock is disabled 1: Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider. +
+CAN_CLK_CTRL@0XF800015C + +31:0 + +3f03f33 + + + +100a01 + +CAN Ref Clock Control +
+

+

Register ( slcr )CAN_MIOCLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CAN_MIOCLK_CTRL + +0XF8000160 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CAN0_MUX + +5:0 + +3f + +0 + +0 + +CAN 0 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. +
+CAN0_REF_SEL + +6:6 + +40 + +0 + +0 + +CAN 0 Reference Clock selection: 0: From internal PLL 1: From MIO based on the next field +
+CAN1_MUX + +21:16 + +3f0000 + +0 + +0 + +CAN 1 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. +
+CAN1_REF_SEL + +22:22 + +400000 + +0 + +0 + +CAN 1 Reference Clock selection: 0: From internal PLL. 1: From MIO based on the next field +
+CAN_MIOCLK_CTRL@0XF8000160 + +31:0 + +7f007f + + + +0 + +CAN MIO Clock Control +
+

+

TRACE CLOCK

+

Register ( slcr )PCAP_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
+

+

Register ( slcr )FPGA0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +6 + +600 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +100600 + +PL Clock 0 Output control +
+

+

Register ( slcr )FPGA1_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +101400 + +PL Clock 1 Output control +
+

+

Register ( slcr )FPGA2_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +100a00 + +PL Clock 2 output control +
+

+

Register ( slcr )FPGA3_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +PL Clock 3 output control +
+

+

Register ( slcr )CLK_621_TRUE

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
+CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
+

+

Register ( slcr )APER_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
+USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
+USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
+GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
+GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
+SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
+SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
+SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
+SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
+CAN0_CPU_1XCLKACT + +16:16 + +10000 + +1 + +10000 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
+CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
+I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
+I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
+UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
+UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
+GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
+LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
+SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
+APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ed044d + +AMBA Peripheral Clock Control +
+

+

THIS SHOULD BE BLANK

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_ddr_init_data_2_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
+ +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
+ +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
+ +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
+ +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
+ +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
+ +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
+ +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
+ +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
+ +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
+ +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
+ +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
+ +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
+ +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
+ +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
+ +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
+ +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
+ +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
+ +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
+ +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
+ +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
+ +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
+ +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
+ +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
+ +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
+ +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
+ +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
+ +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
+ +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
+ +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
+ +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
+ +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
+ +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
+ +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
+ +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
+ +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
+ +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
+ +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
+ +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
+ +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
+ +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
+ +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
+ +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
+ +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
+ +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
+ +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
+ +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
+ +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
+ +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
+ +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
+ +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
+ +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
+ +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
+ +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
+ +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
+ +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
+ +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
+ +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
+ +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
+ +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
+ +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
+ +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
+ +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
+ +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
+ +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
+ +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
+ +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
+ +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
+ +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
+ +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
+ +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
+ +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
+ +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
+ +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
+ +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
+ +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
+ +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
+ +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
+ +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
+ +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
+

+

ps7_ddr_init_data_2_0

+ + + + + + + + + +

DDR INITIALIZATION

+

LOCK DDR

+

Register ( slcr )ddrc_ctrl

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
+

+

Register ( slcr )Two_rank_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
+reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
+reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
+reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
+reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
+reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
+reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
+reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
+Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two Rank Configuration +
+

+

Register ( slcr )HPR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
+reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
+reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
+HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
+

+

Register ( slcr )LPR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
+reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
+reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
+LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
+

+

Register ( slcr )WR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
+reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
+reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
+WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
+

+

Register ( slcr )DRAM_param_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
+reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
+reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
+DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281b + +DRAM Parameters 0 +
+

+

Register ( slcr )DRAM_param_reg1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
+reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
+reg_ddrc_t_faw + +15:10 + +fc00 + +18 + +6000 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
+reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
+reg_ddrc_t_ras_min + +26:22 + +7c00000 + +14 + +5000000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
+reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
+DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +452460d2 + +DRAM Parameters 1 +
+

+

Register ( slcr )DRAM_param_reg2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
+reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
+reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
+reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
+reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
+reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
+reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
+DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
+

+

Register ( slcr )DRAM_param_reg3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
+reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
+reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
+reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
+reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
+reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
+reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
+reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
+reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
+reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
+reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
+reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
+DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
+

+

Register ( slcr )DRAM_param_reg4

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
+reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
+reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
+reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
+reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
+reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
+ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
+reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
+reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
+DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
+

+

Register ( slcr )DRAM_init_param

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
+reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
+reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
+DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
+

+

Register ( slcr )DRAM_EMR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
+reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
+DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
+

+

Register ( slcr )DRAM_EMR_MR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
+reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
+DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
+

+

Register ( slcr )DRAM_burst8_rdwr

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
+reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +105 + +1050 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
+reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
+reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
+DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +11054 + +DRAM Burst 8 read/write +
+

+

Register ( slcr )DRAM_disable_DQ

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
+reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
+reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
+DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
+

+

Register ( slcr )DRAM_addr_map_bank

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
+reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
+reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
+DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
+

+

Register ( slcr )DRAM_addr_map_col

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
+

+

Register ( slcr )DRAM_addr_map_row

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
+reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
+reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
+reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
+reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
+DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
+

+

Register ( slcr )DRAM_ODT_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
+reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
+reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
+reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
+reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
+reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
+reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
+reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
+reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
+reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
+reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
+DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
+

+

Register ( slcr )phy_cmd_timeout_rddata_cpt

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
+reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
+reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
+reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
+reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
+reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
+reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
+

+

Register ( slcr )DLL_calib

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
+reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
+reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
+DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
+

+

Register ( slcr )ODT_delay_hold

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
+reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
+reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
+reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
+ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
+

+

Register ( slcr )ctrl_reg1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
+reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
+reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
+reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
+reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
+reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
+reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
+ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
+

+

Register ( slcr )ctrl_reg2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
+reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
+ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
+

+

Register ( slcr )ctrl_reg3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
+reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
+reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
+ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
+

+

Register ( slcr )ctrl_reg4

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
+dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
+ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
+

+

Register ( slcr )ctrl_reg5

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
+reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
+reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
+ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
+

+

Register ( slcr )ctrl_reg6

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
+ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
+

+

Register ( slcr )CHE_REFRESH_TIMER01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
+refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
+CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
+

+

Register ( slcr )CHE_T_ZQ

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
+reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
+reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
+reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
+reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
+CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
+

+

Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
+dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
+

+

Register ( slcr )deep_pwrdwn_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
+deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
+deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
+

+

Register ( slcr )reg_2c

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
+ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
+reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
+reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
+reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
+reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
+

+

Register ( slcr )reg_2d

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
+reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
+reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
+reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
+

+

Register ( slcr )dfi_timing

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
+reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
+reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
+dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
+

+

RESET ECC ERROR

+

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +1 + +1 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
+Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +1 + +2 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +3 + +ECC error clear +
+

+

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
+Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
+

+

Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
+ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
+

+

Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
+

+

Register ( slcr )CHE_ECC_STATS_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
+STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
+

+

Register ( slcr )ECC_scrub

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
+reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
+ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
+

+

Register ( slcr )phy_rcvr_enable

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
+reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
+phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
+

+

Register ( slcr )PHY_Config0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
+

+

Register ( slcr )PHY_Config1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
+

+

Register ( slcr )PHY_Config2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
+

+

Register ( slcr )PHY_Config3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
+

+

Register ( slcr )phy_init_ratio0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 0. +
+

+

Register ( slcr )phy_init_ratio1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 1. +
+

+

Register ( slcr )phy_init_ratio2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 2. +
+

+

Register ( slcr )phy_init_ratio3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 3. +
+

+

Register ( slcr )phy_rd_dqs_cfg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_rd_dqs_cfg1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
+

+

Register ( slcr )phy_rd_dqs_cfg2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
+

+

Register ( slcr )phy_rd_dqs_cfg3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
+

+

Register ( slcr )phy_wr_dqs_cfg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_wr_dqs_cfg1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
+

+

Register ( slcr )phy_wr_dqs_cfg2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
+

+

Register ( slcr )phy_wr_dqs_cfg3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
+

+

Register ( slcr )phy_we_cfg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +b5 + +PHY FIFO write enable configuration for data slice 0. +
+

+

Register ( slcr )phy_we_cfg1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +b5 + +PHY FIFO write enable configuration for data slice 1. +
+

+

Register ( slcr )phy_we_cfg2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +b5 + +PHY FIFO write enable configuration for data slice 2. +
+

+

Register ( slcr )phy_we_cfg3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +b5 + +PHY FIFO write enable configuration for data slice 3. +
+

+

Register ( slcr )wr_data_slv0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
+

+

Register ( slcr )wr_data_slv1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
+

+

Register ( slcr )wr_data_slv2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
+

+

Register ( slcr )wr_data_slv3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
+

+

Register ( slcr )reg_64

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
+reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
+reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
+reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
+reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
+reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
+reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
+reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
+reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
+reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
+reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
+reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
+reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
+reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
+reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
+

+

Register ( slcr )reg_65

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
+reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
+reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
+reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
+reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
+reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
+reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
+

+

Register ( slcr )page_mask

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
+page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
+

+

Register ( slcr )axi_priority_wr_port0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
+

+

Register ( slcr )axi_priority_wr_port1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
+

+

Register ( slcr )axi_priority_wr_port2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
+

+

Register ( slcr )axi_priority_wr_port3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
+

+

Register ( slcr )axi_priority_rd_port0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

+

Register ( slcr )axi_priority_rd_port1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
+

+

Register ( slcr )axi_priority_rd_port2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
+

+

Register ( slcr )axi_priority_rd_port3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
+

+

Register ( slcr )lpddr_ctrl0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
+reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
+reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
+reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
+lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
+

+

Register ( slcr )lpddr_ctrl1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
+lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
+

+

Register ( slcr )lpddr_ctrl2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
+reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
+reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
+lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
+

+

Register ( slcr )lpddr_ctrl3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
+reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
+lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
+

+

POLL ON DCI STATUS

+

Register ( slcr )DDRIOB_DCI_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
+DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
+

+

UNLOCK DDR

+

Register ( slcr )ddrc_ctrl

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
+

+

CHECK DDR STATUS

+

Register ( slcr )mode_sts_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
+mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
+

+ +

+

ps7_mio_init_data_2_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
+ +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
+ +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
+ +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
+ +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
+ +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
+ +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
+ +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
+ +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
+ +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
+ +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
+ +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
+ +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
+ +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
+ +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
+ +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
+ +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
+ +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
+ +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
+ +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
+ +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
+ +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_mio_init_data_2_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

OCM REMAPPING

+

DDRIOB SETTINGS

+

Register ( slcr )DDRIOB_ADDR0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
+

+

Register ( slcr )DDRIOB_ADDR1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
+

+

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
+

+

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
+

+

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
+

+

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
+

+

Register ( slcr )DDRIOB_CLOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
+

+

Register ( slcr )DDRIOB_DDR_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
+VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
+VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
+VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
+REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
+REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
+REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
+DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
+CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
+DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
+

+

ASSERT RESET

+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
+VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
+

+

DEASSERT RESET

+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
+VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
+

+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
+ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
+VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
+VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
+VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
+VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
+NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
+NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
+NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
+PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
+PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
+UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
+INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
+TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
+TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
+TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
+TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
+INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
+

+

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

+

Register ( slcr )MIO_PIN_12

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1640 + +MIO Pin 12 Control +
+

+

Register ( slcr )MIO_PIN_13

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1640 + +MIO Pin 13 Control +
+

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1621 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1620 + +MIO Pin 15 Control +
+

+

Register ( slcr )MIO_PIN_16

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
+

+

Register ( slcr )MIO_PIN_17

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
+

+

Register ( slcr )MIO_PIN_18

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
+

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
+

+

Register ( slcr )MIO_PIN_21

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
+

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1204 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1205 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1204 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1205 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1204 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1204 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1204 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1204 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1205 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1204 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1204 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1204 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +200 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
+

+

Register ( slcr )SD0_WP_CD_SEL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SDIO0_WP_SEL + +5:0 + +3f + +2f + +2f + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
+SDIO0_CD_SEL + +21:16 + +3f0000 + +2e + +2e0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
+SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2e002f + +SDIO 0 WP CD select +
+

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_peripherals_init_data_2_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
+ +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
+ +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
+ +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+ +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
+ +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
+ +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
+ +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
+ +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
+ +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+ +DIRM_1 + + +0XE000A244 + +32 + +RW + +0x000000 + +Direction mode (GPIO Bank1, MIO) +
+ +MASK_DATA_1_MSW + + +0XE000A00C + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+ +OEN_1 + + +0XE000A248 + +32 + +RW + +0x000000 + +Output enable (GPIO Bank1, MIO) +
+ +MASK_DATA_1_MSW + + +0XE000A00C + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+ +MASK_DATA_1_MSW + + +0XE000A00C + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+

+

ps7_peripherals_init_data_2_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

DDR TERM/IBUF_DISABLE_MODE SETTINGS

+

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
+

+

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
+

+

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
+

+

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
+

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+

SRAM/NOR SET OPMODE

+

UART REGISTERS

+

Register ( slcr )Baud_rate_divider_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
+Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
+

+

Register ( slcr )Baud_rate_gen_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
+Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
+

+

Register ( slcr )Control_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
+STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
+RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
+TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
+TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
+RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
+RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
+TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
+RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
+Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
+

+

Register ( slcr )mode_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
+UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
+CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
+NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
+PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
+CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
+CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
+mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
+

+

QSPI REGISTERS

+

Register ( slcr )Config_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
+Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
+

+

PL POWER ON RESET REGISTERS

+

Register ( slcr )CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
+CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+

+

SMC TIMING CALCULATION REGISTER UPDATE

+

NAND SET CYCLE

+

OPMODE

+

DIRECT COMMAND

+

SRAM/NOR CS0 SET CYCLE

+

DIRECT COMMAND

+

NOR CS0 BASE ADDRESS

+

SRAM/NOR CS1 SET CYCLE

+

DIRECT COMMAND

+

NOR CS1 BASE ADDRESS

+

USB RESET

+

USB0 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

Register ( slcr )DIRM_1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DIRM_1 + +0XE000A244 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DIRECTION_1 + +21:0 + +3fffff + +80000 + +80000 + +Operation is the same as DIRM_0[DIRECTION_0] +
+DIRM_1@0XE000A244 + +31:0 + +3fffff + + + +80000 + +Direction mode (GPIO Bank1, MIO) +
+

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

Register ( slcr )MASK_DATA_1_MSW

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MASK_DATA_1_MSW + +0XE000A00C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_1_MSW + +21:16 + +3f0000 + +37 + +370000 + +Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +
+DATA_1_MSW + +5:0 + +3f + +8 + +8 + +Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +
+MASK_DATA_1_MSW@0XE000A00C + +31:0 + +3f003f + + + +370008 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

Register ( slcr )OEN_1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+OEN_1 + +0XE000A248 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+OP_ENABLE_1 + +21:0 + +3fffff + +80000 + +80000 + +Operation is the same as OEN_0[OP_ENABLE_0] +
+OEN_1@0XE000A248 + +31:0 + +3fffff + + + +80000 + +Output enable (GPIO Bank1, MIO) +
+

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

Register ( slcr )MASK_DATA_1_MSW

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MASK_DATA_1_MSW + +0XE000A00C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_1_MSW + +21:16 + +3f0000 + +37 + +370000 + +Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +
+DATA_1_MSW + +5:0 + +3f + +0 + +0 + +Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +
+MASK_DATA_1_MSW@0XE000A00C + +31:0 + +3f003f + + + +370000 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

Register ( slcr )MASK_DATA_1_MSW

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MASK_DATA_1_MSW + +0XE000A00C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_1_MSW + +21:16 + +3f0000 + +37 + +370000 + +Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +
+DATA_1_MSW + +5:0 + +3f + +8 + +8 + +Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +
+MASK_DATA_1_MSW@0XE000A00C + +31:0 + +3f003f + + + +370008 + +Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) +
+

+

USB1 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

ENET RESET

+

ENET0 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

ENET1 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

I2C RESET

+

I2C0 RESET

+

DIR MODE GPIO BANK0

+

DIR MODE GPIO BANK1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE

+

OUTPUT ENABLE

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

I2C1 RESET

+

DIR MODE GPIO BANK0

+

DIR MODE GPIO BANK1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE

+

OUTPUT ENABLE

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

NOR CHIP SELECT

+

DIR MODE BANK 0

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

OUTPUT ENABLE BANK 0

+ +

+

ps7_post_config_2_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
+ +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_post_config_2_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

ENABLING LEVEL SHIFTER

+

Register ( slcr )LVL_SHFTR_EN

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
+USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
+LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
+

+

FPGA RESETS TO 0

+

Register ( slcr )FPGA_RST_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
+FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
+FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
+FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
+FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
+reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
+FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
+reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
+FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
+FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
+FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
+FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
+FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
+reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
+FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
+FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
+FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
+FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
+

+

AFI REGISTERS

+

AFI0 REGISTERS

+

AFI1 REGISTERS

+

AFI2 REGISTERS

+

AFI3 REGISTERS

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_debug_2_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
+ +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
+ +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
+

+

ps7_debug_2_0

+ + + + + + + + + +

CROSS TRIGGER CONFIGURATIONS

+

UNLOCKING CTI REGISTERS

+

Register ( slcr )LAR

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

+

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

+

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

+

ENABLING CTI MODULES AND CHANNELS

+

MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

+ +

+ + + + +

ps7_pll_init_data_1_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
+ +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
+ +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
+ +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
+ +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_pll_init_data_1_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

PLL SLCR REGISTERS

+

ARM PLL INIT

+

Register ( slcr )ARM_PLL_CFG

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
+LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
+ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
+

+

UPDATE FB_DIV

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
+

+

BY PASS PLL

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
+

+

ASSERT RESET

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
+

+

DEASSERT RESET

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
+

+

CHECK PLL STATUS

+

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
+PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
+

+

REMOVE PLL BY PASS

+

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
+

+

Register ( slcr )ARM_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
+DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
+

+

DDR PLL INIT

+

Register ( slcr )DDR_PLL_CFG

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
+LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
+DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
+

+

UPDATE FB_DIV

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
+

+

BY PASS PLL

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
+

+

ASSERT RESET

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
+

+

DEASSERT RESET

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
+

+

CHECK PLL STATUS

+

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
+PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
+

+

REMOVE PLL BY PASS

+

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
+

+

Register ( slcr )DDR_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
+DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
+DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
+

+

IO PLL INIT

+

Register ( slcr )IO_PLL_CFG

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
+LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
+IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
+

+

UPDATE FB_DIV

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
+

+

BY PASS PLL

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
+

+

ASSERT RESET

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
+

+

DEASSERT RESET

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
+

+

CHECK PLL STATUS

+

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
+PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
+

+

REMOVE PLL BY PASS

+

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
+

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_clock_init_data_1_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
+ +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
+ +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
+ +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
+ +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
+ +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
+ +CAN_CLK_CTRL + + +0XF800015C + +32 + +RW + +0x000000 + +CAN Reference Clock Control +
+ +CAN_MIOCLK_CTRL + + +0XF8000160 + +32 + +RW + +0x000000 + +CAN MIO Clock Control +
+ +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
+ +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
+ +FPGA1_CLK_CTRL + + +0XF8000180 + +32 + +RW + +0x000000 + +FPGA 1 Output Clock Control +
+ +FPGA2_CLK_CTRL + + +0XF8000190 + +32 + +RW + +0x000000 + +FPGA 2 Output Clock Control +
+ +FPGA3_CLK_CTRL + + +0XF80001A0 + +32 + +RW + +0x000000 + +FPGA 3 Output Clock Control +
+ +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
+ +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_clock_init_data_1_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

CLOCK CONTROL SLCR REGISTERS

+

Register ( slcr )DCI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+DIVISOR0 + +13:8 + +3f00 + +23 + +2300 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+DIVISOR1 + +25:20 + +3f00000 + +3 + +300000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +302301 + +DCI clock control +
+

+

Register ( slcr )GEM0_RCLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
+GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
+

+

Register ( slcr )GEM0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
+DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
+

+

Register ( slcr )LQSPI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Linear Quad-SPI Reference Clock Control +
+

+

Register ( slcr )SDIO_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Reference Clock Control +
+

+

Register ( slcr )UART_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
+

+

Register ( slcr )CAN_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CAN_CLK_CTRL + +0XF800015C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +1 + +1 + +CAN 0 Reference Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CLKACT1 + +1:1 + +2 + +0 + +0 + +CAN 1 Reference Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+CAN_CLK_CTRL@0XF800015C + +31:0 + +3f03f33 + + + +100a01 + +CAN Reference Clock Control +
+

+

Register ( slcr )CAN_MIOCLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CAN_MIOCLK_CTRL + +0XF8000160 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CAN0_MUX + +5:0 + +3f + +0 + +0 + +CAN0 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. +
+CAN0_REF_SEL + +6:6 + +40 + +0 + +0 + +CAN 0 Reference Clock selection. 0 - From internal PLL. 1 - From MIO based on the next field +
+CAN1_MUX + +21:16 + +3f0000 + +0 + +0 + +CAN1 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. +
+CAN1_REF_SEL + +22:22 + +400000 + +0 + +0 + +CAN1 Reference Clock selection. 0 - From internal PLL. 1 - From MIO based on the next field +
+CAN_MIOCLK_CTRL@0XF8000160 + +31:0 + +7f007f + + + +0 + +CAN MIO Clock Control +
+

+

TRACE CLOCK

+

Register ( slcr )PCAP_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
+

+

Register ( slcr )FPGA0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +6 + +600 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +100600 + +FPGA 0 Output Clock Control +
+

+

Register ( slcr )FPGA1_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA1_CLK_CTRL + +0XF8000180 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +101400 + +FPGA 1 Output Clock Control +
+

+

Register ( slcr )FPGA2_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA2_CLK_CTRL + +0XF8000190 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +100a00 + +FPGA 2 Output Clock Control +
+

+

Register ( slcr )FPGA3_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA3_CLK_CTRL + +0XF80001A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +100500 + +FPGA 3 Output Clock Control +
+

+

Register ( slcr )CLK_621_TRUE

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
+CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
+

+

Register ( slcr )APER_CLK_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CAN0_CPU_1XCLKACT + +16:16 + +10000 + +1 + +10000 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ed044d + +AMBA Peripheral Clock Control +
+

+

THIS SHOULD BE BLANK

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_ddr_init_data_1_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
+ +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
+ +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
+ +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
+ +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
+ +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
+ +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
+ +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
+ +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
+ +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
+ +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
+ +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
+ +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
+ +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
+ +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
+ +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
+ +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
+ +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
+ +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
+ +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
+ +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
+ +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
+ +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
+ +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
+ +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
+ +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
+ +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
+ +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
+ +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
+ +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
+ +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
+ +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
+ +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
+ +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
+ +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
+ +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
+ +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
+ +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
+ +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
+ +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
+ +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
+ +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
+ +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
+ +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
+ +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
+ +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
+ +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
+ +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
+ +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
+ +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
+ +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
+ +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
+ +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
+ +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
+ +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
+ +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
+ +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
+ +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
+ +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
+ +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
+ +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
+ +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
+ +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
+ +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
+ +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
+ +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
+ +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
+ +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
+ +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
+ +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
+ +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
+ +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
+ +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
+

+

ps7_ddr_init_data_1_0

+ + + + + + + + + +

DDR INITIALIZATION

+

LOCK DDR

+

Register ( slcr )ddrc_ctrl

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
+

+

Register ( slcr )Two_rank_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
+reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
+reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
+reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
+reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
+reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
+reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
+reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
+Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two rank configuration register +
+

+

Register ( slcr )HPR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
+reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
+reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
+HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
+

+

Register ( slcr )LPR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
+reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
+reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
+LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
+

+

Register ( slcr )WR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
+reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
+reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
+WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
+

+

Register ( slcr )DRAM_param_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
+reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
+reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
+DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281b + +DRAM Parameters register 0 +
+

+

Register ( slcr )DRAM_param_reg1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
+reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
+reg_ddrc_t_faw + +15:10 + +fc00 + +18 + +6000 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
+reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
+reg_ddrc_t_ras_min + +26:22 + +7c00000 + +14 + +5000000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
+reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
+DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +452460d2 + +DRAM Parameters register 1 +
+

+

Register ( slcr )DRAM_param_reg2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
+reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
+reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
+reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
+reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
+reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
+reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
+DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters register 2 +
+

+

Register ( slcr )DRAM_param_reg3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
+reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
+reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
+reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
+reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
+reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
+reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
+reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
+reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
+reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
+reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
+reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
+DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
+

+

Register ( slcr )DRAM_param_reg4

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
+reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
+reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
+reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
+reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
+reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
+ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
+reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
+reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
+DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
+

+

Register ( slcr )DRAM_init_param

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
+reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
+reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
+DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
+

+

Register ( slcr )DRAM_EMR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
+reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
+DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
+

+

Register ( slcr )DRAM_EMR_MR_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
+reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
+DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access register +
+

+

Register ( slcr )DRAM_burst8_rdwr

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
+reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +105 + +1050 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
+reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
+reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
+DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +11054 + +DRAM burst 8 read/write register +
+

+

Register ( slcr )DRAM_disable_DQ

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
+reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
+reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
+DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
+

+

Register ( slcr )DRAM_addr_map_bank

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
+reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
+reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
+DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
+

+

Register ( slcr )DRAM_addr_map_col

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
+

+

Register ( slcr )DRAM_addr_map_row

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
+reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
+reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
+reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
+reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
+DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
+

+

Register ( slcr )DRAM_ODT_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
+reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
+reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
+reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
+reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
+reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
+reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
+reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
+reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
+reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
+reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
+DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
+

+

Register ( slcr )phy_cmd_timeout_rddata_cpt

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
+reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
+reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
+reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
+reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
+reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
+reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
+

+

Register ( slcr )DLL_calib

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
+reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
+reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
+DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
+

+

Register ( slcr )ODT_delay_hold

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
+reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
+reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
+reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
+ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
+

+

Register ( slcr )ctrl_reg1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
+reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
+reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
+reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
+reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
+reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
+reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
+ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
+

+

Register ( slcr )ctrl_reg2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
+reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
+ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
+

+

Register ( slcr )ctrl_reg3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
+reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
+reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
+ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
+

+

Register ( slcr )ctrl_reg4

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
+dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
+ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
+

+

Register ( slcr )CHE_REFRESH_TIMER01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
+refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
+CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
+

+

Register ( slcr )CHE_T_ZQ

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
+reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
+reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
+reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
+reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
+CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
+

+

Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
+dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
+

+

Register ( slcr )deep_pwrdwn_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
+deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
+deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
+

+

Register ( slcr )reg_2c

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
+ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
+reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
+reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
+reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
+reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
+

+

Register ( slcr )reg_2d

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
+reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
+reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
+reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
+

+

Register ( slcr )dfi_timing

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
+reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
+reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
+dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
+

+

RESET ECC ERROR

+

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +1 + +1 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
+Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +1 + +2 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +3 + +ECC error clear register +
+

+

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
+Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
+

+

Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
+ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
+

+

Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
+

+

Register ( slcr )CHE_ECC_STATS_REG_OFFSET

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
+STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
+

+

Register ( slcr )ECC_scrub

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
+reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
+ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
+

+

Register ( slcr )phy_rcvr_enable

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
+reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
+phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
+

+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
+

+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
+

+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
+

+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
+

+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 0. +
+

+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 0. +
+

+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 0. +
+

+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +60 + +18000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +18000 + +PHY init ratio register for data slice 0. +
+

+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
+

+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +b5 + +PHY fifo write enable configuration register for data slice 0. +
+

+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +b5 + +PHY fifo write enable configuration register for data slice 0. +
+

+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +b5 + +PHY fifo write enable configuration register for data slice 0. +
+

+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +b5 + +b5 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +b5 + +PHY fifo write enable configuration register for data slice 0. +
+

+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
+

+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
+

+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
+

+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
+

+

Register ( slcr )reg_64

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
+reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
+reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
+reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
+reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
+reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
+reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
+reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
+reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
+reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
+reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
+reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
+reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
+reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
+reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
+

+

Register ( slcr )reg_65

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
+reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
+reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
+reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
+reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
+reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
+reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
+

+

Register ( slcr )page_mask

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
+page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
+

+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
+

+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
+

+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
+

+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
+

+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

+

Register ( slcr )lpddr_ctrl0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
+reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
+reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
+reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
+lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
+

+

Register ( slcr )lpddr_ctrl1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
+lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
+

+

Register ( slcr )lpddr_ctrl2

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
+reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
+reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
+lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
+

+

Register ( slcr )lpddr_ctrl3

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
+reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
+lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
+

+

POLL ON DCI STATUS

+

Register ( slcr )DDRIOB_DCI_STATUS

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
+DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
+

+

UNLOCK DDR

+

Register ( slcr )ddrc_ctrl

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
+

+

CHECK DDR STATUS

+

Register ( slcr )mode_sts_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
+mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
+

+ +

+

ps7_mio_init_data_1_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
+ +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
+ +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
+ +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
+ +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
+ +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
+ +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
+ +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
+ +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
+ +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
+ +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
+ +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
+ +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
+ +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
+ +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
+ +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
+ +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
+ +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
+ +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
+ +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
+ +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
+ +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_mio_init_data_1_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

OCM REMAPPING

+

DDRIOB SETTINGS

+

Register ( slcr )DDRIOB_ADDR0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
+

+

Register ( slcr )DDRIOB_ADDR1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
+

+

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
+

+

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
+

+

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
+

+

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
+

+

Register ( slcr )DDRIOB_CLOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
+

+

Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
+

+

Register ( slcr )DDRIOB_DDR_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
+VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
+VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
+VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
+REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
+REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
+DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
+CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
+DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
+

+

ASSERT RESET

+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
+VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
+

+

DEASSERT RESET

+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
+VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
+

+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
+ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
+VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
+VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
+VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
+VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
+NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
+NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
+NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
+PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
+PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
+UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
+INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
+TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
+TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
+TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
+TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
+INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
+

+

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
+

+

Register ( slcr )MIO_PIN_12

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1640 + +MIO Control for Pin 12 +
+

+

Register ( slcr )MIO_PIN_13

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1640 + +MIO Control for Pin 13 +
+

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1621 + +MIO Control for Pin 14 +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1620 + +MIO Control for Pin 15 +
+

+

Register ( slcr )MIO_PIN_16

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
+

+

Register ( slcr )MIO_PIN_17

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
+

+

Register ( slcr )MIO_PIN_18

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
+

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
+

+

Register ( slcr )MIO_PIN_21

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
+

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 28 +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1205 + +MIO Control for Pin 29 +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 30 +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1205 + +MIO Control for Pin 31 +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 32 +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 33 +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 34 +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 35 +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1205 + +MIO Control for Pin 36 +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 37 +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 38 +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 39 +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 46 +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 50 +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +200 + +MIO Control for Pin 51 +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
+

+

Register ( slcr )SD0_WP_CD_SEL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SDIO0_WP_SEL + +5:0 + +3f + +2f + +2f + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
+SDIO0_CD_SEL + +21:16 + +3f0000 + +2e + +2e0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
+SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2e002f + +SDIO 0 WP CD select register +
+

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_peripherals_init_data_1_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
+ +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
+ +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
+ +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+ +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
+ +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
+ +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
+ +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
+ +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
+ +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+ +DIRM_1 + + +0XE000A244 + +32 + +RW + +0x000000 + +Direction mode configuration register: Configures bank 1 for direction mode, either input or output +
+ +MASK_DATA_1_MSW + + +0XE000A00C + +32 + +RW + +0x000000 + +Maskable single-word-based data access register: Mask and data access for the most significant word of this bank of GPIO pins +
+ +OEN_1 + + +0XE000A248 + +32 + +RW + +0x000000 + +Output enable register: Configures the output enables of bank 1 +
+ +MASK_DATA_1_MSW + + +0XE000A00C + +32 + +RW + +0x000000 + +Maskable single-word-based data access register: Mask and data access for the most significant word of this bank of GPIO pins +
+ +MASK_DATA_1_MSW + + +0XE000A00C + +32 + +RW + +0x000000 + +Maskable single-word-based data access register: Mask and data access for the most significant word of this bank of GPIO pins +
+

+

ps7_peripherals_init_data_1_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

DDR TERM/IBUF_DISABLE_MODE SETTINGS

+

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
+

+

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
+

+

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
+

+

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
+

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+

SRAM/NOR SET OPMODE

+

UART REGISTERS

+

Register ( slcr )Baud_rate_divider_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
+Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
+

+

Register ( slcr )Baud_rate_gen_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
+Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
+

+

Register ( slcr )Control_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
+STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
+RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
+TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
+TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
+RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
+RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
+TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
+RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
+Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
+

+

Register ( slcr )mode_reg0

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
+UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
+CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
+NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
+PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
+CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
+CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
+mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
+

+

QSPI REGISTERS

+

Register ( slcr )Config_reg

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
+Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
+

+

PL POWER ON RESET REGISTERS

+

Register ( slcr )CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
+CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+

+

SMC TIMING CALCULATION REGISTER UPDATE

+

NAND SET CYCLE

+

OPMODE

+

DIRECT COMMAND

+

SRAM/NOR CS0 SET CYCLE

+

DIRECT COMMAND

+

NOR CS0 BASE ADDRESS

+

SRAM/NOR CS1 SET CYCLE

+

DIRECT COMMAND

+

NOR CS1 BASE ADDRESS

+

USB RESET

+

USB0 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

Register ( slcr )DIRM_1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+DIRM_1 + +0XE000A244 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DIRECTION_1 + +21:0 + +3fffff + +80000 + +80000 + +Direction mode for bank 1 0 = input 1 = output Each bit configures the corresponding pin within the 32-bit bank +
+DIRM_1@0XE000A244 + +31:0 + +3fffff + + + +80000 + +Direction mode configuration register: Configures bank 1 for direction mode, either input or output +
+

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

Register ( slcr )MASK_DATA_1_MSW

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MASK_DATA_1_MSW + +0XE000A00C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_1_MSW + +21:16 + +3f0000 + +37 + +370000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_1_MSW + +5:0 + +3f + +8 + +8 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank +
+MASK_DATA_1_MSW@0XE000A00C + +31:0 + +3f003f + + + +370008 + +Maskable single-word-based data access register: Mask and data access for the most significant word of this bank of GPIO pins +
+

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

Register ( slcr )OEN_1

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+OEN_1 + +0XE000A248 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+OP_ENABLE_1 + +21:0 + +3fffff + +80000 + +80000 + +Output enables for bank 1 0 = disabled 1 = enabled Each bit configures the corresponding pin within the 32-bit bank +
+OEN_1@0XE000A248 + +31:0 + +3fffff + + + +80000 + +Output enable register: Configures the output enables of bank 1 +
+

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

Register ( slcr )MASK_DATA_1_MSW

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MASK_DATA_1_MSW + +0XE000A00C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_1_MSW + +21:16 + +3f0000 + +37 + +370000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_1_MSW + +5:0 + +3f + +0 + +0 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank +
+MASK_DATA_1_MSW@0XE000A00C + +31:0 + +3f003f + + + +370000 + +Maskable single-word-based data access register: Mask and data access for the most significant word of this bank of GPIO pins +
+

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

Register ( slcr )MASK_DATA_1_MSW

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MASK_DATA_1_MSW + +0XE000A00C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_1_MSW + +21:16 + +3f0000 + +37 + +370000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_1_MSW + +5:0 + +3f + +8 + +8 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank +
+MASK_DATA_1_MSW@0XE000A00C + +31:0 + +3f003f + + + +370008 + +Maskable single-word-based data access register: Mask and data access for the most significant word of this bank of GPIO pins +
+

+

USB1 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

ENET RESET

+

ENET0 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

ENET1 RESET

+

DIR MODE BANK 0

+

DIR MODE BANK 1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE BANK 0

+

OUTPUT ENABLE BANK 1

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

I2C RESET

+

I2C0 RESET

+

DIR MODE GPIO BANK0

+

DIR MODE GPIO BANK1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE

+

OUTPUT ENABLE

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

I2C1 RESET

+

DIR MODE GPIO BANK0

+

DIR MODE GPIO BANK1

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

OUTPUT ENABLE

+

OUTPUT ENABLE

+

MASK_DATA_0_LSW LOW BANK [15:0]

+

MASK_DATA_0_MSW LOW BANK [31:16]

+

MASK_DATA_1_LSW LOW BANK [47:32]

+

MASK_DATA_1_MSW LOW BANK [53:48]

+

ADD 1 MS DELAY

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

MASK_DATA_0_MSW HIGH BANK [31:16]

+

MASK_DATA_1_LSW HIGH BANK [47:32]

+

MASK_DATA_1_MSW HIGH BANK [53:48]

+

NOR CHIP SELECT

+

DIR MODE BANK 0

+

MASK_DATA_0_LSW HIGH BANK [15:0]

+

OUTPUT ENABLE BANK 0

+ +

+

ps7_post_config_1_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
+ +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
+ +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
+ +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
+

+

ps7_post_config_1_0

+ + + + + + + + + +

SLCR SETTINGS

+

Register ( slcr )SLCR_UNLOCK

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

+

ENABLING LEVEL SHIFTER

+

Register ( slcr )LVL_SHFTR_EN

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
+USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
+LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
+

+

FPGA RESETS TO 0

+

Register ( slcr )FPGA_RST_CTRL

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
+FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
+FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
+FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
+FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
+FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
+reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
+FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
+FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
+reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
+FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
+FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
+FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
+FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
+FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
+FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
+reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
+FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
+FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
+FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
+FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
+FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
+

+

AFI REGISTERS

+

AFI0 REGISTERS

+

AFI1 REGISTERS

+

AFI2 REGISTERS

+

AFI3 REGISTERS

+

LOCK IT BACK

+

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

+

ps7_debug_1_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
+ +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
+ +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
+

+

ps7_debug_1_0

+ + + + + + + + + +

CROSS TRIGGER CONFIGURATIONS

+

UNLOCKING CTI REGISTERS

+

Register ( slcr )LAR

+
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+ + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

+

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

+

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

+

ENABLING CTI MODULES AND CHANNELS

+

MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

+ +

+ + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_init.tcl b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_init.tcl new file mode 100644 index 0000000..265ba7d --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_init.tcl @@ -0,0 +1,863 @@ +proc ps7_pll_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00302301 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF800015C 0x03F03F33 0x00100A01 + mask_write 0XF8000160 0x007F007F 0x00000000 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00100600 + mask_write 0XF8000180 0x03F03F30 0x00101400 + mask_write 0XF8000190 0x03F03F30 0x00100A00 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01ED044D + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281B + mask_write 0XF8006018 0xF7FFFFFF 0x452460D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x00011054 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000003 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00018000 + mask_write 0XF8006130 0x000FFFFF 0x00018000 + mask_write 0XF8006134 0x000FFFFF 0x00018000 + mask_write 0XF8006138 0x000FFFFF 0x00018000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000B5 + mask_write 0XF800616C 0x001FFFFF 0x000000B5 + mask_write 0XF8006170 0x001FFFFF 0x000000B5 + mask_write 0XF8006174 0x001FFFFF 0x000000B5 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001640 + mask_write 0XF8000734 0x00003FFF 0x00001640 + mask_write 0XF8000738 0x00003FFF 0x00001621 + mask_write 0XF800073C 0x00003FFF 0x00001620 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001204 + mask_write 0XF8000774 0x00003FFF 0x00001205 + mask_write 0XF8000778 0x00003FFF 0x00001204 + mask_write 0XF800077C 0x00003FFF 0x00001205 + mask_write 0XF8000780 0x00003FFF 0x00001204 + mask_write 0XF8000784 0x00003FFF 0x00001204 + mask_write 0XF8000788 0x00003FFF 0x00001204 + mask_write 0XF800078C 0x00003FFF 0x00001204 + mask_write 0XF8000790 0x00003FFF 0x00001205 + mask_write 0XF8000794 0x00003FFF 0x00001204 + mask_write 0XF8000798 0x00003FFF 0x00001204 + mask_write 0XF800079C 0x00003FFF 0x00001204 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00000200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002E002F + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mask_write 0XF8000004 0x0000FFFF 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A244 0x003FFFFF 0x00080000 + mask_write 0XE000A00C 0x003F003F 0x00370008 + mask_write 0XE000A248 0x003FFFFF 0x00080000 + mask_write 0XE000A00C 0x003F003F 0x00370000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A00C 0x003F003F 0x00370008 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_debug_3_0 {} { + mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00302301 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF800015C 0x03F03F33 0x00100A01 + mask_write 0XF8000160 0x007F007F 0x00000000 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00100600 + mask_write 0XF8000180 0x03F03F30 0x00101400 + mask_write 0XF8000190 0x03F03F30 0x00100A00 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01ED044D + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281B + mask_write 0XF8006018 0xF7FFFFFF 0x452460D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x00011054 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000003 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00018000 + mask_write 0XF8006130 0x000FFFFF 0x00018000 + mask_write 0XF8006134 0x000FFFFF 0x00018000 + mask_write 0XF8006138 0x000FFFFF 0x00018000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000B5 + mask_write 0XF800616C 0x001FFFFF 0x000000B5 + mask_write 0XF8006170 0x001FFFFF 0x000000B5 + mask_write 0XF8006174 0x001FFFFF 0x000000B5 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001640 + mask_write 0XF8000734 0x00003FFF 0x00001640 + mask_write 0XF8000738 0x00003FFF 0x00001621 + mask_write 0XF800073C 0x00003FFF 0x00001620 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001204 + mask_write 0XF8000774 0x00003FFF 0x00001205 + mask_write 0XF8000778 0x00003FFF 0x00001204 + mask_write 0XF800077C 0x00003FFF 0x00001205 + mask_write 0XF8000780 0x00003FFF 0x00001204 + mask_write 0XF8000784 0x00003FFF 0x00001204 + mask_write 0XF8000788 0x00003FFF 0x00001204 + mask_write 0XF800078C 0x00003FFF 0x00001204 + mask_write 0XF8000790 0x00003FFF 0x00001205 + mask_write 0XF8000794 0x00003FFF 0x00001204 + mask_write 0XF8000798 0x00003FFF 0x00001204 + mask_write 0XF800079C 0x00003FFF 0x00001204 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00000200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002E002F + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mask_write 0XF8000004 0x0000FFFF 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A244 0x003FFFFF 0x00080000 + mask_write 0XE000A00C 0x003F003F 0x00370008 + mask_write 0XE000A248 0x003FFFFF 0x00080000 + mask_write 0XE000A00C 0x003F003F 0x00370000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A00C 0x003F003F 0x00370008 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_debug_2_0 {} { + mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00302301 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF800015C 0x03F03F33 0x00100A01 + mask_write 0XF8000160 0x007F007F 0x00000000 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00100600 + mask_write 0XF8000180 0x03F03F30 0x00101400 + mask_write 0XF8000190 0x03F03F30 0x00100A00 + mask_write 0XF80001A0 0x03F03F30 0x00100500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01ED044D + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281B + mask_write 0XF8006018 0xF7FFFFFF 0x452460D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x00011054 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000003 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00018000 + mask_write 0XF8006130 0x000FFFFF 0x00018000 + mask_write 0XF8006134 0x000FFFFF 0x00018000 + mask_write 0XF8006138 0x000FFFFF 0x00018000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000B5 + mask_write 0XF800616C 0x001FFFFF 0x000000B5 + mask_write 0XF8006170 0x001FFFFF 0x000000B5 + mask_write 0XF8006174 0x001FFFFF 0x000000B5 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001640 + mask_write 0XF8000734 0x00003FFF 0x00001640 + mask_write 0XF8000738 0x00003FFF 0x00001621 + mask_write 0XF800073C 0x00003FFF 0x00001620 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001204 + mask_write 0XF8000774 0x00003FFF 0x00001205 + mask_write 0XF8000778 0x00003FFF 0x00001204 + mask_write 0XF800077C 0x00003FFF 0x00001205 + mask_write 0XF8000780 0x00003FFF 0x00001204 + mask_write 0XF8000784 0x00003FFF 0x00001204 + mask_write 0XF8000788 0x00003FFF 0x00001204 + mask_write 0XF800078C 0x00003FFF 0x00001204 + mask_write 0XF8000790 0x00003FFF 0x00001205 + mask_write 0XF8000794 0x00003FFF 0x00001204 + mask_write 0XF8000798 0x00003FFF 0x00001204 + mask_write 0XF800079C 0x00003FFF 0x00001204 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003F01 0x00001201 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00000200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002E002F + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mask_write 0XF8000004 0x0000FFFF 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A244 0x003FFFFF 0x00080000 + mask_write 0XE000A00C 0x003F003F 0x00370008 + mask_write 0XE000A248 0x003FFFFF 0x00080000 + mask_write 0XE000A00C 0x003F003F 0x00370000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A00C 0x003F003F 0x00370008 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_debug_1_0 {} { + mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} + +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_init_gpl.c b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_init_gpl.c new file mode 100644 index 0000000..c973002 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_init_gpl.c @@ -0,0 +1,13085 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF800015C[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF800015C[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00100A01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x6 + // .. .. ==> 0XF8000170[13:8] = 0x00000006U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000170[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100600U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000180[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000180[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000190[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x18 + // .. .. ==> 0XF8006018[15:10] = 0x00000018U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF800612C[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF8006130[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF8006134[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF8006138[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF8006168[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF800616C[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF8006170[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF8006174[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000730[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000734[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF8000738[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001621U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF800073C[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001620U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 47 + // .. ==> 0XF8000830[5:0] = 0x0000002FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000002FU + // .. SDIO0_CD_SEL = 46 + // .. ==> 0XF8000830[21:16] = 0x0000002EU + // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E002FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x80000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00080000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00080000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00080000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. MASK_1_MSW = 0x37 + // .. .. .. .. ==> 0XE000A00C[21:16] = 0x00000037U + // .. .. .. .. ==> MASK : 0x003F0000U VAL : 0x00370000U + // .. .. .. .. DATA_1_MSW = 0x8 + // .. .. .. .. ==> 0XE000A00C[5:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000003FU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A00C, 0x003F003FU ,0x00370008U), + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x80000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00080000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00080000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00080000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. MASK_1_MSW = 0x37 + // .. .. .. .. ==> 0XE000A00C[21:16] = 0x00000037U + // .. .. .. .. ==> MASK : 0x003F0000U VAL : 0x00370000U + // .. .. .. .. DATA_1_MSW = 0x0 + // .. .. .. .. ==> 0XE000A00C[5:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A00C, 0x003F003FU ,0x00370000U), + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. MASK_1_MSW = 0x37 + // .. .. .. .. ==> 0XE000A00C[21:16] = 0x00000037U + // .. .. .. .. ==> MASK : 0x003F0000U VAL : 0x00370000U + // .. .. .. .. DATA_1_MSW = 0x8 + // .. .. .. .. ==> 0XE000A00C[5:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000003FU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A00C, 0x003F003FU ,0x00370008U), + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF800015C[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF800015C[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00100A01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x6 + // .. .. ==> 0XF8000170[13:8] = 0x00000006U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000170[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100600U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000180[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000180[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000190[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x18 + // .. .. ==> 0XF8006018[15:10] = 0x00000018U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF800612C[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF8006130[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF8006134[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF8006138[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF8006168[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF800616C[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF8006170[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF8006174[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000730[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000734[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF8000738[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001621U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF800073C[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001620U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 47 + // .. ==> 0XF8000830[5:0] = 0x0000002FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000002FU + // .. SDIO0_CD_SEL = 46 + // .. ==> 0XF8000830[21:16] = 0x0000002EU + // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E002FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x80000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00080000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00080000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00080000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. MASK_1_MSW = 0x37 + // .. .. .. .. ==> 0XE000A00C[21:16] = 0x00000037U + // .. .. .. .. ==> MASK : 0x003F0000U VAL : 0x00370000U + // .. .. .. .. DATA_1_MSW = 0x8 + // .. .. .. .. ==> 0XE000A00C[5:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000003FU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A00C, 0x003F003FU ,0x00370008U), + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x80000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00080000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00080000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00080000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. MASK_1_MSW = 0x37 + // .. .. .. .. ==> 0XE000A00C[21:16] = 0x00000037U + // .. .. .. .. ==> MASK : 0x003F0000U VAL : 0x00370000U + // .. .. .. .. DATA_1_MSW = 0x0 + // .. .. .. .. ==> 0XE000A00C[5:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A00C, 0x003F003FU ,0x00370000U), + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. MASK_1_MSW = 0x37 + // .. .. .. .. ==> 0XE000A00C[21:16] = 0x00000037U + // .. .. .. .. ==> MASK : 0x003F0000U VAL : 0x00370000U + // .. .. .. .. DATA_1_MSW = 0x8 + // .. .. .. .. ==> 0XE000A00C[5:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000003FU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A00C, 0x003F003FU ,0x00370008U), + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF800015C[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF800015C[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00100A01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x6 + // .. .. ==> 0XF8000170[13:8] = 0x00000006U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000170[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100600U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000180[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000180[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000190[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x18 + // .. .. ==> 0XF8006018[15:10] = 0x00000018U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF800612C[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF8006130[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF8006134[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x60 + // .. .. ==> 0XF8006138[19:10] = 0x00000060U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00018000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00018000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF8006168[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF800616C[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF8006170[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xb5 + // .. .. ==> 0XF8006174[10:0] = 0x000000B5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000B5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000B5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000730[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000734[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF8000738[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001621U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF800073C[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001620U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 47 + // .. ==> 0XF8000830[5:0] = 0x0000002FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000002FU + // .. SDIO0_CD_SEL = 46 + // .. ==> 0XF8000830[21:16] = 0x0000002EU + // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E002FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x80000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00080000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00080000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00080000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. MASK_1_MSW = 0x37 + // .. .. .. .. ==> 0XE000A00C[21:16] = 0x00000037U + // .. .. .. .. ==> MASK : 0x003F0000U VAL : 0x00370000U + // .. .. .. .. DATA_1_MSW = 0x8 + // .. .. .. .. ==> 0XE000A00C[5:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000003FU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A00C, 0x003F003FU ,0x00370008U), + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x80000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00080000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00080000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00080000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. MASK_1_MSW = 0x37 + // .. .. .. .. ==> 0XE000A00C[21:16] = 0x00000037U + // .. .. .. .. ==> MASK : 0x003F0000U VAL : 0x00370000U + // .. .. .. .. DATA_1_MSW = 0x0 + // .. .. .. .. ==> 0XE000A00C[5:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A00C, 0x003F003FU ,0x00370000U), + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. MASK_1_MSW = 0x37 + // .. .. .. .. ==> 0XE000A00C[21:16] = 0x00000037U + // .. .. .. .. ==> MASK : 0x003F0000U VAL : 0x00370000U + // .. .. .. .. DATA_1_MSW = 0x8 + // .. .. .. .. ==> 0XE000A00C[5:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000003FU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A00C, 0x003F003FU ,0x00370008U), + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + unsigned long *addr = (unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + unsigned long *addr = (unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_init_gpl.h b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_init_gpl.h new file mode 100644 index 0000000..5eac42c --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158731 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 100000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 166666672 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 100000000 +#define FPGA3_FREQ 200000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_parameters.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_parameters.xml new file mode 100644 index 0000000..025d04a --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/ps7_parameters.xml @@ -0,0 +1,629 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/sim/z_turn_processing_system7_0_0.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/sim/z_turn_processing_system7_0_0.v new file mode 100644 index 0000000..46bf2b6 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/sim/z_turn_processing_system7_0_0.v @@ -0,0 +1,726 @@ + + + +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0 +// IP Revision: 1 + +`timescale 1ns/1ps + +module z_turn_processing_system7_0_0 ( +ENET0_PTP_DELAY_REQ_RX, +ENET0_PTP_DELAY_REQ_TX, +ENET0_PTP_PDELAY_REQ_RX, +ENET0_PTP_PDELAY_REQ_TX, +ENET0_PTP_PDELAY_RESP_RX, +ENET0_PTP_PDELAY_RESP_TX, +ENET0_PTP_SYNC_FRAME_RX, +ENET0_PTP_SYNC_FRAME_TX, +ENET0_SOF_RX, +ENET0_SOF_TX, +GPIO_I, +GPIO_O, +GPIO_T, +I2C0_SDA_I, +I2C0_SDA_O, +I2C0_SDA_T, +I2C0_SCL_I, +I2C0_SCL_O, +I2C0_SCL_T, +USB0_PORT_INDCTL, +USB0_VBUS_PWRSELECT, +USB0_VBUS_PWRFAULT, +M_AXI_GP0_ARVALID, +M_AXI_GP0_AWVALID, +M_AXI_GP0_BREADY, +M_AXI_GP0_RREADY, +M_AXI_GP0_WLAST, +M_AXI_GP0_WVALID, +M_AXI_GP0_ARID, +M_AXI_GP0_AWID, +M_AXI_GP0_WID, +M_AXI_GP0_ARBURST, +M_AXI_GP0_ARLOCK, +M_AXI_GP0_ARSIZE, +M_AXI_GP0_AWBURST, +M_AXI_GP0_AWLOCK, +M_AXI_GP0_AWSIZE, +M_AXI_GP0_ARPROT, +M_AXI_GP0_AWPROT, +M_AXI_GP0_ARADDR, +M_AXI_GP0_AWADDR, +M_AXI_GP0_WDATA, +M_AXI_GP0_ARCACHE, +M_AXI_GP0_ARLEN, +M_AXI_GP0_ARQOS, +M_AXI_GP0_AWCACHE, +M_AXI_GP0_AWLEN, +M_AXI_GP0_AWQOS, +M_AXI_GP0_WSTRB, +M_AXI_GP0_ACLK, +M_AXI_GP0_ARREADY, +M_AXI_GP0_AWREADY, +M_AXI_GP0_BVALID, +M_AXI_GP0_RLAST, +M_AXI_GP0_RVALID, +M_AXI_GP0_WREADY, +M_AXI_GP0_BID, +M_AXI_GP0_RID, +M_AXI_GP0_BRESP, +M_AXI_GP0_RRESP, +M_AXI_GP0_RDATA, +S_AXI_HP0_ARREADY, +S_AXI_HP0_AWREADY, +S_AXI_HP0_BVALID, +S_AXI_HP0_RLAST, +S_AXI_HP0_RVALID, +S_AXI_HP0_WREADY, +S_AXI_HP0_BRESP, +S_AXI_HP0_RRESP, +S_AXI_HP0_BID, +S_AXI_HP0_RID, +S_AXI_HP0_RDATA, +S_AXI_HP0_RCOUNT, +S_AXI_HP0_WCOUNT, +S_AXI_HP0_RACOUNT, +S_AXI_HP0_WACOUNT, +S_AXI_HP0_ACLK, +S_AXI_HP0_ARVALID, +S_AXI_HP0_AWVALID, +S_AXI_HP0_BREADY, +S_AXI_HP0_RDISSUECAP1_EN, +S_AXI_HP0_RREADY, +S_AXI_HP0_WLAST, +S_AXI_HP0_WRISSUECAP1_EN, +S_AXI_HP0_WVALID, +S_AXI_HP0_ARBURST, +S_AXI_HP0_ARLOCK, +S_AXI_HP0_ARSIZE, +S_AXI_HP0_AWBURST, +S_AXI_HP0_AWLOCK, +S_AXI_HP0_AWSIZE, +S_AXI_HP0_ARPROT, +S_AXI_HP0_AWPROT, +S_AXI_HP0_ARADDR, +S_AXI_HP0_AWADDR, +S_AXI_HP0_ARCACHE, +S_AXI_HP0_ARLEN, +S_AXI_HP0_ARQOS, +S_AXI_HP0_AWCACHE, +S_AXI_HP0_AWLEN, +S_AXI_HP0_AWQOS, +S_AXI_HP0_ARID, +S_AXI_HP0_AWID, +S_AXI_HP0_WID, +S_AXI_HP0_WDATA, +S_AXI_HP0_WSTRB, +IRQ_F2P, +FCLK_CLK0, +FCLK_CLK1, +FCLK_CLK2, +FCLK_CLK3, +FCLK_RESET0_N, +FCLK_RESET1_N, +FCLK_RESET2_N, +FCLK_RESET3_N, +MIO, +DDR_CAS_n, +DDR_CKE, +DDR_Clk_n, +DDR_Clk, +DDR_CS_n, +DDR_DRSTB, +DDR_ODT, +DDR_RAS_n, +DDR_WEB, +DDR_BankAddr, +DDR_Addr, +DDR_VRN, +DDR_VRP, +DDR_DM, +DDR_DQ, +DDR_DQS_n, +DDR_DQS, +PS_SRSTB, +PS_CLK, +PS_PORB +); +output ENET0_PTP_DELAY_REQ_RX; +output ENET0_PTP_DELAY_REQ_TX; +output ENET0_PTP_PDELAY_REQ_RX; +output ENET0_PTP_PDELAY_REQ_TX; +output ENET0_PTP_PDELAY_RESP_RX; +output ENET0_PTP_PDELAY_RESP_TX; +output ENET0_PTP_SYNC_FRAME_RX; +output ENET0_PTP_SYNC_FRAME_TX; +output ENET0_SOF_RX; +output ENET0_SOF_TX; +input [63 : 0] GPIO_I; +output [63 : 0] GPIO_O; +output [63 : 0] GPIO_T; +input I2C0_SDA_I; +output I2C0_SDA_O; +output I2C0_SDA_T; +input I2C0_SCL_I; +output I2C0_SCL_O; +output I2C0_SCL_T; +output [1 : 0] USB0_PORT_INDCTL; +output USB0_VBUS_PWRSELECT; +input USB0_VBUS_PWRFAULT; +output M_AXI_GP0_ARVALID; +output M_AXI_GP0_AWVALID; +output M_AXI_GP0_BREADY; +output M_AXI_GP0_RREADY; +output M_AXI_GP0_WLAST; +output M_AXI_GP0_WVALID; +output [11 : 0] M_AXI_GP0_ARID; +output [11 : 0] M_AXI_GP0_AWID; +output [11 : 0] M_AXI_GP0_WID; +output [1 : 0] M_AXI_GP0_ARBURST; +output [1 : 0] M_AXI_GP0_ARLOCK; +output [2 : 0] M_AXI_GP0_ARSIZE; +output [1 : 0] M_AXI_GP0_AWBURST; +output [1 : 0] M_AXI_GP0_AWLOCK; +output [2 : 0] M_AXI_GP0_AWSIZE; +output [2 : 0] M_AXI_GP0_ARPROT; +output [2 : 0] M_AXI_GP0_AWPROT; +output [31 : 0] M_AXI_GP0_ARADDR; +output [31 : 0] M_AXI_GP0_AWADDR; +output [31 : 0] M_AXI_GP0_WDATA; +output [3 : 0] M_AXI_GP0_ARCACHE; +output [3 : 0] M_AXI_GP0_ARLEN; +output [3 : 0] M_AXI_GP0_ARQOS; +output [3 : 0] M_AXI_GP0_AWCACHE; +output [3 : 0] M_AXI_GP0_AWLEN; +output [3 : 0] M_AXI_GP0_AWQOS; +output [3 : 0] M_AXI_GP0_WSTRB; +input M_AXI_GP0_ACLK; +input M_AXI_GP0_ARREADY; +input M_AXI_GP0_AWREADY; +input M_AXI_GP0_BVALID; +input M_AXI_GP0_RLAST; +input M_AXI_GP0_RVALID; +input M_AXI_GP0_WREADY; +input [11 : 0] M_AXI_GP0_BID; +input [11 : 0] M_AXI_GP0_RID; +input [1 : 0] M_AXI_GP0_BRESP; +input [1 : 0] M_AXI_GP0_RRESP; +input [31 : 0] M_AXI_GP0_RDATA; +output S_AXI_HP0_ARREADY; +output S_AXI_HP0_AWREADY; +output S_AXI_HP0_BVALID; +output S_AXI_HP0_RLAST; +output S_AXI_HP0_RVALID; +output S_AXI_HP0_WREADY; +output [1 : 0] S_AXI_HP0_BRESP; +output [1 : 0] S_AXI_HP0_RRESP; +output [5 : 0] S_AXI_HP0_BID; +output [5 : 0] S_AXI_HP0_RID; +output [63 : 0] S_AXI_HP0_RDATA; +output [7 : 0] S_AXI_HP0_RCOUNT; +output [7 : 0] S_AXI_HP0_WCOUNT; +output [2 : 0] S_AXI_HP0_RACOUNT; +output [5 : 0] S_AXI_HP0_WACOUNT; +input S_AXI_HP0_ACLK; +input S_AXI_HP0_ARVALID; +input S_AXI_HP0_AWVALID; +input S_AXI_HP0_BREADY; +input S_AXI_HP0_RDISSUECAP1_EN; +input S_AXI_HP0_RREADY; +input S_AXI_HP0_WLAST; +input S_AXI_HP0_WRISSUECAP1_EN; +input S_AXI_HP0_WVALID; +input [1 : 0] S_AXI_HP0_ARBURST; +input [1 : 0] S_AXI_HP0_ARLOCK; +input [2 : 0] S_AXI_HP0_ARSIZE; +input [1 : 0] S_AXI_HP0_AWBURST; +input [1 : 0] S_AXI_HP0_AWLOCK; +input [2 : 0] S_AXI_HP0_AWSIZE; +input [2 : 0] S_AXI_HP0_ARPROT; +input [2 : 0] S_AXI_HP0_AWPROT; +input [31 : 0] S_AXI_HP0_ARADDR; +input [31 : 0] S_AXI_HP0_AWADDR; +input [3 : 0] S_AXI_HP0_ARCACHE; +input [3 : 0] S_AXI_HP0_ARLEN; +input [3 : 0] S_AXI_HP0_ARQOS; +input [3 : 0] S_AXI_HP0_AWCACHE; +input [3 : 0] S_AXI_HP0_AWLEN; +input [3 : 0] S_AXI_HP0_AWQOS; +input [5 : 0] S_AXI_HP0_ARID; +input [5 : 0] S_AXI_HP0_AWID; +input [5 : 0] S_AXI_HP0_WID; +input [63 : 0] S_AXI_HP0_WDATA; +input [7 : 0] S_AXI_HP0_WSTRB; +input [15 : 0] IRQ_F2P; +output FCLK_CLK0; +output FCLK_CLK1; +output FCLK_CLK2; +output FCLK_CLK3; +output FCLK_RESET0_N; +output FCLK_RESET1_N; +output FCLK_RESET2_N; +output FCLK_RESET3_N; +input [53 : 0] MIO; +input DDR_CAS_n; +input DDR_CKE; +input DDR_Clk_n; +input DDR_Clk; +input DDR_CS_n; +input DDR_DRSTB; +input DDR_ODT; +input DDR_RAS_n; +input DDR_WEB; +input [2 : 0] DDR_BankAddr; +input [14 : 0] DDR_Addr; +input DDR_VRN; +input DDR_VRP; +input [3 : 0] DDR_DM; +input [31 : 0] DDR_DQ; +input [3 : 0] DDR_DQS_n; +input [3 : 0] DDR_DQS; +input PS_SRSTB; +input PS_CLK; +input PS_PORB; + + processing_system7_bfm_v2_0_processing_system7_bfm #( + .C_USE_M_AXI_GP0(1), + .C_USE_M_AXI_GP1(0), + .C_USE_S_AXI_ACP(0), + .C_USE_S_AXI_GP0(0), + .C_USE_S_AXI_GP1(0), + .C_USE_S_AXI_HP0(1), + .C_USE_S_AXI_HP1(0), + .C_USE_S_AXI_HP2(0), + .C_USE_S_AXI_HP3(0), + .C_S_AXI_HP0_DATA_WIDTH(64), + .C_S_AXI_HP1_DATA_WIDTH(64), + .C_S_AXI_HP2_DATA_WIDTH(64), + .C_S_AXI_HP3_DATA_WIDTH(64), + .C_HIGH_OCM_EN(0), + .C_FCLK_CLK0_FREQ(166.666672), + .C_FCLK_CLK1_FREQ(50.0), + .C_FCLK_CLK2_FREQ(100.0), + .C_FCLK_CLK3_FREQ(200.0), + .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0), + .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0), + .C_M_AXI_GP0_THREAD_ID_WIDTH (12), + .C_M_AXI_GP1_THREAD_ID_WIDTH (12) + ) inst ( + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), + .M_AXI_GP0_WID(M_AXI_GP0_WID), + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), + .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), + .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), + .M_AXI_GP0_BID(M_AXI_GP0_BID), + .M_AXI_GP0_RID(M_AXI_GP0_RID), + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), + .M_AXI_GP1_ARVALID(), + .M_AXI_GP1_AWVALID(), + .M_AXI_GP1_BREADY(), + .M_AXI_GP1_RREADY(), + .M_AXI_GP1_WLAST(), + .M_AXI_GP1_WVALID(), + .M_AXI_GP1_ARID(), + .M_AXI_GP1_AWID(), + .M_AXI_GP1_WID(), + .M_AXI_GP1_ARBURST(), + .M_AXI_GP1_ARLOCK(), + .M_AXI_GP1_ARSIZE(), + .M_AXI_GP1_AWBURST(), + .M_AXI_GP1_AWLOCK(), + .M_AXI_GP1_AWSIZE(), + .M_AXI_GP1_ARPROT(), + .M_AXI_GP1_AWPROT(), + .M_AXI_GP1_ARADDR(), + .M_AXI_GP1_AWADDR(), + .M_AXI_GP1_WDATA(), + .M_AXI_GP1_ARCACHE(), + .M_AXI_GP1_ARLEN(), + .M_AXI_GP1_ARQOS(), + .M_AXI_GP1_AWCACHE(), + .M_AXI_GP1_AWLEN(), + .M_AXI_GP1_AWQOS(), + .M_AXI_GP1_WSTRB(), + .M_AXI_GP1_ACLK(1'B0), + .M_AXI_GP1_ARREADY(1'B0), + .M_AXI_GP1_AWREADY(1'B0), + .M_AXI_GP1_BVALID(1'B0), + .M_AXI_GP1_RLAST(1'B0), + .M_AXI_GP1_RVALID(1'B0), + .M_AXI_GP1_WREADY(1'B0), + .M_AXI_GP1_BID(12'B0), + .M_AXI_GP1_RID(12'B0), + .M_AXI_GP1_BRESP(2'B0), + .M_AXI_GP1_RRESP(2'B0), + .M_AXI_GP1_RDATA(32'B0), + .S_AXI_GP0_ARREADY(), + .S_AXI_GP0_AWREADY(), + .S_AXI_GP0_BVALID(), + .S_AXI_GP0_RLAST(), + .S_AXI_GP0_RVALID(), + .S_AXI_GP0_WREADY(), + .S_AXI_GP0_BRESP(), + .S_AXI_GP0_RRESP(), + .S_AXI_GP0_RDATA(), + .S_AXI_GP0_BID(), + .S_AXI_GP0_RID(), + .S_AXI_GP0_ACLK(1'B0), + .S_AXI_GP0_ARVALID(1'B0), + .S_AXI_GP0_AWVALID(1'B0), + .S_AXI_GP0_BREADY(1'B0), + .S_AXI_GP0_RREADY(1'B0), + .S_AXI_GP0_WLAST(1'B0), + .S_AXI_GP0_WVALID(1'B0), + .S_AXI_GP0_ARBURST(2'B0), + .S_AXI_GP0_ARLOCK(2'B0), + .S_AXI_GP0_ARSIZE(3'B0), + .S_AXI_GP0_AWBURST(2'B0), + .S_AXI_GP0_AWLOCK(2'B0), + .S_AXI_GP0_AWSIZE(3'B0), + .S_AXI_GP0_ARPROT(3'B0), + .S_AXI_GP0_AWPROT(3'B0), + .S_AXI_GP0_ARADDR(32'B0), + .S_AXI_GP0_AWADDR(32'B0), + .S_AXI_GP0_WDATA(32'B0), + .S_AXI_GP0_ARCACHE(4'B0), + .S_AXI_GP0_ARLEN(4'B0), + .S_AXI_GP0_ARQOS(4'B0), + .S_AXI_GP0_AWCACHE(4'B0), + .S_AXI_GP0_AWLEN(4'B0), + .S_AXI_GP0_AWQOS(4'B0), + .S_AXI_GP0_WSTRB(4'B0), + .S_AXI_GP0_ARID(6'B0), + .S_AXI_GP0_AWID(6'B0), + .S_AXI_GP0_WID(6'B0), + .S_AXI_GP1_ARREADY(), + .S_AXI_GP1_AWREADY(), + .S_AXI_GP1_BVALID(), + .S_AXI_GP1_RLAST(), + .S_AXI_GP1_RVALID(), + .S_AXI_GP1_WREADY(), + .S_AXI_GP1_BRESP(), + .S_AXI_GP1_RRESP(), + .S_AXI_GP1_RDATA(), + .S_AXI_GP1_BID(), + .S_AXI_GP1_RID(), + .S_AXI_GP1_ACLK(1'B0), + .S_AXI_GP1_ARVALID(1'B0), + .S_AXI_GP1_AWVALID(1'B0), + .S_AXI_GP1_BREADY(1'B0), + .S_AXI_GP1_RREADY(1'B0), + .S_AXI_GP1_WLAST(1'B0), + .S_AXI_GP1_WVALID(1'B0), + .S_AXI_GP1_ARBURST(2'B0), + .S_AXI_GP1_ARLOCK(2'B0), + .S_AXI_GP1_ARSIZE(3'B0), + .S_AXI_GP1_AWBURST(2'B0), + .S_AXI_GP1_AWLOCK(2'B0), + .S_AXI_GP1_AWSIZE(3'B0), + .S_AXI_GP1_ARPROT(3'B0), + .S_AXI_GP1_AWPROT(3'B0), + .S_AXI_GP1_ARADDR(32'B0), + .S_AXI_GP1_AWADDR(32'B0), + .S_AXI_GP1_WDATA(32'B0), + .S_AXI_GP1_ARCACHE(4'B0), + .S_AXI_GP1_ARLEN(4'B0), + .S_AXI_GP1_ARQOS(4'B0), + .S_AXI_GP1_AWCACHE(4'B0), + .S_AXI_GP1_AWLEN(4'B0), + .S_AXI_GP1_AWQOS(4'B0), + .S_AXI_GP1_WSTRB(4'B0), + .S_AXI_GP1_ARID(6'B0), + .S_AXI_GP1_AWID(6'B0), + .S_AXI_GP1_WID(6'B0), + .S_AXI_ACP_ARREADY(), + .S_AXI_ACP_AWREADY(), + .S_AXI_ACP_BVALID(), + .S_AXI_ACP_RLAST(), + .S_AXI_ACP_RVALID(), + .S_AXI_ACP_WREADY(), + .S_AXI_ACP_BRESP(), + .S_AXI_ACP_RRESP(), + .S_AXI_ACP_BID(), + .S_AXI_ACP_RID(), + .S_AXI_ACP_RDATA(), + .S_AXI_ACP_ACLK(1'B0), + .S_AXI_ACP_ARVALID(1'B0), + .S_AXI_ACP_AWVALID(1'B0), + .S_AXI_ACP_BREADY(1'B0), + .S_AXI_ACP_RREADY(1'B0), + .S_AXI_ACP_WLAST(1'B0), + .S_AXI_ACP_WVALID(1'B0), + .S_AXI_ACP_ARID(3'B0), + .S_AXI_ACP_ARPROT(3'B0), + .S_AXI_ACP_AWID(3'B0), + .S_AXI_ACP_AWPROT(3'B0), + .S_AXI_ACP_WID(3'B0), + .S_AXI_ACP_ARADDR(32'B0), + .S_AXI_ACP_AWADDR(32'B0), + .S_AXI_ACP_ARCACHE(4'B0), + .S_AXI_ACP_ARLEN(4'B0), + .S_AXI_ACP_ARQOS(4'B0), + .S_AXI_ACP_AWCACHE(4'B0), + .S_AXI_ACP_AWLEN(4'B0), + .S_AXI_ACP_AWQOS(4'B0), + .S_AXI_ACP_ARBURST(2'B0), + .S_AXI_ACP_ARLOCK(2'B0), + .S_AXI_ACP_ARSIZE(3'B0), + .S_AXI_ACP_AWBURST(2'B0), + .S_AXI_ACP_AWLOCK(2'B0), + .S_AXI_ACP_AWSIZE(3'B0), + .S_AXI_ACP_ARUSER(5'B0), + .S_AXI_ACP_AWUSER(5'B0), + .S_AXI_ACP_WDATA(64'B0), + .S_AXI_ACP_WSTRB(8'B0), + .S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY), + .S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY), + .S_AXI_HP0_BVALID(S_AXI_HP0_BVALID), + .S_AXI_HP0_RLAST(S_AXI_HP0_RLAST), + .S_AXI_HP0_RVALID(S_AXI_HP0_RVALID), + .S_AXI_HP0_WREADY(S_AXI_HP0_WREADY), + .S_AXI_HP0_BRESP(S_AXI_HP0_BRESP), + .S_AXI_HP0_RRESP(S_AXI_HP0_RRESP), + .S_AXI_HP0_BID(S_AXI_HP0_BID), + .S_AXI_HP0_RID(S_AXI_HP0_RID), + .S_AXI_HP0_RDATA(S_AXI_HP0_RDATA), + .S_AXI_HP0_ACLK(S_AXI_HP0_ACLK), + .S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID), + .S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID), + .S_AXI_HP0_BREADY(S_AXI_HP0_BREADY), + .S_AXI_HP0_RREADY(S_AXI_HP0_RREADY), + .S_AXI_HP0_WLAST(S_AXI_HP0_WLAST), + .S_AXI_HP0_WVALID(S_AXI_HP0_WVALID), + .S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST), + .S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK), + .S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE), + .S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST), + .S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK), + .S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE), + .S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT), + .S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT), + .S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR), + .S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR), + .S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE), + .S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN), + .S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS), + .S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE), + .S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN), + .S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS), + .S_AXI_HP0_ARID(S_AXI_HP0_ARID), + .S_AXI_HP0_AWID(S_AXI_HP0_AWID), + .S_AXI_HP0_WID(S_AXI_HP0_WID), + .S_AXI_HP0_WDATA(S_AXI_HP0_WDATA), + .S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB), + .S_AXI_HP1_ARREADY(), + .S_AXI_HP1_AWREADY(), + .S_AXI_HP1_BVALID(), + .S_AXI_HP1_RLAST(), + .S_AXI_HP1_RVALID(), + .S_AXI_HP1_WREADY(), + .S_AXI_HP1_BRESP(), + .S_AXI_HP1_RRESP(), + .S_AXI_HP1_BID(), + .S_AXI_HP1_RID(), + .S_AXI_HP1_RDATA(), + .S_AXI_HP1_ACLK(1'B0), + .S_AXI_HP1_ARVALID(1'B0), + .S_AXI_HP1_AWVALID(1'B0), + .S_AXI_HP1_BREADY(1'B0), + .S_AXI_HP1_RREADY(1'B0), + .S_AXI_HP1_WLAST(1'B0), + .S_AXI_HP1_WVALID(1'B0), + .S_AXI_HP1_ARBURST(2'B0), + .S_AXI_HP1_ARLOCK(2'B0), + .S_AXI_HP1_ARSIZE(3'B0), + .S_AXI_HP1_AWBURST(2'B0), + .S_AXI_HP1_AWLOCK(2'B0), + .S_AXI_HP1_AWSIZE(3'B0), + .S_AXI_HP1_ARPROT(3'B0), + .S_AXI_HP1_AWPROT(3'B0), + .S_AXI_HP1_ARADDR(32'B0), + .S_AXI_HP1_AWADDR(32'B0), + .S_AXI_HP1_ARCACHE(4'B0), + .S_AXI_HP1_ARLEN(4'B0), + .S_AXI_HP1_ARQOS(4'B0), + .S_AXI_HP1_AWCACHE(4'B0), + .S_AXI_HP1_AWLEN(4'B0), + .S_AXI_HP1_AWQOS(4'B0), + .S_AXI_HP1_ARID(6'B0), + .S_AXI_HP1_AWID(6'B0), + .S_AXI_HP1_WID(6'B0), + .S_AXI_HP1_WDATA(64'B0), + .S_AXI_HP1_WSTRB(8'B0), + .S_AXI_HP2_ARREADY(), + .S_AXI_HP2_AWREADY(), + .S_AXI_HP2_BVALID(), + .S_AXI_HP2_RLAST(), + .S_AXI_HP2_RVALID(), + .S_AXI_HP2_WREADY(), + .S_AXI_HP2_BRESP(), + .S_AXI_HP2_RRESP(), + .S_AXI_HP2_BID(), + .S_AXI_HP2_RID(), + .S_AXI_HP2_RDATA(), + .S_AXI_HP2_ACLK(1'B0), + .S_AXI_HP2_ARVALID(1'B0), + .S_AXI_HP2_AWVALID(1'B0), + .S_AXI_HP2_BREADY(1'B0), + .S_AXI_HP2_RREADY(1'B0), + .S_AXI_HP2_WLAST(1'B0), + .S_AXI_HP2_WVALID(1'B0), + .S_AXI_HP2_ARBURST(2'B0), + .S_AXI_HP2_ARLOCK(2'B0), + .S_AXI_HP2_ARSIZE(3'B0), + .S_AXI_HP2_AWBURST(2'B0), + .S_AXI_HP2_AWLOCK(2'B0), + .S_AXI_HP2_AWSIZE(3'B0), + .S_AXI_HP2_ARPROT(3'B0), + .S_AXI_HP2_AWPROT(3'B0), + .S_AXI_HP2_ARADDR(32'B0), + .S_AXI_HP2_AWADDR(32'B0), + .S_AXI_HP2_ARCACHE(4'B0), + .S_AXI_HP2_ARLEN(4'B0), + .S_AXI_HP2_ARQOS(4'B0), + .S_AXI_HP2_AWCACHE(4'B0), + .S_AXI_HP2_AWLEN(4'B0), + .S_AXI_HP2_AWQOS(4'B0), + .S_AXI_HP2_ARID(6'B0), + .S_AXI_HP2_AWID(6'B0), + .S_AXI_HP2_WID(6'B0), + .S_AXI_HP2_WDATA(64'B0), + .S_AXI_HP2_WSTRB(8'B0), + .S_AXI_HP3_ARREADY(), + .S_AXI_HP3_AWREADY(), + .S_AXI_HP3_BVALID(), + .S_AXI_HP3_RLAST(), + .S_AXI_HP3_RVALID(), + .S_AXI_HP3_WREADY(), + .S_AXI_HP3_BRESP(), + .S_AXI_HP3_RRESP(), + .S_AXI_HP3_BID(), + .S_AXI_HP3_RID(), + .S_AXI_HP3_RDATA(), + .S_AXI_HP3_ACLK(1'B0), + .S_AXI_HP3_ARVALID(1'B0), + .S_AXI_HP3_AWVALID(1'B0), + .S_AXI_HP3_BREADY(1'B0), + .S_AXI_HP3_RREADY(1'B0), + .S_AXI_HP3_WLAST(1'B0), + .S_AXI_HP3_WVALID(1'B0), + .S_AXI_HP3_ARBURST(2'B0), + .S_AXI_HP3_ARLOCK(2'B0), + .S_AXI_HP3_ARSIZE(3'B0), + .S_AXI_HP3_AWBURST(2'B0), + .S_AXI_HP3_AWLOCK(2'B0), + .S_AXI_HP3_AWSIZE(3'B0), + .S_AXI_HP3_ARPROT(3'B0), + .S_AXI_HP3_AWPROT(3'B0), + .S_AXI_HP3_ARADDR(32'B0), + .S_AXI_HP3_AWADDR(32'B0), + .S_AXI_HP3_ARCACHE(4'B0), + .S_AXI_HP3_ARLEN(4'B0), + .S_AXI_HP3_ARQOS(4'B0), + .S_AXI_HP3_AWCACHE(4'B0), + .S_AXI_HP3_AWLEN(4'B0), + .S_AXI_HP3_AWQOS(4'B0), + .S_AXI_HP3_ARID(6'B0), + .S_AXI_HP3_AWID(6'B0), + .S_AXI_HP3_WID(6'B0), + .S_AXI_HP3_WDATA(64'B0), + .S_AXI_HP3_WSTRB(8'B0), + .FCLK_CLK0(FCLK_CLK0), + + .FCLK_CLK1(FCLK_CLK1), + + .FCLK_CLK2(FCLK_CLK2), + + .FCLK_CLK3(FCLK_CLK3), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET1_N(FCLK_RESET1_N), + .FCLK_RESET2_N(FCLK_RESET2_N), + .FCLK_RESET3_N(FCLK_RESET3_N), + .IRQ_F2P(IRQ_F2P), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/synth/z_turn_processing_system7_0_0.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/synth/z_turn_processing_system7_0_0.v new file mode 100644 index 0000000..eb64c42 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/synth/z_turn_processing_system7_0_0.v @@ -0,0 +1,1197 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:processing_system7:5.5 +// IP Revision: 1 + +(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2015.2" *) +(* CHECK_LICENSE_TYPE = "z_turn_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) +(* CORE_GENERATION_INFO = "z_turn_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=16,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=1,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=true,C_FCLK_CLK2_BUF=true,C_FCLK_CLK3_BUF=true,C_PACKAGE_NAME=clg400}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module z_turn_processing_system7_0_0 ( + ENET0_PTP_DELAY_REQ_RX, + ENET0_PTP_DELAY_REQ_TX, + ENET0_PTP_PDELAY_REQ_RX, + ENET0_PTP_PDELAY_REQ_TX, + ENET0_PTP_PDELAY_RESP_RX, + ENET0_PTP_PDELAY_RESP_TX, + ENET0_PTP_SYNC_FRAME_RX, + ENET0_PTP_SYNC_FRAME_TX, + ENET0_SOF_RX, + ENET0_SOF_TX, + GPIO_I, + GPIO_O, + GPIO_T, + I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + S_AXI_HP0_ARREADY, + S_AXI_HP0_AWREADY, + S_AXI_HP0_BVALID, + S_AXI_HP0_RLAST, + S_AXI_HP0_RVALID, + S_AXI_HP0_WREADY, + S_AXI_HP0_BRESP, + S_AXI_HP0_RRESP, + S_AXI_HP0_BID, + S_AXI_HP0_RID, + S_AXI_HP0_RDATA, + S_AXI_HP0_RCOUNT, + S_AXI_HP0_WCOUNT, + S_AXI_HP0_RACOUNT, + S_AXI_HP0_WACOUNT, + S_AXI_HP0_ACLK, + S_AXI_HP0_ARVALID, + S_AXI_HP0_AWVALID, + S_AXI_HP0_BREADY, + S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RREADY, + S_AXI_HP0_WLAST, + S_AXI_HP0_WRISSUECAP1_EN, + S_AXI_HP0_WVALID, + S_AXI_HP0_ARBURST, + S_AXI_HP0_ARLOCK, + S_AXI_HP0_ARSIZE, + S_AXI_HP0_AWBURST, + S_AXI_HP0_AWLOCK, + S_AXI_HP0_AWSIZE, + S_AXI_HP0_ARPROT, + S_AXI_HP0_AWPROT, + S_AXI_HP0_ARADDR, + S_AXI_HP0_AWADDR, + S_AXI_HP0_ARCACHE, + S_AXI_HP0_ARLEN, + S_AXI_HP0_ARQOS, + S_AXI_HP0_AWCACHE, + S_AXI_HP0_AWLEN, + S_AXI_HP0_AWQOS, + S_AXI_HP0_ARID, + S_AXI_HP0_AWID, + S_AXI_HP0_WID, + S_AXI_HP0_WDATA, + S_AXI_HP0_WSTRB, + IRQ_F2P, + FCLK_CLK0, + FCLK_CLK1, + FCLK_CLK2, + FCLK_CLK3, + FCLK_RESET0_N, + FCLK_RESET1_N, + FCLK_RESET2_N, + FCLK_RESET3_N, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB +); + +(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX" *) +output wire ENET0_PTP_DELAY_REQ_RX; +(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_TX" *) +output wire ENET0_PTP_DELAY_REQ_TX; +(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_RX" *) +output wire ENET0_PTP_PDELAY_REQ_RX; +(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_TX" *) +output wire ENET0_PTP_PDELAY_REQ_TX; +(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_RX" *) +output wire ENET0_PTP_PDELAY_RESP_RX; +(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_TX" *) +output wire ENET0_PTP_PDELAY_RESP_TX; +(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_RX" *) +output wire ENET0_PTP_SYNC_FRAME_RX; +(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_TX" *) +output wire ENET0_PTP_SYNC_FRAME_TX; +(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_RX" *) +output wire ENET0_SOF_RX; +(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_TX" *) +output wire ENET0_SOF_TX; +(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I" *) +input wire [63 : 0] GPIO_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O" *) +output wire [63 : 0] GPIO_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T" *) +output wire [63 : 0] GPIO_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *) +input wire I2C0_SDA_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *) +output wire I2C0_SDA_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *) +output wire I2C0_SDA_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *) +input wire I2C0_SCL_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *) +output wire I2C0_SCL_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *) +output wire I2C0_SCL_T; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) +output wire [1 : 0] USB0_PORT_INDCTL; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) +output wire USB0_VBUS_PWRSELECT; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) +input wire USB0_VBUS_PWRFAULT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) +output wire M_AXI_GP0_ARVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) +output wire M_AXI_GP0_AWVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) +output wire M_AXI_GP0_BREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) +output wire M_AXI_GP0_RREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) +output wire M_AXI_GP0_WLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) +output wire M_AXI_GP0_WVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) +output wire [11 : 0] M_AXI_GP0_ARID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) +output wire [11 : 0] M_AXI_GP0_AWID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) +output wire [11 : 0] M_AXI_GP0_WID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) +output wire [1 : 0] M_AXI_GP0_ARBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) +output wire [1 : 0] M_AXI_GP0_ARLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) +output wire [2 : 0] M_AXI_GP0_ARSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) +output wire [1 : 0] M_AXI_GP0_AWBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) +output wire [1 : 0] M_AXI_GP0_AWLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) +output wire [2 : 0] M_AXI_GP0_AWSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) +output wire [2 : 0] M_AXI_GP0_ARPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) +output wire [2 : 0] M_AXI_GP0_AWPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) +output wire [31 : 0] M_AXI_GP0_ARADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) +output wire [31 : 0] M_AXI_GP0_AWADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) +output wire [31 : 0] M_AXI_GP0_WDATA; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) +output wire [3 : 0] M_AXI_GP0_ARCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) +output wire [3 : 0] M_AXI_GP0_ARLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) +output wire [3 : 0] M_AXI_GP0_ARQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) +output wire [3 : 0] M_AXI_GP0_AWCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) +output wire [3 : 0] M_AXI_GP0_AWLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) +output wire [3 : 0] M_AXI_GP0_AWQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) +output wire [3 : 0] M_AXI_GP0_WSTRB; +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) +input wire M_AXI_GP0_ACLK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) +input wire M_AXI_GP0_ARREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) +input wire M_AXI_GP0_AWREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) +input wire M_AXI_GP0_BVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) +input wire M_AXI_GP0_RLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) +input wire M_AXI_GP0_RVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) +input wire M_AXI_GP0_WREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) +input wire [11 : 0] M_AXI_GP0_BID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) +input wire [11 : 0] M_AXI_GP0_RID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) +input wire [1 : 0] M_AXI_GP0_BRESP; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) +input wire [1 : 0] M_AXI_GP0_RRESP; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) +input wire [31 : 0] M_AXI_GP0_RDATA; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY" *) +output wire S_AXI_HP0_ARREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY" *) +output wire S_AXI_HP0_AWREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID" *) +output wire S_AXI_HP0_BVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST" *) +output wire S_AXI_HP0_RLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID" *) +output wire S_AXI_HP0_RVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY" *) +output wire S_AXI_HP0_WREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BRESP" *) +output wire [1 : 0] S_AXI_HP0_BRESP; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RRESP" *) +output wire [1 : 0] S_AXI_HP0_RRESP; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BID" *) +output wire [5 : 0] S_AXI_HP0_BID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RID" *) +output wire [5 : 0] S_AXI_HP0_RID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RDATA" *) +output wire [63 : 0] S_AXI_HP0_RDATA; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RCOUNT" *) +output wire [7 : 0] S_AXI_HP0_RCOUNT; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WCOUNT" *) +output wire [7 : 0] S_AXI_HP0_WCOUNT; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RACOUNT" *) +output wire [2 : 0] S_AXI_HP0_RACOUNT; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT" *) +output wire [5 : 0] S_AXI_HP0_WACOUNT; +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK" *) +input wire S_AXI_HP0_ACLK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID" *) +input wire S_AXI_HP0_ARVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID" *) +input wire S_AXI_HP0_AWVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY" *) +input wire S_AXI_HP0_BREADY; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN" *) +input wire S_AXI_HP0_RDISSUECAP1_EN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY" *) +input wire S_AXI_HP0_RREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST" *) +input wire S_AXI_HP0_WLAST; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN" *) +input wire S_AXI_HP0_WRISSUECAP1_EN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID" *) +input wire S_AXI_HP0_WVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST" *) +input wire [1 : 0] S_AXI_HP0_ARBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK" *) +input wire [1 : 0] S_AXI_HP0_ARLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE" *) +input wire [2 : 0] S_AXI_HP0_ARSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWBURST" *) +input wire [1 : 0] S_AXI_HP0_AWBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLOCK" *) +input wire [1 : 0] S_AXI_HP0_AWLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWSIZE" *) +input wire [2 : 0] S_AXI_HP0_AWSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT" *) +input wire [2 : 0] S_AXI_HP0_ARPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWPROT" *) +input wire [2 : 0] S_AXI_HP0_AWPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR" *) +input wire [31 : 0] S_AXI_HP0_ARADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR" *) +input wire [31 : 0] S_AXI_HP0_AWADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE" *) +input wire [3 : 0] S_AXI_HP0_ARCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN" *) +input wire [3 : 0] S_AXI_HP0_ARLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS" *) +input wire [3 : 0] S_AXI_HP0_ARQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWCACHE" *) +input wire [3 : 0] S_AXI_HP0_AWCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLEN" *) +input wire [3 : 0] S_AXI_HP0_AWLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWQOS" *) +input wire [3 : 0] S_AXI_HP0_AWQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID" *) +input wire [5 : 0] S_AXI_HP0_ARID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWID" *) +input wire [5 : 0] S_AXI_HP0_AWID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *) +input wire [5 : 0] S_AXI_HP0_WID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *) +input wire [63 : 0] S_AXI_HP0_WDATA; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *) +input wire [7 : 0] S_AXI_HP0_WSTRB; +(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) +input wire [15 : 0] IRQ_F2P; +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) +output wire FCLK_CLK0; +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) +output wire FCLK_CLK1; +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *) +output wire FCLK_CLK2; +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *) +output wire FCLK_CLK3; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) +output wire FCLK_RESET0_N; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET1_N RST" *) +output wire FCLK_RESET1_N; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET2_N RST" *) +output wire FCLK_RESET2_N; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET3_N RST" *) +output wire FCLK_RESET3_N; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) +inout wire [53 : 0] MIO; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) +inout wire DDR_CAS_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) +inout wire DDR_CKE; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) +inout wire DDR_Clk_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) +inout wire DDR_Clk; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) +inout wire DDR_CS_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) +inout wire DDR_DRSTB; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) +inout wire DDR_ODT; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) +inout wire DDR_RAS_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) +inout wire DDR_WEB; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) +inout wire [2 : 0] DDR_BankAddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) +inout wire [14 : 0] DDR_Addr; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) +inout wire DDR_VRN; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) +inout wire DDR_VRP; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) +inout wire [3 : 0] DDR_DM; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) +inout wire [31 : 0] DDR_DQ; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) +inout wire [3 : 0] DDR_DQS_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) +inout wire [3 : 0] DDR_DQS; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) +inout wire PS_SRSTB; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) +inout wire PS_CLK; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) +inout wire PS_PORB; + + processing_system7_v5_5_processing_system7 #( + .C_EN_EMIO_PJTAG(0), + .C_EN_EMIO_ENET0(0), + .C_EN_EMIO_ENET1(0), + .C_EN_EMIO_TRACE(0), + .C_INCLUDE_TRACE_BUFFER(0), + .C_TRACE_BUFFER_FIFO_SIZE(128), + .USE_TRACE_DATA_EDGE_DETECTOR(0), + .C_TRACE_PIPELINE_WIDTH(8), + .C_TRACE_BUFFER_CLOCK_DELAY(12), + .C_EMIO_GPIO_WIDTH(64), + .C_INCLUDE_ACP_TRANS_CHECK(0), + .C_USE_DEFAULT_ACP_USER_VAL(0), + .C_S_AXI_ACP_ARUSER_VAL(31), + .C_S_AXI_ACP_AWUSER_VAL(31), + .C_M_AXI_GP0_ID_WIDTH(12), + .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0), + .C_M_AXI_GP1_ID_WIDTH(12), + .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0), + .C_S_AXI_GP0_ID_WIDTH(6), + .C_S_AXI_GP1_ID_WIDTH(6), + .C_S_AXI_ACP_ID_WIDTH(3), + .C_S_AXI_HP0_ID_WIDTH(6), + .C_S_AXI_HP0_DATA_WIDTH(64), + .C_S_AXI_HP1_ID_WIDTH(6), + .C_S_AXI_HP1_DATA_WIDTH(64), + .C_S_AXI_HP2_ID_WIDTH(6), + .C_S_AXI_HP2_DATA_WIDTH(64), + .C_S_AXI_HP3_ID_WIDTH(6), + .C_S_AXI_HP3_DATA_WIDTH(64), + .C_M_AXI_GP0_THREAD_ID_WIDTH(12), + .C_M_AXI_GP1_THREAD_ID_WIDTH(12), + .C_NUM_F2P_INTR_INPUTS(16), + .C_IRQ_F2P_MODE("DIRECT"), + .C_DQ_WIDTH(32), + .C_DQS_WIDTH(4), + .C_DM_WIDTH(4), + .C_MIO_PRIMITIVE(54), + .C_TRACE_INTERNAL_WIDTH(2), + .C_USE_AXI_NONSECURE(0), + .C_USE_M_AXI_GP0(1), + .C_USE_M_AXI_GP1(0), + .C_USE_S_AXI_GP0(0), + .C_USE_S_AXI_HP0(1), + .C_USE_S_AXI_HP1(0), + .C_USE_S_AXI_HP2(0), + .C_USE_S_AXI_HP3(0), + .C_USE_S_AXI_ACP(0), + .C_PS7_SI_REV("PRODUCTION"), + .C_FCLK_CLK0_BUF("true"), + .C_FCLK_CLK1_BUF("true"), + .C_FCLK_CLK2_BUF("true"), + .C_FCLK_CLK3_BUF("true"), + .C_PACKAGE_NAME("clg400") + ) inst ( + .CAN0_PHY_TX(), + .CAN0_PHY_RX(1'B0), + .CAN1_PHY_TX(), + .CAN1_PHY_RX(1'B0), + .ENET0_GMII_TX_EN(), + .ENET0_GMII_TX_ER(), + .ENET0_MDIO_MDC(), + .ENET0_MDIO_O(), + .ENET0_MDIO_T(), + .ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX), + .ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX), + .ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX), + .ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX), + .ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX), + .ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX), + .ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX), + .ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX), + .ENET0_SOF_RX(ENET0_SOF_RX), + .ENET0_SOF_TX(ENET0_SOF_TX), + .ENET0_GMII_TXD(), + .ENET0_GMII_COL(1'B0), + .ENET0_GMII_CRS(1'B0), + .ENET0_GMII_RX_CLK(1'B0), + .ENET0_GMII_RX_DV(1'B0), + .ENET0_GMII_RX_ER(1'B0), + .ENET0_GMII_TX_CLK(1'B0), + .ENET0_MDIO_I(1'B0), + .ENET0_EXT_INTIN(1'B0), + .ENET0_GMII_RXD(8'B0), + .ENET1_GMII_TX_EN(), + .ENET1_GMII_TX_ER(), + .ENET1_MDIO_MDC(), + .ENET1_MDIO_O(), + .ENET1_MDIO_T(), + .ENET1_PTP_DELAY_REQ_RX(), + .ENET1_PTP_DELAY_REQ_TX(), + .ENET1_PTP_PDELAY_REQ_RX(), + .ENET1_PTP_PDELAY_REQ_TX(), + .ENET1_PTP_PDELAY_RESP_RX(), + .ENET1_PTP_PDELAY_RESP_TX(), + .ENET1_PTP_SYNC_FRAME_RX(), + .ENET1_PTP_SYNC_FRAME_TX(), + .ENET1_SOF_RX(), + .ENET1_SOF_TX(), + .ENET1_GMII_TXD(), + .ENET1_GMII_COL(1'B0), + .ENET1_GMII_CRS(1'B0), + .ENET1_GMII_RX_CLK(1'B0), + .ENET1_GMII_RX_DV(1'B0), + .ENET1_GMII_RX_ER(1'B0), + .ENET1_GMII_TX_CLK(1'B0), + .ENET1_MDIO_I(1'B0), + .ENET1_EXT_INTIN(1'B0), + .ENET1_GMII_RXD(8'B0), + .GPIO_I(GPIO_I), + .GPIO_O(GPIO_O), + .GPIO_T(GPIO_T), + .I2C0_SDA_I(I2C0_SDA_I), + .I2C0_SDA_O(I2C0_SDA_O), + .I2C0_SDA_T(I2C0_SDA_T), + .I2C0_SCL_I(I2C0_SCL_I), + .I2C0_SCL_O(I2C0_SCL_O), + .I2C0_SCL_T(I2C0_SCL_T), + .I2C1_SDA_I(1'B0), + .I2C1_SDA_O(), + .I2C1_SDA_T(), + .I2C1_SCL_I(1'B0), + .I2C1_SCL_O(), + .I2C1_SCL_T(), + .PJTAG_TCK(1'B0), + .PJTAG_TMS(1'B0), + .PJTAG_TDI(1'B0), + .PJTAG_TDO(), + .SDIO0_CLK(), + .SDIO0_CLK_FB(1'B0), + .SDIO0_CMD_O(), + .SDIO0_CMD_I(1'B0), + .SDIO0_CMD_T(), + .SDIO0_DATA_I(4'B0), + .SDIO0_DATA_O(), + .SDIO0_DATA_T(), + .SDIO0_LED(), + .SDIO0_CDN(1'B0), + .SDIO0_WP(1'B0), + .SDIO0_BUSPOW(), + .SDIO0_BUSVOLT(), + .SDIO1_CLK(), + .SDIO1_CLK_FB(1'B0), + .SDIO1_CMD_O(), + .SDIO1_CMD_I(1'B0), + .SDIO1_CMD_T(), + .SDIO1_DATA_I(4'B0), + .SDIO1_DATA_O(), + .SDIO1_DATA_T(), + .SDIO1_LED(), + .SDIO1_CDN(1'B0), + .SDIO1_WP(1'B0), + .SDIO1_BUSPOW(), + .SDIO1_BUSVOLT(), + .SPI0_SCLK_I(1'B0), + .SPI0_SCLK_O(), + .SPI0_SCLK_T(), + .SPI0_MOSI_I(1'B0), + .SPI0_MOSI_O(), + .SPI0_MOSI_T(), + .SPI0_MISO_I(1'B0), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_SS_I(1'B0), + .SPI0_SS_O(), + .SPI0_SS1_O(), + .SPI0_SS2_O(), + .SPI0_SS_T(), + .SPI1_SCLK_I(1'B0), + .SPI1_SCLK_O(), + .SPI1_SCLK_T(), + .SPI1_MOSI_I(1'B0), + .SPI1_MOSI_O(), + .SPI1_MOSI_T(), + .SPI1_MISO_I(1'B0), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_SS_I(1'B0), + .SPI1_SS_O(), + .SPI1_SS1_O(), + .SPI1_SS2_O(), + .SPI1_SS_T(), + .UART0_DTRN(), + .UART0_RTSN(), + .UART0_TX(), + .UART0_CTSN(1'B0), + .UART0_DCDN(1'B0), + .UART0_DSRN(1'B0), + .UART0_RIN(1'B0), + .UART0_RX(1'B1), + .UART1_DTRN(), + .UART1_RTSN(), + .UART1_TX(), + .UART1_CTSN(1'B0), + .UART1_DCDN(1'B0), + .UART1_DSRN(1'B0), + .UART1_RIN(1'B0), + .UART1_RX(1'B1), + .TTC0_WAVE0_OUT(), + .TTC0_WAVE1_OUT(), + .TTC0_WAVE2_OUT(), + .TTC0_CLK0_IN(1'B0), + .TTC0_CLK1_IN(1'B0), + .TTC0_CLK2_IN(1'B0), + .TTC1_WAVE0_OUT(), + .TTC1_WAVE1_OUT(), + .TTC1_WAVE2_OUT(), + .TTC1_CLK0_IN(1'B0), + .TTC1_CLK1_IN(1'B0), + .TTC1_CLK2_IN(1'B0), + .WDT_CLK_IN(1'B0), + .WDT_RST_OUT(), + .TRACE_CLK(1'B0), + .TRACE_CLK_OUT(), + .TRACE_CTL(), + .TRACE_DATA(), + .USB0_PORT_INDCTL(USB0_PORT_INDCTL), + .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT), + .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT), + .USB1_PORT_INDCTL(), + .USB1_VBUS_PWRSELECT(), + .USB1_VBUS_PWRFAULT(1'B0), + .SRAM_INTIN(1'B0), + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), + .M_AXI_GP0_WID(M_AXI_GP0_WID), + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), + .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), + .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), + .M_AXI_GP0_BID(M_AXI_GP0_BID), + .M_AXI_GP0_RID(M_AXI_GP0_RID), + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), + .M_AXI_GP1_ARVALID(), + .M_AXI_GP1_AWVALID(), + .M_AXI_GP1_BREADY(), + .M_AXI_GP1_RREADY(), + .M_AXI_GP1_WLAST(), + .M_AXI_GP1_WVALID(), + .M_AXI_GP1_ARID(), + .M_AXI_GP1_AWID(), + .M_AXI_GP1_WID(), + .M_AXI_GP1_ARBURST(), + .M_AXI_GP1_ARLOCK(), + .M_AXI_GP1_ARSIZE(), + .M_AXI_GP1_AWBURST(), + .M_AXI_GP1_AWLOCK(), + .M_AXI_GP1_AWSIZE(), + .M_AXI_GP1_ARPROT(), + .M_AXI_GP1_AWPROT(), + .M_AXI_GP1_ARADDR(), + .M_AXI_GP1_AWADDR(), + .M_AXI_GP1_WDATA(), + .M_AXI_GP1_ARCACHE(), + .M_AXI_GP1_ARLEN(), + .M_AXI_GP1_ARQOS(), + .M_AXI_GP1_AWCACHE(), + .M_AXI_GP1_AWLEN(), + .M_AXI_GP1_AWQOS(), + .M_AXI_GP1_WSTRB(), + .M_AXI_GP1_ACLK(1'B0), + .M_AXI_GP1_ARREADY(1'B0), + .M_AXI_GP1_AWREADY(1'B0), + .M_AXI_GP1_BVALID(1'B0), + .M_AXI_GP1_RLAST(1'B0), + .M_AXI_GP1_RVALID(1'B0), + .M_AXI_GP1_WREADY(1'B0), + .M_AXI_GP1_BID(12'B0), + .M_AXI_GP1_RID(12'B0), + .M_AXI_GP1_BRESP(2'B0), + .M_AXI_GP1_RRESP(2'B0), + .M_AXI_GP1_RDATA(32'B0), + .S_AXI_GP0_ARREADY(), + .S_AXI_GP0_AWREADY(), + .S_AXI_GP0_BVALID(), + .S_AXI_GP0_RLAST(), + .S_AXI_GP0_RVALID(), + .S_AXI_GP0_WREADY(), + .S_AXI_GP0_BRESP(), + .S_AXI_GP0_RRESP(), + .S_AXI_GP0_RDATA(), + .S_AXI_GP0_BID(), + .S_AXI_GP0_RID(), + .S_AXI_GP0_ACLK(1'B0), + .S_AXI_GP0_ARVALID(1'B0), + .S_AXI_GP0_AWVALID(1'B0), + .S_AXI_GP0_BREADY(1'B0), + .S_AXI_GP0_RREADY(1'B0), + .S_AXI_GP0_WLAST(1'B0), + .S_AXI_GP0_WVALID(1'B0), + .S_AXI_GP0_ARBURST(2'B0), + .S_AXI_GP0_ARLOCK(2'B0), + .S_AXI_GP0_ARSIZE(3'B0), + .S_AXI_GP0_AWBURST(2'B0), + .S_AXI_GP0_AWLOCK(2'B0), + .S_AXI_GP0_AWSIZE(3'B0), + .S_AXI_GP0_ARPROT(3'B0), + .S_AXI_GP0_AWPROT(3'B0), + .S_AXI_GP0_ARADDR(32'B0), + .S_AXI_GP0_AWADDR(32'B0), + .S_AXI_GP0_WDATA(32'B0), + .S_AXI_GP0_ARCACHE(4'B0), + .S_AXI_GP0_ARLEN(4'B0), + .S_AXI_GP0_ARQOS(4'B0), + .S_AXI_GP0_AWCACHE(4'B0), + .S_AXI_GP0_AWLEN(4'B0), + .S_AXI_GP0_AWQOS(4'B0), + .S_AXI_GP0_WSTRB(4'B0), + .S_AXI_GP0_ARID(6'B0), + .S_AXI_GP0_AWID(6'B0), + .S_AXI_GP0_WID(6'B0), + .S_AXI_GP1_ARREADY(), + .S_AXI_GP1_AWREADY(), + .S_AXI_GP1_BVALID(), + .S_AXI_GP1_RLAST(), + .S_AXI_GP1_RVALID(), + .S_AXI_GP1_WREADY(), + .S_AXI_GP1_BRESP(), + .S_AXI_GP1_RRESP(), + .S_AXI_GP1_RDATA(), + .S_AXI_GP1_BID(), + .S_AXI_GP1_RID(), + .S_AXI_GP1_ACLK(1'B0), + .S_AXI_GP1_ARVALID(1'B0), + .S_AXI_GP1_AWVALID(1'B0), + .S_AXI_GP1_BREADY(1'B0), + .S_AXI_GP1_RREADY(1'B0), + .S_AXI_GP1_WLAST(1'B0), + .S_AXI_GP1_WVALID(1'B0), + .S_AXI_GP1_ARBURST(2'B0), + .S_AXI_GP1_ARLOCK(2'B0), + .S_AXI_GP1_ARSIZE(3'B0), + .S_AXI_GP1_AWBURST(2'B0), + .S_AXI_GP1_AWLOCK(2'B0), + .S_AXI_GP1_AWSIZE(3'B0), + .S_AXI_GP1_ARPROT(3'B0), + .S_AXI_GP1_AWPROT(3'B0), + .S_AXI_GP1_ARADDR(32'B0), + .S_AXI_GP1_AWADDR(32'B0), + .S_AXI_GP1_WDATA(32'B0), + .S_AXI_GP1_ARCACHE(4'B0), + .S_AXI_GP1_ARLEN(4'B0), + .S_AXI_GP1_ARQOS(4'B0), + .S_AXI_GP1_AWCACHE(4'B0), + .S_AXI_GP1_AWLEN(4'B0), + .S_AXI_GP1_AWQOS(4'B0), + .S_AXI_GP1_WSTRB(4'B0), + .S_AXI_GP1_ARID(6'B0), + .S_AXI_GP1_AWID(6'B0), + .S_AXI_GP1_WID(6'B0), + .S_AXI_ACP_ARREADY(), + .S_AXI_ACP_AWREADY(), + .S_AXI_ACP_BVALID(), + .S_AXI_ACP_RLAST(), + .S_AXI_ACP_RVALID(), + .S_AXI_ACP_WREADY(), + .S_AXI_ACP_BRESP(), + .S_AXI_ACP_RRESP(), + .S_AXI_ACP_BID(), + .S_AXI_ACP_RID(), + .S_AXI_ACP_RDATA(), + .S_AXI_ACP_ACLK(1'B0), + .S_AXI_ACP_ARVALID(1'B0), + .S_AXI_ACP_AWVALID(1'B0), + .S_AXI_ACP_BREADY(1'B0), + .S_AXI_ACP_RREADY(1'B0), + .S_AXI_ACP_WLAST(1'B0), + .S_AXI_ACP_WVALID(1'B0), + .S_AXI_ACP_ARID(3'B0), + .S_AXI_ACP_ARPROT(3'B0), + .S_AXI_ACP_AWID(3'B0), + .S_AXI_ACP_AWPROT(3'B0), + .S_AXI_ACP_WID(3'B0), + .S_AXI_ACP_ARADDR(32'B0), + .S_AXI_ACP_AWADDR(32'B0), + .S_AXI_ACP_ARCACHE(4'B0), + .S_AXI_ACP_ARLEN(4'B0), + .S_AXI_ACP_ARQOS(4'B0), + .S_AXI_ACP_AWCACHE(4'B0), + .S_AXI_ACP_AWLEN(4'B0), + .S_AXI_ACP_AWQOS(4'B0), + .S_AXI_ACP_ARBURST(2'B0), + .S_AXI_ACP_ARLOCK(2'B0), + .S_AXI_ACP_ARSIZE(3'B0), + .S_AXI_ACP_AWBURST(2'B0), + .S_AXI_ACP_AWLOCK(2'B0), + .S_AXI_ACP_AWSIZE(3'B0), + .S_AXI_ACP_ARUSER(5'B0), + .S_AXI_ACP_AWUSER(5'B0), + .S_AXI_ACP_WDATA(64'B0), + .S_AXI_ACP_WSTRB(8'B0), + .S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY), + .S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY), + .S_AXI_HP0_BVALID(S_AXI_HP0_BVALID), + .S_AXI_HP0_RLAST(S_AXI_HP0_RLAST), + .S_AXI_HP0_RVALID(S_AXI_HP0_RVALID), + .S_AXI_HP0_WREADY(S_AXI_HP0_WREADY), + .S_AXI_HP0_BRESP(S_AXI_HP0_BRESP), + .S_AXI_HP0_RRESP(S_AXI_HP0_RRESP), + .S_AXI_HP0_BID(S_AXI_HP0_BID), + .S_AXI_HP0_RID(S_AXI_HP0_RID), + .S_AXI_HP0_RDATA(S_AXI_HP0_RDATA), + .S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT), + .S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT), + .S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT), + .S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT), + .S_AXI_HP0_ACLK(S_AXI_HP0_ACLK), + .S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID), + .S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID), + .S_AXI_HP0_BREADY(S_AXI_HP0_BREADY), + .S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN), + .S_AXI_HP0_RREADY(S_AXI_HP0_RREADY), + .S_AXI_HP0_WLAST(S_AXI_HP0_WLAST), + .S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN), + .S_AXI_HP0_WVALID(S_AXI_HP0_WVALID), + .S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST), + .S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK), + .S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE), + .S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST), + .S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK), + .S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE), + .S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT), + .S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT), + .S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR), + .S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR), + .S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE), + .S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN), + .S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS), + .S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE), + .S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN), + .S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS), + .S_AXI_HP0_ARID(S_AXI_HP0_ARID), + .S_AXI_HP0_AWID(S_AXI_HP0_AWID), + .S_AXI_HP0_WID(S_AXI_HP0_WID), + .S_AXI_HP0_WDATA(S_AXI_HP0_WDATA), + .S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB), + .S_AXI_HP1_ARREADY(), + .S_AXI_HP1_AWREADY(), + .S_AXI_HP1_BVALID(), + .S_AXI_HP1_RLAST(), + .S_AXI_HP1_RVALID(), + .S_AXI_HP1_WREADY(), + .S_AXI_HP1_BRESP(), + .S_AXI_HP1_RRESP(), + .S_AXI_HP1_BID(), + .S_AXI_HP1_RID(), + .S_AXI_HP1_RDATA(), + .S_AXI_HP1_RCOUNT(), + .S_AXI_HP1_WCOUNT(), + .S_AXI_HP1_RACOUNT(), + .S_AXI_HP1_WACOUNT(), + .S_AXI_HP1_ACLK(1'B0), + .S_AXI_HP1_ARVALID(1'B0), + .S_AXI_HP1_AWVALID(1'B0), + .S_AXI_HP1_BREADY(1'B0), + .S_AXI_HP1_RDISSUECAP1_EN(1'B0), + .S_AXI_HP1_RREADY(1'B0), + .S_AXI_HP1_WLAST(1'B0), + .S_AXI_HP1_WRISSUECAP1_EN(1'B0), + .S_AXI_HP1_WVALID(1'B0), + .S_AXI_HP1_ARBURST(2'B0), + .S_AXI_HP1_ARLOCK(2'B0), + .S_AXI_HP1_ARSIZE(3'B0), + .S_AXI_HP1_AWBURST(2'B0), + .S_AXI_HP1_AWLOCK(2'B0), + .S_AXI_HP1_AWSIZE(3'B0), + .S_AXI_HP1_ARPROT(3'B0), + .S_AXI_HP1_AWPROT(3'B0), + .S_AXI_HP1_ARADDR(32'B0), + .S_AXI_HP1_AWADDR(32'B0), + .S_AXI_HP1_ARCACHE(4'B0), + .S_AXI_HP1_ARLEN(4'B0), + .S_AXI_HP1_ARQOS(4'B0), + .S_AXI_HP1_AWCACHE(4'B0), + .S_AXI_HP1_AWLEN(4'B0), + .S_AXI_HP1_AWQOS(4'B0), + .S_AXI_HP1_ARID(6'B0), + .S_AXI_HP1_AWID(6'B0), + .S_AXI_HP1_WID(6'B0), + .S_AXI_HP1_WDATA(64'B0), + .S_AXI_HP1_WSTRB(8'B0), + .S_AXI_HP2_ARREADY(), + .S_AXI_HP2_AWREADY(), + .S_AXI_HP2_BVALID(), + .S_AXI_HP2_RLAST(), + .S_AXI_HP2_RVALID(), + .S_AXI_HP2_WREADY(), + .S_AXI_HP2_BRESP(), + .S_AXI_HP2_RRESP(), + .S_AXI_HP2_BID(), + .S_AXI_HP2_RID(), + .S_AXI_HP2_RDATA(), + .S_AXI_HP2_RCOUNT(), + .S_AXI_HP2_WCOUNT(), + .S_AXI_HP2_RACOUNT(), + .S_AXI_HP2_WACOUNT(), + .S_AXI_HP2_ACLK(1'B0), + .S_AXI_HP2_ARVALID(1'B0), + .S_AXI_HP2_AWVALID(1'B0), + .S_AXI_HP2_BREADY(1'B0), + .S_AXI_HP2_RDISSUECAP1_EN(1'B0), + .S_AXI_HP2_RREADY(1'B0), + .S_AXI_HP2_WLAST(1'B0), + .S_AXI_HP2_WRISSUECAP1_EN(1'B0), + .S_AXI_HP2_WVALID(1'B0), + .S_AXI_HP2_ARBURST(2'B0), + .S_AXI_HP2_ARLOCK(2'B0), + .S_AXI_HP2_ARSIZE(3'B0), + .S_AXI_HP2_AWBURST(2'B0), + .S_AXI_HP2_AWLOCK(2'B0), + .S_AXI_HP2_AWSIZE(3'B0), + .S_AXI_HP2_ARPROT(3'B0), + .S_AXI_HP2_AWPROT(3'B0), + .S_AXI_HP2_ARADDR(32'B0), + .S_AXI_HP2_AWADDR(32'B0), + .S_AXI_HP2_ARCACHE(4'B0), + .S_AXI_HP2_ARLEN(4'B0), + .S_AXI_HP2_ARQOS(4'B0), + .S_AXI_HP2_AWCACHE(4'B0), + .S_AXI_HP2_AWLEN(4'B0), + .S_AXI_HP2_AWQOS(4'B0), + .S_AXI_HP2_ARID(6'B0), + .S_AXI_HP2_AWID(6'B0), + .S_AXI_HP2_WID(6'B0), + .S_AXI_HP2_WDATA(64'B0), + .S_AXI_HP2_WSTRB(8'B0), + .S_AXI_HP3_ARREADY(), + .S_AXI_HP3_AWREADY(), + .S_AXI_HP3_BVALID(), + .S_AXI_HP3_RLAST(), + .S_AXI_HP3_RVALID(), + .S_AXI_HP3_WREADY(), + .S_AXI_HP3_BRESP(), + .S_AXI_HP3_RRESP(), + .S_AXI_HP3_BID(), + .S_AXI_HP3_RID(), + .S_AXI_HP3_RDATA(), + .S_AXI_HP3_RCOUNT(), + .S_AXI_HP3_WCOUNT(), + .S_AXI_HP3_RACOUNT(), + .S_AXI_HP3_WACOUNT(), + .S_AXI_HP3_ACLK(1'B0), + .S_AXI_HP3_ARVALID(1'B0), + .S_AXI_HP3_AWVALID(1'B0), + .S_AXI_HP3_BREADY(1'B0), + .S_AXI_HP3_RDISSUECAP1_EN(1'B0), + .S_AXI_HP3_RREADY(1'B0), + .S_AXI_HP3_WLAST(1'B0), + .S_AXI_HP3_WRISSUECAP1_EN(1'B0), + .S_AXI_HP3_WVALID(1'B0), + .S_AXI_HP3_ARBURST(2'B0), + .S_AXI_HP3_ARLOCK(2'B0), + .S_AXI_HP3_ARSIZE(3'B0), + .S_AXI_HP3_AWBURST(2'B0), + .S_AXI_HP3_AWLOCK(2'B0), + .S_AXI_HP3_AWSIZE(3'B0), + .S_AXI_HP3_ARPROT(3'B0), + .S_AXI_HP3_AWPROT(3'B0), + .S_AXI_HP3_ARADDR(32'B0), + .S_AXI_HP3_AWADDR(32'B0), + .S_AXI_HP3_ARCACHE(4'B0), + .S_AXI_HP3_ARLEN(4'B0), + .S_AXI_HP3_ARQOS(4'B0), + .S_AXI_HP3_AWCACHE(4'B0), + .S_AXI_HP3_AWLEN(4'B0), + .S_AXI_HP3_AWQOS(4'B0), + .S_AXI_HP3_ARID(6'B0), + .S_AXI_HP3_AWID(6'B0), + .S_AXI_HP3_WID(6'B0), + .S_AXI_HP3_WDATA(64'B0), + .S_AXI_HP3_WSTRB(8'B0), + .IRQ_P2F_DMAC_ABORT(), + .IRQ_P2F_DMAC0(), + .IRQ_P2F_DMAC1(), + .IRQ_P2F_DMAC2(), + .IRQ_P2F_DMAC3(), + .IRQ_P2F_DMAC4(), + .IRQ_P2F_DMAC5(), + .IRQ_P2F_DMAC6(), + .IRQ_P2F_DMAC7(), + .IRQ_P2F_SMC(), + .IRQ_P2F_QSPI(), + .IRQ_P2F_CTI(), + .IRQ_P2F_GPIO(), + .IRQ_P2F_USB0(), + .IRQ_P2F_ENET0(), + .IRQ_P2F_ENET_WAKE0(), + .IRQ_P2F_SDIO0(), + .IRQ_P2F_I2C0(), + .IRQ_P2F_SPI0(), + .IRQ_P2F_UART0(), + .IRQ_P2F_CAN0(), + .IRQ_P2F_USB1(), + .IRQ_P2F_ENET1(), + .IRQ_P2F_ENET_WAKE1(), + .IRQ_P2F_SDIO1(), + .IRQ_P2F_I2C1(), + .IRQ_P2F_SPI1(), + .IRQ_P2F_UART1(), + .IRQ_P2F_CAN1(), + .IRQ_F2P(IRQ_F2P), + .Core0_nFIQ(1'B0), + .Core0_nIRQ(1'B0), + .Core1_nFIQ(1'B0), + .Core1_nIRQ(1'B0), + .DMA0_DATYPE(), + .DMA0_DAVALID(), + .DMA0_DRREADY(), + .DMA1_DATYPE(), + .DMA1_DAVALID(), + .DMA1_DRREADY(), + .DMA2_DATYPE(), + .DMA2_DAVALID(), + .DMA2_DRREADY(), + .DMA3_DATYPE(), + .DMA3_DAVALID(), + .DMA3_DRREADY(), + .DMA0_ACLK(1'B0), + .DMA0_DAREADY(1'B0), + .DMA0_DRLAST(1'B0), + .DMA0_DRVALID(1'B0), + .DMA1_ACLK(1'B0), + .DMA1_DAREADY(1'B0), + .DMA1_DRLAST(1'B0), + .DMA1_DRVALID(1'B0), + .DMA2_ACLK(1'B0), + .DMA2_DAREADY(1'B0), + .DMA2_DRLAST(1'B0), + .DMA2_DRVALID(1'B0), + .DMA3_ACLK(1'B0), + .DMA3_DAREADY(1'B0), + .DMA3_DRLAST(1'B0), + .DMA3_DRVALID(1'B0), + .DMA0_DRTYPE(2'B0), + .DMA1_DRTYPE(2'B0), + .DMA2_DRTYPE(2'B0), + .DMA3_DRTYPE(2'B0), + .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_CLK3(FCLK_CLK3), + .FCLK_CLKTRIG0_N(1'B0), + .FCLK_CLKTRIG1_N(1'B0), + .FCLK_CLKTRIG2_N(1'B0), + .FCLK_CLKTRIG3_N(1'B0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET1_N(FCLK_RESET1_N), + .FCLK_RESET2_N(FCLK_RESET2_N), + .FCLK_RESET3_N(FCLK_RESET3_N), + .FTMD_TRACEIN_DATA(32'B0), + .FTMD_TRACEIN_VALID(1'B0), + .FTMD_TRACEIN_CLK(1'B0), + .FTMD_TRACEIN_ATID(4'B0), + .FTMT_F2P_TRIG_0(1'B0), + .FTMT_F2P_TRIGACK_0(), + .FTMT_F2P_TRIG_1(1'B0), + .FTMT_F2P_TRIGACK_1(), + .FTMT_F2P_TRIG_2(1'B0), + .FTMT_F2P_TRIGACK_2(), + .FTMT_F2P_TRIG_3(1'B0), + .FTMT_F2P_TRIGACK_3(), + .FTMT_F2P_DEBUG(32'B0), + .FTMT_P2F_TRIGACK_0(1'B0), + .FTMT_P2F_TRIG_0(), + .FTMT_P2F_TRIGACK_1(1'B0), + .FTMT_P2F_TRIG_1(), + .FTMT_P2F_TRIGACK_2(1'B0), + .FTMT_P2F_TRIG_2(), + .FTMT_P2F_TRIGACK_3(1'B0), + .FTMT_P2F_TRIG_3(), + .FTMT_P2F_DEBUG(), + .FPGA_IDLE_N(1'B0), + .EVENT_EVENTO(), + .EVENT_STANDBYWFE(), + .EVENT_STANDBYWFI(), + .EVENT_EVENTI(1'B0), + .DDR_ARB(4'B0), + .MIO(MIO), + .DDR_CAS_n(DDR_CAS_n), + .DDR_CKE(DDR_CKE), + .DDR_Clk_n(DDR_Clk_n), + .DDR_Clk(DDR_Clk), + .DDR_CS_n(DDR_CS_n), + .DDR_DRSTB(DDR_DRSTB), + .DDR_ODT(DDR_ODT), + .DDR_RAS_n(DDR_RAS_n), + .DDR_WEB(DDR_WEB), + .DDR_BankAddr(DDR_BankAddr), + .DDR_Addr(DDR_Addr), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_DM(DDR_DM), + .DDR_DQ(DDR_DQ), + .DDR_DQS_n(DDR_DQS_n), + .DDR_DQS(DDR_DQS), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.upgrade_log b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.upgrade_log new file mode 100644 index 0000000..3984711 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.upgrade_log @@ -0,0 +1,22 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +| Date : Fri Jul 10 13:44:12 2015 +| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7z020clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'z_turn_processing_system7_0_0' + +1. Summary +---------- + +SUCCESS in the update of z_turn_processing_system7_0_0 (xilinx.com:ip:processing_system7:5.5 (Rev. 1)) to current project options. + +2. Upgrade messages +------------------- + +WARNING: upgrade cannot add parameter PCW_TRACE_INTERNAL_WIDTH with default value 32 : a parameter called PCW_TRACE_INTERNAL_WIDTH already exists in processing_system7_v5_5 +WARNING: upgrade cannot add parameter PCW_USE_AXI_NONSECURE with default value 0 : a parameter called PCW_USE_AXI_NONSECURE already exists in processing_system7_v5_5 + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.veo b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.veo new file mode 100644 index 0000000..2620880 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.veo @@ -0,0 +1,200 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:processing_system7:5.5 +// IP Revision: 1 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +z_turn_processing_system7_0_0 your_instance_name ( + .ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX), // output wire ENET0_PTP_DELAY_REQ_RX + .ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX), // output wire ENET0_PTP_DELAY_REQ_TX + .ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX), // output wire ENET0_PTP_PDELAY_REQ_RX + .ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX), // output wire ENET0_PTP_PDELAY_REQ_TX + .ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX), // output wire ENET0_PTP_PDELAY_RESP_RX + .ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX), // output wire ENET0_PTP_PDELAY_RESP_TX + .ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX), // output wire ENET0_PTP_SYNC_FRAME_RX + .ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX), // output wire ENET0_PTP_SYNC_FRAME_TX + .ENET0_SOF_RX(ENET0_SOF_RX), // output wire ENET0_SOF_RX + .ENET0_SOF_TX(ENET0_SOF_TX), // output wire ENET0_SOF_TX + .GPIO_I(GPIO_I), // input wire [63 : 0] GPIO_I + .GPIO_O(GPIO_O), // output wire [63 : 0] GPIO_O + .GPIO_T(GPIO_T), // output wire [63 : 0] GPIO_T + .I2C0_SDA_I(I2C0_SDA_I), // input wire I2C0_SDA_I + .I2C0_SDA_O(I2C0_SDA_O), // output wire I2C0_SDA_O + .I2C0_SDA_T(I2C0_SDA_T), // output wire I2C0_SDA_T + .I2C0_SCL_I(I2C0_SCL_I), // input wire I2C0_SCL_I + .I2C0_SCL_O(I2C0_SCL_O), // output wire I2C0_SCL_O + .I2C0_SCL_T(I2C0_SCL_T), // output wire I2C0_SCL_T + .USB0_PORT_INDCTL(USB0_PORT_INDCTL), // output wire [1 : 0] USB0_PORT_INDCTL + .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT), // output wire USB0_VBUS_PWRSELECT + .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT), // input wire USB0_VBUS_PWRFAULT + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), // output wire M_AXI_GP0_ARVALID + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), // output wire M_AXI_GP0_AWVALID + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), // output wire M_AXI_GP0_BREADY + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), // output wire M_AXI_GP0_RREADY + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), // output wire M_AXI_GP0_WLAST + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), // output wire M_AXI_GP0_WVALID + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), // output wire [11 : 0] M_AXI_GP0_ARID + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), // output wire [11 : 0] M_AXI_GP0_AWID + .M_AXI_GP0_WID(M_AXI_GP0_WID), // output wire [11 : 0] M_AXI_GP0_WID + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), // output wire [1 : 0] M_AXI_GP0_ARBURST + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), // output wire [1 : 0] M_AXI_GP0_ARLOCK + .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), // output wire [2 : 0] M_AXI_GP0_ARSIZE + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), // output wire [1 : 0] M_AXI_GP0_AWBURST + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), // output wire [1 : 0] M_AXI_GP0_AWLOCK + .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), // output wire [2 : 0] M_AXI_GP0_AWSIZE + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), // output wire [2 : 0] M_AXI_GP0_ARPROT + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), // output wire [2 : 0] M_AXI_GP0_AWPROT + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), // output wire [31 : 0] M_AXI_GP0_ARADDR + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), // output wire [31 : 0] M_AXI_GP0_AWADDR + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), // output wire [31 : 0] M_AXI_GP0_WDATA + .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), // output wire [3 : 0] M_AXI_GP0_ARCACHE + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), // output wire [3 : 0] M_AXI_GP0_ARLEN + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), // output wire [3 : 0] M_AXI_GP0_ARQOS + .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), // output wire [3 : 0] M_AXI_GP0_AWCACHE + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), // output wire [3 : 0] M_AXI_GP0_AWLEN + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), // output wire [3 : 0] M_AXI_GP0_AWQOS + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), // output wire [3 : 0] M_AXI_GP0_WSTRB + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), // input wire M_AXI_GP0_ACLK + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), // input wire M_AXI_GP0_ARREADY + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), // input wire M_AXI_GP0_AWREADY + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), // input wire M_AXI_GP0_BVALID + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), // input wire M_AXI_GP0_RLAST + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), // input wire M_AXI_GP0_RVALID + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), // input wire M_AXI_GP0_WREADY + .M_AXI_GP0_BID(M_AXI_GP0_BID), // input wire [11 : 0] M_AXI_GP0_BID + .M_AXI_GP0_RID(M_AXI_GP0_RID), // input wire [11 : 0] M_AXI_GP0_RID + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), // input wire [1 : 0] M_AXI_GP0_BRESP + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), // input wire [1 : 0] M_AXI_GP0_RRESP + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), // input wire [31 : 0] M_AXI_GP0_RDATA + .S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY), // output wire S_AXI_HP0_ARREADY + .S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY), // output wire S_AXI_HP0_AWREADY + .S_AXI_HP0_BVALID(S_AXI_HP0_BVALID), // output wire S_AXI_HP0_BVALID + .S_AXI_HP0_RLAST(S_AXI_HP0_RLAST), // output wire S_AXI_HP0_RLAST + .S_AXI_HP0_RVALID(S_AXI_HP0_RVALID), // output wire S_AXI_HP0_RVALID + .S_AXI_HP0_WREADY(S_AXI_HP0_WREADY), // output wire S_AXI_HP0_WREADY + .S_AXI_HP0_BRESP(S_AXI_HP0_BRESP), // output wire [1 : 0] S_AXI_HP0_BRESP + .S_AXI_HP0_RRESP(S_AXI_HP0_RRESP), // output wire [1 : 0] S_AXI_HP0_RRESP + .S_AXI_HP0_BID(S_AXI_HP0_BID), // output wire [5 : 0] S_AXI_HP0_BID + .S_AXI_HP0_RID(S_AXI_HP0_RID), // output wire [5 : 0] S_AXI_HP0_RID + .S_AXI_HP0_RDATA(S_AXI_HP0_RDATA), // output wire [63 : 0] S_AXI_HP0_RDATA + .S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT), // output wire [7 : 0] S_AXI_HP0_RCOUNT + .S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT), // output wire [7 : 0] S_AXI_HP0_WCOUNT + .S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT), // output wire [2 : 0] S_AXI_HP0_RACOUNT + .S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT), // output wire [5 : 0] S_AXI_HP0_WACOUNT + .S_AXI_HP0_ACLK(S_AXI_HP0_ACLK), // input wire S_AXI_HP0_ACLK + .S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID), // input wire S_AXI_HP0_ARVALID + .S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID), // input wire S_AXI_HP0_AWVALID + .S_AXI_HP0_BREADY(S_AXI_HP0_BREADY), // input wire S_AXI_HP0_BREADY + .S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN), // input wire S_AXI_HP0_RDISSUECAP1_EN + .S_AXI_HP0_RREADY(S_AXI_HP0_RREADY), // input wire S_AXI_HP0_RREADY + .S_AXI_HP0_WLAST(S_AXI_HP0_WLAST), // input wire S_AXI_HP0_WLAST + .S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN), // input wire S_AXI_HP0_WRISSUECAP1_EN + .S_AXI_HP0_WVALID(S_AXI_HP0_WVALID), // input wire S_AXI_HP0_WVALID + .S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST), // input wire [1 : 0] S_AXI_HP0_ARBURST + .S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK), // input wire [1 : 0] S_AXI_HP0_ARLOCK + .S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE), // input wire [2 : 0] S_AXI_HP0_ARSIZE + .S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST), // input wire [1 : 0] S_AXI_HP0_AWBURST + .S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK), // input wire [1 : 0] S_AXI_HP0_AWLOCK + .S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE), // input wire [2 : 0] S_AXI_HP0_AWSIZE + .S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT), // input wire [2 : 0] S_AXI_HP0_ARPROT + .S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT), // input wire [2 : 0] S_AXI_HP0_AWPROT + .S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR), // input wire [31 : 0] S_AXI_HP0_ARADDR + .S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR), // input wire [31 : 0] S_AXI_HP0_AWADDR + .S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE), // input wire [3 : 0] S_AXI_HP0_ARCACHE + .S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN), // input wire [3 : 0] S_AXI_HP0_ARLEN + .S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS), // input wire [3 : 0] S_AXI_HP0_ARQOS + .S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE), // input wire [3 : 0] S_AXI_HP0_AWCACHE + .S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN), // input wire [3 : 0] S_AXI_HP0_AWLEN + .S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS), // input wire [3 : 0] S_AXI_HP0_AWQOS + .S_AXI_HP0_ARID(S_AXI_HP0_ARID), // input wire [5 : 0] S_AXI_HP0_ARID + .S_AXI_HP0_AWID(S_AXI_HP0_AWID), // input wire [5 : 0] S_AXI_HP0_AWID + .S_AXI_HP0_WID(S_AXI_HP0_WID), // input wire [5 : 0] S_AXI_HP0_WID + .S_AXI_HP0_WDATA(S_AXI_HP0_WDATA), // input wire [63 : 0] S_AXI_HP0_WDATA + .S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB), // input wire [7 : 0] S_AXI_HP0_WSTRB + .IRQ_F2P(IRQ_F2P), // input wire [15 : 0] IRQ_F2P + .FCLK_CLK0(FCLK_CLK0), // output wire FCLK_CLK0 + .FCLK_CLK1(FCLK_CLK1), // output wire FCLK_CLK1 + .FCLK_CLK2(FCLK_CLK2), // output wire FCLK_CLK2 + .FCLK_CLK3(FCLK_CLK3), // output wire FCLK_CLK3 + .FCLK_RESET0_N(FCLK_RESET0_N), // output wire FCLK_RESET0_N + .FCLK_RESET1_N(FCLK_RESET1_N), // output wire FCLK_RESET1_N + .FCLK_RESET2_N(FCLK_RESET2_N), // output wire FCLK_RESET2_N + .FCLK_RESET3_N(FCLK_RESET3_N), // output wire FCLK_RESET3_N + .MIO(MIO), // inout wire [53 : 0] MIO + .DDR_CAS_n(DDR_CAS_n), // inout wire DDR_CAS_n + .DDR_CKE(DDR_CKE), // inout wire DDR_CKE + .DDR_Clk_n(DDR_Clk_n), // inout wire DDR_Clk_n + .DDR_Clk(DDR_Clk), // inout wire DDR_Clk + .DDR_CS_n(DDR_CS_n), // inout wire DDR_CS_n + .DDR_DRSTB(DDR_DRSTB), // inout wire DDR_DRSTB + .DDR_ODT(DDR_ODT), // inout wire DDR_ODT + .DDR_RAS_n(DDR_RAS_n), // inout wire DDR_RAS_n + .DDR_WEB(DDR_WEB), // inout wire DDR_WEB + .DDR_BankAddr(DDR_BankAddr), // inout wire [2 : 0] DDR_BankAddr + .DDR_Addr(DDR_Addr), // inout wire [14 : 0] DDR_Addr + .DDR_VRN(DDR_VRN), // inout wire DDR_VRN + .DDR_VRP(DDR_VRP), // inout wire DDR_VRP + .DDR_DM(DDR_DM), // inout wire [3 : 0] DDR_DM + .DDR_DQ(DDR_DQ), // inout wire [31 : 0] DDR_DQ + .DDR_DQS_n(DDR_DQS_n), // inout wire [3 : 0] DDR_DQS_n + .DDR_DQS(DDR_DQS), // inout wire [3 : 0] DDR_DQS + .PS_SRSTB(PS_SRSTB), // inout wire PS_SRSTB + .PS_CLK(PS_CLK), // inout wire PS_CLK + .PS_PORB(PS_PORB) // inout wire PS_PORB +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file z_turn_processing_system7_0_0.v when simulating +// the core, z_turn_processing_system7_0_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.xci b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.xci new file mode 100644 index 0000000..b7103f5 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.xci @@ -0,0 +1,1134 @@ + + + xilinx.com + xci + unknown + 1.0 + + + z_turn_processing_system7_0_0 + + + 0x00100000 + 0x3FFFFFFF + 0xE0000000 + 0xE0000FFF + 0xE0001000 + 0xE0001FFF + 0xE0004000 + 0xE0004FFF + 0xE0005000 + 0xE0005FFF + 0xE0006000 + 0xE0006FFF + 0xE0007000 + 0xE0007FFF + 0xE0008000 + 0xE0008FFF + 0xE0009000 + 0xE0009FFF + 0xE000A000 + 0xE000AFFF + 0xE000B000 + 0xE000BFFF + 0xE000C000 + 0xE000CFFF + 0xE0100000 + 0xE0100FFF + 0xE0101000 + 0xE0101FFF + 0xE0102000 + 0xE0102fff + 0xE0103000 + 0xE0103fff + 0xE0104000 + 0xE0104fff + 0xE0105000 + 0xE0105fff + true + true + true + true + 533.333333 + 3 + 15 + 10 + 7 + 6 + 7 + 7 + 49.5 + 36.0 + 45.0 + 0 + 0.0 + 0.0 + 0.0 + 0.0 + 0.0 + 0.0 + 0.0 + 0.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 101.239 + 79.5025 + 60.536 + 71.7715 + 104.5365 + 70.676 + 59.1615 + 81.319 + 54.563 + 54.563 + 54.563 + 54.563 + 160 + 160 + 160 + 160 + 160 + 160 + 160 + 160 + 160 + 160 + 160 + 160 + -0.047 + -0.025 + -0.006 + -0.017 + 0.080 + 0.063 + 0.057 + 0.068 + 667 + 33.333333 + 666.666666 + 10.159 + 200 + 100 + 60 + 60 + 100 + 100 + 166.666666 + 100 + -1 + -1 + 111.111115 + 133.333333 + 50 + 133.333333 + 133.333333 + 133.333333 + 133.333333 + 133.333333 + 133.333333 + 200 + 200 + 166.667 + 50 + 100 + 200 + 666.666687 + 533.333374 + 10.158731 + 200.000000 + 10.000000 + 125.000000 + 10.000000 + 60 + 60 + 100.000000 + 100.000000 + 10.000000 + 100.000000 + 23.8095 + 23.8095 + 50 + 111.111115 + 50 + 200.000000 + 200.000000 + 166.666672 + 50.000000 + 100.000000 + 200.000000 + 111.111115 + 111.111115 + 111.111115 + 111.111115 + 111.111115 + 111.111115 + 166666672 + 50000000 + 100000000 + 200000000 + 0 + 2 + 2 + 1 + 5 + 10 + 10 + 1 + 10 + 1 + 6 + 20 + 10 + 5 + 1 + 1 + 1 + 1 + 8 + 1 + 1 + 1 + 1 + 35 + 3 + 5 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 40 + 30 + 32 + 1333.333 + 1000.000 + 1066.667 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 50 + 10 + 10 + 10 + 10 + 100 + 10 + 10 + 10 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 128 + 0 + 12 + 0 + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64 + 115200 + 115200 + 0 + 12 + 0 + 0 + 12 + 12 + 0 + 0 + 12 + 6 + 6 + 3 + 0 + 0 + 31 + 31 + 6 + 64 + 6 + 64 + 6 + 64 + 6 + 64 + 16 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 32 + 4 + 4 + 54 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + DIRECT + 0 + 0 + 0 + 0 + 3 + None + None + LVCMOS 3.3V + LVCMOS 1.8V + 1 + 0 + DDR 3 + Disabled + 32 Bit + 8 + Normal (0-85) + MT41K256M16 RE-15E + 16 Bits + 4096 MBits + DDR3_1066F + 1 + 1 + 1 + 0 + 0 + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + 0 + 0 + 0 + 0 + HPR(0)/LPR(32) + 2 + 15 + 2 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 1 + MIO 1 .. 6 + 1 + MIO 1 .. 6 + 0 + <Select> + 0 + <Select> + 1 + MIO 8 + 0xFCFFFFFF + 1 + MIO 16 .. 27 + 1 + MIO 52 .. 53 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 1 + MIO 40 .. 45 + 1 + MIO 46 + 1 + MIO 47 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 1 + MIO 48 .. 49 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 1 + MIO 14 .. 15 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 2 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 1 + MIO 28 .. 39 + 1 + Share reset pin + 1 + MIO 51 + 0 + <Select> + 0 + <Select> + 1 + EMIO + 1 + EMIO + 0 + <Select> + 1 + MIO 12 .. 13 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + 1 + MIO + 1 + 64 + 6:2:1 + 1000 Mbps + 1000 Mbps + ARM PLL + DDR PLL + IO PLL + IO PLL + IO PLL + IO PLL + IO PLL + IO PLL + IO PLL + IO PLL + IO PLL + IO PLL + IO PLL + IO PLL + External + External + External + CPU_1X + CPU_1X + CPU_1X + CPU_1X + CPU_1X + CPU_1X + CPU_1X + DDR PLL + IO PLL + Active Low + Active Low + Active Low + enabled + LVCMOS 3.3V + inout + slow + enabled + LVCMOS 3.3V + out + slow + disabled + LVCMOS 3.3V + inout + slow + disabled + LVCMOS 3.3V + inout + slow + disabled + LVCMOS 3.3V + inout + slow + disabled + LVCMOS 3.3V + inout + slow + disabled + LVCMOS 3.3V + out + slow + disabled + LVCMOS 3.3V + out + slow + disabled + LVCMOS 3.3V + out + slow + enabled + LVCMOS 3.3V + inout + slow + enabled + LVCMOS 3.3V + in + slow + enabled + LVCMOS 3.3V + out + slow + enabled + LVCMOS 3.3V + inout + slow + enabled + LVCMOS 3.3V + inout + slow + enabled + LVCMOS 3.3V + in + slow + enabled + LVCMOS 3.3V + out + slow + enabled + LVCMOS 1.8V + out + slow + enabled + LVCMOS 1.8V + out + slow + enabled + LVCMOS 1.8V + out + slow + enabled + LVCMOS 1.8V + out + slow + enabled + LVCMOS 1.8V + out + slow + enabled + LVCMOS 1.8V + out + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + out + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + inout + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + out + slow + enabled + LVCMOS 1.8V + in + slow + enabled + LVCMOS 1.8V + inout + slow + disabled + LVCMOS 1.8V + out + slow + enabled + LVCMOS 1.8V + out + slow + enabled + LVCMOS 1.8V + inout + slow + None + NA + GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#I2C 1#I2C 1#CAN 0#CAN 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#UART 1#UART 1#GPIO#USB Reset#Enet 0#Enet 0 + gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#scl#sda#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#wp#tx#rx#gpio[50]#reset#mdc#mdio + PRODUCTION + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 2 + 2 + 0 + 1 + 1 + 1 + 1 + 2 + 2 + 0 + 1 + 1 + 1 + 1 + 2 + 2 + 0 + 1 + 1 + 1 + 1 + 2 + 2 + 0 + 1 + 1 + 1 + 1 + 1 + 2 + 2 + NA + NA + NA + NA + NA + NA + NA + clg400 + z_turn_processing_system7_0_0 + 0 + 8 + 8 + z_turn_processing_system7_0_0_FCLK_CLK1 + 0.000 + 16 + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 12 + 50000000 + AXI3 + 32 + AXI3 + READ_WRITE + 64 + 32 + 0 + 0 + 0 + 0 + 0 + 6 + 1 + 16 + 100000000 + z_turn_processing_system7_0_0_FCLK_CLK2 + 166666672 + + + z_turn_processing_system7_0_0_FCLK_CLK0 + 0.000 + 50000000 + + + z_turn_processing_system7_0_0_FCLK_CLK1 + 0.000 + 100000000 + + + z_turn_processing_system7_0_0_FCLK_CLK2 + 0.000 + 200000000 + + + z_turn_processing_system7_0_0_FCLK_CLK3 + 0.000 + 16 + LEVEL_HIGH + 50000000 + z_turn_processing_system7_0_0_FCLK_CLK1 + 100000000 + z_turn_processing_system7_0_0_FCLK_CLK2 + zynq + xc7z020 + clg400 + -1 + C + + VERILOG + MIXED + TRUE + TRUE + + TRUE + 2015.2 + 1 + OUT_OF_CONTEXT + + . + ../../../../ipshared + IP_Integrator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.xdc b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.xdc new file mode 100644 index 0000000..0e95a86 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.xdc @@ -0,0 +1,712 @@ +############################################################################ +## +## Xilinx, Inc. 2006 www.xilinx.com +############################################################################ +## File name : ps7_constraints.xdc +## +## Details : Constraints file +## FPGA family: zynq +## FPGA: xc7z020clg400-1 +## Device Size: xc7z020 +## Package: clg400 +## Speedgrade: -1 +## +## +############################################################################ +############################################################################ +############################################################################ +# Clock constraints # +############################################################################ +create_clock -name clk_fpga_2 -period "10" [get_pins "PS7_i/FCLKCLK[2]"] +set_input_jitter clk_fpga_2 0.3 +#The clocks are asynchronous, user should constrain them appropriately.# +create_clock -name clk_fpga_0 -period "6" [get_pins "PS7_i/FCLKCLK[0]"] +set_input_jitter clk_fpga_0 0.18 +#The clocks are asynchronous, user should constrain them appropriately.# +create_clock -name clk_fpga_1 -period "20" [get_pins "PS7_i/FCLKCLK[1]"] +set_input_jitter clk_fpga_1 0.6 +#The clocks are asynchronous, user should constrain them appropriately.# +create_clock -name clk_fpga_3 -period "5" [get_pins "PS7_i/FCLKCLK[3]"] +set_input_jitter clk_fpga_3 0.15 +#The clocks are asynchronous, user should constrain them appropriately.# + + +############################################################################ +# I/O STANDARDS and Location Constraints # +############################################################################ + +# Enet 0 / mdio / MIO[53] +set_property iostandard "LVCMOS18" [get_ports "MIO[53]"] +set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"] +set_property slew "slow" [get_ports "MIO[53]"] +set_property drive "8" [get_ports "MIO[53]"] +set_property pullup "TRUE" [get_ports "MIO[53]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"] +# Enet 0 / mdc / MIO[52] +set_property iostandard "LVCMOS18" [get_ports "MIO[52]"] +set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"] +set_property slew "slow" [get_ports "MIO[52]"] +set_property drive "8" [get_ports "MIO[52]"] +set_property pullup "TRUE" [get_ports "MIO[52]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"] +# USB Reset / reset / MIO[51] +set_property iostandard "LVCMOS18" [get_ports "MIO[51]"] +set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"] +set_property slew "slow" [get_ports "MIO[51]"] +set_property drive "8" [get_ports "MIO[51]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[51]"] +# GPIO / gpio[50] / MIO[50] +set_property iostandard "LVCMOS18" [get_ports "MIO[50]"] +set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"] +set_property slew "slow" [get_ports "MIO[50]"] +set_property drive "8" [get_ports "MIO[50]"] +set_property pullup "TRUE" [get_ports "MIO[50]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"] +# UART 1 / rx / MIO[49] +set_property iostandard "LVCMOS18" [get_ports "MIO[49]"] +set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"] +set_property slew "slow" [get_ports "MIO[49]"] +set_property drive "8" [get_ports "MIO[49]"] +set_property pullup "TRUE" [get_ports "MIO[49]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"] +# UART 1 / tx / MIO[48] +set_property iostandard "LVCMOS18" [get_ports "MIO[48]"] +set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"] +set_property slew "slow" [get_ports "MIO[48]"] +set_property drive "8" [get_ports "MIO[48]"] +set_property pullup "TRUE" [get_ports "MIO[48]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"] +# SD 0 / wp / MIO[47] +set_property iostandard "LVCMOS18" [get_ports "MIO[47]"] +set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"] +set_property slew "slow" [get_ports "MIO[47]"] +set_property drive "8" [get_ports "MIO[47]"] +set_property pullup "TRUE" [get_ports "MIO[47]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"] +# SD 0 / cd / MIO[46] +set_property iostandard "LVCMOS18" [get_ports "MIO[46]"] +set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"] +set_property slew "slow" [get_ports "MIO[46]"] +set_property drive "8" [get_ports "MIO[46]"] +set_property pullup "TRUE" [get_ports "MIO[46]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[46]"] +# SD 0 / data[3] / MIO[45] +set_property iostandard "LVCMOS18" [get_ports "MIO[45]"] +set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"] +set_property slew "slow" [get_ports "MIO[45]"] +set_property drive "8" [get_ports "MIO[45]"] +set_property pullup "TRUE" [get_ports "MIO[45]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"] +# SD 0 / data[2] / MIO[44] +set_property iostandard "LVCMOS18" [get_ports "MIO[44]"] +set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"] +set_property slew "slow" [get_ports "MIO[44]"] +set_property drive "8" [get_ports "MIO[44]"] +set_property pullup "TRUE" [get_ports "MIO[44]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"] +# SD 0 / data[1] / MIO[43] +set_property iostandard "LVCMOS18" [get_ports "MIO[43]"] +set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"] +set_property slew "slow" [get_ports "MIO[43]"] +set_property drive "8" [get_ports "MIO[43]"] +set_property pullup "TRUE" [get_ports "MIO[43]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"] +# SD 0 / data[0] / MIO[42] +set_property iostandard "LVCMOS18" [get_ports "MIO[42]"] +set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"] +set_property slew "slow" [get_ports "MIO[42]"] +set_property drive "8" [get_ports "MIO[42]"] +set_property pullup "TRUE" [get_ports "MIO[42]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"] +# SD 0 / cmd / MIO[41] +set_property iostandard "LVCMOS18" [get_ports "MIO[41]"] +set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"] +set_property slew "slow" [get_ports "MIO[41]"] +set_property drive "8" [get_ports "MIO[41]"] +set_property pullup "TRUE" [get_ports "MIO[41]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"] +# SD 0 / clk / MIO[40] +set_property iostandard "LVCMOS18" [get_ports "MIO[40]"] +set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"] +set_property slew "slow" [get_ports "MIO[40]"] +set_property drive "8" [get_ports "MIO[40]"] +set_property pullup "TRUE" [get_ports "MIO[40]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"] +# USB 0 / data[7] / MIO[39] +set_property iostandard "LVCMOS18" [get_ports "MIO[39]"] +set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"] +set_property slew "slow" [get_ports "MIO[39]"] +set_property drive "8" [get_ports "MIO[39]"] +set_property pullup "TRUE" [get_ports "MIO[39]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"] +# USB 0 / data[6] / MIO[38] +set_property iostandard "LVCMOS18" [get_ports "MIO[38]"] +set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"] +set_property slew "slow" [get_ports "MIO[38]"] +set_property drive "8" [get_ports "MIO[38]"] +set_property pullup "TRUE" [get_ports "MIO[38]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"] +# USB 0 / data[5] / MIO[37] +set_property iostandard "LVCMOS18" [get_ports "MIO[37]"] +set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"] +set_property slew "slow" [get_ports "MIO[37]"] +set_property drive "8" [get_ports "MIO[37]"] +set_property pullup "TRUE" [get_ports "MIO[37]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"] +# USB 0 / clk / MIO[36] +set_property iostandard "LVCMOS18" [get_ports "MIO[36]"] +set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"] +set_property slew "slow" [get_ports "MIO[36]"] +set_property drive "8" [get_ports "MIO[36]"] +set_property pullup "TRUE" [get_ports "MIO[36]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"] +# USB 0 / data[3] / MIO[35] +set_property iostandard "LVCMOS18" [get_ports "MIO[35]"] +set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"] +set_property slew "slow" [get_ports "MIO[35]"] +set_property drive "8" [get_ports "MIO[35]"] +set_property pullup "TRUE" [get_ports "MIO[35]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"] +# USB 0 / data[2] / MIO[34] +set_property iostandard "LVCMOS18" [get_ports "MIO[34]"] +set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"] +set_property slew "slow" [get_ports "MIO[34]"] +set_property drive "8" [get_ports "MIO[34]"] +set_property pullup "TRUE" [get_ports "MIO[34]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"] +# USB 0 / data[1] / MIO[33] +set_property iostandard "LVCMOS18" [get_ports "MIO[33]"] +set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"] +set_property slew "slow" [get_ports "MIO[33]"] +set_property drive "8" [get_ports "MIO[33]"] +set_property pullup "TRUE" [get_ports "MIO[33]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"] +# USB 0 / data[0] / MIO[32] +set_property iostandard "LVCMOS18" [get_ports "MIO[32]"] +set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"] +set_property slew "slow" [get_ports "MIO[32]"] +set_property drive "8" [get_ports "MIO[32]"] +set_property pullup "TRUE" [get_ports "MIO[32]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"] +# USB 0 / nxt / MIO[31] +set_property iostandard "LVCMOS18" [get_ports "MIO[31]"] +set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"] +set_property slew "slow" [get_ports "MIO[31]"] +set_property drive "8" [get_ports "MIO[31]"] +set_property pullup "TRUE" [get_ports "MIO[31]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"] +# USB 0 / stp / MIO[30] +set_property iostandard "LVCMOS18" [get_ports "MIO[30]"] +set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"] +set_property slew "slow" [get_ports "MIO[30]"] +set_property drive "8" [get_ports "MIO[30]"] +set_property pullup "TRUE" [get_ports "MIO[30]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"] +# USB 0 / dir / MIO[29] +set_property iostandard "LVCMOS18" [get_ports "MIO[29]"] +set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"] +set_property slew "slow" [get_ports "MIO[29]"] +set_property drive "8" [get_ports "MIO[29]"] +set_property pullup "TRUE" [get_ports "MIO[29]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"] +# USB 0 / data[4] / MIO[28] +set_property iostandard "LVCMOS18" [get_ports "MIO[28]"] +set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"] +set_property slew "slow" [get_ports "MIO[28]"] +set_property drive "8" [get_ports "MIO[28]"] +set_property pullup "TRUE" [get_ports "MIO[28]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"] +# Enet 0 / rx_ctl / MIO[27] +set_property iostandard "LVCMOS18" [get_ports "MIO[27]"] +set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"] +set_property slew "slow" [get_ports "MIO[27]"] +set_property drive "8" [get_ports "MIO[27]"] +set_property pullup "TRUE" [get_ports "MIO[27]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"] +# Enet 0 / rxd[3] / MIO[26] +set_property iostandard "LVCMOS18" [get_ports "MIO[26]"] +set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"] +set_property slew "slow" [get_ports "MIO[26]"] +set_property drive "8" [get_ports "MIO[26]"] +set_property pullup "TRUE" [get_ports "MIO[26]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"] +# Enet 0 / rxd[2] / MIO[25] +set_property iostandard "LVCMOS18" [get_ports "MIO[25]"] +set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"] +set_property slew "slow" [get_ports "MIO[25]"] +set_property drive "8" [get_ports "MIO[25]"] +set_property pullup "TRUE" [get_ports "MIO[25]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"] +# Enet 0 / rxd[1] / MIO[24] +set_property iostandard "LVCMOS18" [get_ports "MIO[24]"] +set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"] +set_property slew "slow" [get_ports "MIO[24]"] +set_property drive "8" [get_ports "MIO[24]"] +set_property pullup "TRUE" [get_ports "MIO[24]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"] +# Enet 0 / rxd[0] / MIO[23] +set_property iostandard "LVCMOS18" [get_ports "MIO[23]"] +set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"] +set_property slew "slow" [get_ports "MIO[23]"] +set_property drive "8" [get_ports "MIO[23]"] +set_property pullup "TRUE" [get_ports "MIO[23]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"] +# Enet 0 / rx_clk / MIO[22] +set_property iostandard "LVCMOS18" [get_ports "MIO[22]"] +set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"] +set_property slew "slow" [get_ports "MIO[22]"] +set_property drive "8" [get_ports "MIO[22]"] +set_property pullup "TRUE" [get_ports "MIO[22]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"] +# Enet 0 / tx_ctl / MIO[21] +set_property iostandard "LVCMOS18" [get_ports "MIO[21]"] +set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"] +set_property slew "slow" [get_ports "MIO[21]"] +set_property drive "8" [get_ports "MIO[21]"] +set_property pullup "TRUE" [get_ports "MIO[21]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"] +# Enet 0 / txd[3] / MIO[20] +set_property iostandard "LVCMOS18" [get_ports "MIO[20]"] +set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"] +set_property slew "slow" [get_ports "MIO[20]"] +set_property drive "8" [get_ports "MIO[20]"] +set_property pullup "TRUE" [get_ports "MIO[20]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"] +# Enet 0 / txd[2] / MIO[19] +set_property iostandard "LVCMOS18" [get_ports "MIO[19]"] +set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"] +set_property slew "slow" [get_ports "MIO[19]"] +set_property drive "8" [get_ports "MIO[19]"] +set_property pullup "TRUE" [get_ports "MIO[19]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"] +# Enet 0 / txd[1] / MIO[18] +set_property iostandard "LVCMOS18" [get_ports "MIO[18]"] +set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"] +set_property slew "slow" [get_ports "MIO[18]"] +set_property drive "8" [get_ports "MIO[18]"] +set_property pullup "TRUE" [get_ports "MIO[18]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"] +# Enet 0 / txd[0] / MIO[17] +set_property iostandard "LVCMOS18" [get_ports "MIO[17]"] +set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"] +set_property slew "slow" [get_ports "MIO[17]"] +set_property drive "8" [get_ports "MIO[17]"] +set_property pullup "TRUE" [get_ports "MIO[17]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"] +# Enet 0 / tx_clk / MIO[16] +set_property iostandard "LVCMOS18" [get_ports "MIO[16]"] +set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"] +set_property slew "slow" [get_ports "MIO[16]"] +set_property drive "8" [get_ports "MIO[16]"] +set_property pullup "TRUE" [get_ports "MIO[16]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"] +# CAN 0 / tx / MIO[15] +set_property iostandard "LVCMOS33" [get_ports "MIO[15]"] +set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"] +set_property slew "slow" [get_ports "MIO[15]"] +set_property drive "8" [get_ports "MIO[15]"] +set_property pullup "TRUE" [get_ports "MIO[15]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[15]"] +# CAN 0 / rx / MIO[14] +set_property iostandard "LVCMOS33" [get_ports "MIO[14]"] +set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"] +set_property slew "slow" [get_ports "MIO[14]"] +set_property drive "8" [get_ports "MIO[14]"] +set_property pullup "TRUE" [get_ports "MIO[14]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[14]"] +# I2C 1 / sda / MIO[13] +set_property iostandard "LVCMOS33" [get_ports "MIO[13]"] +set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"] +set_property slew "slow" [get_ports "MIO[13]"] +set_property drive "8" [get_ports "MIO[13]"] +set_property pullup "TRUE" [get_ports "MIO[13]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"] +# I2C 1 / scl / MIO[12] +set_property iostandard "LVCMOS33" [get_ports "MIO[12]"] +set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"] +set_property slew "slow" [get_ports "MIO[12]"] +set_property drive "8" [get_ports "MIO[12]"] +set_property pullup "TRUE" [get_ports "MIO[12]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"] +# GPIO / gpio[11] / MIO[11] +set_property iostandard "LVCMOS33" [get_ports "MIO[11]"] +set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"] +set_property slew "slow" [get_ports "MIO[11]"] +set_property drive "8" [get_ports "MIO[11]"] +set_property pullup "TRUE" [get_ports "MIO[11]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"] +# GPIO / gpio[10] / MIO[10] +set_property iostandard "LVCMOS33" [get_ports "MIO[10]"] +set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"] +set_property slew "slow" [get_ports "MIO[10]"] +set_property drive "8" [get_ports "MIO[10]"] +set_property pullup "TRUE" [get_ports "MIO[10]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"] +# GPIO / gpio[9] / MIO[9] +set_property iostandard "LVCMOS33" [get_ports "MIO[9]"] +set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"] +set_property slew "slow" [get_ports "MIO[9]"] +set_property drive "8" [get_ports "MIO[9]"] +set_property pullup "TRUE" [get_ports "MIO[9]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"] +# Quad SPI Flash / qspi_fbclk / MIO[8] +set_property iostandard "LVCMOS33" [get_ports "MIO[8]"] +set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"] +set_property slew "slow" [get_ports "MIO[8]"] +set_property drive "8" [get_ports "MIO[8]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"] +# GPIO / gpio[7] / MIO[7] +set_property iostandard "LVCMOS33" [get_ports "MIO[7]"] +set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"] +set_property slew "slow" [get_ports "MIO[7]"] +set_property drive "8" [get_ports "MIO[7]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"] +# Quad SPI Flash / qspi0_sclk / MIO[6] +set_property iostandard "LVCMOS33" [get_ports "MIO[6]"] +set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"] +set_property slew "slow" [get_ports "MIO[6]"] +set_property drive "8" [get_ports "MIO[6]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"] +# Quad SPI Flash / qspi0_io[3] / MIO[5] +set_property iostandard "LVCMOS33" [get_ports "MIO[5]"] +set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"] +set_property slew "slow" [get_ports "MIO[5]"] +set_property drive "8" [get_ports "MIO[5]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"] +# Quad SPI Flash / qspi0_io[2] / MIO[4] +set_property iostandard "LVCMOS33" [get_ports "MIO[4]"] +set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"] +set_property slew "slow" [get_ports "MIO[4]"] +set_property drive "8" [get_ports "MIO[4]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"] +# Quad SPI Flash / qspi0_io[1] / MIO[3] +set_property iostandard "LVCMOS33" [get_ports "MIO[3]"] +set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"] +set_property slew "slow" [get_ports "MIO[3]"] +set_property drive "8" [get_ports "MIO[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"] +# Quad SPI Flash / qspi0_io[0] / MIO[2] +set_property iostandard "LVCMOS33" [get_ports "MIO[2]"] +set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"] +set_property slew "slow" [get_ports "MIO[2]"] +set_property drive "8" [get_ports "MIO[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"] +# Quad SPI Flash / qspi0_ss_b / MIO[1] +set_property iostandard "LVCMOS33" [get_ports "MIO[1]"] +set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"] +set_property slew "slow" [get_ports "MIO[1]"] +set_property drive "8" [get_ports "MIO[1]"] +set_property pullup "TRUE" [get_ports "MIO[1]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"] +# GPIO / gpio[0] / MIO[0] +set_property iostandard "LVCMOS33" [get_ports "MIO[0]"] +set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"] +set_property slew "slow" [get_ports "MIO[0]"] +set_property drive "8" [get_ports "MIO[0]"] +set_property pullup "TRUE" [get_ports "MIO[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"] +set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"] +set_property slew "FAST" [get_ports "DDR_VRP"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"] +set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"] +set_property slew "FAST" [get_ports "DDR_VRN"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"] +set_property iostandard "SSTL15" [get_ports "DDR_WEB"] +set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"] +set_property slew "SLOW" [get_ports "DDR_WEB"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"] +set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"] +set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"] +set_property slew "SLOW" [get_ports "DDR_RAS_n"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"] +set_property iostandard "SSTL15" [get_ports "DDR_ODT"] +set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"] +set_property slew "SLOW" [get_ports "DDR_ODT"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"] +set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"] +set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"] +set_property slew "FAST" [get_ports "DDR_DRSTB"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"] +set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"] +set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"] +set_property slew "FAST" [get_ports "DDR_DQS[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"] +set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"] +set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"] +set_property slew "FAST" [get_ports "DDR_DQS[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"] +set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"] +set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"] +set_property slew "FAST" [get_ports "DDR_DQS[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"] +set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"] +set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"] +set_property slew "FAST" [get_ports "DDR_DQS[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"] +set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"] +set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"] +set_property slew "FAST" [get_ports "DDR_DQS_n[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"] +set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"] +set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"] +set_property slew "FAST" [get_ports "DDR_DQS_n[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"] +set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"] +set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"] +set_property slew "FAST" [get_ports "DDR_DQS_n[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"] +set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"] +set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"] +set_property slew "FAST" [get_ports "DDR_DQS_n[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"] +set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"] +set_property slew "FAST" [get_ports "DDR_DQ[9]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"] +set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"] +set_property slew "FAST" [get_ports "DDR_DQ[8]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"] +set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"] +set_property slew "FAST" [get_ports "DDR_DQ[7]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"] +set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"] +set_property slew "FAST" [get_ports "DDR_DQ[6]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"] +set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"] +set_property slew "FAST" [get_ports "DDR_DQ[5]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"] +set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"] +set_property slew "FAST" [get_ports "DDR_DQ[4]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"] +set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"] +set_property slew "FAST" [get_ports "DDR_DQ[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"] +set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"] +set_property slew "FAST" [get_ports "DDR_DQ[31]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"] +set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"] +set_property slew "FAST" [get_ports "DDR_DQ[30]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"] +set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"] +set_property slew "FAST" [get_ports "DDR_DQ[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"] +set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"] +set_property slew "FAST" [get_ports "DDR_DQ[29]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"] +set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"] +set_property slew "FAST" [get_ports "DDR_DQ[28]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"] +set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"] +set_property slew "FAST" [get_ports "DDR_DQ[27]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"] +set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"] +set_property slew "FAST" [get_ports "DDR_DQ[26]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"] +set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"] +set_property slew "FAST" [get_ports "DDR_DQ[25]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"] +set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"] +set_property slew "FAST" [get_ports "DDR_DQ[24]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"] +set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"] +set_property slew "FAST" [get_ports "DDR_DQ[23]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"] +set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"] +set_property slew "FAST" [get_ports "DDR_DQ[22]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"] +set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"] +set_property slew "FAST" [get_ports "DDR_DQ[21]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"] +set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"] +set_property slew "FAST" [get_ports "DDR_DQ[20]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"] +set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"] +set_property slew "FAST" [get_ports "DDR_DQ[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"] +set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"] +set_property slew "FAST" [get_ports "DDR_DQ[19]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"] +set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"] +set_property slew "FAST" [get_ports "DDR_DQ[18]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"] +set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"] +set_property slew "FAST" [get_ports "DDR_DQ[17]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"] +set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"] +set_property slew "FAST" [get_ports "DDR_DQ[16]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"] +set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"] +set_property slew "FAST" [get_ports "DDR_DQ[15]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"] +set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"] +set_property slew "FAST" [get_ports "DDR_DQ[14]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"] +set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"] +set_property slew "FAST" [get_ports "DDR_DQ[13]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"] +set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"] +set_property slew "FAST" [get_ports "DDR_DQ[12]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"] +set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"] +set_property slew "FAST" [get_ports "DDR_DQ[11]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"] +set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"] +set_property slew "FAST" [get_ports "DDR_DQ[10]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"] +set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"] +set_property slew "FAST" [get_ports "DDR_DQ[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"] +set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"] +set_property slew "FAST" [get_ports "DDR_DM[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"] +set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"] +set_property slew "FAST" [get_ports "DDR_DM[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"] +set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"] +set_property slew "FAST" [get_ports "DDR_DM[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"] +set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"] +set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"] +set_property slew "FAST" [get_ports "DDR_DM[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"] +set_property iostandard "SSTL15" [get_ports "DDR_CS_n"] +set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"] +set_property slew "SLOW" [get_ports "DDR_CS_n"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"] +set_property iostandard "SSTL15" [get_ports "DDR_CKE"] +set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"] +set_property slew "SLOW" [get_ports "DDR_CKE"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"] +set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"] +set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"] +set_property slew "FAST" [get_ports "DDR_Clk"] +set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"] +set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"] +set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"] +set_property slew "FAST" [get_ports "DDR_Clk_n"] +set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"] +set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"] +set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"] +set_property slew "SLOW" [get_ports "DDR_CAS_n"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"] +set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"] +set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"] +set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"] +set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"] +set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"] +set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"] +set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"] +set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"] +set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"] +set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"] +set_property slew "SLOW" [get_ports "DDR_Addr[9]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"] +set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"] +set_property slew "SLOW" [get_ports "DDR_Addr[8]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"] +set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"] +set_property slew "SLOW" [get_ports "DDR_Addr[7]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"] +set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"] +set_property slew "SLOW" [get_ports "DDR_Addr[6]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"] +set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"] +set_property slew "SLOW" [get_ports "DDR_Addr[5]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"] +set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"] +set_property slew "SLOW" [get_ports "DDR_Addr[4]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"] +set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"] +set_property slew "SLOW" [get_ports "DDR_Addr[3]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"] +set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"] +set_property slew "SLOW" [get_ports "DDR_Addr[2]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"] +set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"] +set_property slew "SLOW" [get_ports "DDR_Addr[1]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"] +set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"] +set_property slew "SLOW" [get_ports "DDR_Addr[14]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"] +set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"] +set_property slew "SLOW" [get_ports "DDR_Addr[13]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"] +set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"] +set_property slew "SLOW" [get_ports "DDR_Addr[12]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"] +set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"] +set_property slew "SLOW" [get_ports "DDR_Addr[11]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"] +set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"] +set_property slew "SLOW" [get_ports "DDR_Addr[10]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"] +set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"] +set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"] +set_property slew "SLOW" [get_ports "DDR_Addr[0]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"] +set_property iostandard "LVCMOS33" [get_ports "PS_PORB"] +set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"] +set_property slew "slow" [get_ports "PS_PORB"] +set_property drive "8" [get_ports "PS_PORB"] +set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"] +set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"] +set_property slew "slow" [get_ports "PS_SRSTB"] +set_property drive "8" [get_ports "PS_SRSTB"] +set_property iostandard "LVCMOS33" [get_ports "PS_CLK"] +set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"] +set_property slew "slow" [get_ports "PS_CLK"] +set_property drive "8" [get_ports "PS_CLK"] + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.xml new file mode 100644 index 0000000..35942e1 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.xml @@ -0,0 +1,48500 @@ + + + xilinx.com + customized_ip + z_turn_processing_system7_0_0 + 1.0 + + + GMII_ETHERNET_0 + + + + false + + + + TX_EN + + + ENET0_GMII_TX_EN + + + + + TX_ER + + + ENET0_GMII_TX_ER + + + + + TXD + + + ENET0_GMII_TXD + + + + + COL + + + ENET0_GMII_COL + + + + + CRS + + + ENET0_GMII_CRS + + + + + RX_CLK + + + ENET0_GMII_RX_CLK + + + + + RX_DV + + + ENET0_GMII_RX_DV + + + + + RX_ER + + + ENET0_GMII_RX_ER + + + + + TX_CLK + + + ENET0_GMII_TX_CLK + + + + + RXD + + + ENET0_GMII_RXD + + + + + + + optional + false + + + + + + MDIO_ETHERNET_0 + + + + false + + + + MDC + + + ENET0_MDIO_MDC + + + + + MDIO_O + + + ENET0_MDIO_O + + + + + MDIO_T + + + ENET0_MDIO_T + + + + + MDIO_I + + + ENET0_MDIO_I + + + + + + + optional + false + + + + + + PTP_ETHERNET_0 + + + + false + + + + DELAY_REQ_RX + + + ENET0_PTP_DELAY_REQ_RX + + + + + DELAY_REQ_TX + + + ENET0_PTP_DELAY_REQ_TX + + + + + PDELAY_REQ_RX + + + ENET0_PTP_PDELAY_REQ_RX + + + + + PDELAY_REQ_TX + + + ENET0_PTP_PDELAY_REQ_TX + + + + + PDELAY_RESP_RX + + + ENET0_PTP_PDELAY_RESP_RX + + + + + PDELAY_RESP_TX + + + ENET0_PTP_PDELAY_RESP_TX + + + + + SYNC_FRAME_RX + + + ENET0_PTP_SYNC_FRAME_RX + + + + + SYNC_FRAME_TX + + + ENET0_PTP_SYNC_FRAME_TX + + + + + SOF_RX + + + ENET0_SOF_RX + + + + + SOF_TX + + + ENET0_SOF_TX + + + + + + + optional + true + + + + + + ENET0_EXT_INTIN + + + + false + + + + INTERRUPT + + + ENET0_EXT_INTIN + + + + + + + optional + false + + + + + + GMII_ETHERNET_1 + + + + false + + + + TX_EN + + + ENET1_GMII_TX_EN + + + + + TX_ER + + + ENET1_GMII_TX_ER + + + + + TXD + + + ENET1_GMII_TXD + + + + + COL + + + ENET1_GMII_COL + + + + + CRS + + + ENET1_GMII_CRS + + + + + RX_CLK + + + ENET1_GMII_RX_CLK + + + + + RX_DV + + + ENET1_GMII_RX_DV + + + + + RX_ER + + + ENET1_GMII_RX_ER + + + + + TX_CLK + + + ENET1_GMII_TX_CLK + + + + + RXD + + + ENET1_GMII_RXD + + + + + + + optional + false + + + + + + MDIO_ETHERNET_1 + + + + false + + + + MDC + + + ENET1_MDIO_MDC + + + + + MDIO_O + + + ENET1_MDIO_O + + + + + MDIO_T + + + ENET1_MDIO_T + + + + + MDIO_I + + + ENET1_MDIO_I + + + + + + + optional + false + + + + + + PTP_ETHERNET_1 + + + + false + + + + DELAY_REQ_RX + + + ENET1_PTP_DELAY_REQ_RX + + + + + DELAY_REQ_TX + + + ENET1_PTP_DELAY_REQ_TX + + + + + PDELAY_REQ_RX + + + ENET1_PTP_PDELAY_REQ_RX + + + + + PDELAY_REQ_TX + + + ENET1_PTP_PDELAY_REQ_TX + + + + + PDELAY_RESP_RX + + + ENET1_PTP_PDELAY_RESP_RX + + + + + PDELAY_RESP_TX + + + ENET1_PTP_PDELAY_RESP_TX + + + + + SYNC_FRAME_RX + + + ENET1_PTP_SYNC_FRAME_RX + + + + + SYNC_FRAME_TX + + + ENET1_PTP_SYNC_FRAME_TX + + + + + SOF_RX + + + ENET1_SOF_RX + + + + + SOF_TX + + + ENET1_SOF_TX + + + + + + + optional + false + + + + + + ENET1_EXT_INTIN + + + + false + + + + INTERRUPT + + + ENET1_EXT_INTIN + + + + + + + optional + false + + + + + + GPIO_0 + + + + false + + + + TRI_I + + + GPIO_I + + + + + TRI_O + + + GPIO_O + + + + + TRI_T + + + GPIO_T + + + + + + + optional + true + + + + + + DDR + + + + false + + + + CAS_N + + + DDR_CAS_n + + + + + CKE + + + DDR_CKE + + + + + CK_N + + + DDR_Clk_n + + + + + CK_P + + + DDR_Clk + + + + + CS_N + + + DDR_CS_n + + + + + RESET_N + + + DDR_DRSTB + + + + + ODT + + + DDR_ODT + + + + + RAS_N + + + DDR_RAS_n + + + + + WE_N + + + DDR_WEB + + + + + BA + + + DDR_BankAddr + + + + + ADDR + + + DDR_Addr + + + + + DM + + + DDR_DM + + + + + DQ + + + DDR_DQ + + + + + DQS_N + + + DDR_DQS_n + + + + + DQS_P + + + DDR_DQS + + + + + + + optional + true + + + + + + FIXED_IO + + + + false + + + + MIO + + + MIO + + + + + DDR_VRN + + + DDR_VRN + + + + + DDR_VRP + + + DDR_VRP + + + + + PS_SRSTB + + + PS_SRSTB + + + + + PS_CLK + + + PS_CLK + + + + + PS_PORB + + + PS_PORB + + + + + + UART_0 + + + + false + + + + DTRn + + + UART0_DTRN + + + + + RTSn + + + UART0_RTSN + + + + + TxD + + + UART0_TX + + + + + CTSn + + + UART0_CTSN + + + + + DCDn + + + UART0_DCDN + + + + + DSRn + + + UART0_DSRN + + + + + RI + + + UART0_RIN + + + + + RxD + + + UART0_RX + + + + + + + optional + false + + + + + + UART_1 + + + + false + + + + DTRn + + + UART1_DTRN + + + + + RTSn + + + UART1_RTSN + + + + + TxD + + + UART1_TX + + + + + CTSn + + + UART1_CTSN + + + + + DCDn + + + UART1_DCDN + + + + + DSRn + + + UART1_DSRN + + + + + RI + + + UART1_RIN + + + + + RxD + + + UART1_RX + + + + + + + optional + false + + + + + + IIC_0 + + + + false + + + + SDA_I + + + I2C0_SDA_I + + + + + SDA_O + + + I2C0_SDA_O + + + + + SDA_T + + + I2C0_SDA_T + + + + + SCL_I + + + I2C0_SCL_I + + + + + SCL_O + + + I2C0_SCL_O + + + + + SCL_T + + + I2C0_SCL_T + + + + + + + optional + true + + + + + + IIC_1 + + + + false + + + + SDA_I + + + I2C1_SDA_I + + + + + SDA_O + + + I2C1_SDA_O + + + + + SDA_T + + + I2C1_SDA_T + + + + + SCL_I + + + I2C1_SCL_I + + + + + SCL_O + + + I2C1_SCL_O + + + + + SCL_T + + + I2C1_SCL_T + + + + + + + optional + false + + + + + + SPI_0 + + + + false + + + + SCK_I + + + SPI0_SCLK_I + + + + + SCK_O + + + SPI0_SCLK_O + + + + + SCK_T + + + SPI0_SCLK_T + + + + + IO0_I + + + SPI0_MOSI_I + + + + + IO0_O + + + SPI0_MOSI_O + + + + + IO0_T + + + SPI0_MOSI_T + + + + + IO1_I + + + SPI0_MISO_I + + + + + IO1_O + + + SPI0_MISO_O + + + + + IO1_T + + + SPI0_MISO_T + + + + + SS_I + + + SPI0_SS_I + + + + + SS_O + + + SPI0_SS_O + + + + + SS1_O + + + SPI0_SS1_O + + + + + SS2_O + + + SPI0_SS2_O + + + + + SS_T + + + SPI0_SS_T + + + + + + + optional + false + + + + + + SPI_1 + + + + false + + + + SCK_I + + + SPI1_SCLK_I + + + + + SCK_O + + + SPI1_SCLK_O + + + + + SCK_T + + + SPI1_SCLK_T + + + + + IO0_I + + + SPI1_MOSI_I + + + + + IO0_O + + + SPI1_MOSI_O + + + + + IO0_T + + + SPI1_MOSI_T + + + + + IO1_I + + + SPI1_MISO_I + + + + + IO1_O + + + SPI1_MISO_O + + + + + IO1_T + + + SPI1_MISO_T + + + + + SS_I + + + SPI1_SS_I + + + + + SS_O + + + SPI1_SS_O + + + + + SS1_O + + + SPI1_SS1_O + + + + + SS2_O + + + SPI1_SS2_O + + + + + SS_T + + + SPI1_SS_T + + + + + + + optional + false + + + + + + CAN_0 + + + + false + + + + TX + + + CAN0_PHY_TX + + + + + RX + + + CAN0_PHY_RX + + + + + + + optional + false + + + + + + CAN_1 + + + + false + + + + TX + + + CAN1_PHY_TX + + + + + RX + + + CAN1_PHY_RX + + + + + + + optional + false + + + + + + PJTAG + + + + false + + + + TCK + + + PJTAG_TCK + + + + + TMS + + + PJTAG_TMS + + + + + TDI + + + PJTAG_TDI + + + + + TDO + + + PJTAG_TDO + + + + + + + optional + false + + + + + + SDIO_0 + + + + false + + + + CLK + + + SDIO0_CLK + + + + + CLK_FB + + + SDIO0_CLK_FB + + + + + CMD_O + + + SDIO0_CMD_O + + + + + CMD_I + + + SDIO0_CMD_I + + + + + CMD_T + + + SDIO0_CMD_T + + + + + DATA_I + + + SDIO0_DATA_I + + + + + DATA_O + + + SDIO0_DATA_O + + + + + DATA_T + + + SDIO0_DATA_T + + + + + LED + + + SDIO0_LED + + + + + CDN + + + SDIO0_CDN + + + + + WP + + + SDIO0_WP + + + + + BUSPOW + + + SDIO0_BUSPOW + + + + + BUSVOLT + + + SDIO0_BUSVOLT + + + + + + + optional + false + + + + + + SDIO_1 + + + + false + + + + CLK + + + SDIO1_CLK + + + + + CLK_FB + + + SDIO1_CLK_FB + + + + + CMD_O + + + SDIO1_CMD_O + + + + + CMD_I + + + SDIO1_CMD_I + + + + + CMD_T + + + SDIO1_CMD_T + + + + + DATA_I + + + SDIO1_DATA_I + + + + + DATA_O + + + SDIO1_DATA_O + + + + + DATA_T + + + SDIO1_DATA_T + + + + + LED + + + SDIO1_LED + + + + + CDN + + + SDIO1_CDN + + + + + WP + + + SDIO1_WP + + + + + BUSPOW + + + SDIO1_BUSPOW + + + + + BUSVOLT + + + SDIO1_BUSVOLT + + + + + + + optional + false + + + + + + TRACE_0 + + + + false + + + + CLK_O + + + TRACE_CLK_OUT + + + + + CLK_I + + + TRACE_CLK + + + + + CTL + + + TRACE_CTL + + + + + DATA + + + TRACE_DATA + + + + + + + optional + false + + + + + + USBIND_0 + + + + false + + + + PORT_INDCTL + + + USB0_PORT_INDCTL + + + + + VBUS_PWRSELECT + + + USB0_VBUS_PWRSELECT + + + + + VBUS_PWRFAULT + + + USB0_VBUS_PWRFAULT + + + + + + + optional + true + + + + + + USBIND_1 + + + + false + + + + PORT_INDCTL + + + USB1_PORT_INDCTL + + + + + VBUS_PWRSELECT + + + USB1_VBUS_PWRSELECT + + + + + VBUS_PWRFAULT + + + USB1_VBUS_PWRFAULT + + + + + + + optional + false + + + + + + S_AXI_HP0_FIFO_CTRL + + + + false + + + + RCOUNT + + + S_AXI_HP0_RCOUNT + + + + + WCOUNT + + + S_AXI_HP0_WCOUNT + + + + + RACOUNT + + + S_AXI_HP0_RACOUNT + + + + + WACOUNT + + + S_AXI_HP0_WACOUNT + + + + + RDISSUECAPEN + + + S_AXI_HP0_RDISSUECAP1_EN + + + + + WRISSUECAPEN + + + S_AXI_HP0_WRISSUECAP1_EN + + + + + + + optional + true + + + + + + S_AXI_HP1_FIFO_CTRL + + + + false + + + + RCOUNT + + + S_AXI_HP1_RCOUNT + + + + + WCOUNT + + + S_AXI_HP1_WCOUNT + + + + + RACOUNT + + + S_AXI_HP1_RACOUNT + + + + + WACOUNT + + + S_AXI_HP1_WACOUNT + + + + + RDISSUECAPEN + + + S_AXI_HP1_RDISSUECAP1_EN + + + + + WRISSUECAPEN + + + S_AXI_HP1_WRISSUECAP1_EN + + + + + + + optional + false + + + + + + S_AXI_HP2_FIFO_CTRL + + + + false + + + + RCOUNT + + + S_AXI_HP2_RCOUNT + + + + + WCOUNT + + + S_AXI_HP2_WCOUNT + + + + + RACOUNT + + + S_AXI_HP2_RACOUNT + + + + + WACOUNT + + + S_AXI_HP2_WACOUNT + + + + + RDISSUECAPEN + + + S_AXI_HP2_RDISSUECAP1_EN + + + + + WRISSUECAPEN + + + S_AXI_HP2_WRISSUECAP1_EN + + + + + + + optional + false + + + + + + S_AXI_HP3_FIFO_CTRL + + + + false + + + + RCOUNT + + + S_AXI_HP3_RCOUNT + + + + + WCOUNT + + + S_AXI_HP3_WCOUNT + + + + + RACOUNT + + + S_AXI_HP3_RACOUNT + + + + + WACOUNT + + + S_AXI_HP3_WACOUNT + + + + + RDISSUECAPEN + + + S_AXI_HP3_RDISSUECAP1_EN + + + + + WRISSUECAPEN + + + S_AXI_HP3_WRISSUECAP1_EN + + + + + + + optional + false + + + + + + DMA0_REQ + + + + false + + + + TREADY + + + DMA0_DRREADY + + + + + TLAST + + + DMA0_DRLAST + + + + + TVALID + + + DMA0_DRVALID + + + + + TUSER + + + DMA0_DRTYPE + + + + + + + optional + false + + + + + + DMA0_ACK + + + + false + + + + TUSER + + + DMA0_DATYPE + + + + + TVALID + + + DMA0_DAVALID + + + + + TREADY + + + DMA0_DAREADY + + + + + + + optional + false + + + + + + DMA1_REQ + + + + false + + + + TREADY + + + DMA1_DRREADY + + + + + TLAST + + + DMA1_DRLAST + + + + + TVALID + + + DMA1_DRVALID + + + + + TUSER + + + DMA1_DRTYPE + + + + + + + optional + false + + + + + + DMA1_ACK + + + + false + + + + TUSER + + + DMA1_DATYPE + + + + + TVALID + + + DMA1_DAVALID + + + + + TREADY + + + DMA1_DAREADY + + + + + + + optional + false + + + + + + DMA2_REQ + + + + false + + + + TREADY + + + DMA2_DRREADY + + + + + TLAST + + + DMA2_DRLAST + + + + + TVALID + + + DMA2_DRVALID + + + + + TUSER + + + DMA2_DRTYPE + + + + + + + optional + false + + + + + + DMA2_ACK + + + + false + + + + TUSER + + + DMA2_DATYPE + + + + + TVALID + + + DMA2_DAVALID + + + + + TREADY + + + DMA2_DAREADY + + + + + + + optional + false + + + + + + DMA3_REQ + + + + false + + + + TREADY + + + DMA3_DRREADY + + + + + TLAST + + + DMA3_DRLAST + + + + + TVALID + + + DMA3_DRVALID + + + + + TUSER + + + DMA3_DRTYPE + + + + + + + optional + false + + + + + + DMA3_ACK + + + + false + + + + TUSER + + + DMA3_DATYPE + + + + + TVALID + + + DMA3_DAVALID + + + + + TREADY + + + DMA3_DAREADY + + + + + + + optional + false + + + + + + FTM_TRACE_DATA + + + + false + + + + TDATA + + + FTMD_TRACEIN_DATA + + + + + TVALID + + + FTMD_TRACEIN_VALID + + + + + TID + + + FTMD_TRACEIN_ATID + + + + + + + optional + false + + + + + + PROC_EVENT + + + + false + + + + EVENTO + + + EVENT_EVENTO + + + + + STANDBYWFE + + + EVENT_STANDBYWFE + + + + + STANDBYWFI + + + EVENT_STANDBYWFI + + + + + EVENTI + + + EVENT_EVENTI + + + + + + + optional + false + + + + + + M_AXI_GP0 + + + + + 0x40000000 + + + false + + + + ARVALID + + + M_AXI_GP0_ARVALID + + + + + AWVALID + + + M_AXI_GP0_AWVALID + + + + + BREADY + + + M_AXI_GP0_BREADY + + + + + RREADY + + + M_AXI_GP0_RREADY + + + + + WLAST + + + M_AXI_GP0_WLAST + + + + + WVALID + + + M_AXI_GP0_WVALID + + + + + ARID + + + M_AXI_GP0_ARID + + + + + AWID + + + M_AXI_GP0_AWID + + + + + WID + + + M_AXI_GP0_WID + + + + + ARBURST + + + M_AXI_GP0_ARBURST + + + + + ARLOCK + + + M_AXI_GP0_ARLOCK + + + + + ARSIZE + + + M_AXI_GP0_ARSIZE + + + + + AWBURST + + + M_AXI_GP0_AWBURST + + + + + AWLOCK + + + M_AXI_GP0_AWLOCK + + + + + AWSIZE + + + M_AXI_GP0_AWSIZE + + + + + ARPROT + + + M_AXI_GP0_ARPROT + + + + + AWPROT + + + M_AXI_GP0_AWPROT + + + + + ARADDR + + + M_AXI_GP0_ARADDR + + + + + AWADDR + + + M_AXI_GP0_AWADDR + + + + + WDATA + + + M_AXI_GP0_WDATA + + + + + ARCACHE + + + M_AXI_GP0_ARCACHE + + + + + ARLEN + + + M_AXI_GP0_ARLEN + + + + + ARQOS + + + M_AXI_GP0_ARQOS + + + + + AWCACHE + + + M_AXI_GP0_AWCACHE + + + + + AWLEN + + + M_AXI_GP0_AWLEN + + + + + AWQOS + + + M_AXI_GP0_AWQOS + + + + + WSTRB + + + M_AXI_GP0_WSTRB + + + + + ARREADY + + + M_AXI_GP0_ARREADY + + + + + AWREADY + + + M_AXI_GP0_AWREADY + + + + + BVALID + + + M_AXI_GP0_BVALID + + + + + RLAST + + + M_AXI_GP0_RLAST + + + + + RVALID + + + M_AXI_GP0_RVALID + + + + + WREADY + + + M_AXI_GP0_WREADY + + + + + BID + + + M_AXI_GP0_BID + + + + + RID + + + M_AXI_GP0_RID + + + + + BRESP + + + M_AXI_GP0_BRESP + + + + + RRESP + + + M_AXI_GP0_RRESP + + + + + RDATA + + + M_AXI_GP0_RDATA + + + + + + SUPPORTS_NARROW_BURST + 0 + + + + optional + true + + + + + + NUM_WRITE_OUTSTANDING + NUM WRITE OUTSTANDING + 8 + + + NUM_READ_OUTSTANDING + NUM READ OUTSTANDING + 8 + + + CLK_DOMAIN + z_turn_processing_system7_0_0_FCLK_CLK1 + + + PHASE + 0.000 + + + MAX_BURST_LENGTH + 16 + + + READ_WRITE_MODE + READ_WRITE + + + BUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + AWUSER_WIDTH + 0 + + + ADDR_WIDTH + 32 + + + ID_WIDTH + 12 + + + FREQ_HZ + 50000000 + + + PROTOCOL + AXI3 + + + DATA_WIDTH + 32 + + + + + + optional + true + + + + + + M_AXI_GP1 + + + + + 0x80000000 + + + false + + + + ARVALID + + + M_AXI_GP1_ARVALID + + + + + AWVALID + + + M_AXI_GP1_AWVALID + + + + + BREADY + + + M_AXI_GP1_BREADY + + + + + RREADY + + + M_AXI_GP1_RREADY + + + + + WLAST + + + M_AXI_GP1_WLAST + + + + + WVALID + + + M_AXI_GP1_WVALID + + + + + ARID + + + M_AXI_GP1_ARID + + + + + AWID + + + M_AXI_GP1_AWID + + + + + WID + + + M_AXI_GP1_WID + + + + + ARBURST + + + M_AXI_GP1_ARBURST + + + + + ARLOCK + + + M_AXI_GP1_ARLOCK + + + + + ARSIZE + + + M_AXI_GP1_ARSIZE + + + + + AWBURST + + + M_AXI_GP1_AWBURST + + + + + AWLOCK + + + M_AXI_GP1_AWLOCK + + + + + AWSIZE + + + M_AXI_GP1_AWSIZE + + + + + ARPROT + + + M_AXI_GP1_ARPROT + + + + + AWPROT + + + M_AXI_GP1_AWPROT + + + + + ARADDR + + + M_AXI_GP1_ARADDR + + + + + AWADDR + + + M_AXI_GP1_AWADDR + + + + + WDATA + + + M_AXI_GP1_WDATA + + + + + ARCACHE + + + M_AXI_GP1_ARCACHE + + + + + ARLEN + + + M_AXI_GP1_ARLEN + + + + + ARQOS + + + M_AXI_GP1_ARQOS + + + + + AWCACHE + + + M_AXI_GP1_AWCACHE + + + + + AWLEN + + + M_AXI_GP1_AWLEN + + + + + AWQOS + + + M_AXI_GP1_AWQOS + + + + + WSTRB + + + M_AXI_GP1_WSTRB + + + + + ARREADY + + + M_AXI_GP1_ARREADY + + + + + AWREADY + + + M_AXI_GP1_AWREADY + + + + + BVALID + + + M_AXI_GP1_BVALID + + + + + RLAST + + + M_AXI_GP1_RLAST + + + + + RVALID + + + M_AXI_GP1_RVALID + + + + + WREADY + + + M_AXI_GP1_WREADY + + + + + BID + + + M_AXI_GP1_BID + + + + + RID + + + M_AXI_GP1_RID + + + + + BRESP + + + M_AXI_GP1_BRESP + + + + + RRESP + + + M_AXI_GP1_RRESP + + + + + RDATA + + + M_AXI_GP1_RDATA + + + + + + NUM_WRITE_OUTSTANDING + NUM WRITE OUTSTANDING + 8 + + + NUM_READ_OUTSTANDING + NUM READ OUTSTANDING + 8 + + + SUPPORTS_NARROW_BURST + 0 + + + + optional + false + + + + + + + + + optional + false + + + + + + S_AXI_ACP + + + + + + false + + + + ARREADY + + + S_AXI_ACP_ARREADY + + + + + AWREADY + + + S_AXI_ACP_AWREADY + + + + + BVALID + + + S_AXI_ACP_BVALID + + + + + RLAST + + + S_AXI_ACP_RLAST + + + + + RVALID + + + S_AXI_ACP_RVALID + + + + + WREADY + + + S_AXI_ACP_WREADY + + + + + BRESP + + + S_AXI_ACP_BRESP + + + + + RRESP + + + S_AXI_ACP_RRESP + + + + + BID + + + S_AXI_ACP_BID + + + + + RID + + + S_AXI_ACP_RID + + + + + RDATA + + + S_AXI_ACP_RDATA + + + + + ARVALID + + + S_AXI_ACP_ARVALID + + + + + AWVALID + + + S_AXI_ACP_AWVALID + + + + + BREADY + + + S_AXI_ACP_BREADY + + + + + RREADY + + + S_AXI_ACP_RREADY + + + + + WLAST + + + S_AXI_ACP_WLAST + + + + + WVALID + + + S_AXI_ACP_WVALID + + + + + ARID + + + S_AXI_ACP_ARID + + + + + ARPROT + + + S_AXI_ACP_ARPROT + + + + + AWID + + + S_AXI_ACP_AWID + + + + + AWPROT + + + S_AXI_ACP_AWPROT + + + + + WID + + + S_AXI_ACP_WID + + + + + ARADDR + + + S_AXI_ACP_ARADDR + + + + + AWADDR + + + S_AXI_ACP_AWADDR + + + + + ARCACHE + + + S_AXI_ACP_ARCACHE + + + + + ARLEN + + + S_AXI_ACP_ARLEN + + + + + ARQOS + + + S_AXI_ACP_ARQOS + + + + + AWCACHE + + + S_AXI_ACP_AWCACHE + + + + + AWLEN + + + S_AXI_ACP_AWLEN + + + + + AWQOS + + + S_AXI_ACP_AWQOS + + + + + ARBURST + + + S_AXI_ACP_ARBURST + + + + + ARLOCK + + + S_AXI_ACP_ARLOCK + + + + + ARSIZE + + + S_AXI_ACP_ARSIZE + + + + + AWBURST + + + S_AXI_ACP_AWBURST + + + + + AWLOCK + + + S_AXI_ACP_AWLOCK + + + + + AWSIZE + + + S_AXI_ACP_AWSIZE + + + + + ARUSER + + + S_AXI_ACP_ARUSER + + + + + AWUSER + + + S_AXI_ACP_AWUSER + + + + + WDATA + + + S_AXI_ACP_WDATA + + + + + WSTRB + + + S_AXI_ACP_WSTRB + + + + + + NUM_WRITE_OUTSTANDING + NUM WRITE OUTSTANDING + 8 + + + NUM_READ_OUTSTANDING + NUM READ OUTSTANDING + 8 + + + + + + optional + false + + + + + + S_AXI_GP0 + + + + + + false + + + + ARREADY + + + S_AXI_GP0_ARREADY + + + + + AWREADY + + + S_AXI_GP0_AWREADY + + + + + BVALID + + + S_AXI_GP0_BVALID + + + + + RLAST + + + S_AXI_GP0_RLAST + + + + + RVALID + + + S_AXI_GP0_RVALID + + + + + WREADY + + + S_AXI_GP0_WREADY + + + + + BRESP + + + S_AXI_GP0_BRESP + + + + + RRESP + + + S_AXI_GP0_RRESP + + + + + RDATA + + + S_AXI_GP0_RDATA + + + + + BID + + + S_AXI_GP0_BID + + + + + RID + + + S_AXI_GP0_RID + + + + + ARVALID + + + S_AXI_GP0_ARVALID + + + + + AWVALID + + + S_AXI_GP0_AWVALID + + + + + BREADY + + + S_AXI_GP0_BREADY + + + + + RREADY + + + S_AXI_GP0_RREADY + + + + + WLAST + + + S_AXI_GP0_WLAST + + + + + WVALID + + + S_AXI_GP0_WVALID + + + + + ARBURST + + + S_AXI_GP0_ARBURST + + + + + ARLOCK + + + S_AXI_GP0_ARLOCK + + + + + ARSIZE + + + S_AXI_GP0_ARSIZE + + + + + AWBURST + + + S_AXI_GP0_AWBURST + + + + + AWLOCK + + + S_AXI_GP0_AWLOCK + + + + + AWSIZE + + + S_AXI_GP0_AWSIZE + + + + + ARPROT + + + S_AXI_GP0_ARPROT + + + + + AWPROT + + + S_AXI_GP0_AWPROT + + + + + ARADDR + + + S_AXI_GP0_ARADDR + + + + + AWADDR + + + S_AXI_GP0_AWADDR + + + + + WDATA + + + S_AXI_GP0_WDATA + + + + + ARCACHE + + + S_AXI_GP0_ARCACHE + + + + + ARLEN + + + S_AXI_GP0_ARLEN + + + + + ARQOS + + + S_AXI_GP0_ARQOS + + + + + AWCACHE + + + S_AXI_GP0_AWCACHE + + + + + AWLEN + + + S_AXI_GP0_AWLEN + + + + + AWQOS + + + S_AXI_GP0_AWQOS + + + + + WSTRB + + + S_AXI_GP0_WSTRB + + + + + ARID + + + S_AXI_GP0_ARID + + + + + AWID + + + S_AXI_GP0_AWID + + + + + WID + + + S_AXI_GP0_WID + + + + + + NUM_WRITE_OUTSTANDING + NUM WRITE OUTSTANDING + 8 + + + NUM_READ_OUTSTANDING + NUM READ OUTSTANDING + 8 + + + + + + optional + false + + + + + + S_AXI_GP1 + + + + + + false + + + + ARREADY + + + S_AXI_GP1_ARREADY + + + + + AWREADY + + + S_AXI_GP1_AWREADY + + + + + BVALID + + + S_AXI_GP1_BVALID + + + + + RLAST + + + S_AXI_GP1_RLAST + + + + + RVALID + + + S_AXI_GP1_RVALID + + + + + WREADY + + + S_AXI_GP1_WREADY + + + + + BRESP + + + S_AXI_GP1_BRESP + + + + + RRESP + + + S_AXI_GP1_RRESP + + + + + RDATA + + + S_AXI_GP1_RDATA + + + + + BID + + + S_AXI_GP1_BID + + + + + RID + + + S_AXI_GP1_RID + + + + + ARVALID + + + S_AXI_GP1_ARVALID + + + + + AWVALID + + + S_AXI_GP1_AWVALID + + + + + BREADY + + + S_AXI_GP1_BREADY + + + + + RREADY + + + S_AXI_GP1_RREADY + + + + + WLAST + + + S_AXI_GP1_WLAST + + + + + WVALID + + + S_AXI_GP1_WVALID + + + + + ARBURST + + + S_AXI_GP1_ARBURST + + + + + ARLOCK + + + S_AXI_GP1_ARLOCK + + + + + ARSIZE + + + S_AXI_GP1_ARSIZE + + + + + AWBURST + + + S_AXI_GP1_AWBURST + + + + + AWLOCK + + + S_AXI_GP1_AWLOCK + + + + + AWSIZE + + + S_AXI_GP1_AWSIZE + + + + + ARPROT + + + S_AXI_GP1_ARPROT + + + + + AWPROT + + + S_AXI_GP1_AWPROT + + + + + ARADDR + + + S_AXI_GP1_ARADDR + + + + + AWADDR + + + S_AXI_GP1_AWADDR + + + + + WDATA + + + S_AXI_GP1_WDATA + + + + + ARCACHE + + + S_AXI_GP1_ARCACHE + + + + + ARLEN + + + S_AXI_GP1_ARLEN + + + + + ARQOS + + + S_AXI_GP1_ARQOS + + + + + AWCACHE + + + S_AXI_GP1_AWCACHE + + + + + AWLEN + + + S_AXI_GP1_AWLEN + + + + + AWQOS + + + S_AXI_GP1_AWQOS + + + + + WSTRB + + + S_AXI_GP1_WSTRB + + + + + ARID + + + S_AXI_GP1_ARID + + + + + AWID + + + S_AXI_GP1_AWID + + + + + WID + + + S_AXI_GP1_WID + + + + + + NUM_WRITE_OUTSTANDING + NUM WRITE OUTSTANDING + 8 + + + NUM_READ_OUTSTANDING + NUM READ OUTSTANDING + 8 + + + + + + optional + false + + + + + + S_AXI_HP0 + + + + + + false + + + + ARREADY + + + S_AXI_HP0_ARREADY + + + + + AWREADY + + + S_AXI_HP0_AWREADY + + + + + BVALID + + + S_AXI_HP0_BVALID + + + + + RLAST + + + S_AXI_HP0_RLAST + + + + + RVALID + + + S_AXI_HP0_RVALID + + + + + WREADY + + + S_AXI_HP0_WREADY + + + + + BRESP + + + S_AXI_HP0_BRESP + + + + + RRESP + + + S_AXI_HP0_RRESP + + + + + BID + + + S_AXI_HP0_BID + + + + + RID + + + S_AXI_HP0_RID + + + + + RDATA + + + S_AXI_HP0_RDATA + + + + + ARVALID + + + S_AXI_HP0_ARVALID + + + + + AWVALID + + + S_AXI_HP0_AWVALID + + + + + BREADY + + + S_AXI_HP0_BREADY + + + + + RREADY + + + S_AXI_HP0_RREADY + + + + + WLAST + + + S_AXI_HP0_WLAST + + + + + WVALID + + + S_AXI_HP0_WVALID + + + + + ARBURST + + + S_AXI_HP0_ARBURST + + + + + ARLOCK + + + S_AXI_HP0_ARLOCK + + + + + ARSIZE + + + S_AXI_HP0_ARSIZE + + + + + AWBURST + + + S_AXI_HP0_AWBURST + + + + + AWLOCK + + + S_AXI_HP0_AWLOCK + + + + + AWSIZE + + + S_AXI_HP0_AWSIZE + + + + + ARPROT + + + S_AXI_HP0_ARPROT + + + + + AWPROT + + + S_AXI_HP0_AWPROT + + + + + ARADDR + + + S_AXI_HP0_ARADDR + + + + + AWADDR + + + S_AXI_HP0_AWADDR + + + + + ARCACHE + + + S_AXI_HP0_ARCACHE + + + + + ARLEN + + + S_AXI_HP0_ARLEN + + + + + ARQOS + + + S_AXI_HP0_ARQOS + + + + + AWCACHE + + + S_AXI_HP0_AWCACHE + + + + + AWLEN + + + S_AXI_HP0_AWLEN + + + + + AWQOS + + + S_AXI_HP0_AWQOS + + + + + ARID + + + S_AXI_HP0_ARID + + + + + AWID + + + S_AXI_HP0_AWID + + + + + WID + + + S_AXI_HP0_WID + + + + + WDATA + + + S_AXI_HP0_WDATA + + + + + WSTRB + + + S_AXI_HP0_WSTRB + + + + + + NUM_WRITE_OUTSTANDING + NUM WRITE OUTSTANDING + 8 + + + NUM_READ_OUTSTANDING + NUM READ OUTSTANDING + 8 + + + PROTOCOL + AXI3 + + + READ_WRITE_MODE + READ_WRITE + + + DATA_WIDTH + 64 + + + ADDR_WIDTH + 32 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + ID_WIDTH + 6 + + + SUPPORTS_NARROW_BURST + 1 + + + MAX_BURST_LENGTH + 16 + + + FREQ_HZ + 100000000 + + + CLK_DOMAIN + z_turn_processing_system7_0_0_FCLK_CLK2 + + + + + + optional + true + + + + + + S_AXI_HP1 + + + + + + false + + + + ARREADY + + + S_AXI_HP1_ARREADY + + + + + AWREADY + + + S_AXI_HP1_AWREADY + + + + + BVALID + + + S_AXI_HP1_BVALID + + + + + RLAST + + + S_AXI_HP1_RLAST + + + + + RVALID + + + S_AXI_HP1_RVALID + + + + + WREADY + + + S_AXI_HP1_WREADY + + + + + BRESP + + + S_AXI_HP1_BRESP + + + + + RRESP + + + S_AXI_HP1_RRESP + + + + + BID + + + S_AXI_HP1_BID + + + + + RID + + + S_AXI_HP1_RID + + + + + RDATA + + + S_AXI_HP1_RDATA + + + + + ARVALID + + + S_AXI_HP1_ARVALID + + + + + AWVALID + + + S_AXI_HP1_AWVALID + + + + + BREADY + + + S_AXI_HP1_BREADY + + + + + RREADY + + + S_AXI_HP1_RREADY + + + + + WLAST + + + S_AXI_HP1_WLAST + + + + + WVALID + + + S_AXI_HP1_WVALID + + + + + ARBURST + + + S_AXI_HP1_ARBURST + + + + + ARLOCK + + + S_AXI_HP1_ARLOCK + + + + + ARSIZE + + + S_AXI_HP1_ARSIZE + + + + + AWBURST + + + S_AXI_HP1_AWBURST + + + + + AWLOCK + + + S_AXI_HP1_AWLOCK + + + + + AWSIZE + + + S_AXI_HP1_AWSIZE + + + + + ARPROT + + + S_AXI_HP1_ARPROT + + + + + AWPROT + + + S_AXI_HP1_AWPROT + + + + + ARADDR + + + S_AXI_HP1_ARADDR + + + + + AWADDR + + + S_AXI_HP1_AWADDR + + + + + ARCACHE + + + S_AXI_HP1_ARCACHE + + + + + ARLEN + + + S_AXI_HP1_ARLEN + + + + + ARQOS + + + S_AXI_HP1_ARQOS + + + + + AWCACHE + + + S_AXI_HP1_AWCACHE + + + + + AWLEN + + + S_AXI_HP1_AWLEN + + + + + AWQOS + + + S_AXI_HP1_AWQOS + + + + + ARID + + + S_AXI_HP1_ARID + + + + + AWID + + + S_AXI_HP1_AWID + + + + + WID + + + S_AXI_HP1_WID + + + + + WDATA + + + S_AXI_HP1_WDATA + + + + + WSTRB + + + S_AXI_HP1_WSTRB + + + + + + NUM_WRITE_OUTSTANDING + NUM WRITE OUTSTANDING + 8 + + + NUM_READ_OUTSTANDING + NUM READ OUTSTANDING + 8 + + + + + + optional + false + + + + + + S_AXI_HP2 + + + + + + false + + + + ARREADY + + + S_AXI_HP2_ARREADY + + + + + AWREADY + + + S_AXI_HP2_AWREADY + + + + + BVALID + + + S_AXI_HP2_BVALID + + + + + RLAST + + + S_AXI_HP2_RLAST + + + + + RVALID + + + S_AXI_HP2_RVALID + + + + + WREADY + + + S_AXI_HP2_WREADY + + + + + BRESP + + + S_AXI_HP2_BRESP + + + + + RRESP + + + S_AXI_HP2_RRESP + + + + + BID + + + S_AXI_HP2_BID + + + + + RID + + + S_AXI_HP2_RID + + + + + RDATA + + + S_AXI_HP2_RDATA + + + + + ARVALID + + + S_AXI_HP2_ARVALID + + + + + AWVALID + + + S_AXI_HP2_AWVALID + + + + + BREADY + + + S_AXI_HP2_BREADY + + + + + RREADY + + + S_AXI_HP2_RREADY + + + + + WLAST + + + S_AXI_HP2_WLAST + + + + + WVALID + + + S_AXI_HP2_WVALID + + + + + ARBURST + + + S_AXI_HP2_ARBURST + + + + + ARLOCK + + + S_AXI_HP2_ARLOCK + + + + + ARSIZE + + + S_AXI_HP2_ARSIZE + + + + + AWBURST + + + S_AXI_HP2_AWBURST + + + + + AWLOCK + + + S_AXI_HP2_AWLOCK + + + + + AWSIZE + + + S_AXI_HP2_AWSIZE + + + + + ARPROT + + + S_AXI_HP2_ARPROT + + + + + AWPROT + + + S_AXI_HP2_AWPROT + + + + + ARADDR + + + S_AXI_HP2_ARADDR + + + + + AWADDR + + + S_AXI_HP2_AWADDR + + + + + ARCACHE + + + S_AXI_HP2_ARCACHE + + + + + ARLEN + + + S_AXI_HP2_ARLEN + + + + + ARQOS + + + S_AXI_HP2_ARQOS + + + + + AWCACHE + + + S_AXI_HP2_AWCACHE + + + + + AWLEN + + + S_AXI_HP2_AWLEN + + + + + AWQOS + + + S_AXI_HP2_AWQOS + + + + + ARID + + + S_AXI_HP2_ARID + + + + + AWID + + + S_AXI_HP2_AWID + + + + + WID + + + S_AXI_HP2_WID + + + + + WDATA + + + S_AXI_HP2_WDATA + + + + + WSTRB + + + S_AXI_HP2_WSTRB + + + + + + NUM_WRITE_OUTSTANDING + NUM WRITE OUTSTANDING + 8 + + + NUM_READ_OUTSTANDING + NUM READ OUTSTANDING + 8 + + + + + + optional + false + + + + + + S_AXI_HP3 + + + + + + false + + + + ARREADY + + + S_AXI_HP3_ARREADY + + + + + AWREADY + + + S_AXI_HP3_AWREADY + + + + + BVALID + + + S_AXI_HP3_BVALID + + + + + RLAST + + + S_AXI_HP3_RLAST + + + + + RVALID + + + S_AXI_HP3_RVALID + + + + + WREADY + + + S_AXI_HP3_WREADY + + + + + BRESP + + + S_AXI_HP3_BRESP + + + + + RRESP + + + S_AXI_HP3_RRESP + + + + + BID + + + S_AXI_HP3_BID + + + + + RID + + + S_AXI_HP3_RID + + + + + RDATA + + + S_AXI_HP3_RDATA + + + + + ARVALID + + + S_AXI_HP3_ARVALID + + + + + AWVALID + + + S_AXI_HP3_AWVALID + + + + + BREADY + + + S_AXI_HP3_BREADY + + + + + RREADY + + + S_AXI_HP3_RREADY + + + + + WLAST + + + S_AXI_HP3_WLAST + + + + + WVALID + + + S_AXI_HP3_WVALID + + + + + ARBURST + + + S_AXI_HP3_ARBURST + + + + + ARLOCK + + + S_AXI_HP3_ARLOCK + + + + + ARSIZE + + + S_AXI_HP3_ARSIZE + + + + + AWBURST + + + S_AXI_HP3_AWBURST + + + + + AWLOCK + + + S_AXI_HP3_AWLOCK + + + + + AWSIZE + + + S_AXI_HP3_AWSIZE + + + + + ARPROT + + + S_AXI_HP3_ARPROT + + + + + AWPROT + + + S_AXI_HP3_AWPROT + + + + + ARADDR + + + S_AXI_HP3_ARADDR + + + + + AWADDR + + + S_AXI_HP3_AWADDR + + + + + ARCACHE + + + S_AXI_HP3_ARCACHE + + + + + ARLEN + + + S_AXI_HP3_ARLEN + + + + + ARQOS + + + S_AXI_HP3_ARQOS + + + + + AWCACHE + + + S_AXI_HP3_AWCACHE + + + + + AWLEN + + + S_AXI_HP3_AWLEN + + + + + AWQOS + + + S_AXI_HP3_AWQOS + + + + + ARID + + + S_AXI_HP3_ARID + + + + + AWID + + + S_AXI_HP3_AWID + + + + + WID + + + S_AXI_HP3_WID + + + + + WDATA + + + S_AXI_HP3_WDATA + + + + + WSTRB + + + S_AXI_HP3_WSTRB + + + + + + NUM_WRITE_OUTSTANDING + NUM WRITE OUTSTANDING + 8 + + + NUM_READ_OUTSTANDING + NUM READ OUTSTANDING + 8 + + + + + + optional + false + + + + + + FCLK_CLK0 + + + + false + + + + CLK + + + FCLK_CLK0 + + + + + + FREQ_HZ + 166666672 + + + ASSOCIATED_RESET + + + + ASSOCIATED_BUSIF + + + + CLK_DOMAIN + z_turn_processing_system7_0_0_FCLK_CLK0 + + + PHASE + 0.000 + + + + + + optional + true + + + + + + FCLK_CLK1 + + + + false + + + + CLK + + + FCLK_CLK1 + + + + + + FREQ_HZ + 50000000 + + + ASSOCIATED_RESET + + + + ASSOCIATED_BUSIF + + + + CLK_DOMAIN + z_turn_processing_system7_0_0_FCLK_CLK1 + + + PHASE + 0.000 + + + + + + optional + true + + + + + + FCLK_CLK2 + + + + false + + + + CLK + + + FCLK_CLK2 + + + + + + FREQ_HZ + 100000000 + + + ASSOCIATED_RESET + + + + ASSOCIATED_BUSIF + + + + CLK_DOMAIN + z_turn_processing_system7_0_0_FCLK_CLK2 + + + PHASE + 0.000 + + + + + + optional + true + + + + + + FCLK_CLK3 + + + + false + + + + CLK + + + FCLK_CLK3 + + + + + + FREQ_HZ + 200000000 + + + ASSOCIATED_RESET + + + + ASSOCIATED_BUSIF + + + + CLK_DOMAIN + z_turn_processing_system7_0_0_FCLK_CLK3 + + + PHASE + 0.000 + + + + + + optional + true + + + + + + FCLK_RESET0_N + + + + false + + + + RST + + + FCLK_RESET0_N + + + + + + + optional + true + + + + + + FCLK_RESET1_N + + + + false + + + + RST + + + FCLK_RESET1_N + + + + + + + optional + true + + + + + + FCLK_RESET2_N + + + + false + + + + RST + + + FCLK_RESET2_N + + + + + + + optional + true + + + + + + FCLK_RESET3_N + + + + false + + + + RST + + + FCLK_RESET3_N + + + + + + + optional + true + + + + + + IRQ_P2F_DMAC_ABORT + + + + false + + + + INTERRUPT + + + IRQ_P2F_DMAC_ABORT + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_DMAC0 + + + + false + + + + INTERRUPT + + + IRQ_P2F_DMAC0 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_DMAC1 + + + + false + + + + INTERRUPT + + + IRQ_P2F_DMAC1 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_DMAC2 + + + + false + + + + INTERRUPT + + + IRQ_P2F_DMAC2 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_DMAC3 + + + + false + + + + INTERRUPT + + + IRQ_P2F_DMAC3 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_DMAC4 + + + + false + + + + INTERRUPT + + + IRQ_P2F_DMAC4 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_DMAC5 + + + + false + + + + INTERRUPT + + + IRQ_P2F_DMAC5 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_DMAC6 + + + + false + + + + INTERRUPT + + + IRQ_P2F_DMAC6 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_DMAC7 + + + + false + + + + INTERRUPT + + + IRQ_P2F_DMAC7 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_SMC + + + + false + + + + INTERRUPT + + + IRQ_P2F_SMC + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_QSPI + + + + false + + + + INTERRUPT + + + IRQ_P2F_QSPI + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_CTI + + + + false + + + + INTERRUPT + + + IRQ_P2F_CTI + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_GPIO + + + + false + + + + INTERRUPT + + + IRQ_P2F_GPIO + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_USB0 + + + + false + + + + INTERRUPT + + + IRQ_P2F_USB0 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_ENET0 + + + + false + + + + INTERRUPT + + + IRQ_P2F_ENET0 + + + + + + SENSITIVITY + EDGE_RISING + + + + + + optional + false + + + + + + IRQ_P2F_ENET_WAKE0 + + + + false + + + + INTERRUPT + + + IRQ_P2F_ENET_WAKE0 + + + + + + SENSITIVITY + EDGE_RISING + + + + + + optional + false + + + + + + IRQ_P2F_SDIO0 + + + + false + + + + INTERRUPT + + + IRQ_P2F_SDIO0 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_I2C0 + + + + false + + + + INTERRUPT + + + IRQ_P2F_I2C0 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_SPI0 + + + + false + + + + INTERRUPT + + + IRQ_P2F_SPI0 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_UART0 + + + + false + + + + INTERRUPT + + + IRQ_P2F_UART0 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_CAN0 + + + + false + + + + INTERRUPT + + + IRQ_P2F_CAN0 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_USB1 + + + + false + + + + INTERRUPT + + + IRQ_P2F_USB1 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_ENET1 + + + + false + + + + INTERRUPT + + + IRQ_P2F_ENET1 + + + + + + SENSITIVITY + EDGE_RISING + + + + + + optional + false + + + + + + IRQ_P2F_ENET_WAKE1 + + + + false + + + + INTERRUPT + + + IRQ_P2F_ENET_WAKE1 + + + + + + SENSITIVITY + EDGE_RISING + + + + + + optional + false + + + + + + IRQ_P2F_SDIO1 + + + + false + + + + INTERRUPT + + + IRQ_P2F_SDIO1 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_I2C1 + + + + false + + + + INTERRUPT + + + IRQ_P2F_I2C1 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_SPI1 + + + + false + + + + INTERRUPT + + + IRQ_P2F_SPI1 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_UART1 + + + + false + + + + INTERRUPT + + + IRQ_P2F_UART1 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_P2F_CAN1 + + + + false + + + + INTERRUPT + + + IRQ_P2F_CAN1 + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + false + + + + + + IRQ_F2P + + + + false + + + + INTERRUPT + + + IRQ_F2P + + + + + + PortWidth + 16 + + + SENSITIVITY + LEVEL_HIGH + + + + + + optional + true + + + + + + Core0_nFIQ + + + + false + + + + INTERRUPT + + + Core0_nFIQ + + + + + + + optional + false + + + + + + Core0_nIRQ + + + + false + + + + INTERRUPT + + + Core0_nIRQ + + + + + + + optional + false + + + + + + Core1_nFIQ + + + + false + + + + INTERRUPT + + + Core1_nFIQ + + + + + + + optional + false + + + + + + Core1_nIRQ + + + + false + + + + INTERRUPT + + + Core1_nIRQ + + + + + + + optional + false + + + + + + M_AXI_GP0_ACLK + + + + false + + + + CLK + + + M_AXI_GP0_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXI_GP0 + + + FREQ_HZ + 50000000 + + + CLK_DOMAIN + z_turn_processing_system7_0_0_FCLK_CLK1 + + + + + + optional + true + + + + + + M_AXI_GP1_ACLK + + + + false + + + + CLK + + + M_AXI_GP1_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXI_GP1 + + + + + + optional + false + + + + + + S_AXI_ACP_ACLK + + + + false + + + + CLK + + + S_AXI_ACP_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_ACP + + + + + + optional + false + + + + + + S_AXI_GP0_ACLK + + + + false + + + + CLK + + + S_AXI_GP0_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_GP0 + + + + + + optional + false + + + + + + S_AXI_GP1_ACLK + + + + false + + + + CLK + + + S_AXI_GP1_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_GP1 + + + + + + optional + false + + + + + + S_AXI_HP0_ACLK + + + + false + + + + CLK + + + S_AXI_HP0_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_HP0 + + + FREQ_HZ + 100000000 + + + CLK_DOMAIN + z_turn_processing_system7_0_0_FCLK_CLK2 + + + + + + optional + true + + + + + + S_AXI_HP1_ACLK + + + + false + + + + CLK + + + S_AXI_HP1_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_HP1 + + + + + + optional + false + + + + + + S_AXI_HP2_ACLK + + + + false + + + + CLK + + + S_AXI_HP2_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_HP2 + + + + + + optional + false + + + + + + S_AXI_HP3_ACLK + + + + false + + + + CLK + + + S_AXI_HP3_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_HP3 + + + + + + optional + false + + + + + + FTMD_TRACEIN_CLK + + + + false + + + + CLK + + + FTMD_TRACEIN_CLK + + + + + + ASSOCIATED_BUSIF + FTM_TRACE_DATA + + + + + + optional + false + + + + + + DMA0_ACLK + + + + false + + + + CLK + + + DMA0_ACLK + + + + + + ASSOCIATED_BUSIF + DMA0_ACK:DMA0_REQ + + + + + + optional + false + + + + + + DMA1_ACLK + + + + false + + + + CLK + + + DMA1_ACLK + + + + + + ASSOCIATED_BUSIF + DMA1_ACK:DMA1_REQ + + + + + + optional + false + + + + + + DMA2_ACLK + + + + false + + + + CLK + + + DMA2_ACLK + + + + + + ASSOCIATED_BUSIF + DMA2_ACK:DMA2_REQ + + + + + + optional + false + + + + + + DMA3_ACLK + + + + false + + + + CLK + + + DMA3_ACLK + + + + + + ASSOCIATED_BUSIF + DMA3_ACK:DMA3_REQ + + + + + + optional + false + + + + + + TRIGGER_IN_0 + + + + false + + + + TRIG + + + FTMT_F2P_TRIG_0 + + + + + ACK + + + FTMT_F2P_TRIGACK_0 + + + + + + + optional + false + + + + + + TRIGGER_IN_1 + + + + false + + + + TRIG + + + FTMT_F2P_TRIG_1 + + + + + ACK + + + FTMT_F2P_TRIGACK_1 + + + + + + + optional + false + + + + + + TRIGGER_IN_2 + + + + false + + + + TRIG + + + FTMT_F2P_TRIG_2 + + + + + ACK + + + FTMT_F2P_TRIGACK_2 + + + + + + + optional + false + + + + + + TRIGGER_IN_3 + + + + false + + + + TRIG + + + FTMT_F2P_TRIG_3 + + + + + ACK + + + FTMT_F2P_TRIGACK_3 + + + + + + + optional + false + + + + + + TRIGGER_OUT_0 + + + + false + + + + ACK + + + FTMT_P2F_TRIGACK_0 + + + + + TRIG + + + FTMT_P2F_TRIG_0 + + + + + + + optional + false + + + + + + TRIGGER_OUT_1 + + + + false + + + + ACK + + + FTMT_P2F_TRIGACK_1 + + + + + TRIG + + + FTMT_P2F_TRIG_1 + + + + + + + optional + false + + + + + + TRIGGER_OUT_2 + + + + false + + + + ACK + + + FTMT_P2F_TRIGACK_2 + + + + + TRIG + + + FTMT_P2F_TRIG_2 + + + + + + + optional + false + + + + + + TRIGGER_OUT_3 + + + + false + + + + ACK + + + FTMT_P2F_TRIGACK_3 + + + + + TRIG + + + FTMT_P2F_TRIG_3 + + + + + + + optional + false + + + + + + + + Data + Data + 4G + 32 + + + segment1 + segment1 + 0x00000000 + 0x00040000 + + + segment2 + segment2 + 0x00040000 + 0x00040000 + + + segment3 + segment3 + 0x00080000 + 0x00080000 + + + segment4 + segment4 + 0x00100000 + 0x3ff00000 + + + M_AXI_GP0 + M_AXI_GP0 + 0x40000000 + 0x40000000 + + + M_AXI_GP1 + M_AXI_GP1 + 0x80000000 + 0x40000000 + + + IO_Peripheral_Registers + IO Peripheral Registers + 0xe0000000 + 0x00300000 + + + SMC_Memories + SMC Memories + 0xe1000000 + 0x05000000 + + + SLCR_Registers + SLCR Registers + 0xf8000000 + 0x00000c00 + + + PS_System_Registers + PS System Registers + 0xf8001000 + 0x0080f000 + + + CPU_Private_Registers + CPU Private Registers + 0xf8900000 + 0x00603000 + + + segment5 + segment5 + 0xfc000000 + 0x02000000 + + + segment6 + segment6 + 0xfffc0000 + 0x00040000 + + + 8 + + + + + S_AXI_HP0 + + HP0_LOW_OCM + HP0 LOW OCM + 0x00000000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + HP0_DDR_LOWOCM + HP0 DDR LOWOCM + 0x00000000 + 1073741824 + 32 + memory + + + + optional + true + + + + + + HP0_HIGH_OCM + HP0 HIGH OCM + 0xfffc0000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + + + optional + true + + + + + + S_AXI_HP1 + + HP1_LOW_OCM + HP1 LOW OCM + 0x00000000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + HP1_DDR_LOWOCM + HP1 DDR LOWOCM + 0x00000000 + 1073741824 + 32 + memory + + + + optional + true + + + + + + HP1_HIGH_OCM + HP1 HIGH OCM + 0xfffc0000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + + + optional + false + + + + + + S_AXI_HP2 + + HP2_LOW_OCM + HP2 LOW OCM + 0x00000000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + HP2_DDR_LOWOCM + HP2 DDR LOWOCM + 0x00000000 + 1073741824 + 32 + memory + + + + optional + true + + + + + + HP2_HIGH_OCM + HP2 HIGH OCM + 0xfffc0000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + + + optional + false + + + + + + S_AXI_HP3 + + HP3_LOW_OCM + HP3 LOW OCM + 0x00000000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + HP3_DDR_LOWOCM + HP3 DDR LOWOCM + 0x00000000 + 1073741824 + 32 + memory + + + + optional + true + + + + + + HP3_HIGH_OCM + HP3 HIGH OCM + 0xfffc0000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + + + optional + false + + + + + + S_AXI_GP0 + + GP0_LOW_OCM + GP0 LOW OCM + 0x00000000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + GP0_DDR_LOWOCM + GP0 DDR LOWOCM + 0x00000000 + 1073741824 + 32 + memory + + + + optional + true + + + + + + GP0_HIGH_OCM + GP0 HIGH OCM + 0xfffc0000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + GP0_QSPI_LINEAR + GP0 QSPI LINEAR + 0xfc000000 + 16777216 + 32 + memory + + + + optional + true + + + + + + GP0_SRAM_NOR0 + GP0 SRAM NOR 0 + 0xe2000000 + 0x02000000 + 32 + memory + + + + optional + false + + + + + + GP0_SRAM_NOR1 + GP0 SRAM NOR 1 + 0xe4000000 + 0x02000000 + 32 + memory + + + + optional + false + + + + + + GP0_NAND + GP0 NAND + 0xe1000000 + 0x01000000 + 32 + memory + + + + optional + false + + + + + + GP0_IOP + GP0 IOP + 0xe0000000 + 0x00400000 + 32 + register + + + + optional + true + + + + + + GP0_UART0 + GP0 UART0 + 0xe0000000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_UART1 + GP0 UART0 + 0xe0001000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_USB0 + GP0 USB0 + 0xe0002000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_USB1 + GP0 USB1 + 0xe0003000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_IIC0 + GP0 IIC0 + 0xe0004000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_IIC1 + GP0 IIC1 + 0xe0005000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_SPI0 + GP0 SPI0 + 0xe0006000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_SPI1 + GP0 SPI1 + 0xe0007000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_CAN0 + GP0 CAN0 + 0xe0008000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_CAN1 + GP0 CAN1 + 0xe0009000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_GPIO + GP0 GPIO + 0xe000A000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_ENET0 + GP0 ENET0 + 0xe000B000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_ENET1 + GP0 ENET1 + 0xe000C000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_QSPI + GP0 QSPI + 0xe000D000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_SMC + GP0 SMC + 0xe000e000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_SDIO0 + GP0 SDIO0 + 0xe0100000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_SDIO1 + GP0 SDIO1 + 0xe0101000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_PS_SLCR_REGS + GP0 PS REG + 0xf8000000 + 0x00010000 + 32 + register + + + + optional + false + + + + + + GP0_SLCR + GP0 SLCR + 0xf8000000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_TTC0 + GP0 TTC0 + 0xf8001000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_TTC1 + GP0 TTC1 + 0xf8002000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_DMAC_S + GP0 DMAC S + 0xf8003000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_DMAC_NS + GP0 DMAC NS + 0xf8004000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_SWDT + GP0 SWDT + 0xf8005000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_DDRC + GP0 DDRC + 0xf8006000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_DEVCFG + GP0 DEVCFG + 0xf8007000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_AFI0 + GP0 AFI0 + 0xf8008000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_AFI1 + GP0 AFI1 + 0xf8009000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_AFI2 + GP0 AFI2 + 0xf800A000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_AFI3 + GP0 AFI3 + 0xf800B000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_OCM_REG + GP0 OCM REG + 0xf800C000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP0_CORESIGHT + GP0 CORESIGHT + 0xf8800000 + 0x00100000 + 32 + register + + + + optional + false + + + + + + GP0_M_AXI_GP0 + GP0 M AXI GP0 + 0x40000000 + 0x40000000 + 32 + register + + + + optional + true + + + + + + GP0_M_AXI_GP1 + GP0 M AXI GP1 + 0x80000000 + 0x40000000 + 32 + register + + + + optional + false + + + + + + + + optional + false + + + + + + S_AXI_GP1 + + GP1_LOW_OCM + GP1 LOW OCM + 0x00000000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + GP1_DDR_LOWOCM + GP1 DDR LOWOCM + 0x00000000 + 1073741824 + 32 + memory + + + + optional + true + + + + + + GP1_HIGH_OCM + GP1 HIGH OCM + 0xfffc0000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + GP1_QSPI_LINEAR + GP1 QSPI LINEAR + 0xfc000000 + 16777216 + 32 + memory + + + + optional + true + + + + + + GP1_SRAM_NOR0 + GP1 SRAM NOR 0 + 0xe2000000 + 0x02000000 + 32 + memory + + + + optional + false + + + + + + GP1_SRAM_NOR1 + GP1 SRAM NOR 1 + 0xe4000000 + 0x02000000 + 32 + memory + + + + optional + false + + + + + + GP1_NAND + GP1 NAND + 0xe1000000 + 0x01000000 + 32 + memory + + + + optional + false + + + + + + GP1_IOP + GP1 IOP + 0xe0000000 + 0x00400000 + 32 + register + + + + optional + true + + + + + + GP1_UART0 + GP1 UART0 + 0xe0000000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_UART1 + GP1 UART0 + 0xe0001000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_USB0 + GP1 USB0 + 0xe0002000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_USB1 + GP1 USB1 + 0xe0003000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_IIC0 + GP1 IIC0 + 0xe0004000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_IIC1 + GP1 IIC1 + 0xe0005000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_SPI0 + GP1 SPI0 + 0xe0006000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_SPI1 + GP1 SPI1 + 0xe0007000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_CAN0 + GP1 CAN0 + 0xe0008000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_CAN1 + GP1 CAN1 + 0xe0009000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_GPIO + GP1 GPIO + 0xe000A000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_ENET0 + GP1 ENET0 + 0xe000B000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_ENET1 + GP1 ENET1 + 0xe000C000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_QSPI + GP1 QSPI + 0xe000D000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_SMC + GP1 SMC + 0xe000e000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_SDIO0 + GP1 SDIO0 + 0xe0100000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_SDIO1 + GP1 SDIO1 + 0xe0101000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_PS_SLCR_REGS + GP1 PS REG + 0xf8000000 + 0x00010000 + 32 + register + + + + optional + false + + + + + + GP1_SLCR + GP1 SLCR + 0xf8000000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_TTC0 + GP1 TTC0 + 0xf8001000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_TTC1 + GP1 TTC1 + 0xf8002000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_DMAC_S + GP1 DMAC S + 0xf8003000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_DMAC_NS + GP1 DMAC NS + 0xf8004000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_SWDT + GP1 SWDT + 0xf8005000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_DDRC + GP1 DDRC + 0xf8006000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_DEVCFG + GP1 DEVCFG + 0xf8007000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_AFI0 + GP1 AFI0 + 0xf8008000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_AFI1 + GP1 AFI1 + 0xf8009000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_AFI2 + GP1 AFI2 + 0xf800A000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_AFI3 + GP1 AFI3 + 0xf800B000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_OCM_REG + GP1 OCM REG + 0xf800C000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + GP1_CORESIGHT + GP1 CORESIGHT + 0xf8800000 + 0x00100000 + 32 + register + + + + optional + false + + + + + + GP1_M_AXI_GP0 + GP1 M AXI GP0 + 0x40000000 + 0x40000000 + 32 + register + + + + optional + true + + + + + + GP1_M_AXI_GP1 + GP1 M AXI GP1 + 0x80000000 + 0x40000000 + 32 + register + + + + optional + false + + + + + + + + optional + false + + + + + + S_AXI_ACP + + ACP_LOW_OCM + ACP LOW OCM + 0x00000000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + ACP_DDR_LOWOCM + ACP DDR LOWOCM + 0x00000000 + 1073741824 + 32 + memory + + + + optional + true + + + + + + ACP_HIGH_OCM + ACP HIGH OCM + 0xfffc0000 + 0x00040000 + 32 + memory + + + + optional + false + + + + + + ACP_QSPI_LINEAR + ACP QSPI LINEAR + 0xfc000000 + 16777216 + 32 + memory + + + + optional + true + + + + + + ACP_SRAM_NOR0 + ACP SRAM NOR 0 + 0xe2000000 + 0x02000000 + 32 + memory + + + + optional + false + + + + + + ACP_SRAM_NOR1 + ACP SRAM NOR 1 + 0xe4000000 + 0x02000000 + 32 + memory + + + + optional + false + + + + + + ACP_NAND + ACP NAND + 0xe1000000 + 0x01000000 + 32 + memory + + + + optional + false + + + + + + ACP_IOP + ACP IOP + 0xe0000000 + 0x00400000 + 32 + register + + + + optional + true + + + + + + ACP_UART0 + ACP UART0 + 0xe0000000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_UART1 + ACP UART0 + 0xe0001000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_USB0 + ACP USB0 + 0xe0002000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_USB1 + ACP USB1 + 0xe0003000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_IIC0 + ACP IIC0 + 0xe0004000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_IIC1 + ACP IIC1 + 0xe0005000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_SPI0 + ACP SPI0 + 0xe0006000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_SPI1 + ACP SPI1 + 0xe0007000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_CAN0 + ACP CAN0 + 0xe0008000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_CAN1 + ACP CAN1 + 0xe0009000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_GPIO + ACP GPIO + 0xe000A000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_ENET0 + ACP ENET0 + 0xe000B000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_ENET1 + ACP ENET1 + 0xe000C000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_QSPI + ACP QSPI + 0xe000D000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_SMC + ACP SMC + 0xe000e000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_SDIO0 + ACP SDIO0 + 0xe0100000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_SDIO1 + ACP SDIO1 + 0xe0101000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_PS_SLCR_REGS + ACP PS REG + 0xf8000000 + 0x00010000 + 32 + register + + + + optional + false + + + + + + ACP_SLCR + ACP SLCR + 0xf8000000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_TTC0 + ACP TTC0 + 0xf8001000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_TTC1 + ACP TTC1 + 0xf8002000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_DMAC_S + ACP DMAC S + 0xf8003000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_DMAC_NS + ACP DMAC NS + 0xf8004000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_SWDT + ACP SWDT + 0xf8005000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_DDRC + ACP DDRC + 0xf8006000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_DEVCFG + ACP DEVCFG + 0xf8007000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_AFI0 + ACP AFI0 + 0xf8008000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_AFI1 + ACP AFI1 + 0xf8009000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_AFI2 + ACP AFI2 + 0xf800A000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_AFI3 + ACP AFI3 + 0xf800B000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_OCM_REG + ACP OCM REG + 0xf800C000 + 0x00001000 + 32 + register + + + + optional + false + + + + + + ACP_CORESIGHT + ACP CORESIGHT + 0xf8800000 + 0x00100000 + 32 + register + + + + optional + false + + + + + + ACP_M_AXI_GP0 + ACP M AXI GP0 + 0x40000000 + 0x40000000 + 32 + register + + + + optional + true + + + + + + ACP_M_AXI_GP1 + ACP M AXI GP1 + 0x80000000 + 0x40000000 + 32 + register + + + + optional + false + + + + + + + + optional + false + + + + + + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + customizationCRC + a9001dcd + + + customizationCRCversion + 5 + + + boundaryCRC + 2cc787ac + + + boundaryCRCversion + 1 + + + GENtimestamp + Wed Jul 15 03:10:10 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + + xilinx_anylanguagesynthesis_view_fileset + + + + customizationCRC + a9001dcd + + + customizationCRCversion + 5 + + + boundaryCRC + 2cc787ac + + + boundaryCRCversion + 1 + + + GENtimestamp + Wed Jul 15 03:10:34 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + + xilinx_verilogsynthesiswrapper_view_fileset + + + + customizationCRC + a9001dcd + + + customizationCRCversion + 5 + + + boundaryCRC + 2cc787ac + + + boundaryCRCversion + 1 + + + GENtimestamp + Wed Jul 15 03:10:34 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_processing_system7_bfm_2_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + customizationCRC + b15c4959 + + + customizationCRCversion + 5 + + + boundaryCRC + 2cc787ac + + + boundaryCRCversion + 1 + + + + + xilinx_anylanguagesimulationwrapper + Simulation Wrapper + :vivado.xilinx.com:simulation.wrapper + + xilinx_anylanguagesimulationwrapper_view_fileset + + + + customizationCRC + b15c4959 + + + customizationCRCversion + 5 + + + boundaryCRC + 2cc787ac + + + boundaryCRCversion + 1 + + + GENtimestamp + Wed Jul 15 03:10:35 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_miscfiles + Miscellaneous + :vivado.xilinx.com:misc.files + + xilinx_miscfiles_view_fileset + + + + customizationCRC + a9001dcd + + + customizationCRCversion + 5 + + + boundaryCRC + 2cc787ac + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 03 07:52:02 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + customizationCRC + a9001dcd + + + customizationCRCversion + 5 + + + boundaryCRC + 2cc787ac + + + boundaryCRCversion + 1 + + + GENtimestamp + Wed Jul 15 03:10:35 UTC 2015 + + + StaleAtRelink + false + + + + + + + CAN0_PHY_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + CAN0_PHY_RX + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + CAN1_PHY_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + CAN1_PHY_RX + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET0_GMII_TX_EN + + out + + 0 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET0_GMII_TX_ER + + out + + 0 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET0_MDIO_MDC + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET0_MDIO_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET0_MDIO_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET0_PTP_DELAY_REQ_RX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + ENET0_PTP_DELAY_REQ_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + ENET0_PTP_PDELAY_REQ_RX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + ENET0_PTP_PDELAY_REQ_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + ENET0_PTP_PDELAY_RESP_RX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + ENET0_PTP_PDELAY_RESP_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + ENET0_PTP_SYNC_FRAME_RX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + ENET0_PTP_SYNC_FRAME_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + ENET0_SOF_RX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + ENET0_SOF_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + ENET0_GMII_TXD + + out + + 7 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET0_GMII_COL + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET0_GMII_CRS + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET0_GMII_RX_CLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET0_GMII_RX_DV + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET0_GMII_RX_ER + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET0_GMII_TX_CLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET0_MDIO_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET0_EXT_INTIN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET0_GMII_RXD + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET1_GMII_TX_EN + + out + + 0 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_GMII_TX_ER + + out + + 0 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_MDIO_MDC + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_MDIO_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_MDIO_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_PTP_DELAY_REQ_RX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_PTP_DELAY_REQ_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_PTP_PDELAY_REQ_RX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_PTP_PDELAY_REQ_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_PTP_PDELAY_RESP_RX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_PTP_PDELAY_RESP_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_PTP_SYNC_FRAME_RX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_PTP_SYNC_FRAME_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_SOF_RX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_SOF_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_GMII_TXD + + out + + 7 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_GMII_COL + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET1_GMII_CRS + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET1_GMII_RX_CLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_GMII_RX_DV + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET1_GMII_RX_ER + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET1_GMII_TX_CLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + ENET1_MDIO_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET1_EXT_INTIN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + ENET1_GMII_RXD + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + GPIO_I + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + GPIO_O + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + GPIO_T + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + I2C0_SDA_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + I2C0_SDA_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + I2C0_SDA_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + I2C0_SCL_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + I2C0_SCL_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + I2C0_SCL_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + I2C1_SDA_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + I2C1_SDA_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + I2C1_SDA_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + I2C1_SCL_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + I2C1_SCL_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + I2C1_SCL_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + PJTAG_TCK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + PJTAG_TMS + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + PJTAG_TDI + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + PJTAG_TDO + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO0_CLK + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO0_CLK_FB + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SDIO0_CMD_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO0_CMD_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SDIO0_CMD_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO0_DATA_I + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SDIO0_DATA_O + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO0_DATA_T + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO0_LED + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO0_CDN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SDIO0_WP + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SDIO0_BUSPOW + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO0_BUSVOLT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO1_CLK + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO1_CLK_FB + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SDIO1_CMD_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO1_CMD_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SDIO1_CMD_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO1_DATA_I + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SDIO1_DATA_O + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO1_DATA_T + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO1_LED + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO1_CDN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SDIO1_WP + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SDIO1_BUSPOW + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SDIO1_BUSVOLT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI0_SCLK_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SPI0_SCLK_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI0_SCLK_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI0_MOSI_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SPI0_MOSI_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI0_MOSI_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI0_MISO_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SPI0_MISO_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI0_MISO_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI0_SS_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SPI0_SS_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI0_SS1_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI0_SS2_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI0_SS_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI1_SCLK_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SPI1_SCLK_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI1_SCLK_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI1_MOSI_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SPI1_MOSI_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI1_MOSI_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI1_MISO_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SPI1_MISO_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI1_MISO_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI1_SS_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SPI1_SS_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI1_SS1_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI1_SS2_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + SPI1_SS_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + UART0_DTRN + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + UART0_RTSN + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + UART0_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + UART0_CTSN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + UART0_DCDN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + UART0_DSRN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + UART0_RIN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + UART0_RX + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + optional + false + + + + + + UART1_DTRN + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + UART1_RTSN + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + UART1_TX + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + UART1_CTSN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + UART1_DCDN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + UART1_DSRN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + UART1_RIN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + UART1_RX + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + optional + false + + + + + + TTC0_WAVE0_OUT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + TTC0_WAVE1_OUT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + TTC0_WAVE2_OUT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + TTC0_CLK0_IN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + TTC0_CLK1_IN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + TTC0_CLK2_IN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + TTC1_WAVE0_OUT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + TTC1_WAVE1_OUT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + TTC1_WAVE2_OUT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + TTC1_CLK0_IN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + TTC1_CLK1_IN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + TTC1_CLK2_IN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + WDT_CLK_IN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + WDT_RST_OUT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + TRACE_CLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + TRACE_CLK_OUT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + TRACE_CTL + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + TRACE_DATA + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + USB0_PORT_INDCTL + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + USB0_VBUS_PWRSELECT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + USB0_VBUS_PWRFAULT + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + USB1_PORT_INDCTL + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + USB1_VBUS_PWRSELECT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + USB1_VBUS_PWRFAULT + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + SRAM_INTIN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP0_ARVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_AWVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_BREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_RREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_WLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_WVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_ARID + + out + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_AWID + + out + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_WID + + out + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_ARBURST + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_ARLOCK + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_ARSIZE + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_AWBURST + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_AWLOCK + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_AWSIZE + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_ARPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_AWPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_ARADDR + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_AWADDR + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_WDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_ARCACHE + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_ARLEN + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_ARQOS + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_AWCACHE + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_AWLEN + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_AWQOS + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_WSTRB + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + M_AXI_GP0_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP0_ARREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP0_AWREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP0_BVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP0_RLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP0_RVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP0_WREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP0_BID + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP0_RID + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP0_BRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP0_RRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP0_RDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + M_AXI_GP1_ARVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_AWVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_BREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_RREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_WLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_WVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_ARID + + out + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_AWID + + out + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_WID + + out + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_ARBURST + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_ARLOCK + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_ARSIZE + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_AWBURST + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_AWLOCK + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_AWSIZE + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_ARPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_AWPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_ARADDR + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_AWADDR + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_WDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_ARCACHE + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_ARLEN + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_ARQOS + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_AWCACHE + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_AWLEN + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_AWQOS + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_WSTRB + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + M_AXI_GP1_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP1_ARREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP1_AWREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP1_BVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP1_RLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP1_RVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP1_WREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP1_BID + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP1_RID + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP1_BRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP1_RRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + M_AXI_GP1_RDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP0_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP0_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP0_RLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP0_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP0_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP0_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP0_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP0_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP0_BID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP0_RID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP0_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_AWVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_WLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_ARBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_ARLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_ARSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_AWBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_AWLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_AWSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_ARPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_AWPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_WDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_ARCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_ARLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_ARQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_AWCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_AWLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_AWQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_ARID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_AWID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP0_WID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP1_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP1_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP1_RLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP1_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP1_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP1_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP1_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP1_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP1_BID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP1_RID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_GP1_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_AWVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_WLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_ARBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_ARLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_ARSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_AWBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_AWLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_AWSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_ARPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_AWPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_WDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_ARCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_ARLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_ARQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_AWCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_AWLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_AWQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_ARID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_AWID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_GP1_WID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_ACP_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_ACP_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_ACP_RLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_ACP_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_ACP_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_ACP_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_ACP_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_ACP_BID + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_ACP_RID + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_ACP_RDATA + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_ACP_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_AWVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_WLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARID + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_AWID + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_AWPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_WID + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_AWCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_AWLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_AWQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_AWBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_AWLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_AWSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_ARUSER + + in + + 4 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_AWUSER + + in + + 4 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_WDATA + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_ACP_WSTRB + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP0_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_RLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_BID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_RID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_RDATA + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_RCOUNT + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_WCOUNT + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_RACOUNT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_WACOUNT + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + S_AXI_HP0_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_AWVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_RDISSUECAP1_EN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_WLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_WRISSUECAP1_EN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_ARBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_ARLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_ARSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_AWBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_AWLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_AWSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_ARPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_AWPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_ARCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_ARLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_ARQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_AWCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_AWLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_AWQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_ARID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_AWID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_WID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_WDATA + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP0_WSTRB + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + S_AXI_HP1_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_RLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_BID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_RID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_RDATA + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_RCOUNT + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_WCOUNT + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_RACOUNT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_WACOUNT + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP1_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_AWVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_RDISSUECAP1_EN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_WLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_WRISSUECAP1_EN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_ARBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_ARLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_ARSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_AWBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_AWLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_AWSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_ARPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_AWPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_ARCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_ARLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_ARQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_AWCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_AWLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_AWQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_ARID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_AWID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_WID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_WDATA + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP1_WSTRB + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_RLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_BID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_RID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_RDATA + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_RCOUNT + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_WCOUNT + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_RACOUNT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_WACOUNT + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP2_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_AWVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_RDISSUECAP1_EN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_WLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_WRISSUECAP1_EN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_ARBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_ARLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_ARSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_AWBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_AWLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_AWSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_ARPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_AWPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_ARCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_ARLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_ARQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_AWCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_AWLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_AWQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_ARID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_AWID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_WID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_WDATA + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP2_WSTRB + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_RLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_BID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_RID + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_RDATA + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_RCOUNT + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_WCOUNT + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_RACOUNT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_WACOUNT + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + S_AXI_HP3_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_AWVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_RDISSUECAP1_EN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_WLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_WRISSUECAP1_EN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_ARBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_ARLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_ARSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_AWBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_AWLOCK + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_AWSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_ARPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_AWPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_ARCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_ARLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_ARQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_AWCACHE + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_AWLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_AWQOS + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_ARID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_AWID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_WID + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_WDATA + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + S_AXI_HP3_WSTRB + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + IRQ_P2F_DMAC_ABORT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_DMAC0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_DMAC1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_DMAC2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_DMAC3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_DMAC4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_DMAC5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_DMAC6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_DMAC7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_SMC + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_QSPI + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_CTI + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_GPIO + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_USB0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_ENET0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_ENET_WAKE0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_SDIO0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_I2C0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_SPI0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_UART0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_CAN0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_USB1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_ENET1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_ENET_WAKE1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_SDIO1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_I2C1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_SPI1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_UART1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_P2F_CAN1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + IRQ_F2P + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + Core0_nFIQ + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + Core0_nIRQ + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + Core1_nFIQ + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + Core1_nIRQ + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA0_DATYPE + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA0_DAVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA0_DRREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA1_DATYPE + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA1_DAVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA1_DRREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA2_DATYPE + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA2_DAVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA2_DRREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA3_DATYPE + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA3_DAVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA3_DRREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + DMA0_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA0_DAREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA0_DRLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA0_DRVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA1_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA1_DAREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA1_DRLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA1_DRVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA2_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA2_DAREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA2_DRLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA2_DRVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA3_ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA3_DAREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA3_DRLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA3_DRVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA0_DRTYPE + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA1_DRTYPE + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA2_DRTYPE + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DMA3_DRTYPE + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FCLK_CLK0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + FCLK_CLK1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + FCLK_CLK2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + FCLK_CLK3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + FCLK_CLKTRIG0_N + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FCLK_CLKTRIG1_N + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FCLK_CLKTRIG2_N + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FCLK_CLKTRIG3_N + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FCLK_RESET0_N + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + FCLK_RESET1_N + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + FCLK_RESET2_N + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + FCLK_RESET3_N + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + FTMD_TRACEIN_DATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMD_TRACEIN_VALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMD_TRACEIN_CLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMD_TRACEIN_ATID + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMT_F2P_TRIG_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMT_F2P_TRIGACK_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + FTMT_F2P_TRIG_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMT_F2P_TRIGACK_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + FTMT_F2P_TRIG_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMT_F2P_TRIGACK_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + FTMT_F2P_TRIG_3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMT_F2P_TRIGACK_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + FTMT_F2P_DEBUG + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMT_P2F_TRIGACK_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMT_P2F_TRIG_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + FTMT_P2F_TRIGACK_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMT_P2F_TRIG_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + FTMT_P2F_TRIGACK_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMT_P2F_TRIG_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + FTMT_P2F_TRIGACK_3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + FTMT_P2F_TRIG_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + FTMT_P2F_DEBUG + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + FPGA_IDLE_N + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + EVENT_EVENTO + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + EVENT_STANDBYWFE + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + EVENT_STANDBYWFI + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + false + + + + + + EVENT_EVENTI + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + DDR_ARB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + MIO + + inout + + 53 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + DDR_CAS_n + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_CKE + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_Clk_n + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_Clk + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_CS_n + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_DRSTB + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_ODT + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_RAS_n + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_WEB + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_BankAddr + + inout + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_Addr + + inout + + 14 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_VRN + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_VRP + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_DM + + inout + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_DQ + + inout + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_DQS_n + + inout + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + DDR_DQS + + inout + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + optional + true + + + + + + PS_SRSTB + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + PS_CLK + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + PS_PORB + + inout + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + + + C_EN_EMIO_PJTAG + 0 + + + C_EN_EMIO_ENET0 + 0 + + + C_EN_EMIO_ENET1 + 0 + + + C_EN_EMIO_TRACE + 0 + + + C_INCLUDE_TRACE_BUFFER + 0 + + + C_TRACE_BUFFER_FIFO_SIZE + 128 + + + USE_TRACE_DATA_EDGE_DETECTOR + 0 + + + C_TRACE_PIPELINE_WIDTH + 8 + + + C_TRACE_BUFFER_CLOCK_DELAY + 12 + + + C_EMIO_GPIO_WIDTH + 64 + + + C_INCLUDE_ACP_TRANS_CHECK + 0 + + + C_USE_DEFAULT_ACP_USER_VAL + 0 + + + C_S_AXI_ACP_ARUSER_VAL + 31 + + + C_S_AXI_ACP_AWUSER_VAL + 31 + + + C_M_AXI_GP0_ID_WIDTH + 12 + + + C_M_AXI_GP0_ENABLE_STATIC_REMAP + 0 + + + C_M_AXI_GP1_ID_WIDTH + 12 + + + C_M_AXI_GP1_ENABLE_STATIC_REMAP + 0 + + + C_S_AXI_GP0_ID_WIDTH + 6 + + + C_S_AXI_GP1_ID_WIDTH + 6 + + + C_S_AXI_ACP_ID_WIDTH + 3 + + + C_S_AXI_HP0_ID_WIDTH + 6 + + + C_S_AXI_HP0_DATA_WIDTH + 64 + + + C_S_AXI_HP1_ID_WIDTH + 6 + + + C_S_AXI_HP1_DATA_WIDTH + 64 + + + C_S_AXI_HP2_ID_WIDTH + 6 + + + C_S_AXI_HP2_DATA_WIDTH + 64 + + + C_S_AXI_HP3_ID_WIDTH + 6 + + + C_S_AXI_HP3_DATA_WIDTH + 64 + + + C_M_AXI_GP0_THREAD_ID_WIDTH + 12 + + + C_M_AXI_GP1_THREAD_ID_WIDTH + 12 + + + C_NUM_F2P_INTR_INPUTS + 16 + + + C_IRQ_F2P_MODE + DIRECT + + + C_DQ_WIDTH + 32 + + + C_DQS_WIDTH + 4 + + + C_DM_WIDTH + 4 + + + C_MIO_PRIMITIVE + 54 + + + C_TRACE_INTERNAL_WIDTH + 2 + + + C_USE_AXI_NONSECURE + 0 + + + C_USE_M_AXI_GP0 + 1 + + + C_USE_M_AXI_GP1 + 0 + + + C_USE_S_AXI_GP0 + 0 + + + C_USE_S_AXI_HP0 + 1 + + + C_USE_S_AXI_HP1 + 0 + + + C_USE_S_AXI_HP2 + 0 + + + C_USE_S_AXI_HP3 + 0 + + + C_USE_S_AXI_ACP + 0 + + + C_PS7_SI_REV + PRODUCTION + + + C_FCLK_CLK0_BUF + true + + + C_FCLK_CLK1_BUF + true + + + C_FCLK_CLK2_BUF + true + + + C_FCLK_CLK3_BUF + true + + + C_PACKAGE_NAME + clg400 + + + + + + choices_0 + 0x00100000 + 0x00040000 + + + choices_1 + 0x3FFFFFFF + + + choices_2 + 0xE0000000 + + + choices_3 + 0xE0000FFF + + + choices_4 + 0xE0001000 + + + choices_5 + 0xE0001FFF + + + choices_6 + 0xE0004000 + + + choices_7 + 0xE0004FFF + + + choices_8 + 0xE0005000 + + + choices_9 + 0xE0005FFF + + + choices_10 + 0xE0006000 + + + choices_11 + 0xE0006FFF + + + choices_12 + 0xE0007000 + + + choices_13 + 0xE0007FFF + + + choices_14 + 0xE0008000 + + + choices_15 + 0xE0008FFF + + + choices_16 + 0xE0009000 + + + choices_17 + 0xE0009FFF + + + choices_18 + 0xE000A000 + + + choices_19 + 0xE000AFFF + + + choices_20 + 0xE000B000 + + + choices_21 + 0xE000BFFF + + + choices_22 + 0xE000C000 + + + choices_23 + 0xE000CFFF + + + choices_24 + 0xE0100000 + + + choices_25 + 0xE0100FFF + + + choices_26 + 0xE0101000 + + + choices_27 + 0xE0101FFF + + + choices_28 + 0xE0102000 + + + choices_29 + 0xE0102fff + + + choices_30 + 0xE0103000 + + + choices_31 + 0xE0103fff + + + choices_32 + 0xE0104000 + + + choices_33 + 0xE0104fff + + + choices_34 + 0xE0105000 + + + choices_35 + 0xE0105fff + + + choices_36 + false + true + + + choices_37 + false + true + + + choices_38 + false + true + + + choices_39 + false + true + + + choices_40 + 0 + 1 + + + choices_41 + 0 + 1 + + + choices_42 + 0 + 1 + + + choices_43 + 0 + 1 + + + choices_44 + 0 + 1 + + + choices_45 + 0 + 1 + + + choices_46 + 0 + 1 + + + choices_47 + 0 + 1 + + + choices_48 + 0 + 1 + + + choices_49 + 0 + 1 + + + choices_50 + 0 + 1 + + + choices_51 + 0 + 1 + + + choices_52 + 0 + 1 + + + choices_53 + 0 + 1 + + + choices_54 + 0 + 1 + + + choices_55 + 0 + 1 + + + choices_56 + 0 + 1 + + + choices_57 + 0 + 1 + + + choices_58 + 0 + 1 + + + choices_59 + 0 + 1 + + + choices_60 + 0 + 1 + + + choices_61 + 0 + 1 + + + choices_62 + 0 + 1 + + + choices_63 + 0 + 1 + + + choices_64 + 0 + 1 + + + choices_65 + 0 + 1 + + + choices_66 + 0 + 1 + + + choices_67 + 0 + 1 + + + choices_68 + 0 + 1 + + + choices_69 + 0 + 1 + + + choices_70 + 1 + 0 + + + choices_71 + 0 + 1 + + + choices_72 + 0 + 1 + + + choices_73 + 0 + 1 + + + choices_74 + 0 + 1 + + + choices_75 + 0 + 1 + + + choices_76 + 0 + 1 + + + choices_77 + 0 + 1 + + + choices_78 + 0 + 1 + + + choices_79 + 0 + 1 + + + choices_80 + 0 + 1 + + + choices_81 + 0 + 1 + + + choices_82 + 0 + 1 + + + choices_83 + 0 + 1 + + + choices_84 + 0 + 1 + + + choices_85 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + + + choices_86 + 0 + 1 + + + choices_87 + 32 + 64 + 128 + 256 + + + choices_88 + 0 + 1 + + + choices_89 + 12 + + + choices_90 + 0 + 1 + + + choices_91 + <Select> + DISABLED + CPU0 DBG_REQ + CPU1 DBG_REQ + BOTH + + + choices_92 + <Select> + DISABLED + CPU0 DBG_REQ + CPU1 DBG_REQ + BOTH + + + choices_93 + <Select> + DISABLED + CPU0 DBG_REQ + CPU1 DBG_REQ + BOTH + + + choices_94 + <Select> + DISABLED + CPU0 DBG_REQ + CPU1 DBG_REQ + BOTH + + + choices_95 + <Select> + DISABLED + CPU0 DBG_ACK + CPU1 DBG_ACK + BOTH + + + choices_96 + <Select> + DISABLED + CPU0 DBG_ACK + CPU1 DBG_ACK + BOTH + + + choices_97 + <Select> + DISABLED + CPU0 DBG_ACK + CPU1 DBG_ACK + BOTH + + + choices_98 + <Select> + DISABLED + CPU0 DBG_ACK + CPU1 DBG_ACK + BOTH + + + choices_99 + 0 + 1 + + + choices_100 + 0 + 1 + + + choices_101 + 0 + 1 + + + choices_102 + 0 + 1 + + + choices_103 + 0 + 1 + + + choices_104 + 0 + 1 + + + choices_105 + 0 + 1 + + + choices_106 + 0 + 1 + + + choices_107 + 0 + 1 + + + choices_108 + 0 + 1 + + + choices_109 + 0 + 1 + + + choices_110 + 0 + 1 + + + choices_111 + 110 + 300 + 1200 + 2400 + 4800 + 9600 + 19200 + 38400 + 57600 + 115200 + 128000 + 230400 + 460800 + 921600 + + + choices_112 + 110 + 300 + 1200 + 2400 + 4800 + 9600 + 19200 + 38400 + 57600 + 115200 + 128000 + 230400 + 460800 + 921600 + + + choices_113 + 0 + 1 + + + choices_114 + 12 + + + choices_115 + 0 + 1 + + + choices_116 + 0 + 1 + + + choices_117 + 0 + 1 + + + choices_118 + 6 + 12 + + + choices_119 + 12 + + + choices_120 + 0 + 1 + + + choices_121 + 0 + 1 + + + choices_122 + 0 + 1 + + + choices_123 + 6 + 12 + + + choices_124 + 6 + + + choices_125 + 6 + + + choices_126 + 0 + 1 + + + choices_127 + 0 + 1 + + + choices_128 + 6 + + + choices_129 + 32 + 64 + + + choices_130 + 6 + + + choices_131 + 32 + 64 + + + choices_132 + 6 + + + choices_133 + 32 + 64 + + + choices_134 + 6 + + + choices_135 + 32 + 64 + + + choices_136 + 0 + 1 + + + choices_137 + 0 + 1 + + + choices_138 + 0 + 1 + + + choices_139 + 0 + 1 + + + choices_140 + 0 + 1 + + + choices_141 + 0 + 1 + + + choices_142 + 0 + 1 + + + choices_143 + 0 + 1 + + + choices_144 + 0 + 1 + + + choices_145 + 0 + 1 + + + choices_146 + 0 + 1 + + + choices_147 + 0 + 1 + + + choices_148 + 0 + 1 + + + choices_149 + 0 + 1 + + + choices_150 + 0 + 1 + + + choices_151 + 0 + 1 + + + choices_152 + 0 + 1 + + + choices_153 + 0 + 1 + + + choices_154 + 0 + 1 + + + choices_155 + 0 + 1 + + + choices_156 + 0 + 1 + + + choices_157 + 0 + 1 + + + choices_158 + 0 + 1 + + + choices_159 + 0 + 1 + + + choices_160 + 0 + 1 + + + choices_161 + 32 + 16 + + + choices_162 + 4 + 2 + + + choices_163 + 4 + 2 + + + choices_164 + 54 + 32 + + + choices_165 + 0 + 1 + + + choices_166 + 0 + 1 + + + choices_167 + 0 + 1 + + + choices_168 + 0 + 1 + + + choices_169 + 0 + 1 + + + choices_170 + 0 + 1 + + + choices_171 + 0 + 1 + + + choices_172 + 0 + 1 + + + choices_173 + 0 + 1 + + + choices_174 + 0 + 1 + + + choices_175 + 0 + 1 + + + choices_176 + 0 + 1 + + + choices_177 + 0 + 1 + + + choices_178 + 0 + 1 + + + choices_179 + 0 + 1 + + + choices_180 + 0 + 1 + + + choices_181 + 0 + 1 + + + choices_182 + 0 + 1 + + + choices_183 + 0 + 1 + + + choices_184 + 0 + 1 + + + choices_185 + 0 + 1 + + + choices_186 + 0 + 1 + + + choices_187 + 0 + 1 + + + choices_188 + 0 + 1 + + + choices_189 + 0 + 1 + + + choices_190 + 0 + 1 + + + choices_191 + 0 + 1 + + + choices_192 + 0 + 1 + + + choices_193 + 0 + 1 + + + choices_194 + 0 + 1 + + + choices_195 + 0 + 1 + + + choices_196 + 0 + 1 + + + choices_197 + 0 + 1 + + + choices_198 + 0 + 1 + + + choices_199 + 0 + 1 + + + choices_200 + 0 + 1 + + + choices_201 + 0 + 1 + + + choices_202 + 0 + 1 + + + choices_203 + 0 + 1 + + + choices_204 + 0 + 1 + + + choices_205 + DIRECT + REVERSE + + + choices_206 + 0 + 1 + + + choices_207 + 0 + 1 + + + choices_208 + 0 + 1 + + + choices_209 + 0 + 1 + + + choices_210 + 1 + 2 + 3 + + + choices_211 + LVCMOS 3.3V + LVCMOS 2.5V + HSTL 1.8V + LVCMOS 1.8V + + + choices_212 + LVCMOS 1.8V + LVCMOS 2.5V + LVCMOS 3.3V + HSTL 1.8V + + + choices_213 + 0 + 1 + + + choices_214 + 0 + 1 + + + choices_215 + LPDDR 2 + DDR 2 + DDR 3 + DDR 3 (Low Voltage) + + + choices_216 + Disabled + Enabled + + + choices_217 + 16 Bit + 32 Bit + + + choices_218 + 4 + 8 + + + choices_219 + Normal (0-85) + High (95 Max) + + + choices_220 + MT41J128M8 JP-125 + MT41J128M8 JP-15E + MT41J64M16 JT-125G + MT41J64M16 JT-15E + MT41J256M8 DA-107 + MT41K128M16 JT-125 + MT41J256M8 HX-125 + MT41J256M8 HX-15E + MT41J256M8 HX-187E + MT41J128M16 HA-107G + MT41J128M16 HA-125 + MT41J128M16 HA-15E + MT41J128M16 HA-187E + MT41J512M8 RA-15E + MT41K128M16 HA-15E + MT41K256M16 RE-125 + MT41K256M16 RE-15E + MT41K256M8 DA-125 + MT41K256M8 DA-15E + MT41K256M8 HX-15E + MT41J256M16 RE-125 + Custom + + + choices_221 + 8 Bits + 16 Bits + 32 Bits + + + choices_222 + 128 MBits + 256 MBits + 512 MBits + 1024 MBits + 2048 MBits + 4096 MBits + 8192 MBits + + + choices_223 + DDR3_800D + DDR3_800E + DDR3_1066E + DDR3_1066F + DDR3_1066G + DDR3_1333F + DDR3_1333G + DDR3_1333H + DDR3_1333J + DDR3_1600G + DDR3_1600H + DDR3_1600J + DDR3_1600K + + + choices_224 + 0 + 1 + + + choices_225 + 0 + 1 + + + choices_226 + 0 + 1 + + + choices_227 + 0 + 1 + + + choices_228 + 0 + 1 + + + choices_229 + <Select> + Low + Medium + High + + + choices_230 + <Select> + Low + Medium + High + + + choices_231 + <Select> + Low + Medium + High + + + choices_232 + <Select> + Low + Medium + High + + + choices_233 + <Select> + Low + Medium + High + + + choices_234 + <Select> + Low + Medium + High + + + choices_235 + <Select> + Low + Medium + High + + + choices_236 + <Select> + Low + Medium + High + + + choices_237 + 0 + 1 + + + choices_238 + 0 + 1 + + + choices_239 + 0 + 1 + + + choices_240 + 0 + 1 + + + choices_241 + HPR(0)/LPR(32) + HPR(8)/LPR(24) + HPR(16)/LPR(16) + HPR(24)/LPR(8) + HPR(32)/LPR(0) + + + choices_242 + 0 + 1 + + + choices_243 + <Select> + MIO 0 2.. 14 + + + choices_244 + 0 + 1 + + + choices_245 + <Select> + MIO 16 .. 23 + + + choices_246 + 0 + 1 + + + choices_247 + <Select> + MIO 3 .. 39 + + + choices_248 + 0 + 1 + + + choices_249 + <Select> + MIO 1 + + + choices_250 + 0 + 1 + + + choices_251 + <Select> + MIO 0 + + + choices_252 + 0 + 1 + + + choices_253 + <Select> + MIO 0 + + + choices_254 + 0 + 1 + + + choices_255 + <Select> + MIO 1 + + + choices_256 + 0 + 1 + + + choices_257 + <Select> + MIO 1 + + + choices_258 + 0 + 1 + + + choices_259 + <Select> + EMIO + + + choices_260 + 0 + 1 + + + choices_261 + MIO 1 .. 6 + + + choices_262 + 0 + 1 + + + choices_263 + MIO 1 .. 6 + + + choices_264 + 0 + 1 + + + choices_265 + <Select> + MIO 0 + + + choices_266 + 0 + 1 + + + choices_267 + <Select> + MIO 0 9 .. 13 + + + choices_268 + 0 + 1 + + + choices_269 + MIO 8 + + + choices_270 + 0xFCFFFFFF + + + choices_271 + 0 + 1 + + + choices_272 + EMIO + MIO 16 .. 27 + + + choices_273 + 0 + 1 + + + choices_274 + MIO 52 .. 53 + + + choices_275 + 0 + 1 + + + choices_276 + <Select> + Share reset pin + + + choices_277 + 0 + 1 + + + choices_278 + <Select> + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_279 + 0 + 1 + + + choices_280 + <Select> + EMIO + MIO 28 .. 39 + + + choices_281 + 0 + 1 + + + choices_282 + <Select> + EMIO + MIO 52 .. 53 + + + choices_283 + 0 + 1 + + + choices_284 + <Select> + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_285 + 0 + 1 + + + choices_286 + EMIO + MIO 16 .. 21 + MIO 28 .. 33 + MIO 40 .. 45 + + + choices_287 + 0 + 1 + + + choices_288 + EMIO + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_289 + 0 + 1 + + + choices_290 + EMIO + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_291 + 0 + 1 + + + choices_292 + <Select> + MIO 0 + MIO 2 + MIO 4 + MIO 6 + MIO 8 + MIO 10 + MIO 12 + MIO 14 + MIO 16 + MIO 18 + MIO 20 + MIO 22 + MIO 24 + MIO 26 + MIO 28 + MIO 30 + MIO 32 + MIO 34 + MIO 36 + MIO 38 + MIO 40 + MIO 42 + MIO 44 + MIO 46 + MIO 48 + MIO 50 + MIO 52 + + + choices_293 + 0 + 1 + + + choices_294 + <Select> + EMIO + MIO 10 .. 15 + MIO 22 .. 27 + MIO 34 .. 39 + MIO 46 .. 51 + + + choices_295 + 0 + 1 + + + choices_296 + <Select> + EMIO + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_297 + 0 + 1 + + + choices_298 + <Select> + EMIO + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_299 + 0 + 1 + + + choices_300 + <Select> + MIO 1 + MIO 3 + MIO 5 + MIO 7 + MIO 9 + MIO 11 + MIO 13 + MIO 15 + MIO 17 + MIO 19 + MIO 21 + MIO 23 + MIO 25 + MIO 27 + MIO 29 + MIO 31 + MIO 33 + MIO 35 + MIO 37 + MIO 39 + MIO 41 + MIO 43 + MIO 45 + MIO 47 + MIO 49 + MIO 51 + MIO 53 + + + choices_301 + 0 + 1 + + + choices_302 + <Select> + EMIO + MIO 10 .. 11 + MIO 14 .. 15 + MIO 18 .. 19 + MIO 22 .. 23 + MIO 26 .. 27 + MIO 30 .. 31 + MIO 34 .. 35 + MIO 38 .. 39 + MIO 42 .. 43 + MIO 46 .. 47 + MIO 50 .. 51 + + + choices_303 + 0 + 1 + + + choices_304 + <Select> + EMIO + + + choices_305 + 0 + 1 + + + choices_306 + EMIO + MIO 8 .. 9 + MIO 12 .. 13 + MIO 16 .. 17 + MIO 20 .. 21 + MIO 24 .. 25 + MIO 28 .. 29 + MIO 32 .. 33 + MIO 36 .. 37 + MIO 40 .. 41 + MIO 44 .. 45 + MIO 48 .. 49 + MIO 52 .. 53 + + + choices_307 + 0 + 1 + + + choices_308 + <Select> + EMIO + + + choices_309 + 0 + 1 + + + choices_310 + <Select> + EMIO + MIO 16 .. 21 + MIO 28 .. 33 + MIO 40 .. 45 + + + choices_311 + 0 + 1 + + + choices_312 + <Select> + EMIO + MIO 18 + MIO 30 + MIO 42 + + + choices_313 + 0 + 1 + + + choices_314 + <Select> + EMIO + MIO 19 + MIO 31 + MIO 43 + + + choices_315 + 0 + 1 + + + choices_316 + <Select> + EMIO + MIO 20 + MIO 32 + MIO 44 + + + choices_317 + 0 + 1 + + + choices_318 + <Select> + EMIO + MIO 10 .. 15 + MIO 22 .. 27 + MIO 34 .. 39 + MIO 46 .. 51 + + + choices_319 + 0 + 1 + + + choices_320 + <Select> + EMIO + MIO 13 + MIO 25 + MIO 37 + MIO 49 + + + choices_321 + 0 + 1 + + + choices_322 + <Select> + EMIO + MIO 14 + MIO 26 + MIO 38 + MIO 50 + + + choices_323 + 0 + 1 + + + choices_324 + <Select> + EMIO + MIO 15 + MIO 27 + MIO 39 + MIO 51 + + + choices_325 + 0 + 1 + + + choices_326 + EMIO + MIO 10 .. 11 + MIO 14 .. 15 + MIO 18 .. 19 + MIO 22 .. 23 + MIO 26 .. 27 + MIO 30 .. 31 + MIO 34 .. 35 + MIO 38 .. 39 + MIO 42 .. 43 + MIO 46 .. 47 + MIO 50 .. 51 + + + choices_327 + 0 + 1 + + + choices_328 + <Select> + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_329 + 0 + 1 + + + choices_330 + <Select> + EMIO + MIO 8 .. 9 + MIO 12 .. 13 + MIO 16 .. 17 + MIO 20 .. 21 + MIO 24 .. 25 + MIO 28 .. 29 + MIO 32 .. 33 + MIO 36 .. 37 + MIO 40 .. 41 + MIO 44 .. 45 + MIO 48 .. 49 + MIO 52 .. 53 + + + choices_331 + 0 + 1 + + + choices_332 + <Select> + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_333 + 0 + 1 + + + choices_334 + <Select> + EMIO + MIO 12 .. 13 + MIO 24 .. 25 + + + choices_335 + 0 + 1 + + + choices_336 + <Select> + EMIO + MIO 14 .. 15 + MIO 26 .. 27 + + + choices_337 + 0 + 1 + + + choices_338 + <Select> + EMIO + MIO 10 .. 11 + MIO 22 .. 23 + + + choices_339 + 0 + 1 + + + choices_340 + <Select> + EMIO + MIO 16 .. 19 + + + choices_341 + 0 + 1 + + + choices_342 + <Select> + EMIO + MIO 2 .. 9 + + + choices_343 + 0 + 1 + + + choices_344 + <Select> + EMIO + + + choices_345 + 2 + 4 + 8 + 16 + 32 + + + choices_346 + 0 + 1 + + + choices_347 + <Select> + EMIO + MIO 14 .. 15 + MIO 26 .. 27 + MIO 38 .. 39 + MIO 50 .. 51 + MIO 52 .. 53 + + + choices_348 + 0 + 1 + + + choices_349 + <Select> + EMIO + MIO 18 .. 19 + MIO 30 .. 31 + MIO 42 .. 43 + + + choices_350 + 0 + 1 + + + choices_351 + <Select> + EMIO + MIO 16 .. 17 + MIO 28 .. 29 + MIO 40 .. 41 + + + choices_352 + 0 + 1 + + + choices_353 + <Select> + EMIO + MIO 10 .. 13 + MIO 22 .. 25 + MIO 34 .. 37 + MIO 46 .. 49 + + + choices_354 + 0 + 1 + + + choices_355 + MIO 28 .. 39 + + + choices_356 + 0 + 1 + + + choices_357 + Share reset pin + + + choices_358 + 0 + 1 + + + choices_359 + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_360 + 0 + 1 + + + choices_361 + <Select> + MIO 40 .. 51 + + + choices_362 + 0 + 1 + + + choices_363 + <Select> + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_364 + 0 + 1 + + + choices_365 + EMIO + MIO 10 .. 11 + MIO 14 .. 15 + MIO 18 .. 19 + MIO 22 .. 23 + MIO 26 .. 27 + MIO 30 .. 31 + MIO 34 .. 35 + MIO 38 .. 39 + MIO 42 .. 43 + MIO 46 .. 47 + MIO 50 .. 51 + + + choices_366 + 0 + 1 + + + choices_367 + EMIO + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_368 + 0 + 1 + + + choices_369 + <Select> + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_370 + 0 + 1 + + + choices_371 + EMIO + MIO 12 .. 13 + MIO 16 .. 17 + MIO 20 .. 21 + MIO 24 .. 25 + MIO 28 .. 29 + MIO 32 .. 33 + MIO 36 .. 37 + MIO 40 .. 41 + MIO 44 .. 45 + MIO 48 .. 49 + MIO 52 .. 53 + + + choices_372 + 0 + 1 + + + choices_373 + <Select> + EMIO + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_374 + 0 + 1 + + + choices_375 + <Select> + Share reset pin + Separate reset pins + + + choices_376 + 0 + 1 + + + choices_377 + <Select> + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choices_378 + 0 + 1 + + + choices_379 + 0 + 1 + + + choices_380 + MIO + + + choices_381 + 0 + 1 + + + choices_382 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + 30 + 31 + 32 + 33 + 34 + 35 + 36 + 37 + 38 + 39 + 40 + 41 + 42 + 43 + 44 + 45 + 46 + 47 + 48 + 49 + 50 + 51 + 52 + 53 + 54 + 55 + 56 + 57 + 58 + 59 + 60 + 61 + 62 + 63 + 64 + + + choices_383 + 6:2:1 + 4:2:1 + + + choices_384 + 1000 Mbps + 100 Mbps + 10 Mbps + + + choices_385 + 1000 Mbps + 100 Mbps + 10 Mbps + + + choices_386 + ARM PLL + DDR PLL + IO PLL + + + choices_387 + DDR PLL + + + choices_388 + ARM PLL + DDR PLL + IO PLL + + + choices_389 + ARM PLL + DDR PLL + IO PLL + + + choices_390 + ARM PLL + DDR PLL + IO PLL + + + choices_391 + ARM PLL + DDR PLL + IO PLL + + + choices_392 + ARM PLL + DDR PLL + IO PLL + + + choices_393 + ARM PLL + DDR PLL + IO PLL + + + choices_394 + ARM PLL + DDR PLL + IO PLL + + + choices_395 + ARM PLL + DDR PLL + IO PLL + + + choices_396 + ARM PLL + DDR PLL + IO PLL + + + choices_397 + ARM PLL + DDR PLL + IO PLL + + + choices_398 + ARM PLL + IO PLL + DDR PLL + External + + + choices_399 + ARM PLL + DDR PLL + External + IO PLL + + + choices_400 + External + + + choices_401 + External + + + choices_402 + ARM PLL + DDR PLL + IO PLL + External + + + choices_403 + CPU_1X + External + + + choices_404 + CPU_1X + External + + + choices_405 + CPU_1X + External + + + choices_406 + CPU_1X + External + + + choices_407 + CPU_1X + External + + + choices_408 + CPU_1X + External + + + choices_409 + CPU_1X + External + + + choices_410 + DDR PLL + + + choices_411 + DDR PLL + ARM PLL + IO PLL + + + choices_412 + Active High + Active Low + + + choices_413 + Active High + Active Low + + + choices_414 + Active High + Active Low + + + choices_415 + disabled + enabled + + + choices_416 + LVCMOS 3.3V + + + choices_417 + in + out + inout + + + choices_418 + fast + slow + + + choices_419 + disabled + enabled + + + choices_420 + LVCMOS 3.3V + + + choices_421 + in + out + inout + + + choices_422 + fast + slow + + + choices_423 + disabled + enabled + + + choices_424 + LVCMOS 3.3V + + + choices_425 + in + out + inout + + + choices_426 + fast + slow + + + choices_427 + disabled + enabled + + + choices_428 + LVCMOS 3.3V + + + choices_429 + in + out + inout + + + choices_430 + fast + slow + + + choices_431 + disabled + enabled + + + choices_432 + LVCMOS 3.3V + + + choices_433 + in + out + inout + + + choices_434 + fast + slow + + + choices_435 + disabled + enabled + + + choices_436 + LVCMOS 3.3V + + + choices_437 + in + out + inout + + + choices_438 + fast + slow + + + choices_439 + disabled + enabled + + + choices_440 + LVCMOS 3.3V + + + choices_441 + in + out + inout + + + choices_442 + fast + slow + + + choices_443 + disabled + enabled + + + choices_444 + LVCMOS 3.3V + + + choices_445 + in + out + inout + + + choices_446 + fast + slow + + + choices_447 + disabled + enabled + + + choices_448 + LVCMOS 3.3V + + + choices_449 + in + out + inout + + + choices_450 + fast + slow + + + choices_451 + disabled + enabled + + + choices_452 + LVCMOS 3.3V + + + choices_453 + in + out + inout + + + choices_454 + fast + slow + + + choices_455 + disabled + enabled + + + choices_456 + LVCMOS 3.3V + + + choices_457 + in + out + inout + + + choices_458 + fast + slow + + + choices_459 + disabled + enabled + + + choices_460 + LVCMOS 3.3V + + + choices_461 + in + out + inout + + + choices_462 + fast + slow + + + choices_463 + disabled + enabled + + + choices_464 + LVCMOS 3.3V + + + choices_465 + in + out + inout + + + choices_466 + fast + slow + + + choices_467 + disabled + enabled + + + choices_468 + LVCMOS 3.3V + + + choices_469 + in + out + inout + + + choices_470 + fast + slow + + + choices_471 + disabled + enabled + + + choices_472 + LVCMOS 3.3V + + + choices_473 + in + out + inout + + + choices_474 + fast + slow + + + choices_475 + disabled + enabled + + + choices_476 + LVCMOS 3.3V + + + choices_477 + in + out + inout + + + choices_478 + fast + slow + + + choices_479 + disabled + enabled + + + choices_480 + LVCMOS 1.8V + HSTL 1.8V + + + choices_481 + in + out + inout + + + choices_482 + fast + slow + + + choices_483 + disabled + enabled + + + choices_484 + LVCMOS 1.8V + HSTL 1.8V + + + choices_485 + in + out + inout + + + choices_486 + fast + slow + + + choices_487 + disabled + enabled + + + choices_488 + LVCMOS 1.8V + HSTL 1.8V + + + choices_489 + in + out + inout + + + choices_490 + fast + slow + + + choices_491 + disabled + enabled + + + choices_492 + LVCMOS 1.8V + HSTL 1.8V + + + choices_493 + in + out + inout + + + choices_494 + fast + slow + + + choices_495 + disabled + enabled + + + choices_496 + LVCMOS 1.8V + HSTL 1.8V + + + choices_497 + in + out + inout + + + choices_498 + fast + slow + + + choices_499 + disabled + enabled + + + choices_500 + LVCMOS 1.8V + HSTL 1.8V + + + choices_501 + in + out + inout + + + choices_502 + fast + slow + + + choices_503 + disabled + enabled + + + choices_504 + LVCMOS 1.8V + HSTL 1.8V + + + choices_505 + in + out + inout + + + choices_506 + fast + slow + + + choices_507 + disabled + enabled + + + choices_508 + LVCMOS 1.8V + HSTL 1.8V + + + choices_509 + in + out + inout + + + choices_510 + fast + slow + + + choices_511 + disabled + enabled + + + choices_512 + LVCMOS 1.8V + HSTL 1.8V + + + choices_513 + in + out + inout + + + choices_514 + fast + slow + + + choices_515 + disabled + enabled + + + choices_516 + LVCMOS 1.8V + HSTL 1.8V + + + choices_517 + in + out + inout + + + choices_518 + fast + slow + + + choices_519 + disabled + enabled + + + choices_520 + LVCMOS 1.8V + HSTL 1.8V + + + choices_521 + in + out + inout + + + choices_522 + fast + slow + + + choices_523 + disabled + enabled + + + choices_524 + LVCMOS 1.8V + HSTL 1.8V + + + choices_525 + in + out + inout + + + choices_526 + fast + slow + + + choices_527 + disabled + enabled + + + choices_528 + LVCMOS 1.8V + HSTL 1.8V + + + choices_529 + in + out + inout + + + choices_530 + fast + slow + + + choices_531 + disabled + enabled + + + choices_532 + LVCMOS 1.8V + HSTL 1.8V + + + choices_533 + in + out + inout + + + choices_534 + fast + slow + + + choices_535 + disabled + enabled + + + choices_536 + LVCMOS 1.8V + HSTL 1.8V + + + choices_537 + in + out + inout + + + choices_538 + fast + slow + + + choices_539 + disabled + enabled + + + choices_540 + LVCMOS 1.8V + HSTL 1.8V + + + choices_541 + in + out + inout + + + choices_542 + fast + slow + + + choices_543 + disabled + enabled + + + choices_544 + LVCMOS 1.8V + HSTL 1.8V + + + choices_545 + in + out + inout + + + choices_546 + fast + slow + + + choices_547 + disabled + enabled + + + choices_548 + LVCMOS 1.8V + HSTL 1.8V + + + choices_549 + in + out + inout + + + choices_550 + fast + slow + + + choices_551 + disabled + enabled + + + choices_552 + LVCMOS 1.8V + HSTL 1.8V + + + choices_553 + in + out + inout + + + choices_554 + fast + slow + + + choices_555 + disabled + enabled + + + choices_556 + LVCMOS 1.8V + HSTL 1.8V + + + choices_557 + in + out + inout + + + choices_558 + fast + slow + + + choices_559 + disabled + enabled + + + choices_560 + LVCMOS 1.8V + HSTL 1.8V + + + choices_561 + in + out + inout + + + choices_562 + fast + slow + + + choices_563 + disabled + enabled + + + choices_564 + LVCMOS 1.8V + HSTL 1.8V + + + choices_565 + in + out + inout + + + choices_566 + fast + slow + + + choices_567 + disabled + enabled + + + choices_568 + LVCMOS 1.8V + HSTL 1.8V + + + choices_569 + in + out + inout + + + choices_570 + fast + slow + + + choices_571 + disabled + enabled + + + choices_572 + LVCMOS 1.8V + HSTL 1.8V + + + choices_573 + in + out + inout + + + choices_574 + fast + slow + + + choices_575 + disabled + enabled + + + choices_576 + LVCMOS 1.8V + HSTL 1.8V + + + choices_577 + in + out + inout + + + choices_578 + fast + slow + + + choices_579 + disabled + enabled + + + choices_580 + LVCMOS 1.8V + HSTL 1.8V + + + choices_581 + in + out + inout + + + choices_582 + fast + slow + + + choices_583 + disabled + enabled + + + choices_584 + LVCMOS 1.8V + HSTL 1.8V + + + choices_585 + in + out + inout + + + choices_586 + fast + slow + + + choices_587 + disabled + enabled + + + choices_588 + LVCMOS 1.8V + HSTL 1.8V + + + choices_589 + in + out + inout + + + choices_590 + fast + slow + + + choices_591 + disabled + enabled + + + choices_592 + LVCMOS 1.8V + HSTL 1.8V + + + choices_593 + in + out + inout + + + choices_594 + fast + slow + + + choices_595 + disabled + enabled + + + choices_596 + LVCMOS 1.8V + HSTL 1.8V + + + choices_597 + in + out + inout + + + choices_598 + fast + slow + + + choices_599 + disabled + enabled + + + choices_600 + LVCMOS 1.8V + HSTL 1.8V + + + choices_601 + in + out + inout + + + choices_602 + fast + slow + + + choices_603 + disabled + enabled + + + choices_604 + LVCMOS 1.8V + HSTL 1.8V + + + choices_605 + in + out + inout + + + choices_606 + fast + slow + + + choices_607 + disabled + enabled + + + choices_608 + LVCMOS 1.8V + HSTL 1.8V + + + choices_609 + in + out + inout + + + choices_610 + fast + slow + + + choices_611 + disabled + enabled + + + choices_612 + LVCMOS 1.8V + HSTL 1.8V + + + choices_613 + in + out + inout + + + choices_614 + fast + slow + + + choices_615 + disabled + enabled + + + choices_616 + LVCMOS 1.8V + HSTL 1.8V + + + choices_617 + in + out + inout + + + choices_618 + fast + slow + + + choices_619 + disabled + enabled + + + choices_620 + LVCMOS 1.8V + HSTL 1.8V + + + choices_621 + in + out + inout + + + choices_622 + fast + slow + + + choices_623 + disabled + enabled + + + choices_624 + LVCMOS 1.8V + HSTL 1.8V + + + choices_625 + in + out + inout + + + choices_626 + fast + slow + + + choices_627 + disabled + enabled + + + choices_628 + LVCMOS 1.8V + HSTL 1.8V + + + choices_629 + in + out + inout + + + choices_630 + fast + slow + + + choices_631 + None + Default + ZC702 + ZC706 + ZedBoard + + + choices_632 + PRODUCTION + + + choices_633 + 0 + 1 + + + choices_634 + 0 + 1 + + + choices_635 + 0 + 1 + + + choices_636 + 0 + 1 + + + choices_637 + clg484 + clg225 + clg400 + ffg676 + fbg676 + fbg484 + ffg900 + cl400 + cl484 + rf676 + fb484 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + z_turn_processing_system7_0_0.veo + verilogTemplate + + + + xilinx_anylanguagesynthesis_view_fileset + + z_turn_processing_system7_0_0.xdc + xdc + + processing_order + early + + + + ps7_init.c + cSource + USED_IN_hw_handoff + + + ps7_init.h + cSource + USED_IN_hw_handoff + + + ps7_init_gpl.c + cSource + USED_IN_hw_handoff + + + ps7_init_gpl.h + cSource + USED_IN_hw_handoff + + + ps7_init.tcl + tclSource + USED_IN_hw_handoff + + + ps7_init.html + html + USED_IN_hw_handoff + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_aw_atc.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_b_atc.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_w_atc.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_atc.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_trace_buffer.v + verilogSource + + + processing_system7.txt + text + + + hdl/verilog/processing_system7_v5_5_processing_system7.v + verilogSource + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/z_turn_processing_system7_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_processing_system7_bfm_2_0__ref_view_fileset + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_local_params.v + verilogSource + true + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_wr.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_rd.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_wr_4.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_rd_4.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ssw_hp.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_sparse_mem.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_params.v + verilogSource + true + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_init.v + verilogSource + true + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_map.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ocm_mem.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_fmsw_gp.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_regc.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ocmc.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_interconnect_model.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_gen_reset.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_gen_clock.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ddrc.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_slave.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_master.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_afi_slave.v + verilogSource + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_apis.v + verilogSource + true + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_unused_ports.v + verilogSource + true + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_gp.v + verilogSource + true + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_acp.v + verilogSource + true + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_hp.v + verilogSource + true + + + ../../../../ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v + verilogSource + + + + + + + + + + + xilinx_anylanguagesimulationwrapper_view_fileset + + sim/z_turn_processing_system7_0_0.v + verilogSource + + + + xilinx_miscfiles_view_fileset + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/fixedio.xml + xml + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/fixedio_rtl.xml + xml + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/jtag.xml + xml + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/jtag_rtl.xml + xml + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hpstatusctrl.xml + xml + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hpstatusctrl_rtl.xml + xml + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/usbctrl.xml + xml + + + ../../../../ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/usbctrl_rtl.xml + xml + + + + xilinx_versioninformation_view_fileset + + doc/processing_system7_v5_5_changelog.txt + text + + + + + + CPU0_A9 + + + + is_visible + FALSE + + + processor_type + ARM + + + + + CPU1_A9 + + + + is_visible + FALSE + + + processor_type + ARM + + + + + Arm dual core SOC with Zynq fpga + + + PCW_DDR_RAM_BASEADDR + PCW DDR RAM BASEADDR + 0x00100000 + + + + optional + true + + + + + + PCW_DDR_RAM_HIGHADDR + PCW DDR RAM HIGHADDR + 0x3FFFFFFF + + + + optional + true + + + + + + PCW_UART0_BASEADDR + PCW UART0 BASEADDR + 0xE0000000 + + + + optional + false + + + + + + PCW_UART0_HIGHADDR + PCW UART0 HIGHADDR + 0xE0000FFF + + + + optional + false + + + + + + PCW_UART1_BASEADDR + PCW UART1 BASEADDR + 0xE0001000 + + + + optional + true + + + + + + PCW_UART1_HIGHADDR + PCW UART1 HIGHADDR + 0xE0001FFF + + + + optional + true + + + + + + PCW_I2C0_BASEADDR + PCW I2C0 BASEADDR + 0xE0004000 + + + + optional + true + + + + + + PCW_I2C0_HIGHADDR + PCW I2C0 HIGHADDR + 0xE0004FFF + + + + optional + true + + + + + + PCW_I2C1_BASEADDR + PCW I2C1 BASEADDR + 0xE0005000 + + + + optional + true + + + + + + PCW_I2C1_HIGHADDR + PCW I2C1 HIGHADDR + 0xE0005FFF + + + + optional + true + + + + + + PCW_SPI0_BASEADDR + PCW SPI0 BASEADDR + 0xE0006000 + + + + optional + false + + + + + + PCW_SPI0_HIGHADDR + PCW SPI0 HIGHADDR + 0xE0006FFF + + + + optional + false + + + + + + PCW_SPI1_BASEADDR + PCW SPI1 BASEADDR + 0xE0007000 + + + + optional + false + + + + + + PCW_SPI1_HIGHADDR + PCW SPI1 HIGHADDR + 0xE0007FFF + + + + optional + false + + + + + + PCW_CAN0_BASEADDR + PCW CAN0 BASEADDR + 0xE0008000 + + + + optional + true + + + + + + PCW_CAN0_HIGHADDR + PCW CAN0 HIGHADDR + 0xE0008FFF + + + + optional + true + + + + + + PCW_CAN1_BASEADDR + PCW CAN1 BASEADDR + 0xE0009000 + + + + optional + false + + + + + + PCW_CAN1_HIGHADDR + PCW CAN1 HIGHADDR + 0xE0009FFF + + + + optional + false + + + + + + PCW_GPIO_BASEADDR + PCW GPIO BASEADDR + 0xE000A000 + + + + optional + true + + + + + + PCW_GPIO_HIGHADDR + PCW GPIO HIGHADDR + 0xE000AFFF + + + + optional + true + + + + + + PCW_ENET0_BASEADDR + PCW ENET0 BASEADDR + 0xE000B000 + + + + optional + true + + + + + + PCW_ENET0_HIGHADDR + PCW ENET0 HIGHADDR + 0xE000BFFF + + + + optional + true + + + + + + PCW_ENET1_BASEADDR + PCW ENET1 BASEADDR + 0xE000C000 + + + + optional + false + + + + + + PCW_ENET1_HIGHADDR + PCW ENET1 HIGHADDR + 0xE000CFFF + + + + optional + false + + + + + + PCW_SDIO0_BASEADDR + PCW SDIO0 BASEADDR + 0xE0100000 + + + + optional + true + + + + + + PCW_SDIO0_HIGHADDR + PCW SDIO0 HIGHADDR + 0xE0100FFF + + + + optional + true + + + + + + PCW_SDIO1_BASEADDR + PCW SDIO1 BASEADDR + 0xE0101000 + + + + optional + false + + + + + + PCW_SDIO1_HIGHADDR + PCW SDIO1 HIGHADDR + 0xE0101FFF + + + + optional + false + + + + + + PCW_USB0_BASEADDR + PCW USB0 BASEADDR + 0xE0102000 + + + + optional + true + + + + + + PCW_USB0_HIGHADDR + PCW USB0 HIGHADDR + 0xE0102fff + + + + optional + true + + + + + + PCW_USB1_BASEADDR + PCW USB1 BASEADDR + 0xE0103000 + + + + optional + false + + + + + + PCW_USB1_HIGHADDR + PCW USB1 HIGHADDR + 0xE0103fff + + + + optional + false + + + + + + PCW_TTC0_BASEADDR + PCW TTC0 BASEADDR + 0xE0104000 + + + + optional + false + + + + + + PCW_TTC0_HIGHADDR + PCW TTC0 HIGHADDR + 0xE0104fff + + + + optional + false + + + + + + PCW_TTC1_BASEADDR + PCW TTC1 BASEADDR + 0xE0105000 + + + + optional + false + + + + + + PCW_TTC1_HIGHADDR + PCW TTC1 HIGHADDR + 0xE0105fff + + + + optional + false + + + + + + PCW_FCLK_CLK0_BUF + PCW FCLK CLK0 BUF + true + + + + optional + true + + + + + + PCW_FCLK_CLK1_BUF + PCW FCLK CLK1 BUF + true + + + + optional + true + + + + + + PCW_FCLK_CLK2_BUF + PCW FCLK CLK2 BUF + true + + + + optional + true + + + + + + PCW_FCLK_CLK3_BUF + PCW FCLK CLK3 BUF + true + + + + optional + true + + + + + + PCW_UIPARAM_DDR_FREQ_MHZ + PCW UIPARAM DDR FREQ MHZ + 533.333333 + + + + true + + + + + + PCW_UIPARAM_DDR_BANK_ADDR_COUNT + PCW UIPARAM DDR BANK ADDR COUNT + 3 + + + + false + + + + + + PCW_UIPARAM_DDR_ROW_ADDR_COUNT + PCW UIPARAM DDR ROW ADDR COUNT + 15 + + + + false + + + + + + PCW_UIPARAM_DDR_COL_ADDR_COUNT + PCW UIPARAM DDR COL ADDR COUNT + 10 + + + + false + + + + + + PCW_UIPARAM_DDR_CL + PCW UIPARAM DDR CL + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_CWL + PCW UIPARAM DDR CWL + 6 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RCD + PCW UIPARAM DDR T RCD + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RP + PCW UIPARAM DDR T RP + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RC + PCW UIPARAM DDR T RC + 49.5 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RAS_MIN + PCW UIPARAM DDR T RAS MIN + 36.0 + + + + false + + + + + + PCW_UIPARAM_DDR_T_FAW + PCW UIPARAM DDR T FAW + 45.0 + + + + false + + + + + + PCW_UIPARAM_DDR_AL + PCW UIPARAM DDR AL + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 + PCW UIPARAM DDR DQS TO CLK DELAY 0 + 0.0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 + PCW UIPARAM DDR DQS TO CLK DELAY 1 + 0.0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 + PCW UIPARAM DDR DQS TO CLK DELAY 2 + 0.0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 + PCW UIPARAM DDR DQS TO CLK DELAY 3 + 0.0 + + + + true + + + + + + PCW_UIPARAM_DDR_BOARD_DELAY0 + PCW UIPARAM DDR BOARD DELAY0 + 0.0 + + + + true + + + + + + PCW_UIPARAM_DDR_BOARD_DELAY1 + PCW UIPARAM DDR BOARD DELAY1 + 0.0 + + + + true + + + + + + PCW_UIPARAM_DDR_BOARD_DELAY2 + PCW UIPARAM DDR BOARD DELAY2 + 0.0 + + + + true + + + + + + PCW_UIPARAM_DDR_BOARD_DELAY3 + PCW UIPARAM DDR BOARD DELAY3 + 0.0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_0_LENGTH_MM + PCW UIPARAM DDR DQS 0 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_1_LENGTH_MM + PCW UIPARAM DDR DQS 1 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_2_LENGTH_MM + PCW UIPARAM DDR DQS 2 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_3_LENGTH_MM + PCW UIPARAM DDR DQS 3 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_0_LENGTH_MM + PCW UIPARAM DDR DQ 0 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_1_LENGTH_MM + PCW UIPARAM DDR DQ 1 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_2_LENGTH_MM + PCW UIPARAM DDR DQ 2 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_3_LENGTH_MM + PCW UIPARAM DDR DQ 3 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM + PCW UIPARAM DDR CLOCK 0 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM + PCW UIPARAM DDR CLOCK 1 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM + PCW UIPARAM DDR CLOCK 2 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM + PCW UIPARAM DDR CLOCK 3 LENGTH MM + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 0 PACKAGE LENGTH + 101.239 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 1 PACKAGE LENGTH + 79.5025 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 2 PACKAGE LENGTH + 60.536 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 3 PACKAGE LENGTH + 71.7715 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 0 PACKAGE LENGTH + 104.5365 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 1 PACKAGE LENGTH + 70.676 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 2 PACKAGE LENGTH + 59.1615 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 3 PACKAGE LENGTH + 81.319 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 0 PACKAGE LENGTH + 54.563 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 1 PACKAGE LENGTH + 54.563 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 2 PACKAGE LENGTH + 54.563 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 3 PACKAGE LENGTH + 54.563 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 0 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 1 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 2 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 3 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 0 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 1 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 2 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 3 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 0 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 1 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 2 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 3 PROPOGATION DELAY + 160 + + + + true + + + + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 + PCW PACKAGE DDR DQS TO CLK DELAY 0 + -0.047 + + + + true + + + + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 + PCW PACKAGE DDR DQS TO CLK DELAY 1 + -0.025 + + + + true + + + + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 + PCW PACKAGE DDR DQS TO CLK DELAY 2 + -0.006 + + + + true + + + + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 + PCW PACKAGE DDR DQS TO CLK DELAY 3 + -0.017 + + + + true + + + + + + PCW_PACKAGE_DDR_BOARD_DELAY0 + PCW PACKAGE DDR BOARD DELAY0 + 0.080 + + + + true + + + + + + PCW_PACKAGE_DDR_BOARD_DELAY1 + PCW PACKAGE DDR BOARD DELAY1 + 0.063 + + + + true + + + + + + PCW_PACKAGE_DDR_BOARD_DELAY2 + PCW PACKAGE DDR BOARD DELAY2 + 0.057 + + + + true + + + + + + PCW_PACKAGE_DDR_BOARD_DELAY3 + PCW PACKAGE DDR BOARD DELAY3 + 0.068 + + + + true + + + + + + PCW_CPU_CPU_6X4X_MAX_RANGE + PCW CPU CPU 6X4X MAX RANGE + 667 + + + + true + + + + + + PCW_CRYSTAL_PERIPHERAL_FREQMHZ + PCW CRYSTAL PERIPHERAL FREQMHZ + 33.333333 + + + + true + + + + + + PCW_APU_PERIPHERAL_FREQMHZ + PCW APU PERIPHERAL FREQMHZ + 666.666666 + + + + true + + + + + + PCW_DCI_PERIPHERAL_FREQMHZ + PCW DCI PERIPHERAL FREQMHZ + 10.159 + + + + true + + + + + + PCW_QSPI_PERIPHERAL_FREQMHZ + PCW QSPI PERIPHERAL FREQMHZ + 200 + + + + true + + + + + + PCW_SMC_PERIPHERAL_FREQMHZ + PCW SMC PERIPHERAL FREQMHZ + 100 + + + + false + + + + + + PCW_USB0_PERIPHERAL_FREQMHZ + PCW USB0 PERIPHERAL FREQMHZ + 60 + + + + false + + + + + + PCW_USB1_PERIPHERAL_FREQMHZ + PCW USB1 PERIPHERAL FREQMHZ + 60 + + + + false + + + + + + PCW_SDIO_PERIPHERAL_FREQMHZ + PCW SDIO PERIPHERAL FREQMHZ + 100 + + + + true + + + + + + PCW_UART_PERIPHERAL_FREQMHZ + PCW UART PERIPHERAL FREQMHZ + 100 + + + + true + + + + + + PCW_SPI_PERIPHERAL_FREQMHZ + PCW SPI PERIPHERAL FREQMHZ + 166.666666 + + + + false + + + + + + PCW_CAN_PERIPHERAL_FREQMHZ + PCW CAN PERIPHERAL FREQMHZ + 100 + + + + true + + + + + + PCW_CAN0_PERIPHERAL_FREQMHZ + PCW CAN0 PERIPHERAL FREQMHZ + -1 + + + + false + + + + + + PCW_CAN1_PERIPHERAL_FREQMHZ + PCW CAN1 PERIPHERAL FREQMHZ + -1 + + + + false + + + + + + PCW_I2C_PERIPHERAL_FREQMHZ + PCW I2C PERIPHERAL FREQMHZ + 111.111115 + + + + true + + + + + + PCW_WDT_PERIPHERAL_FREQMHZ + PCW WDT PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC_PERIPHERAL_FREQMHZ + PCW TTC PERIPHERAL FREQMHZ + 50 + + + + false + + + + + + PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ + PCW TTC0 CLK0 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ + PCW TTC0 CLK1 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ + PCW TTC0 CLK2 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ + PCW TTC1 CLK0 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ + PCW TTC1 CLK1 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ + PCW TTC1 CLK2 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_PCAP_PERIPHERAL_FREQMHZ + PCW PCAP PERIPHERAL FREQMHZ + 200 + + + + true + + + + + + PCW_TPIU_PERIPHERAL_FREQMHZ + PCW TPIU PERIPHERAL FREQMHZ + 200 + + + + false + + + + + + PCW_FPGA0_PERIPHERAL_FREQMHZ + PCW FPGA0 PERIPHERAL FREQMHZ + 166.667 + + + + true + + + + + + PCW_FPGA1_PERIPHERAL_FREQMHZ + PCW FPGA1 PERIPHERAL FREQMHZ + 50 + + + + true + + + + + + PCW_FPGA2_PERIPHERAL_FREQMHZ + PCW FPGA2 PERIPHERAL FREQMHZ + 100 + + + + true + + + + + + PCW_FPGA3_PERIPHERAL_FREQMHZ + PCW FPGA3 PERIPHERAL FREQMHZ + 200 + + + + true + + + + + + PCW_ACT_APU_PERIPHERAL_FREQMHZ + PCW ACT APU PERIPHERAL FREQMHZ + 666.666687 + + + + true + + + + + + PCW_UIPARAM_ACT_DDR_FREQ_MHZ + PCW UIPARAM ACT DDR FREQ MHZ + 533.333374 + + + + true + + + + + + PCW_ACT_DCI_PERIPHERAL_FREQMHZ + PCW ACT DCI PERIPHERAL FREQMHZ + 10.158731 + + + + true + + + + + + PCW_ACT_QSPI_PERIPHERAL_FREQMHZ + PCW ACT QSPI PERIPHERAL FREQMHZ + 200.000000 + + + + true + + + + + + PCW_ACT_SMC_PERIPHERAL_FREQMHZ + PCW ACT SMC PERIPHERAL FREQMHZ + 10.000000 + + + + true + + + + + + PCW_ACT_ENET0_PERIPHERAL_FREQMHZ + PCW ACT ENET0 PERIPHERAL FREQMHZ + 125.000000 + + + + true + + + + + + PCW_ACT_ENET1_PERIPHERAL_FREQMHZ + PCW ACT ENET1 PERIPHERAL FREQMHZ + 10.000000 + + + + true + + + + + + PCW_ACT_USB0_PERIPHERAL_FREQMHZ + PCW ACT USB0 PERIPHERAL FREQMHZ + 60 + + + + true + + + + + + PCW_ACT_USB1_PERIPHERAL_FREQMHZ + PCW ACT USB1 PERIPHERAL FREQMHZ + 60 + + + + true + + + + + + PCW_ACT_SDIO_PERIPHERAL_FREQMHZ + PCW ACT SDIO PERIPHERAL FREQMHZ + 100.000000 + + + + true + + + + + + PCW_ACT_UART_PERIPHERAL_FREQMHZ + PCW ACT UART PERIPHERAL FREQMHZ + 100.000000 + + + + true + + + + + + PCW_ACT_SPI_PERIPHERAL_FREQMHZ + PCW ACT SPI PERIPHERAL FREQMHZ + 10.000000 + + + + true + + + + + + PCW_ACT_CAN_PERIPHERAL_FREQMHZ + PCW ACT CAN PERIPHERAL FREQMHZ + 100.000000 + + + + true + + + + + + PCW_ACT_CAN0_PERIPHERAL_FREQMHZ + PCW ACT CAN0 PERIPHERAL FREQMHZ + 23.8095 + + + PCW_ACT_CAN1_PERIPHERAL_FREQMHZ + PCW ACT CAN0 PERIPHERAL FREQMHZ + 23.8095 + + + PCW_ACT_I2C_PERIPHERAL_FREQMHZ + PCW ACT I2C PERIPHERAL FREQMHZ + 50 + + + + true + + + + + + PCW_ACT_WDT_PERIPHERAL_FREQMHZ + PCW ACT WDT PERIPHERAL FREQMHZ + 111.111115 + + + + true + + + + + + PCW_ACT_TTC_PERIPHERAL_FREQMHZ + PCW ACT TTC PERIPHERAL FREQMHZ + 50 + + + + true + + + + + + PCW_ACT_PCAP_PERIPHERAL_FREQMHZ + PCW ACT PCAP PERIPHERAL FREQMHZ + 200.000000 + + + + true + + + + + + PCW_ACT_TPIU_PERIPHERAL_FREQMHZ + PCW ACT TPIU PERIPHERAL FREQMHZ + 200.000000 + + + + true + + + + + + PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ + PCW ACT FPGA0 PERIPHERAL FREQMHZ + 166.666672 + + + + true + + + + + + PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ + PCW ACT FPGA1 PERIPHERAL FREQMHZ + 50.000000 + + + + true + + + + + + PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ + PCW ACT FPGA2 PERIPHERAL FREQMHZ + 100.000000 + + + + true + + + + + + PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ + PCW ACT FPGA3 PERIPHERAL FREQMHZ + 200.000000 + + + + true + + + + + + PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK0 PERIPHERAL FREQMHZ + 111.111115 + + + + true + + + + + + PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK1 PERIPHERAL FREQMHZ + 111.111115 + + + + true + + + + + + PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK2 PERIPHERAL FREQMHZ + 111.111115 + + + + true + + + + + + PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK0 PERIPHERAL FREQMHZ + 111.111115 + + + + true + + + + + + PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK1 PERIPHERAL FREQMHZ + 111.111115 + + + + true + + + + + + PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK2 PERIPHERAL FREQMHZ + 111.111115 + + + + true + + + + + + PCW_CLK0_FREQ + PCW CLK0 FREQ + 166666672 + + + + true + + + + + + PCW_CLK1_FREQ + PCW CLK1 FREQ + 50000000 + + + + true + + + + + + PCW_CLK2_FREQ + PCW CLK2 FREQ + 100000000 + + + + true + + + + + + PCW_CLK3_FREQ + PCW CLK3 FREQ + 200000000 + + + + true + + + + + + PCW_OVERRIDE_BASIC_CLOCK + PCW OVERRIDE FREQ + 0 + + + + true + + + + + + PCW_CPU_PERIPHERAL_DIVISOR0 + CLKPARAM + 2 + + + + false + + + + + + PCW_DDR_PERIPHERAL_DIVISOR0 + CLKPARAM + 2 + + + + false + + + + + + PCW_SMC_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_QSPI_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_SDIO_PERIPHERAL_DIVISOR0 + CLKPARAM + 10 + + + + false + + + + + + PCW_UART_PERIPHERAL_DIVISOR0 + CLKPARAM + 10 + + + + false + + + + + + PCW_SPI_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_CAN_PERIPHERAL_DIVISOR0 + CLKPARAM + 10 + + + + false + + + + + + PCW_CAN_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 6 + + + + false + + + + + + PCW_FCLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 20 + + + + false + + + + + + PCW_FCLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 10 + + + + false + + + + + + PCW_FCLK3_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_FCLK0_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK1_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK2_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK3_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET0_PERIPHERAL_DIVISOR0 + CLKPARAM + 8 + + + + false + + + + + + PCW_ENET1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET0_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET1_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_TPIU_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_DCI_PERIPHERAL_DIVISOR0 + CLKPARAM + 35 + + + + false + + + + + + PCW_DCI_PERIPHERAL_DIVISOR1 + CLKPARAM + 3 + + + + false + + + + + + PCW_PCAP_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + true + + + + + + PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + true + + + + + + PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + true + + + + + + PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + true + + + + + + PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + true + + + + + + PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + true + + + + + + PCW_WDT_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + true + + + + + + PCW_ARMPLL_CTRL_FBDIV + CLKPARAM + 40 + + + + false + + + + + + PCW_IOPLL_CTRL_FBDIV + CLKPARAM + 30 + + + + false + + + + + + PCW_DDRPLL_CTRL_FBDIV + CLKPARAM + 32 + + + + false + + + + + + PCW_CPU_CPU_PLL_FREQMHZ + CLKPARAM + 1333.333 + + + + false + + + + + + PCW_IO_IO_PLL_FREQMHZ + CLKPARAM + 1000.000 + + + + false + + + + + + PCW_DDR_DDR_PLL_FREQMHZ + CLKPARAM + 1066.667 + + + + false + + + + + + PCW_SMC_PERIPHERAL_VALID + PCW SMC PERIPHERAL VALID + 0 + + + + true + + + + + + PCW_SDIO_PERIPHERAL_VALID + PCW SDIO PERIPHERAL VALID + 1 + + + + true + + + + + + PCW_SPI_PERIPHERAL_VALID + PCW SPI PERIPHERAL VALID + 0 + + + + true + + + + + + PCW_CAN_PERIPHERAL_VALID + PCW CAN PERIPHERAL VALID + 1 + + + + true + + + + + + PCW_UART_PERIPHERAL_VALID + PCW UART PERIPHERAL VALID + 1 + + + + true + + + + + + PCW_EN_EMIO_CAN0 + PCW EN EMIO CAN0 + 0 + + + + true + + + + + + PCW_EN_EMIO_CAN1 + PCW EN EMIO CAN1 + 0 + + + + true + + + + + + PCW_EN_EMIO_ENET0 + PCW EN EMIO ENET0 + 0 + + + + true + + + + + + PCW_EN_EMIO_ENET1 + PCW EN EMIO ENET1 + 0 + + + + true + + + + + + PCW_EN_EMIO_GPIO + PCW EN EMIO GPIO + 1 + + + + true + + + + + + PCW_EN_EMIO_I2C0 + PCW EN EMIO I2C0 + 1 + + + + true + + + + + + PCW_EN_EMIO_I2C1 + PCW EN EMIO I2C1 + 0 + + + + true + + + + + + PCW_EN_EMIO_PJTAG + PCW EN EMIO PJTAG + 0 + + + + true + + + + + + PCW_EN_EMIO_SDIO0 + PCW EN EMIO SDIO0 + 0 + + + + true + + + + + + PCW_EN_EMIO_CD_SDIO0 + PCW EN EMIO CD SDIO0 + 0 + + + + true + + + + + + PCW_EN_EMIO_WP_SDIO0 + PCW EN EMIO WP SDIO0 + 0 + + + + true + + + + + + PCW_EN_EMIO_SDIO1 + PCW EN EMIO SDIO1 + 0 + + + + true + + + + + + PCW_EN_EMIO_CD_SDIO1 + PCW EN EMIO CD SDIO1 + 0 + + + + true + + + + + + PCW_EN_EMIO_WP_SDIO1 + PCW EN EMIO WP SDIO1 + 0 + + + + true + + + + + + PCW_EN_EMIO_SPI0 + PCW EN EMIO SPI0 + 0 + + + + true + + + + + + PCW_EN_EMIO_SPI1 + PCW EN EMIO SPI1 + 0 + + + + true + + + + + + PCW_EN_EMIO_UART0 + PCW EN EMIO UART0 + 0 + + + + true + + + + + + PCW_EN_EMIO_UART1 + PCW EN EMIO UART1 + 0 + + + + true + + + + + + PCW_EN_EMIO_MODEM_UART0 + PCW EN EMIO MODEM UART0 + 0 + + + + true + + + + + + PCW_EN_EMIO_MODEM_UART1 + PCW EN EMIO MODEM UART1 + 0 + + + + true + + + + + + PCW_EN_EMIO_TTC0 + PCW EN EMIO TTC0 + 0 + + + + true + + + + + + PCW_EN_EMIO_TTC1 + PCW EN EMIO TTC1 + 0 + + + + true + + + + + + PCW_EN_EMIO_WDT + PCW EN EMIO WDT + 0 + + + + true + + + + + + PCW_EN_EMIO_TRACE + PCW EN EMIO TRACE + 0 + + + + true + + + + + + PCW_USE_AXI_NONSECURE + PCW USE AXI NON SECURE + 0 + + + + true + + + + + + PCW_USE_M_AXI_GP0 + PCW USE M AXI GP0 + 1 + + + PCW_USE_M_AXI_GP1 + PCW USE M AXI GP1 + 0 + + + PCW_USE_S_AXI_GP0 + PCW USE S AXI GP0 + 0 + + + PCW_USE_S_AXI_GP1 + PCW USE S AXI GP1 + 0 + + + PCW_USE_S_AXI_ACP + PCW USE S AXI ACP + 0 + + + PCW_USE_S_AXI_HP0 + PCW USE S AXI HP0 + 1 + + + PCW_USE_S_AXI_HP1 + PCW USE S AXI HP1 + 0 + + + PCW_USE_S_AXI_HP2 + PCW USE S AXI HP2 + 0 + + + PCW_USE_S_AXI_HP3 + PCW USE S AXI HP3 + 0 + + + PCW_M_AXI_GP0_FREQMHZ + PCW M AXI GP0 FREQMHZ + 50 + + + + optional + true + + + + + + PCW_M_AXI_GP1_FREQMHZ + PCW M AXI GP1 FREQMHZ + 10 + + + + optional + false + + + + + + PCW_S_AXI_GP0_FREQMHZ + PCW S AXI GP0 FREQMHZ + 10 + + + + optional + false + + + + + + PCW_S_AXI_GP1_FREQMHZ + PCW S AXI GP1 FREQMHZ + 10 + + + + optional + false + + + + + + PCW_S_AXI_ACP_FREQMHZ + PCW S AXI ACP FREQMHZ + 10 + + + + optional + false + + + + + + PCW_S_AXI_HP0_FREQMHZ + PCW S AXI HP0 FREQMHZ + 100 + + + + optional + true + + + + + + PCW_S_AXI_HP1_FREQMHZ + PCW S AXI HP1 FREQMHZ + 10 + + + + optional + false + + + + + + PCW_S_AXI_HP2_FREQMHZ + PCW S AXI HP2 FREQMHZ + 10 + + + + optional + false + + + + + + PCW_S_AXI_HP3_FREQMHZ + PCW S AXI HP3 FREQMHZ + 10 + + + + optional + false + + + + + + PCW_USE_DMA0 + PCW USE DMA0 + 0 + + + PCW_USE_DMA1 + PCW USE DMA1 + 0 + + + PCW_USE_DMA2 + PCW USE DMA2 + 0 + + + PCW_USE_DMA3 + PCW USE DMA3 + 0 + + + PCW_USE_TRACE + PCW USE TRACE + Enable FTM Trace interface used to capture data from PL to PS debug system + 0 + + + PCW_TRACE_PIPELINE_WIDTH + PCW TRACE PIPELINE WIDTH + 8 + + + + optional + false + + + + + + PCW_INCLUDE_TRACE_BUFFER + PCW INCLUDE TRACE BUFFER + 0 + + + + optional + false + + + + + + PCW_TRACE_BUFFER_FIFO_SIZE + PCW TRACE BUFFER FIFO SIZE + 128 + + + + optional + false + + + + + + PCW_USE_TRACE_DATA_EDGE_DETECTOR + PCW USE TRACE DATA EDGE DETECTOR + 0 + + + + optional + false + + + + + + PCW_TRACE_BUFFER_CLOCK_DELAY + PCW TRACE BUFFER CLOCK DELAY + 12 + + + + optional + false + + + + + + PCW_USE_CROSS_TRIGGER + PCW USE CROSS TRIGGER + 0 + + + + true + + + + + + PCW_FTM_CTI_IN0 + <Select> + + + + optional + false + + + + + + PCW_FTM_CTI_IN1 + <Select> + + + + optional + false + + + + + + PCW_FTM_CTI_IN2 + <Select> + + + + optional + false + + + + + + PCW_FTM_CTI_IN3 + <Select> + + + + optional + false + + + + + + PCW_FTM_CTI_OUT0 + <Select> + + + + optional + false + + + + + + PCW_FTM_CTI_OUT1 + <Select> + + + + optional + false + + + + + + PCW_FTM_CTI_OUT2 + <Select> + + + + optional + false + + + + + + PCW_FTM_CTI_OUT3 + <Select> + + + + optional + false + + + + + + PCW_USE_DEBUG + PCW USE DEBUG + 0 + + + PCW_USE_CR_FABRIC + PCW USE CR FABRIC + 1 + + + PCW_USE_AXI_FABRIC_IDLE + PCW USE AXI FABRIC IDLE + Enables idle AXI signal to the PS used to indicate that there are no outstanding AXI transactions in the PL + 0 + + + PCW_USE_DDR_BYPASS + PCW USE DDR BYPASS + Enables DDR urgent/arb signal used to signal a critical memory starvation situation to the DDR arbitration for the four AXI ports of the PS DDR memory controller + 0 + + + PCW_USE_FABRIC_INTERRUPT + PCW USE FABRIC INTERRUPT + 1 + + + PCW_USE_PROC_EVENT_BUS + PCW USE PROC EVENT BUS + 0 + + + PCW_USE_EXPANDED_IOP + PCW USE EXPANDED IOP + 0 + + + PCW_USE_HIGH_OCM + PCW USE HIGH OCM + 0 + + + PCW_USE_PS_SLCR_REGISTERS + PCW USE PS SLCR REGISTERS + 0 + + + PCW_USE_EXPANDED_PS_SLCR_REGISTERS + PCW USE EXPANDED PS SLCR REGISTERS + 0 + + + + optional + false + + + + + + PCW_USE_CORESIGHT + PCW USE CORESIGHT + 0 + + + PCW_EN_EMIO_SRAM_INT + PCW EN EMIO SRAM INT + 0 + + + + true + + + + + + PCW_GPIO_EMIO_GPIO_WIDTH + PCW EMIO GPIO WIDTH + 64 + + + + optional + true + + + + + + PCW_UART0_BAUD_RATE + PCW UART0 BAUD RATE + Configure baud rate to determine UART0 operating frequency + 115200 + + + + optional + false + + + + + + PCW_UART1_BAUD_RATE + PCW UART1 BAUD RATE + Configure baud rate to determine UART1 operating frequency + 115200 + + + + optional + true + + + + + + PCW_EN_4K_TIMER + PCW EN 4K TIMER + 0 + + + + true + + + + + + PCW_M_AXI_GP0_ID_WIDTH + PCW M AXI GP0 ID WIDTH + 12 + + + + optional + true + + + + + + PCW_M_AXI_GP0_ENABLE_STATIC_REMAP + PCW M AXI GP0 ENABLE STATIC REMAP + 0 + + + + optional + true + + + + + + PCW_M_AXI_GP0_SUPPORT_NARROW_BURST + PCW M AXI GP0 SUPPORT NARROW BURST + 0 + + + + optional + true + + + + + + PCW_M_AXI_GP0_THREAD_ID_WIDTH + PCW M AXI GP0 THREAD ID WIDTH + 12 + + + + optional + true + + + + + + PCW_M_AXI_GP1_ID_WIDTH + PCW M AXI GP1 ID WIDTH + 12 + + + + optional + false + + + + + + PCW_M_AXI_GP1_ENABLE_STATIC_REMAP + PCW M AXI GP1 ENABLE STATIC REMAP + 0 + + + + optional + false + + + + + + PCW_M_AXI_GP1_SUPPORT_NARROW_BURST + PCW M AXI GP1 SUPPORT NARROW BURST + 0 + + + + optional + false + + + + + + PCW_M_AXI_GP1_THREAD_ID_WIDTH + PCW M AXI GP1 THREAD ID WIDTH + 12 + + + + optional + false + + + + + + PCW_S_AXI_GP0_ID_WIDTH + PCW S AXI GP0 ID WIDTH + 6 + + + + optional + false + + + + + + PCW_S_AXI_GP1_ID_WIDTH + PCW S AXI GP1 ID WIDTH + 6 + + + + optional + false + + + + + + PCW_S_AXI_ACP_ID_WIDTH + PCW S AXI ACP ID WIDTH + 3 + + + + optional + false + + + + + + PCW_INCLUDE_ACP_TRANS_CHECK + PCW INCLUDE ACP TRANS CHECK + 0 + + + PCW_USE_DEFAULT_ACP_USER_VAL + PCW USE DEFAULT ACP USER VAL + 0 + + + + optional + false + + + + + + PCW_S_AXI_ACP_ARUSER_VAL + PCW S AXI ACP ARUSER VAL + 31 + + + + optional + false + + + + + + PCW_S_AXI_ACP_AWUSER_VAL + PCW S AXI ACP AWUSER VAL + 31 + + + + optional + false + + + + + + PCW_S_AXI_HP0_ID_WIDTH + PCW S AXI HP0 ID WIDTH + 6 + + + + optional + true + + + + + + PCW_S_AXI_HP0_DATA_WIDTH + PCW S AXI HP0 DATA WIDTH + 64 + + + + optional + true + + + + + + PCW_S_AXI_HP1_ID_WIDTH + PCW S AXI HP1 ID WIDTH + 6 + + + + optional + false + + + + + + PCW_S_AXI_HP1_DATA_WIDTH + PCW S AXI HP1 DATA WIDTH + 64 + + + + optional + true + + + + + + PCW_S_AXI_HP2_ID_WIDTH + PCW S AXI HP2 ID WIDTH + 6 + + + + optional + false + + + + + + PCW_S_AXI_HP2_DATA_WIDTH + PCW S AXI HP2 DATA WIDTH + 64 + + + + optional + true + + + + + + PCW_S_AXI_HP3_ID_WIDTH + PCW S AXI HP3 ID WIDTH + 6 + + + + optional + false + + + + + + PCW_S_AXI_HP3_DATA_WIDTH + PCW S AXI HP3 DATA WIDTH + 64 + + + + optional + true + + + + + + PCW_NUM_F2P_INTR_INPUTS + PCW NUM F2P INTR INPUTS + 16 + + + + optional + true + + + + + + PCW_EN_DDR + PCW EN DDR + 1 + + + + true + + + + + + PCW_EN_SMC + PCW EN SMC + 0 + + + + true + + + + + + PCW_EN_QSPI + PCW EN QSPI + 1 + + + + true + + + + + + PCW_EN_CAN0 + PCW EN CAN0 + 1 + + + + true + + + + + + PCW_EN_CAN1 + PCW EN CAN1 + 0 + + + + true + + + + + + PCW_EN_ENET0 + PCW EN ENET0 + 1 + + + + true + + + + + + PCW_EN_ENET1 + PCW EN ENET1 + 0 + + + + true + + + + + + PCW_EN_GPIO + PCW EN GPIO + 1 + + + + true + + + + + + PCW_EN_I2C0 + PCW EN I2C0 + 1 + + + + true + + + + + + PCW_EN_I2C1 + PCW EN I2C1 + 1 + + + + true + + + + + + PCW_EN_PJTAG + PCW EN PJTAG + 0 + + + + true + + + + + + PCW_EN_SDIO0 + PCW EN SDIO0 + 1 + + + + true + + + + + + PCW_EN_SDIO1 + PCW EN SDIO1 + 0 + + + + true + + + + + + PCW_EN_SPI0 + PCW EN SPI0 + 0 + + + + true + + + + + + PCW_EN_SPI1 + PCW EN SPI1 + 0 + + + + true + + + + + + PCW_EN_UART0 + PCW EN UART0 + 0 + + + + true + + + + + + PCW_EN_UART1 + PCW EN UART1 + 1 + + + + true + + + + + + PCW_EN_MODEM_UART0 + PCW EN MODEM UART0 + 0 + + + + true + + + + + + PCW_EN_MODEM_UART1 + PCW EN MODEM UART1 + 0 + + + + true + + + + + + PCW_EN_TTC0 + PCW EN TTC0 + 0 + + + + true + + + + + + PCW_EN_TTC1 + PCW EN TTC1 + 0 + + + + true + + + + + + PCW_EN_WDT + PCW EN WDT + 0 + + + + true + + + + + + PCW_EN_TRACE + PCW EN TRACE + 0 + + + + true + + + + + + PCW_EN_USB0 + PCW EN USB0 + 1 + + + + true + + + + + + PCW_EN_USB1 + PCW EN USB1 + 0 + + + + true + + + + + + PCW_DQ_WIDTH + PCW DQ WIDTH + 32 + + + PCW_DQS_WIDTH + PCW DQS WIDTH + 4 + + + PCW_DM_WIDTH + PCW DM WIDTH + 4 + + + PCW_MIO_PRIMITIVE + PCW MIO PRIMITIVE + 54 + + + PCW_EN_CLK0_PORT + PCW EN CLK0 PORT + 1 + + + + optional + true + + + + + + PCW_EN_CLK1_PORT + PCW EN CLK1 PORT + 1 + + + + optional + true + + + + + + PCW_EN_CLK2_PORT + PCW EN CLK2 PORT + 1 + + + + optional + true + + + + + + PCW_EN_CLK3_PORT + PCW EN CLK3 PORT + 1 + + + + optional + true + + + + + + PCW_EN_RST0_PORT + PCW EN RST0 PORT + Enables general purpose reset signal 0 for PL logic + 1 + + + + optional + true + + + + + + PCW_EN_RST1_PORT + PCW EN RST1 PORT + Enables general purpose reset signal 1 for PL logic + 1 + + + + optional + true + + + + + + PCW_EN_RST2_PORT + PCW EN RST2 PORT + Enables general purpose reset signal 2 for PL logic + 1 + + + + optional + true + + + + + + PCW_EN_RST3_PORT + PCW EN RST3 PORT + Enables general purpose reset signal 3 for PL logic + 1 + + + + optional + true + + + + + + PCW_EN_CLKTRIG0_PORT + PCW EN CLKTRIG0 PORT + Enables PL clock trigger signal 0 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + optional + true + + + + + + PCW_EN_CLKTRIG1_PORT + PCW EN CLKTRIG1 PORT + Enables PL clock trigger signal 1 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + optional + true + + + + + + PCW_EN_CLKTRIG2_PORT + PCW EN CLKTRIG2 PORT + Enables PL clock trigger signal 2 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + optional + true + + + + + + PCW_EN_CLKTRIG3_PORT + PCW EN CLKTRIG3 PORT + Enables PL clock trigger signal 3 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + optional + true + + + + + + PCW_P2F_DMAC_ABORT_INTR + PCW P2F DMAC ABORT INTR + 0 + + + + optional + false + + + + + + PCW_P2F_DMAC0_INTR + PCW P2F DMAC0 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_DMAC1_INTR + PCW P2F DMAC1 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_DMAC2_INTR + PCW P2F DMAC2 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_DMAC3_INTR + PCW P2F DMAC3 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_DMAC4_INTR + PCW P2F DMAC4 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_DMAC5_INTR + PCW P2F DMAC5 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_DMAC6_INTR + PCW P2F DMAC6 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_DMAC7_INTR + PCW P2F DMAC7 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_SMC_INTR + PCW P2F SMC INTR + 0 + + + + optional + false + + + + + + PCW_P2F_QSPI_INTR + PCW P2F QSPI INTR + 0 + + + + optional + true + + + + + + PCW_P2F_CTI_INTR + PCW P2F CTI INTR + 0 + + + + optional + false + + + + + + PCW_P2F_GPIO_INTR + PCW P2F GPIO INTR + 0 + + + + optional + true + + + + + + PCW_P2F_USB0_INTR + PCW P2F USB0 INTR + 0 + + + + optional + true + + + + + + PCW_P2F_ENET0_INTR + PCW P2F ENET0 INTR + 0 + + + + optional + true + + + + + + PCW_P2F_SDIO0_INTR + PCW P2F SDIO0 INTR + 0 + + + + optional + true + + + + + + PCW_P2F_I2C0_INTR + PCW P2F I2C0 INTR + 0 + + + + optional + true + + + + + + PCW_P2F_SPI0_INTR + PCW P2F SPI0 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_UART0_INTR + PCW P2F UART0 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_CAN0_INTR + PCW P2F CAN0 INTR + 0 + + + + optional + true + + + + + + PCW_P2F_USB1_INTR + PCW P2F USB1 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_ENET1_INTR + PCW P2F ENET1 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_SDIO1_INTR + PCW P2F SDIO1 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_I2C1_INTR + PCW P2F I2C1 INTR + 0 + + + + optional + true + + + + + + PCW_P2F_SPI1_INTR + PCW P2F SPI1 INTR + 0 + + + + optional + false + + + + + + PCW_P2F_UART1_INTR + PCW P2F UART1 INTR + 0 + + + + optional + true + + + + + + PCW_P2F_CAN1_INTR + PCW P2F CAN1 INTR + 0 + + + + optional + false + + + + + + PCW_IRQ_F2P_INTR + PCW IRQ F2P INTR + 1 + + + + optional + true + + + + + + PCW_IRQ_F2P_MODE + PCW IRQ F2P MODE + DIRECT + + + + optional + true + + + + + + PCW_CORE0_FIQ_INTR + PCW CORE0 FIQ INTR + 0 + + + + optional + true + + + + + + PCW_CORE0_IRQ_INTR + PCW CORE0 IRQ INTR + 0 + + + + optional + true + + + + + + PCW_CORE1_FIQ_INTR + PCW CORE1 FIQ INTR + 0 + + + + optional + true + + + + + + PCW_CORE1_IRQ_INTR + PCW CORE1 IRQ INTR + 0 + + + + optional + true + + + + + + PCW_VALUE_SILVERSION + PCW VALUE SILVERSION + 3 + + + PCW_IMPORT_BOARD_PRESET + PCW IMPORT BOARD PRESET + None + + + PCW_PERIPHERAL_BOARD_PRESET + PCW PERIPHERAL BOARD PRESET + None + + + PCW_PRESET_BANK0_VOLTAGE + PCW PRESET BANK0 VOLTAGE + LVCMOS 3.3V + + + + true + + + + + + PCW_PRESET_BANK1_VOLTAGE + PCW PRESET BANK1 VOLTAGE + LVCMOS 1.8V + + + + true + + + + + + PCW_UIPARAM_DDR_ENABLE + PCW UIPARAM DDR ENABLE + 1 + + + + true + + + + + + PCW_UIPARAM_DDR_ADV_ENABLE + PCW UIPARAM DDR ADV ENABLE + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_MEMORY_TYPE + PCW UIPARAM DDR MEMORY TYPE + DDR 3 + + + + true + + + + + + PCW_UIPARAM_DDR_ECC + PCW UIPARAM DDR ECC + Disabled + + + + false + + + + + + PCW_UIPARAM_DDR_BUS_WIDTH + PCW UIPARAM DDR BUS WIDTH + 32 Bit + + + + true + + + + + + PCW_UIPARAM_DDR_BL + PCW UIPARAM DDR BL + 8 + + + + true + + + + + + PCW_UIPARAM_DDR_HIGH_TEMP + PCW UIPARAM DDR HIGH TEMP + Normal (0-85) + + + + true + + + + + + PCW_UIPARAM_DDR_PARTNO + PCW UIPARAM DDR PARTNO + MT41K256M16 RE-15E + + + + true + + + + + + PCW_UIPARAM_DDR_DRAM_WIDTH + PCW UIPARAM DDR DRAM WIDTH + 16 Bits + + + + false + + + + + + PCW_UIPARAM_DDR_DEVICE_CAPACITY + PCW UIPARAM DDR DEVICE CAPACITY + 4096 MBits + + + + false + + + + + + PCW_UIPARAM_DDR_SPEED_BIN + PCW UIPARAM DDR SPEED BIN + DDR3_1066F + + + + false + + + + + + PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL + PCW UIPARAM DDR TRAIN WRITE LEVEL + 1 + + + + true + + + + + + PCW_UIPARAM_DDR_TRAIN_READ_GATE + PCW UIPARAM DDR TRAIN READ GATE + 1 + + + + true + + + + + + PCW_UIPARAM_DDR_TRAIN_DATA_EYE + PCW UIPARAM DDR TRAIN DATA EYE + 1 + + + + true + + + + + + PCW_UIPARAM_DDR_CLOCK_STOP_EN + PCW UIPARAM DDR CLOCK STOP EN + 0 + + + + true + + + + + + PCW_UIPARAM_DDR_USE_INTERNAL_VREF + PCW UIPARAM DDR USE INTERNAL VREF + 0 + + + + true + + + + + + PCW_DDR_PRIORITY_WRITEPORT_0 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_1 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_2 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_3 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_0 + PCW DDR PRIORITY READPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_1 + PCW DDR PRIORITY READPORT 1 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_2 + PCW DDR PRIORITY READPORT 2 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_3 + PCW DDR PRIORITY READPORT 3 + <Select> + + + + false + + + + + + PCW_DDR_PORT0_HPR_ENABLE + PCW DDR PORT0 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT1_HPR_ENABLE + PCW DDR PORT1 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT2_HPR_ENABLE + PCW DDR PORT2 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT3_HPR_ENABLE + PCW DDR PORT3 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_HPRLPR_QUEUE_PARTITION + PCW DDR HPRLPR QUEUE PARTITION + HPR(0)/LPR(32) + + + + false + + + + + + PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR LPR TO CRITICAL PRIORITY LEVEL + 2 + + + + false + + + + + + PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR HPR TO CRITICAL PRIORITY LEVEL + 15 + + + + false + + + + + + PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR WRITE TO CRITICAL PRIORITY LEVEL + 2 + + + + false + + + + + + PCW_NAND_PERIPHERAL_ENABLE + PCW NAND PERIPHERAL ENABLE + 0 + + + + false + + + + + + PCW_NAND_NAND_IO + PCW NAND NAND IO + <Select> + + + + false + + + + + + PCW_NAND_GRP_D8_ENABLE + 0 + + + + false + + + + + + PCW_NAND_GRP_D8_IO + PCW NAND GRP D8 IO + <Select> + + + + false + + + + + + PCW_NOR_PERIPHERAL_ENABLE + PCW NOR PERIPHERAL ENABLE + 0 + + + + false + + + + + + PCW_NOR_NOR_IO + PCW NOR NOR IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_A25_ENABLE + PCW NOR GRP A25 IO + 0 + + + + false + + + + + + PCW_NOR_GRP_A25_IO + PCW NOR GRP CS0 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_CS0_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_CS0_IO + PCW NOR GRP CS1 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS0_ENABLE + PCW NOR GRP SRAM CS0 ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS0_IO + PCW NOR GRP SRAM CS1 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_CS1_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_CS1_IO + PCW NOR GRP SRAM CS0 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS1_ENABLE + PCW NOR GRP SRAM CS1 ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS1_IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_INT_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_INT_IO + <Select> + + + + false + + + + + + PCW_QSPI_PERIPHERAL_ENABLE + PCW QSPI PERIPHERAL ENABLE + 1 + + + + true + + + + + + PCW_QSPI_QSPI_IO + PCW QSPI QSPI IO + MIO 1 .. 6 + + + + true + + + + + + PCW_QSPI_GRP_SINGLE_SS_ENABLE + PCW QSPI GRP SINGLE SS ENABLE + 1 + + + + true + + + + + + PCW_QSPI_GRP_SINGLE_SS_IO + PCW QSPI GRP SINGLE SS IO + MIO 1 .. 6 + + + + true + + + + + + PCW_QSPI_GRP_SS1_ENABLE + 0 + + + + true + + + + + + PCW_QSPI_GRP_SS1_IO + PCW QSPI GRP SS1 IO + <Select> + + + + false + + + + + + PCW_QSPI_GRP_IO1_ENABLE + 0 + + + + true + + + + + + PCW_QSPI_GRP_IO1_IO + PCW QSPI GRP IO1 IO + <Select> + + + + false + + + + + + PCW_QSPI_GRP_FBCLK_ENABLE + 1 + + + + true + + + + + + PCW_QSPI_GRP_FBCLK_IO + PCW QSPI GRP FBCLK IO + MIO 8 + + + + true + + + + + + PCW_QSPI_INTERNAL_HIGHADDRESS + PCW QSPI INTERNAL HIGHADDRESS + 0xFCFFFFFF + + + + true + + + + + + PCW_ENET0_PERIPHERAL_ENABLE + PCW ENET0 PERIPHERAL ENABLE + 1 + + + + true + + + + + + PCW_ENET0_ENET0_IO + PCW ENET0 ENET0 IO + MIO 16 .. 27 + + + + true + + + + + + PCW_ENET0_GRP_MDIO_ENABLE + 1 + + + + true + + + + + + PCW_ENET0_GRP_MDIO_IO + PCW ENET0 GRP MDIO IO + MIO 52 .. 53 + + + + true + + + + + + PCW_ENET_RESET_ENABLE + 0 + + + + true + + + + + + PCW_ENET_RESET_SELECT + <Select> + + + + false + + + + + + PCW_ENET0_RESET_ENABLE + 0 + + + + false + + + + + + PCW_ENET0_RESET_IO + <Select> + + + + false + + + + + + PCW_ENET1_PERIPHERAL_ENABLE + PCW ENET1 PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_ENET1_ENET1_IO + PCW ENET1 ENET1 IO + <Select> + + + + false + + + + + + PCW_ENET1_GRP_MDIO_ENABLE + 0 + + + + false + + + + + + PCW_ENET1_GRP_MDIO_IO + PCW ENET1 GRP MDIO IO + <Select> + + + + false + + + + + + PCW_ENET1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_ENET1_RESET_IO + <Select> + + + + false + + + + + + PCW_SD0_PERIPHERAL_ENABLE + PCW SD0 PERIPHERAL ENABLE + 1 + + + + true + + + + + + PCW_SD0_SD0_IO + PCW SD0 SD0 IO + MIO 40 .. 45 + + + + true + + + + + + PCW_SD0_GRP_CD_ENABLE + 1 + + + + true + + + + + + PCW_SD0_GRP_CD_IO + PCW SD0 GRP CD IO + MIO 46 + + + + true + + + + + + PCW_SD0_GRP_WP_ENABLE + 1 + + + + true + + + + + + PCW_SD0_GRP_WP_IO + PCW SD0 GRP WP IO + MIO 47 + + + + true + + + + + + PCW_SD0_GRP_POW_ENABLE + 0 + + + + true + + + + + + PCW_SD0_GRP_POW_IO + PCW SD0 GRP POW IO + <Select> + + + + false + + + + + + PCW_SD1_PERIPHERAL_ENABLE + PCW SD1 PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_SD1_SD1_IO + PCW SD1 SD1 IO + <Select> + + + + false + + + + + + PCW_SD1_GRP_CD_ENABLE + 0 + + + + false + + + + + + PCW_SD1_GRP_CD_IO + PCW SD1 GRP CD IO + <Select> + + + + false + + + + + + PCW_SD1_GRP_WP_ENABLE + 0 + + + + false + + + + + + PCW_SD1_GRP_WP_IO + PCW SD1 GRP WP IO + <Select> + + + + false + + + + + + PCW_SD1_GRP_POW_ENABLE + 0 + + + + false + + + + + + PCW_SD1_GRP_POW_IO + PCW SD1 GRP POW IO + <Select> + + + + false + + + + + + PCW_UART0_PERIPHERAL_ENABLE + PCW UART0 PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_UART0_UART0_IO + PCW UART0 UART0 IO + <Select> + + + + false + + + + + + PCW_UART0_GRP_FULL_ENABLE + 0 + + + + false + + + + + + PCW_UART0_GRP_FULL_IO + <Select> + + + + false + + + + + + PCW_UART1_PERIPHERAL_ENABLE + PCW UART1 PERIPHERAL ENABLE + 1 + + + + true + + + + + + PCW_UART1_UART1_IO + PCW UART1 UART1 IO + MIO 48 .. 49 + + + + true + + + + + + PCW_UART1_GRP_FULL_ENABLE + 0 + + + + true + + + + + + PCW_UART1_GRP_FULL_IO + <Select> + + + + false + + + + + + PCW_SPI0_PERIPHERAL_ENABLE + PCW SPI0 PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_SPI0_SPI0_IO + PCW SPI0 SPI0 IO + <Select> + + + + false + + + + + + PCW_SPI0_GRP_SS0_ENABLE + 0 + + + + false + + + + + + PCW_SPI0_GRP_SS0_IO + PCW SPI0 GRP SS0 IO + <Select> + + + + false + + + + + + PCW_SPI0_GRP_SS1_ENABLE + 0 + + + + false + + + + + + PCW_SPI0_GRP_SS1_IO + PCW SPI0 GRP SS1 IO + <Select> + + + + false + + + + + + PCW_SPI0_GRP_SS2_ENABLE + 0 + + + + false + + + + + + PCW_SPI0_GRP_SS2_IO + PCW SPI0 GRP SS2 IO + <Select> + + + + false + + + + + + PCW_SPI1_PERIPHERAL_ENABLE + PCW SPI1 PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_SPI1_SPI1_IO + PCW SPI1 SPI1 IO + <Select> + + + + false + + + + + + PCW_SPI1_GRP_SS0_ENABLE + 0 + + + + false + + + + + + PCW_SPI1_GRP_SS0_IO + PCW SPI1 GRP SS0 IO + <Select> + + + + false + + + + + + PCW_SPI1_GRP_SS1_ENABLE + 0 + + + + false + + + + + + PCW_SPI1_GRP_SS1_IO + PCW SPI1 GRP SS1 IO + <Select> + + + + false + + + + + + PCW_SPI1_GRP_SS2_ENABLE + 0 + + + + false + + + + + + PCW_SPI1_GRP_SS2_IO + PCW SPI1 GRP SS2 IO + <Select> + + + + false + + + + + + PCW_CAN0_PERIPHERAL_ENABLE + PCW CAN0 PERIPHERAL ENABLE + 1 + + + + true + + + + + + PCW_CAN0_CAN0_IO + PCW CAN0 CAN0 IO + MIO 14 .. 15 + + + + true + + + + + + PCW_CAN0_GRP_CLK_ENABLE + 0 + + + + true + + + + + + PCW_CAN0_GRP_CLK_IO + PCW CAN0 GRP CLK IO + <Select> + + + + false + + + + + + PCW_CAN1_PERIPHERAL_ENABLE + PCW CAN1 PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_CAN1_CAN1_IO + PCW CAN1 CAN1 IO + <Select> + + + + false + + + + + + PCW_CAN1_GRP_CLK_ENABLE + 0 + + + + false + + + + + + PCW_CAN1_GRP_CLK_IO + PCW CAN1 GRP CLK IO + <Select> + + + + false + + + + + + PCW_TRACE_PERIPHERAL_ENABLE + PCW TRACE PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_TRACE_TRACE_IO + PCW TRACE TRACE IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_2BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_2BIT_IO + PCW TRACE GRP 2BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_4BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_4BIT_IO + PCW TRACE GRP 4BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_8BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_8BIT_IO + PCW TRACE GRP 8BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_16BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_16BIT_IO + PCW TRACE GRP 16BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_32BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_32BIT_IO + PCW TRACE GRP 32BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_INTERNAL_WIDTH + PCW TRACE INTERNAL WIDTH + 2 + + + + true + + + + + + PCW_WDT_PERIPHERAL_ENABLE + PCW WDT PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_WDT_WDT_IO + PCW WDT WDT IO + <Select> + + + + false + + + + + + PCW_TTC0_PERIPHERAL_ENABLE + PCW TTC0 PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_TTC0_TTC0_IO + PCW TTC0 TTC0 IO + <Select> + + + + false + + + + + + PCW_TTC1_PERIPHERAL_ENABLE + PCW TTC1 PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_TTC1_TTC1_IO + PCW TTC1 TTC1 IO + <Select> + + + + false + + + + + + PCW_PJTAG_PERIPHERAL_ENABLE + PCW PJTAG PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_PJTAG_PJTAG_IO + PCW PJTAG PJTAG IO + <Select> + + + + false + + + + + + PCW_USB0_PERIPHERAL_ENABLE + PCW USB0 PERIPHERAL ENABLE + 1 + + + + true + + + + + + PCW_USB0_USB0_IO + PCW USB0 USB0 IO + MIO 28 .. 39 + + + + true + + + + + + PCW_USB_RESET_ENABLE + 1 + + + + true + + + + + + PCW_USB_RESET_SELECT + Share reset pin + + + + true + + + + + + PCW_USB0_RESET_ENABLE + 1 + + + + true + + + + + + PCW_USB0_RESET_IO + MIO 51 + + + + true + + + + + + PCW_USB1_PERIPHERAL_ENABLE + PCW USB1 PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_USB1_USB1_IO + PCW USB1 USB1 IO + <Select> + + + + false + + + + + + PCW_USB1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_USB1_RESET_IO + <Select> + + + + false + + + + + + PCW_I2C0_PERIPHERAL_ENABLE + PCW I2C0 PERIPHERAL ENABLE + 1 + + + + true + + + + + + PCW_I2C0_I2C0_IO + PCW I2C0 I2C0 IO + EMIO + + + + true + + + + + + PCW_I2C0_GRP_INT_ENABLE + 1 + + + + false + + + + + + PCW_I2C0_GRP_INT_IO + PCW I2C0 GRP INT IO + EMIO + + + + false + + + + + + PCW_I2C0_RESET_ENABLE + 0 + + + + false + + + + + + PCW_I2C0_RESET_IO + <Select> + + + + false + + + + + + PCW_I2C1_PERIPHERAL_ENABLE + PCW I2C1 PERIPHERAL ENABLE + 1 + + + + true + + + + + + PCW_I2C1_I2C1_IO + PCW I2C1 I2C1 IO + MIO 12 .. 13 + + + + true + + + + + + PCW_I2C1_GRP_INT_ENABLE + 0 + + + + true + + + + + + PCW_I2C1_GRP_INT_IO + PCW I2C1 GRP INT IO + <Select> + + + + false + + + + + + PCW_I2C_RESET_ENABLE + 0 + + + + true + + + + + + PCW_I2C_RESET_SELECT + <Select> + + + + false + + + + + + PCW_I2C1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_I2C1_RESET_IO + <Select> + + + + false + + + + + + PCW_GPIO_PERIPHERAL_ENABLE + PCW GPIO PERIPHERAL ENABLE + 0 + + + + true + + + + + + PCW_GPIO_MIO_GPIO_ENABLE + 1 + + + + true + + + + + + PCW_GPIO_MIO_GPIO_IO + PCW GPIO MIO GPIO IO + MIO + + + + true + + + + + + PCW_GPIO_EMIO_GPIO_ENABLE + PCW GPIO EMIO GPIO ENABLE + 1 + + + + true + + + + + + PCW_GPIO_EMIO_GPIO_IO + PCW GPIO EMIO GPIO IO + 64 + + + + true + + + + + + PCW_APU_CLK_RATIO_ENABLE + PCW APU CLK RATIO ENABLE + 6:2:1 + + + + true + + + + + + PCW_ENET0_PERIPHERAL_FREQMHZ + PCW ENET0 PERIPHERAL FREQMHZ + 1000 Mbps + + + + true + + + + + + PCW_ENET1_PERIPHERAL_FREQMHZ + PCW ENET1 PERIPHERAL FREQMHZ + 1000 Mbps + + + + false + + + + + + PCW_CPU_PERIPHERAL_CLKSRC + PCW CPU PERIPHERAL CLKSRC + ARM PLL + + + + true + + + + + + PCW_DDR_PERIPHERAL_CLKSRC + PCW DDR PERIPHERAL CLKSRC + DDR PLL + + + + true + + + + + + PCW_SMC_PERIPHERAL_CLKSRC + PCW SMC PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_QSPI_PERIPHERAL_CLKSRC + PCW QSPI PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_SDIO_PERIPHERAL_CLKSRC + PCW SDIO PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_UART_PERIPHERAL_CLKSRC + PCW UART PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_SPI_PERIPHERAL_CLKSRC + PCW SPI PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_CAN_PERIPHERAL_CLKSRC + PCW CAN PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_FCLK0_PERIPHERAL_CLKSRC + PCW FCLK0 PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_FCLK1_PERIPHERAL_CLKSRC + PCW FCLK1 PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_FCLK2_PERIPHERAL_CLKSRC + PCW FCLK2 PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_FCLK3_PERIPHERAL_CLKSRC + PCW FCLK3 PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_ENET0_PERIPHERAL_CLKSRC + PCW ENET0 PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_ENET1_PERIPHERAL_CLKSRC + PCW ENET1 PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_CAN0_PERIPHERAL_CLKSRC + PCW CAN0 PERIPHERAL CLKSRC + External + + + + true + + + + + + PCW_CAN1_PERIPHERAL_CLKSRC + PCW CAN1 PERIPHERAL CLKSRC + External + + + + true + + + + + + PCW_TPIU_PERIPHERAL_CLKSRC + PCW TPIU PERIPHERAL CLKSRC + External + + + + true + + + + + + PCW_TTC0_CLK0_PERIPHERAL_CLKSRC + PCW TTC0 CLK0 PERIPHERAL CLKSRC + CPU_1X + + + + true + + + + + + PCW_TTC0_CLK1_PERIPHERAL_CLKSRC + PCW TTC0 CLK1 PERIPHERAL CLKSRC + CPU_1X + + + + true + + + + + + PCW_TTC0_CLK2_PERIPHERAL_CLKSRC + PCW TTC0 CLK2 PERIPHERAL CLKSRC + CPU_1X + + + + true + + + + + + PCW_TTC1_CLK0_PERIPHERAL_CLKSRC + PCW TTC1 CLK0 PERIPHERAL CLKSRC + CPU_1X + + + + true + + + + + + PCW_TTC1_CLK1_PERIPHERAL_CLKSRC + PCW TTC1 CLK1 PERIPHERAL CLKSRC + CPU_1X + + + + true + + + + + + PCW_TTC1_CLK2_PERIPHERAL_CLKSRC + PCW TTC1 CLK2 PERIPHERAL CLKSRC + CPU_1X + + + + true + + + + + + PCW_WDT_PERIPHERAL_CLKSRC + PCW WDT PERIPHERAL CLKSRC + CPU_1X + + + + true + + + + + + PCW_DCI_PERIPHERAL_CLKSRC + PCW DCI PERIPHERAL CLKSRC + DDR PLL + + + + true + + + + + + PCW_PCAP_PERIPHERAL_CLKSRC + PCW PCAP PERIPHERAL CLKSRC + IO PLL + + + + true + + + + + + PCW_USB_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + + true + + + + + + PCW_ENET_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + + true + + + + + + PCW_I2C_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + + true + + + + + + PCW_MIO_0_PULLUP + PCW MIO 0 PULLUP + enabled + + + + true + + + + + + PCW_MIO_0_IOTYPE + PCW MIO 0 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_0_DIRECTION + PCW MIO 0 DIRECTION + inout + + + + false + + + + + + PCW_MIO_0_SLEW + PCW MIO 0 SLEW + slow + + + + true + + + + + + PCW_MIO_1_PULLUP + PCW MIO 1 PULLUP + enabled + + + + true + + + + + + PCW_MIO_1_IOTYPE + PCW MIO 1 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_1_DIRECTION + PCW MIO 1 DIRECTION + out + + + + false + + + + + + PCW_MIO_1_SLEW + PCW MIO 1 SLEW + slow + + + + true + + + + + + PCW_MIO_2_PULLUP + PCW MIO 2 PULLUP + disabled + + + + false + + + + + + PCW_MIO_2_IOTYPE + PCW MIO 2 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_2_DIRECTION + PCW MIO 2 DIRECTION + inout + + + + false + + + + + + PCW_MIO_2_SLEW + PCW MIO 2 SLEW + slow + + + + true + + + + + + PCW_MIO_3_PULLUP + PCW MIO 3 PULLUP + disabled + + + + false + + + + + + PCW_MIO_3_IOTYPE + PCW MIO 3 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_3_DIRECTION + PCW MIO 3 DIRECTION + inout + + + + false + + + + + + PCW_MIO_3_SLEW + PCW MIO 3 SLEW + slow + + + + true + + + + + + PCW_MIO_4_PULLUP + PCW MIO 4 PULLUP + disabled + + + + false + + + + + + PCW_MIO_4_IOTYPE + PCW MIO 4 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_4_DIRECTION + PCW MIO 4 DIRECTION + inout + + + + false + + + + + + PCW_MIO_4_SLEW + PCW MIO 4 SLEW + slow + + + + true + + + + + + PCW_MIO_5_PULLUP + PCW MIO 5 PULLUP + disabled + + + + false + + + + + + PCW_MIO_5_IOTYPE + PCW MIO 5 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_5_DIRECTION + PCW MIO 5 DIRECTION + inout + + + + false + + + + + + PCW_MIO_5_SLEW + PCW MIO 5 SLEW + slow + + + + true + + + + + + PCW_MIO_6_PULLUP + PCW MIO 6 PULLUP + disabled + + + + false + + + + + + PCW_MIO_6_IOTYPE + PCW MIO 6 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_6_DIRECTION + PCW MIO 6 DIRECTION + out + + + + false + + + + + + PCW_MIO_6_SLEW + PCW MIO 6 SLEW + slow + + + + true + + + + + + PCW_MIO_7_PULLUP + PCW MIO 7 PULLUP + disabled + + + + false + + + + + + PCW_MIO_7_IOTYPE + PCW MIO 7 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_7_DIRECTION + PCW MIO 7 DIRECTION + out + + + + false + + + + + + PCW_MIO_7_SLEW + PCW MIO 7 SLEW + slow + + + + true + + + + + + PCW_MIO_8_PULLUP + PCW MIO 8 PULLUP + disabled + + + + false + + + + + + PCW_MIO_8_IOTYPE + PCW MIO 8 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_8_DIRECTION + PCW MIO 8 DIRECTION + out + + + + false + + + + + + PCW_MIO_8_SLEW + PCW MIO 8 SLEW + slow + + + + true + + + + + + PCW_MIO_9_PULLUP + PCW MIO 9 PULLUP + enabled + + + + true + + + + + + PCW_MIO_9_IOTYPE + PCW MIO 9 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_9_DIRECTION + PCW MIO 9 DIRECTION + inout + + + + false + + + + + + PCW_MIO_9_SLEW + PCW MIO 9 SLEW + slow + + + + true + + + + + + PCW_MIO_10_PULLUP + PCW MIO 10 PULLUP + enabled + + + + true + + + + + + PCW_MIO_10_IOTYPE + PCW MIO 10 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_10_DIRECTION + PCW MIO 10 DIRECTION + in + + + + false + + + + + + PCW_MIO_10_SLEW + PCW MIO 10 SLEW + slow + + + + true + + + + + + PCW_MIO_11_PULLUP + PCW MIO 11 PULLUP + enabled + + + + true + + + + + + PCW_MIO_11_IOTYPE + PCW MIO 11 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_11_DIRECTION + PCW MIO 11 DIRECTION + out + + + + false + + + + + + PCW_MIO_11_SLEW + PCW MIO 11 SLEW + slow + + + + true + + + + + + PCW_MIO_12_PULLUP + PCW MIO 12 PULLUP + enabled + + + + true + + + + + + PCW_MIO_12_IOTYPE + PCW MIO 12 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_12_DIRECTION + PCW MIO 12 DIRECTION + inout + + + + false + + + + + + PCW_MIO_12_SLEW + PCW MIO 12 SLEW + slow + + + + true + + + + + + PCW_MIO_13_PULLUP + PCW MIO 13 PULLUP + enabled + + + + true + + + + + + PCW_MIO_13_IOTYPE + PCW MIO 13 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_13_DIRECTION + PCW MIO 13 DIRECTION + inout + + + + false + + + + + + PCW_MIO_13_SLEW + PCW MIO 13 SLEW + slow + + + + true + + + + + + PCW_MIO_14_PULLUP + PCW MIO 14 PULLUP + enabled + + + + true + + + + + + PCW_MIO_14_IOTYPE + PCW MIO 14 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_14_DIRECTION + PCW MIO 14 DIRECTION + in + + + + false + + + + + + PCW_MIO_14_SLEW + PCW MIO 14 SLEW + slow + + + + true + + + + + + PCW_MIO_15_PULLUP + PCW MIO 15 PULLUP + enabled + + + + true + + + + + + PCW_MIO_15_IOTYPE + PCW MIO 15 IOTYPE + LVCMOS 3.3V + + + + true + + + + + + PCW_MIO_15_DIRECTION + PCW MIO 15 DIRECTION + out + + + + false + + + + + + PCW_MIO_15_SLEW + PCW MIO 15 SLEW + slow + + + + true + + + + + + PCW_MIO_16_PULLUP + PCW MIO 16 PULLUP + enabled + + + + true + + + + + + PCW_MIO_16_IOTYPE + PCW MIO 16 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_16_DIRECTION + PCW MIO 16 DIRECTION + out + + + + false + + + + + + PCW_MIO_16_SLEW + PCW MIO 16 SLEW + slow + + + + true + + + + + + PCW_MIO_17_PULLUP + PCW MIO 17 PULLUP + enabled + + + + true + + + + + + PCW_MIO_17_IOTYPE + PCW MIO 17 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_17_DIRECTION + PCW MIO 17 DIRECTION + out + + + + false + + + + + + PCW_MIO_17_SLEW + PCW MIO 17 SLEW + slow + + + + true + + + + + + PCW_MIO_18_PULLUP + PCW MIO 18 PULLUP + enabled + + + + true + + + + + + PCW_MIO_18_IOTYPE + PCW MIO 18 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_18_DIRECTION + PCW MIO 18 DIRECTION + out + + + + false + + + + + + PCW_MIO_18_SLEW + PCW MIO 18 SLEW + slow + + + + true + + + + + + PCW_MIO_19_PULLUP + PCW MIO 19 PULLUP + enabled + + + + true + + + + + + PCW_MIO_19_IOTYPE + PCW MIO 19 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_19_DIRECTION + PCW MIO 19 DIRECTION + out + + + + false + + + + + + PCW_MIO_19_SLEW + PCW MIO 19 SLEW + slow + + + + true + + + + + + PCW_MIO_20_PULLUP + PCW MIO 20 PULLUP + enabled + + + + true + + + + + + PCW_MIO_20_IOTYPE + PCW MIO 20 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_20_DIRECTION + PCW MIO 20 DIRECTION + out + + + + false + + + + + + PCW_MIO_20_SLEW + PCW MIO 20 SLEW + slow + + + + true + + + + + + PCW_MIO_21_PULLUP + PCW MIO 21 PULLUP + enabled + + + + true + + + + + + PCW_MIO_21_IOTYPE + PCW MIO 21 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_21_DIRECTION + PCW MIO 21 DIRECTION + out + + + + false + + + + + + PCW_MIO_21_SLEW + PCW MIO 21 SLEW + slow + + + + true + + + + + + PCW_MIO_22_PULLUP + PCW MIO 22 PULLUP + enabled + + + + true + + + + + + PCW_MIO_22_IOTYPE + PCW MIO 22 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_22_DIRECTION + PCW MIO 22 DIRECTION + in + + + + false + + + + + + PCW_MIO_22_SLEW + PCW MIO 22 SLEW + slow + + + + true + + + + + + PCW_MIO_23_PULLUP + PCW MIO 23 PULLUP + enabled + + + + true + + + + + + PCW_MIO_23_IOTYPE + PCW MIO 23 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_23_DIRECTION + PCW MIO 23 DIRECTION + in + + + + false + + + + + + PCW_MIO_23_SLEW + PCW MIO 23 SLEW + slow + + + + true + + + + + + PCW_MIO_24_PULLUP + PCW MIO 24 PULLUP + enabled + + + + true + + + + + + PCW_MIO_24_IOTYPE + PCW MIO 24 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_24_DIRECTION + PCW MIO 24 DIRECTION + in + + + + false + + + + + + PCW_MIO_24_SLEW + PCW MIO 24 SLEW + slow + + + + true + + + + + + PCW_MIO_25_PULLUP + PCW MIO 25 PULLUP + enabled + + + + true + + + + + + PCW_MIO_25_IOTYPE + PCW MIO 25 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_25_DIRECTION + PCW MIO 25 DIRECTION + in + + + + false + + + + + + PCW_MIO_25_SLEW + PCW MIO 25 SLEW + slow + + + + true + + + + + + PCW_MIO_26_PULLUP + PCW MIO 26 PULLUP + enabled + + + + true + + + + + + PCW_MIO_26_IOTYPE + PCW MIO 26 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_26_DIRECTION + PCW MIO 26 DIRECTION + in + + + + false + + + + + + PCW_MIO_26_SLEW + PCW MIO 26 SLEW + slow + + + + true + + + + + + PCW_MIO_27_PULLUP + PCW MIO 27 PULLUP + enabled + + + + true + + + + + + PCW_MIO_27_IOTYPE + PCW MIO 27 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_27_DIRECTION + PCW MIO 27 DIRECTION + in + + + + false + + + + + + PCW_MIO_27_SLEW + PCW MIO 27 SLEW + slow + + + + true + + + + + + PCW_MIO_28_PULLUP + PCW MIO 28 PULLUP + enabled + + + + true + + + + + + PCW_MIO_28_IOTYPE + PCW MIO 28 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_28_DIRECTION + PCW MIO 28 DIRECTION + inout + + + + false + + + + + + PCW_MIO_28_SLEW + PCW MIO 28 SLEW + slow + + + + true + + + + + + PCW_MIO_29_PULLUP + PCW MIO 29 PULLUP + enabled + + + + true + + + + + + PCW_MIO_29_IOTYPE + PCW MIO 29 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_29_DIRECTION + PCW MIO 29 DIRECTION + in + + + + false + + + + + + PCW_MIO_29_SLEW + PCW MIO 29 SLEW + slow + + + + true + + + + + + PCW_MIO_30_PULLUP + PCW MIO 30 PULLUP + enabled + + + + true + + + + + + PCW_MIO_30_IOTYPE + PCW MIO 30 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_30_DIRECTION + PCW MIO 30 DIRECTION + out + + + + false + + + + + + PCW_MIO_30_SLEW + PCW MIO 30 SLEW + slow + + + + true + + + + + + PCW_MIO_31_PULLUP + PCW MIO 31 PULLUP + enabled + + + + true + + + + + + PCW_MIO_31_IOTYPE + PCW MIO 31 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_31_DIRECTION + PCW MIO 31 DIRECTION + in + + + + false + + + + + + PCW_MIO_31_SLEW + PCW MIO 31 SLEW + slow + + + + true + + + + + + PCW_MIO_32_PULLUP + PCW MIO 32 PULLUP + enabled + + + + true + + + + + + PCW_MIO_32_IOTYPE + PCW MIO 32 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_32_DIRECTION + PCW MIO 32 DIRECTION + inout + + + + false + + + + + + PCW_MIO_32_SLEW + PCW MIO 32 SLEW + slow + + + + true + + + + + + PCW_MIO_33_PULLUP + PCW MIO 33 PULLUP + enabled + + + + true + + + + + + PCW_MIO_33_IOTYPE + PCW MIO 33 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_33_DIRECTION + PCW MIO 33 DIRECTION + inout + + + + false + + + + + + PCW_MIO_33_SLEW + PCW MIO 33 SLEW + slow + + + + true + + + + + + PCW_MIO_34_PULLUP + PCW MIO 34 PULLUP + enabled + + + + true + + + + + + PCW_MIO_34_IOTYPE + PCW MIO 34 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_34_DIRECTION + PCW MIO 34 DIRECTION + inout + + + + false + + + + + + PCW_MIO_34_SLEW + PCW MIO 34 SLEW + slow + + + + true + + + + + + PCW_MIO_35_PULLUP + PCW MIO 35 PULLUP + enabled + + + + true + + + + + + PCW_MIO_35_IOTYPE + PCW MIO 35 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_35_DIRECTION + PCW MIO 35 DIRECTION + inout + + + + false + + + + + + PCW_MIO_35_SLEW + PCW MIO 35 SLEW + slow + + + + true + + + + + + PCW_MIO_36_PULLUP + PCW MIO 36 PULLUP + enabled + + + + true + + + + + + PCW_MIO_36_IOTYPE + PCW MIO 36 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_36_DIRECTION + PCW MIO 36 DIRECTION + in + + + + false + + + + + + PCW_MIO_36_SLEW + PCW MIO 36 SLEW + slow + + + + true + + + + + + PCW_MIO_37_PULLUP + PCW MIO 37 PULLUP + enabled + + + + true + + + + + + PCW_MIO_37_IOTYPE + PCW MIO 37 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_37_DIRECTION + PCW MIO 37 DIRECTION + inout + + + + false + + + + + + PCW_MIO_37_SLEW + PCW MIO 37 SLEW + slow + + + + true + + + + + + PCW_MIO_38_PULLUP + PCW MIO 38 PULLUP + enabled + + + + true + + + + + + PCW_MIO_38_IOTYPE + PCW MIO 38 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_38_DIRECTION + PCW MIO 38 DIRECTION + inout + + + + false + + + + + + PCW_MIO_38_SLEW + PCW MIO 38 SLEW + slow + + + + true + + + + + + PCW_MIO_39_PULLUP + PCW MIO 39 PULLUP + enabled + + + + true + + + + + + PCW_MIO_39_IOTYPE + PCW MIO 39 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_39_DIRECTION + PCW MIO 39 DIRECTION + inout + + + + false + + + + + + PCW_MIO_39_SLEW + PCW MIO 39 SLEW + slow + + + + true + + + + + + PCW_MIO_40_PULLUP + PCW MIO 40 PULLUP + enabled + + + + true + + + + + + PCW_MIO_40_IOTYPE + PCW MIO 40 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_40_DIRECTION + PCW MIO 40 DIRECTION + inout + + + + false + + + + + + PCW_MIO_40_SLEW + PCW MIO 40 SLEW + slow + + + + true + + + + + + PCW_MIO_41_PULLUP + PCW MIO 41 PULLUP + enabled + + + + true + + + + + + PCW_MIO_41_IOTYPE + PCW MIO 41 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_41_DIRECTION + PCW MIO 41 DIRECTION + inout + + + + false + + + + + + PCW_MIO_41_SLEW + PCW MIO 41 SLEW + slow + + + + true + + + + + + PCW_MIO_42_PULLUP + PCW MIO 42 PULLUP + enabled + + + + true + + + + + + PCW_MIO_42_IOTYPE + PCW MIO 42 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_42_DIRECTION + PCW MIO 42 DIRECTION + inout + + + + false + + + + + + PCW_MIO_42_SLEW + PCW MIO 42 SLEW + slow + + + + true + + + + + + PCW_MIO_43_PULLUP + PCW MIO 43 PULLUP + enabled + + + + true + + + + + + PCW_MIO_43_IOTYPE + PCW MIO 43 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_43_DIRECTION + PCW MIO 43 DIRECTION + inout + + + + false + + + + + + PCW_MIO_43_SLEW + PCW MIO 43 SLEW + slow + + + + true + + + + + + PCW_MIO_44_PULLUP + PCW MIO 44 PULLUP + enabled + + + + true + + + + + + PCW_MIO_44_IOTYPE + PCW MIO 44 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_44_DIRECTION + PCW MIO 44 DIRECTION + inout + + + + false + + + + + + PCW_MIO_44_SLEW + PCW MIO 44 SLEW + slow + + + + true + + + + + + PCW_MIO_45_PULLUP + PCW MIO 45 PULLUP + enabled + + + + true + + + + + + PCW_MIO_45_IOTYPE + PCW MIO 45 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_45_DIRECTION + PCW MIO 45 DIRECTION + inout + + + + false + + + + + + PCW_MIO_45_SLEW + PCW MIO 45 SLEW + slow + + + + true + + + + + + PCW_MIO_46_PULLUP + PCW MIO 46 PULLUP + enabled + + + + true + + + + + + PCW_MIO_46_IOTYPE + PCW MIO 46 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_46_DIRECTION + PCW MIO 46 DIRECTION + in + + + + false + + + + + + PCW_MIO_46_SLEW + PCW MIO 46 SLEW + slow + + + + true + + + + + + PCW_MIO_47_PULLUP + PCW MIO 47 PULLUP + enabled + + + + true + + + + + + PCW_MIO_47_IOTYPE + PCW MIO 47 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_47_DIRECTION + PCW MIO 47 DIRECTION + in + + + + false + + + + + + PCW_MIO_47_SLEW + PCW MIO 47 SLEW + slow + + + + true + + + + + + PCW_MIO_48_PULLUP + PCW MIO 48 PULLUP + enabled + + + + true + + + + + + PCW_MIO_48_IOTYPE + PCW MIO 48 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_48_DIRECTION + PCW MIO 48 DIRECTION + out + + + + false + + + + + + PCW_MIO_48_SLEW + PCW MIO 48 SLEW + slow + + + + true + + + + + + PCW_MIO_49_PULLUP + PCW MIO 49 PULLUP + enabled + + + + true + + + + + + PCW_MIO_49_IOTYPE + PCW MIO 49 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_49_DIRECTION + PCW MIO 49 DIRECTION + in + + + + false + + + + + + PCW_MIO_49_SLEW + PCW MIO 49 SLEW + slow + + + + true + + + + + + PCW_MIO_50_PULLUP + PCW MIO 50 PULLUP + enabled + + + + true + + + + + + PCW_MIO_50_IOTYPE + PCW MIO 50 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_50_DIRECTION + PCW MIO 50 DIRECTION + inout + + + + false + + + + + + PCW_MIO_50_SLEW + PCW MIO 50 SLEW + slow + + + + true + + + + + + PCW_MIO_51_PULLUP + PCW MIO 51 PULLUP + disabled + + + + true + + + + + + PCW_MIO_51_IOTYPE + PCW MIO 51 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_51_DIRECTION + PCW MIO 51 DIRECTION + out + + + + false + + + + + + PCW_MIO_51_SLEW + PCW MIO 51 SLEW + slow + + + + true + + + + + + PCW_MIO_52_PULLUP + PCW MIO 52 PULLUP + enabled + + + + true + + + + + + PCW_MIO_52_IOTYPE + PCW MIO 52 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_52_DIRECTION + PCW MIO 52 DIRECTION + out + + + + false + + + + + + PCW_MIO_52_SLEW + PCW MIO 52 SLEW + slow + + + + true + + + + + + PCW_MIO_53_PULLUP + PCW MIO 53 PULLUP + enabled + + + + true + + + + + + PCW_MIO_53_IOTYPE + PCW MIO 53 IOTYPE + LVCMOS 1.8V + + + + true + + + + + + PCW_MIO_53_DIRECTION + PCW MIO 53 DIRECTION + inout + + + + false + + + + + + PCW_MIO_53_SLEW + PCW MIO 53 SLEW + slow + + + + true + + + + + + preset + preset + None + + + PCW_UIPARAM_GENERATE_SUMMARY + PCW UIPARAM GENERATE SUMMARY + NA + + + PCW_MIO_TREE_PERIPHERALS + PCW MIO TREE PERIPHERALS + GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#I2C 1#I2C 1#CAN 0#CAN 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#UART 1#UART 1#GPIO#USB Reset#Enet 0#Enet 0 + + + + true + + + + + + PCW_MIO_TREE_SIGNALS + PCW MIO TREE SIGNALS + gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#scl#sda#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#wp#tx#rx#gpio[50]#reset#mdc#mdio + + + + true + + + + + + PCW_PS7_SI_REV + PCW PS7 SI REV + PRODUCTION + + + PCW_FPGA_FCLK0_ENABLE + PCW FPGA FCLK0 ENABLE + 1 + + + + optional + true + + + + + + PCW_FPGA_FCLK1_ENABLE + PCW FPGA FCLK1 ENABLE + 1 + + + + optional + true + + + + + + PCW_FPGA_FCLK2_ENABLE + PCW FPGA FCLK2 ENABLE + 1 + + + + optional + true + + + + + + PCW_FPGA_FCLK3_ENABLE + PCW FPGA FCLK3 ENABLE + 1 + + + + optional + true + + + + + + PCW_NOR_SRAM_CS0_T_TR + PCW NOR SRAM CS0 T TR + 1 + + + + true + + + + + + PCW_NOR_SRAM_CS0_T_PC + PCW NOR SRAM CS0 T PC + 1 + + + + true + + + + + + PCW_NOR_SRAM_CS0_T_WP + PCW NOR SRAM CS0 T WP + 1 + + + + true + + + + + + PCW_NOR_SRAM_CS0_T_CEOE + PCW NOR SRAM CS0 T CEOE + 1 + + + + true + + + + + + PCW_NOR_SRAM_CS0_T_WC + PCW NOR SRAM CS0 T WC + 2 + + + + true + + + + + + PCW_NOR_SRAM_CS0_T_RC + PCW NOR SRAM CS0 T RC + 2 + + + + true + + + + + + PCW_NOR_SRAM_CS0_WE_TIME + PCW NOR SRAM CS0 WE TIME + 0 + + + + true + + + + + + PCW_NOR_SRAM_CS1_T_TR + PCW NOR SRAM CS1 T TR + 1 + + + + true + + + + + + PCW_NOR_SRAM_CS1_T_PC + PCW NOR SRAM CS1 T PC + 1 + + + + true + + + + + + PCW_NOR_SRAM_CS1_T_WP + PCW NOR SRAM CS1 T WP + 1 + + + + true + + + + + + PCW_NOR_SRAM_CS1_T_CEOE + PCW NOR SRAM CS1 T CEOE + 1 + + + + true + + + + + + PCW_NOR_SRAM_CS1_T_WC + PCW NOR SRAM CS1 T WC + 2 + + + + true + + + + + + PCW_NOR_SRAM_CS1_T_RC + PCW NOR SRAM CS1 T RC + 2 + + + + true + + + + + + PCW_NOR_SRAM_CS1_WE_TIME + PCW NOR SRAM CS1 WE TIME + 0 + + + + true + + + + + + PCW_NOR_CS0_T_TR + PCW NOR CS0 T TR + 1 + + + + true + + + + + + PCW_NOR_CS0_T_PC + PCW NOR CS0 T PC + 1 + + + + true + + + + + + PCW_NOR_CS0_T_WP + PCW NOR CS0 T WP + 1 + + + + true + + + + + + PCW_NOR_CS0_T_CEOE + PCW NOR CS0 T CEOE + 1 + + + + true + + + + + + PCW_NOR_CS0_T_WC + PCW NOR CS0 T WC + 2 + + + + true + + + + + + PCW_NOR_CS0_T_RC + PCW NOR CS0 T RC + 2 + + + + true + + + + + + PCW_NOR_CS0_WE_TIME + PCW NOR CS0 WE TIME + 0 + + + + true + + + + + + PCW_NOR_CS1_T_TR + PCW NOR CS1 T TR + 1 + + + + true + + + + + + PCW_NOR_CS1_T_PC + PCW NOR CS1 T PC + 1 + + + + true + + + + + + PCW_NOR_CS1_T_WP + PCW NOR CS1 T WP + 1 + + + + true + + + + + + PCW_NOR_CS1_T_CEOE + PCW NOR CS1 T CEOE + 1 + + + + true + + + + + + PCW_NOR_CS1_T_WC + PCW NOR CS1 T WC + 2 + + + + true + + + + + + PCW_NOR_CS1_T_RC + PCW NOR CS1 T RC + 2 + + + + true + + + + + + PCW_NOR_CS1_WE_TIME + PCW NOR CS1 WE TIME + 0 + + + + true + + + + + + PCW_NAND_CYCLES_T_RR + PCW NAND CYCLES T RR + 1 + + + + true + + + + + + PCW_NAND_CYCLES_T_AR + PCW NAND CYCLES T AR + 1 + + + + true + + + + + + PCW_NAND_CYCLES_T_CLR + PCW NAND CYCLES T CLR + 1 + + + + true + + + + + + PCW_NAND_CYCLES_T_WP + PCW NAND CYCLES T WP + 1 + + + + true + + + + + + PCW_NAND_CYCLES_T_REA + PCW NAND CYCLES T REA + 1 + + + + true + + + + + + PCW_NAND_CYCLES_T_WC + PCW NAND CYCLES T WC + 2 + + + + true + + + + + + PCW_NAND_CYCLES_T_RC + PCW NAND CYCLES T RC + 2 + + + + true + + + + + + PCW_SMC_CYCLE_T0 + PCW SMC CYCLE T0 + NA + + + PCW_SMC_CYCLE_T1 + PCW SMC CYCLE T1 + NA + + + PCW_SMC_CYCLE_T2 + PCW SMC CYCLE T2 + NA + + + PCW_SMC_CYCLE_T3 + PCW SMC CYCLE T3 + NA + + + PCW_SMC_CYCLE_T4 + PCW SMC CYCLE T4 + NA + + + PCW_SMC_CYCLE_T5 + PCW SMC CYCLE T5 + NA + + + PCW_SMC_CYCLE_T6 + PCW SMC CYCLE T6 + NA + + + PCW_PACKAGE_NAME + PCW PACKAGE NAME + clg400 + + + Component_Name + z_turn_processing_system7_0_0 + + + + + + azynq + qzynq + zynq + + + /Embedded Processing/Processor/ + + ZYNQ7 Processing System + 1 + + xilinx.com:ip:processing_system7:5.01 + xilinx.com:ip:processing_system7:5.2 + xilinx.com:ip:processing_system7:5.3 + xilinx.com:ip:processing_system7:5.4 + + 2015-06-23T16:16:11Z + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2015.2 + + + \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.upgrade_log b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.upgrade_log new file mode 100644 index 0000000..7ac9eb5 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.upgrade_log @@ -0,0 +1,16 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +| Date : Fri Jul 10 13:44:15 2015 +| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7z020clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'z_turn_ps_7_axi_periph_0' + +1. Summary +---------- + +SUCCESS in the update of z_turn_ps_7_axi_periph_0 (xilinx.com:ip:axi_interconnect:2.1 (Rev. 6)) to current project options. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.xci b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.xci new file mode 100644 index 0000000..399ed8a --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.xci @@ -0,0 +1,341 @@ + + + xilinx.com + xci + unknown + 1.0 + + + z_turn_ps_7_axi_periph_0 + + + 1 + 1 + 0 + 0 + 0 + 32 + 0 + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + z_turn_ps_7_axi_periph_0 + zynq + xc7z020 + clg400 + -1 + C + + VERILOG + MIXED + TRUE + TRUE + + TRUE + 2015.2 + 6 + GLOBAL + + . + ../../../../ipshared + IP_Integrator_AppCore + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.xml new file mode 100644 index 0000000..91e4100 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.xml @@ -0,0 +1,4459 @@ + + + xilinx.com + customized_ip + z_turn_ps_7_axi_periph_0 + 1.0 + + + + choices_0 + 0 + 1 + 2 + + + choices_1 + 0 + 1 + + + choices_2 + 0 + 1 + + + choices_3 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choices_4 + 2 + 4 + 8 + 16 + 32 + 64 + + + choices_5 + 2 + 4 + 8 + 16 + 32 + 64 + + + choices_6 + 0 + 1 + 3 + 4 + + + choices_7 + 0 + 1 + 3 + 4 + + + choices_8 + 0 + 1 + 3 + 4 + + + choices_9 + 0 + 1 + 3 + 4 + + + choices_10 + 0 + 1 + 3 + 4 + + + choices_11 + 0 + 1 + 3 + 4 + + + choices_12 + 0 + 1 + 3 + 4 + + + choices_13 + 0 + 1 + 3 + 4 + + + choices_14 + 0 + 1 + 3 + 4 + + + choices_15 + 0 + 1 + 3 + 4 + + + choices_16 + 0 + 1 + 3 + 4 + + + choices_17 + 0 + 1 + 3 + 4 + + + choices_18 + 0 + 1 + 3 + 4 + + + choices_19 + 0 + 1 + 3 + 4 + + + choices_20 + 0 + 1 + 3 + 4 + + + choices_21 + 0 + 1 + 3 + 4 + + + choices_22 + 0 + 1 + 3 + 4 + + + choices_23 + 0 + 1 + 3 + 4 + + + choices_24 + 0 + 1 + 3 + 4 + + + choices_25 + 0 + 1 + 3 + 4 + + + choices_26 + 0 + 1 + 3 + 4 + + + choices_27 + 0 + 1 + 3 + 4 + + + choices_28 + 0 + 1 + 3 + 4 + + + choices_29 + 0 + 1 + 3 + 4 + + + choices_30 + 0 + 1 + 3 + 4 + + + choices_31 + 0 + 1 + 3 + 4 + + + choices_32 + 0 + 1 + 3 + 4 + + + choices_33 + 0 + 1 + 3 + 4 + + + choices_34 + 0 + 1 + 3 + 4 + + + choices_35 + 0 + 1 + 3 + 4 + + + choices_36 + 0 + 1 + 3 + 4 + + + choices_37 + 0 + 1 + 3 + 4 + + + choices_38 + 0 + 1 + 3 + 4 + + + choices_39 + 0 + 1 + 3 + 4 + + + choices_40 + 0 + 1 + 3 + 4 + + + choices_41 + 0 + 1 + 3 + 4 + + + choices_42 + 0 + 1 + 3 + 4 + + + choices_43 + 0 + 1 + 3 + 4 + + + choices_44 + 0 + 1 + 3 + 4 + + + choices_45 + 0 + 1 + 3 + 4 + + + choices_46 + 0 + 1 + 3 + 4 + + + choices_47 + 0 + 1 + 3 + 4 + + + choices_48 + 0 + 1 + 3 + 4 + + + choices_49 + 0 + 1 + 3 + 4 + + + choices_50 + 0 + 1 + 3 + 4 + + + choices_51 + 0 + 1 + 3 + 4 + + + choices_52 + 0 + 1 + 3 + 4 + + + choices_53 + 0 + 1 + 3 + 4 + + + choices_54 + 0 + 1 + 3 + 4 + + + choices_55 + 0 + 1 + 3 + 4 + + + choices_56 + 0 + 1 + 3 + 4 + + + choices_57 + 0 + 1 + 3 + 4 + + + choices_58 + 0 + 1 + 3 + 4 + + + choices_59 + 0 + 1 + 3 + 4 + + + choices_60 + 0 + 1 + 3 + 4 + + + choices_61 + 0 + 1 + 3 + 4 + + + choices_62 + 0 + 1 + 3 + 4 + + + choices_63 + 0 + 1 + 3 + 4 + + + choices_64 + 0 + 1 + 3 + 4 + + + choices_65 + 0 + 1 + 3 + 4 + + + choices_66 + 0 + 1 + 3 + 4 + + + choices_67 + 0 + 1 + 3 + 4 + + + choices_68 + 0 + 1 + 3 + 4 + + + choices_69 + 0 + 1 + 3 + 4 + + + choices_70 + 0 + 1 + 2 + + + choices_71 + 0 + 1 + 2 + + + choices_72 + 0 + 1 + 2 + + + choices_73 + 0 + 1 + 2 + + + choices_74 + 0 + 1 + 2 + + + choices_75 + 0 + 1 + 2 + + + choices_76 + 0 + 1 + 2 + + + choices_77 + 0 + 1 + 2 + + + choices_78 + 0 + 1 + 2 + + + choices_79 + 0 + 1 + 2 + + + choices_80 + 0 + 1 + 2 + + + choices_81 + 0 + 1 + 2 + + + choices_82 + 0 + 1 + 2 + + + choices_83 + 0 + 1 + 2 + + + choices_84 + 0 + 1 + 2 + + + choices_85 + 0 + 1 + 2 + + + choices_86 + 0 + 1 + 2 + + + choices_87 + 0 + 1 + 2 + + + choices_88 + 0 + 1 + 2 + + + choices_89 + 0 + 1 + 2 + + + choices_90 + 0 + 1 + 2 + + + choices_91 + 0 + 1 + 2 + + + choices_92 + 0 + 1 + 2 + + + choices_93 + 0 + 1 + 2 + + + choices_94 + 0 + 1 + 2 + + + choices_95 + 0 + 1 + 2 + + + choices_96 + 0 + 1 + 2 + + + choices_97 + 0 + 1 + 2 + + + choices_98 + 0 + 1 + 2 + + + choices_99 + 0 + 1 + 2 + + + choices_100 + 0 + 1 + 2 + + + choices_101 + 0 + 1 + 2 + + + choices_102 + 0 + 1 + 2 + + + choices_103 + 0 + 1 + 2 + + + choices_104 + 0 + 1 + 2 + + + choices_105 + 0 + 1 + 2 + + + choices_106 + 0 + 1 + 2 + + + choices_107 + 0 + 1 + 2 + + + choices_108 + 0 + 1 + 2 + + + choices_109 + 0 + 1 + 2 + + + choices_110 + 0 + 1 + 2 + + + choices_111 + 0 + 1 + 2 + + + choices_112 + 0 + 1 + 2 + + + choices_113 + 0 + 1 + 2 + + + choices_114 + 0 + 1 + 2 + + + choices_115 + 0 + 1 + 2 + + + choices_116 + 0 + 1 + 2 + + + choices_117 + 0 + 1 + 2 + + + choices_118 + 0 + 1 + 2 + + + choices_119 + 0 + 1 + 2 + + + choices_120 + 0 + 1 + 2 + + + choices_121 + 0 + 1 + 2 + + + choices_122 + 0 + 1 + 2 + + + choices_123 + 0 + 1 + 2 + + + choices_124 + 0 + 1 + 2 + + + choices_125 + 0 + 1 + 2 + + + choices_126 + 0 + 1 + 2 + + + choices_127 + 0 + 1 + 2 + + + choices_128 + 0 + 1 + 2 + + + choices_129 + 0 + 1 + 2 + + + choices_130 + 0 + 1 + 2 + + + choices_131 + 0 + 1 + 2 + + + choices_132 + 0 + 1 + 2 + + + choices_133 + 0 + 1 + 2 + + + choices_134 + 0 + 1 + 3 + 4 + + + choices_135 + 0 + 1 + 3 + 4 + + + choices_136 + 0 + 1 + 3 + 4 + + + choices_137 + 0 + 1 + 3 + 4 + + + choices_138 + 0 + 1 + 3 + 4 + + + choices_139 + 0 + 1 + 3 + 4 + + + choices_140 + 0 + 1 + 3 + 4 + + + choices_141 + 0 + 1 + 3 + 4 + + + choices_142 + 0 + 1 + 3 + 4 + + + choices_143 + 0 + 1 + 3 + 4 + + + choices_144 + 0 + 1 + 3 + 4 + + + choices_145 + 0 + 1 + 3 + 4 + + + choices_146 + 0 + 1 + 3 + 4 + + + choices_147 + 0 + 1 + 3 + 4 + + + choices_148 + 0 + 1 + 3 + 4 + + + choices_149 + 0 + 1 + 3 + 4 + + + choices_150 + 0 + 1 + 2 + + + choices_151 + 0 + 1 + 2 + + + choices_152 + 0 + 1 + 2 + + + choices_153 + 0 + 1 + 2 + + + choices_154 + 0 + 1 + 2 + + + choices_155 + 0 + 1 + 2 + + + choices_156 + 0 + 1 + 2 + + + choices_157 + 0 + 1 + 2 + + + choices_158 + 0 + 1 + 2 + + + choices_159 + 0 + 1 + 2 + + + choices_160 + 0 + 1 + 2 + + + choices_161 + 0 + 1 + 2 + + + choices_162 + 0 + 1 + 2 + + + choices_163 + 0 + 1 + 2 + + + choices_164 + 0 + 1 + 2 + + + choices_165 + 0 + 1 + 2 + + + choices_166 + 0 + 1 + + + choices_167 + 0 + 1 + + + choices_168 + 0 + 1 + + + choices_169 + 0 + 1 + + + choices_170 + 0 + 1 + + + choices_171 + 0 + 1 + + + choices_172 + 0 + 1 + + + choices_173 + 0 + 1 + + + choices_174 + 0 + 1 + + + choices_175 + 0 + 1 + + + choices_176 + 0 + 1 + + + choices_177 + 0 + 1 + + + choices_178 + 0 + 1 + + + choices_179 + 0 + 1 + + + choices_180 + 0 + 1 + + + choices_181 + 0 + 1 + + + choices_182 + 0 + 1 + + + choices_183 + 0 + 1 + + + choices_184 + 0 + 1 + + + choices_185 + 0 + 1 + + + choices_186 + 0 + 1 + + + choices_187 + 0 + 1 + + + choices_188 + 0 + 1 + + + choices_189 + 0 + 1 + + + choices_190 + 0 + 1 + + + choices_191 + 0 + 1 + + + choices_192 + 0 + 1 + + + choices_193 + 0 + 1 + + + choices_194 + 0 + 1 + + + choices_195 + 0 + 1 + + + choices_196 + 0 + 1 + + + choices_197 + 0 + 1 + + + choices_198 + 0 + 1 + + + choices_199 + 0 + 1 + + + choices_200 + 0 + 1 + + + choices_201 + 0 + 1 + + + choices_202 + 0 + 1 + + + choices_203 + 0 + 1 + + + choices_204 + 0 + 1 + + + choices_205 + 0 + 1 + + + choices_206 + 0 + 1 + + + choices_207 + 0 + 1 + + + choices_208 + 0 + 1 + + + choices_209 + 0 + 1 + + + choices_210 + 0 + 1 + + + choices_211 + 0 + 1 + + + choices_212 + 0 + 1 + + + choices_213 + 0 + 1 + + + choices_214 + 0 + 1 + + + choices_215 + 0 + 1 + + + choices_216 + 0 + 1 + + + choices_217 + 0 + 1 + + + choices_218 + 0 + 1 + + + choices_219 + 0 + 1 + + + choices_220 + 0 + 1 + + + choices_221 + 0 + 1 + + + choices_222 + 0 + 1 + + + choices_223 + 0 + 1 + + + choices_224 + 0 + 1 + + + choices_225 + 0 + 1 + + + choices_226 + 0 + 1 + + + choices_227 + 0 + 1 + + + choices_228 + 0 + 1 + + + choices_229 + 0 + 1 + + + choices_230 + 0 + 1 + + + choices_231 + 0 + 1 + + + choices_232 + 0 + 1 + + + choices_233 + 0 + 1 + + + choices_234 + 0 + 1 + + + choices_235 + 0 + 1 + + + choices_236 + 0 + 1 + + + choices_237 + 0 + 1 + + + choices_238 + 0 + 1 + + + choices_239 + 0 + 1 + + + choices_240 + 0 + 1 + + + choices_241 + 0 + 1 + + + choices_242 + 0 + 1 + + + choices_243 + 0 + 1 + + + choices_244 + 0 + 1 + + + choices_245 + 0 + 1 + + + choices_246 + 0 + 1 + + + choices_247 + 0 + 1 + + + choices_248 + 0 + 1 + + + choices_249 + 0 + 1 + + + choices_250 + 0 + 1 + + + choices_251 + 0 + 1 + + + choices_252 + 0 + 1 + + + choices_253 + 0 + 1 + + + choices_254 + 0 + 1 + + + choices_255 + 0 + 1 + + + choices_256 + 0 + 1 + + + choices_257 + 0 + 1 + + + choices_258 + 0 + 1 + + + choices_259 + 0 + 1 + + + choices_260 + 0 + 1 + + + choices_261 + 0 + 1 + + + choices_262 + 0 + 1 + + + choices_263 + 0 + 1 + + + choices_264 + 0 + 1 + + + choices_265 + 0 + 1 + + + choices_266 + 0 + 1 + + + choices_267 + 0 + 1 + + + choices_268 + 0 + 1 + + + choices_269 + 0 + 1 + + + choices_270 + 0 + 1 + + + choices_271 + 0 + 1 + + + choices_272 + 0 + 1 + + + choices_273 + 0 + 1 + + + choices_274 + 0 + 1 + + + choices_275 + 0 + 1 + + + choices_276 + 0 + 1 + + + choices_277 + 0 + 1 + + + choices_278 + 0 + 1 + + + choices_279 + 0 + 1 + + + choices_280 + 0 + 1 + + + choices_281 + 0 + 1 + + + choices_282 + 0 + 1 + + + choices_283 + 0 + 1 + + + choices_284 + 0 + 1 + + + choices_285 + 0 + 1 + + + choices_286 + 0 + 1 + + + choices_287 + 0 + 1 + + + choices_288 + 0 + 1 + + + choices_289 + 0 + 1 + + + choices_290 + 0 + 1 + + + choices_291 + 0 + 1 + + + choices_292 + 0 + 1 + + + choices_293 + 0 + 1 + + + The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices + + + NUM_SI + Number of Slave Interfaces + 1 + + + NUM_MI + Number of Master Interfaces + 1 + + + STRATEGY + Interconnect Optimization Strategy + 0 + + + ENABLE_ADVANCED_OPTIONS + Enable Advanced Configuration Options + 0 + + + ENABLE_PROTOCOL_CHECKERS + Enable Protocol Checkers and mark interfaces for debug + 0 + + + XBAR_DATA_WIDTH + Data Width of the AXI Crossbar + 32 + + + PCHK_WAITS + Maximum number of idle cycles for READY monitoring + 0 + + + PCHK_MAX_RD_BURSTS + Maximum outstanding READ Transactions per ID + 2 + + + PCHK_MAX_WR_BURSTS + Maximum outstanding WRITE Transactions per ID + 2 + + + SYNCHRONIZATION_STAGES + Synchronization Stages + 2 + + + M00_HAS_REGSLICE + Enable Register Slice on interface M00_AXI + 0 + + + M01_HAS_REGSLICE + Enable Register Slice on interface M01_AXI + 0 + + + M02_HAS_REGSLICE + Enable Register Slice on interface M02_AXI + 0 + + + M03_HAS_REGSLICE + Enable Register Slice on interface M03_AXI + 0 + + + M04_HAS_REGSLICE + Enable Register Slice on interface M04_AXI + 0 + + + M05_HAS_REGSLICE + Enable Register Slice on interface M05_AXI + 0 + + + M06_HAS_REGSLICE + Enable Register Slice on interface M06_AXI + 0 + + + M07_HAS_REGSLICE + Enable Register Slice on interface M07_AXI + 0 + + + M08_HAS_REGSLICE + Enable Register Slice on interface M08_AXI + 0 + + + M09_HAS_REGSLICE + Enable Register Slice on interface M09_AXI + 0 + + + M10_HAS_REGSLICE + Enable Register Slice on interface M10_AXI + 0 + + + M11_HAS_REGSLICE + Enable Register Slice on interface M11_AXI + 0 + + + M12_HAS_REGSLICE + Enable Register Slice on interface M12_AXI + 0 + + + M13_HAS_REGSLICE + Enable Register Slice on interface M13_AXI + 0 + + + M14_HAS_REGSLICE + Enable Register Slice on interface M14_AXI + 0 + + + M15_HAS_REGSLICE + Enable Register Slice on interface M15_AXI + 0 + + + M16_HAS_REGSLICE + Enable Register Slice on interface M16_AXI + 0 + + + M17_HAS_REGSLICE + Enable Register Slice on interface M17_AXI + 0 + + + M18_HAS_REGSLICE + Enable Register Slice on interface M18_AXI + 0 + + + M19_HAS_REGSLICE + Enable Register Slice on interface M19_AXI + 0 + + + M20_HAS_REGSLICE + Enable Register Slice on interface M20_AXI + 0 + + + M21_HAS_REGSLICE + Enable Register Slice on interface M21_AXI + 0 + + + M22_HAS_REGSLICE + Enable Register Slice on interface M22_AXI + 0 + + + M23_HAS_REGSLICE + Enable Register Slice on interface M23_AXI + 0 + + + M24_HAS_REGSLICE + Enable Register Slice on interface M24_AXI + 0 + + + M25_HAS_REGSLICE + Enable Register Slice on interface M25_AXI + 0 + + + M26_HAS_REGSLICE + Enable Register Slice on interface M26_AXI + 0 + + + M27_HAS_REGSLICE + Enable Register Slice on interface M27_AXI + 0 + + + M28_HAS_REGSLICE + Enable Register Slice on interface M28_AXI + 0 + + + M29_HAS_REGSLICE + Enable Register Slice on interface M29_AXI + 0 + + + M30_HAS_REGSLICE + Enable Register Slice on interface M30_AXI + 0 + + + M31_HAS_REGSLICE + Enable Register Slice on interface M31_AXI + 0 + + + M32_HAS_REGSLICE + Enable Register Slice on interface M32_AXI + 0 + + + M33_HAS_REGSLICE + Enable Register Slice on interface M33_AXI + 0 + + + M34_HAS_REGSLICE + Enable Register Slice on interface M34_AXI + 0 + + + M35_HAS_REGSLICE + Enable Register Slice on interface M35_AXI + 0 + + + M36_HAS_REGSLICE + Enable Register Slice on interface M36_AXI + 0 + + + M37_HAS_REGSLICE + Enable Register Slice on interface M37_AXI + 0 + + + M38_HAS_REGSLICE + Enable Register Slice on interface M38_AXI + 0 + + + M39_HAS_REGSLICE + Enable Register Slice on interface M39_AXI + 0 + + + M40_HAS_REGSLICE + Enable Register Slice on interface M40_AXI + 0 + + + M41_HAS_REGSLICE + Enable Register Slice on interface M41_AXI + 0 + + + M42_HAS_REGSLICE + Enable Register Slice on interface M42_AXI + 0 + + + M43_HAS_REGSLICE + Enable Register Slice on interface M43_AXI + 0 + + + M44_HAS_REGSLICE + Enable Register Slice on interface M44_AXI + 0 + + + M45_HAS_REGSLICE + Enable Register Slice on interface M45_AXI + 0 + + + M46_HAS_REGSLICE + Enable Register Slice on interface M46_AXI + 0 + + + M47_HAS_REGSLICE + Enable Register Slice on interface M47_AXI + 0 + + + M48_HAS_REGSLICE + Enable Register Slice on interface M48_AXI + 0 + + + M49_HAS_REGSLICE + Enable Register Slice on interface M49_AXI + 0 + + + M50_HAS_REGSLICE + Enable Register Slice on interface M50_AXI + 0 + + + M51_HAS_REGSLICE + Enable Register Slice on interface M51_AXI + 0 + + + M52_HAS_REGSLICE + Enable Register Slice on interface M52_AXI + 0 + + + M53_HAS_REGSLICE + Enable Register Slice on interface M53_AXI + 0 + + + M54_HAS_REGSLICE + Enable Register Slice on interface M54_AXI + 0 + + + M55_HAS_REGSLICE + Enable Register Slice on interface M55_AXI + 0 + + + M56_HAS_REGSLICE + Enable Register Slice on interface M56_AXI + 0 + + + M57_HAS_REGSLICE + Enable Register Slice on interface M57_AXI + 0 + + + M58_HAS_REGSLICE + Enable Register Slice on interface M58_AXI + 0 + + + M59_HAS_REGSLICE + Enable Register Slice on interface M59_AXI + 0 + + + M60_HAS_REGSLICE + Enable Register Slice on interface M60_AXI + 0 + + + M61_HAS_REGSLICE + Enable Register Slice on interface M61_AXI + 0 + + + M62_HAS_REGSLICE + Enable Register Slice on interface M62_AXI + 0 + + + M63_HAS_REGSLICE + Enable Register Slice on interface M63_AXI + 0 + + + M00_HAS_DATA_FIFO + Enable Data FIFO on interface M00_AXI + 0 + + + M01_HAS_DATA_FIFO + Enable Data FIFO on interface M01_AXI + 0 + + + M02_HAS_DATA_FIFO + Enable Data FIFO on interface M02_AXI + 0 + + + M03_HAS_DATA_FIFO + Enable Data FIFO on interface M03_AXI + 0 + + + M04_HAS_DATA_FIFO + Enable Data FIFO on interface M04_AXI + 0 + + + M05_HAS_DATA_FIFO + Enable Data FIFO on interface M05_AXI + 0 + + + M06_HAS_DATA_FIFO + Enable Data FIFO on interface M06_AXI + 0 + + + M07_HAS_DATA_FIFO + Enable Data FIFO on interface M07_AXI + 0 + + + M08_HAS_DATA_FIFO + Enable Data FIFO on interface M08_AXI + 0 + + + M09_HAS_DATA_FIFO + Enable Data FIFO on interface M09_AXI + 0 + + + M10_HAS_DATA_FIFO + Enable Data FIFO on interface M10_AXI + 0 + + + M11_HAS_DATA_FIFO + Enable Data FIFO on interface M11_AXI + 0 + + + M12_HAS_DATA_FIFO + Enable Data FIFO on interface M12_AXI + 0 + + + M13_HAS_DATA_FIFO + Enable Data FIFO on interface M13_AXI + 0 + + + M14_HAS_DATA_FIFO + Enable Data FIFO on interface M14_AXI + 0 + + + M15_HAS_DATA_FIFO + Enable Data FIFO on interface M15_AXI + 0 + + + M16_HAS_DATA_FIFO + Enable Data FIFO on interface M16_AXI + 0 + + + M17_HAS_DATA_FIFO + Enable Data FIFO on interface M17_AXI + 0 + + + M18_HAS_DATA_FIFO + Enable Data FIFO on interface M18_AXI + 0 + + + M19_HAS_DATA_FIFO + Enable Data FIFO on interface M19_AXI + 0 + + + M20_HAS_DATA_FIFO + Enable Data FIFO on interface M20_AXI + 0 + + + M21_HAS_DATA_FIFO + Enable Data FIFO on interface M21_AXI + 0 + + + M22_HAS_DATA_FIFO + Enable Data FIFO on interface M22_AXI + 0 + + + M23_HAS_DATA_FIFO + Enable Data FIFO on interface M23_AXI + 0 + + + M24_HAS_DATA_FIFO + Enable Data FIFO on interface M24_AXI + 0 + + + M25_HAS_DATA_FIFO + Enable Data FIFO on interface M25_AXI + 0 + + + M26_HAS_DATA_FIFO + Enable Data FIFO on interface M26_AXI + 0 + + + M27_HAS_DATA_FIFO + Enable Data FIFO on interface M27_AXI + 0 + + + M28_HAS_DATA_FIFO + Enable Data FIFO on interface M28_AXI + 0 + + + M29_HAS_DATA_FIFO + Enable Data FIFO on interface M29_AXI + 0 + + + M30_HAS_DATA_FIFO + Enable Data FIFO on interface M30_AXI + 0 + + + M31_HAS_DATA_FIFO + Enable Data FIFO on interface M31_AXI + 0 + + + M32_HAS_DATA_FIFO + Enable Data FIFO on interface M32_AXI + 0 + + + M33_HAS_DATA_FIFO + Enable Data FIFO on interface M33_AXI + 0 + + + M34_HAS_DATA_FIFO + Enable Data FIFO on interface M34_AXI + 0 + + + M35_HAS_DATA_FIFO + Enable Data FIFO on interface M35_AXI + 0 + + + M36_HAS_DATA_FIFO + Enable Data FIFO on interface M36_AXI + 0 + + + M37_HAS_DATA_FIFO + Enable Data FIFO on interface M37_AXI + 0 + + + M38_HAS_DATA_FIFO + Enable Data FIFO on interface M38_AXI + 0 + + + M39_HAS_DATA_FIFO + Enable Data FIFO on interface M39_AXI + 0 + + + M40_HAS_DATA_FIFO + Enable Data FIFO on interface M40_AXI + 0 + + + M41_HAS_DATA_FIFO + Enable Data FIFO on interface M41_AXI + 0 + + + M42_HAS_DATA_FIFO + Enable Data FIFO on interface M42_AXI + 0 + + + M43_HAS_DATA_FIFO + Enable Data FIFO on interface M43_AXI + 0 + + + M44_HAS_DATA_FIFO + Enable Data FIFO on interface M44_AXI + 0 + + + M45_HAS_DATA_FIFO + Enable Data FIFO on interface M45_AXI + 0 + + + M46_HAS_DATA_FIFO + Enable Data FIFO on interface M46_AXI + 0 + + + M47_HAS_DATA_FIFO + Enable Data FIFO on interface M47_AXI + 0 + + + M48_HAS_DATA_FIFO + Enable Data FIFO on interface M48_AXI + 0 + + + M49_HAS_DATA_FIFO + Enable Data FIFO on interface M49_AXI + 0 + + + M50_HAS_DATA_FIFO + Enable Data FIFO on interface M50_AXI + 0 + + + M51_HAS_DATA_FIFO + Enable Data FIFO on interface M51_AXI + 0 + + + M52_HAS_DATA_FIFO + Enable Data FIFO on interface M52_AXI + 0 + + + M53_HAS_DATA_FIFO + Enable Data FIFO on interface M53_AXI + 0 + + + M54_HAS_DATA_FIFO + Enable Data FIFO on interface M54_AXI + 0 + + + M55_HAS_DATA_FIFO + Enable Data FIFO on interface M55_AXI + 0 + + + M56_HAS_DATA_FIFO + Enable Data FIFO on interface M56_AXI + 0 + + + M57_HAS_DATA_FIFO + Enable Data FIFO on interface M57_AXI + 0 + + + M58_HAS_DATA_FIFO + Enable Data FIFO on interface M58_AXI + 0 + + + M59_HAS_DATA_FIFO + Enable Data FIFO on interface M59_AXI + 0 + + + M60_HAS_DATA_FIFO + Enable Data FIFO on interface M60_AXI + 0 + + + M61_HAS_DATA_FIFO + Enable Data FIFO on interface M61_AXI + 0 + + + M62_HAS_DATA_FIFO + Enable Data FIFO on interface M62_AXI + 0 + + + M63_HAS_DATA_FIFO + Enable Data FIFO on interface M63_AXI + 0 + + + S00_HAS_REGSLICE + Enable Register Slice on interface S00_AXI + 0 + + + S01_HAS_REGSLICE + Enable Register Slice on interface S01_AXI + 0 + + + S02_HAS_REGSLICE + Enable Register Slice on interface S02_AXI + 0 + + + S03_HAS_REGSLICE + Enable Register Slice on interface S03_AXI + 0 + + + S04_HAS_REGSLICE + Enable Register Slice on interface S04_AXI + 0 + + + S05_HAS_REGSLICE + Enable Register Slice on interface S05_AXI + 0 + + + S06_HAS_REGSLICE + Enable Register Slice on interface S06_AXI + 0 + + + S07_HAS_REGSLICE + Enable Register Slice on interface S07_AXI + 0 + + + S08_HAS_REGSLICE + Enable Register Slice on interface S08_AXI + 0 + + + S09_HAS_REGSLICE + Enable Register Slice on interface S09_AXI + 0 + + + S10_HAS_REGSLICE + Enable Register Slice on interface S10_AXI + 0 + + + S11_HAS_REGSLICE + Enable Register Slice on interface S11_AXI + 0 + + + S12_HAS_REGSLICE + Enable Register Slice on interface S12_AXI + 0 + + + S13_HAS_REGSLICE + Enable Register Slice on interface S13_AXI + 0 + + + S14_HAS_REGSLICE + Enable Register Slice on interface S14_AXI + 0 + + + S15_HAS_REGSLICE + Enable Register Slice on interface S15_AXI + 0 + + + S00_HAS_DATA_FIFO + Enable Data FIFO on interface S00_AXI + 0 + + + S01_HAS_DATA_FIFO + Enable Data FIFO on interface S01_AXI + 0 + + + S02_HAS_DATA_FIFO + Enable Data FIFO on interface S02_AXI + 0 + + + S03_HAS_DATA_FIFO + Enable Data FIFO on interface S03_AXI + 0 + + + S04_HAS_DATA_FIFO + Enable Data FIFO on interface S04_AXI + 0 + + + S05_HAS_DATA_FIFO + Enable Data FIFO on interface S05_AXI + 0 + + + S06_HAS_DATA_FIFO + Enable Data FIFO on interface S06_AXI + 0 + + + S07_HAS_DATA_FIFO + Enable Data FIFO on interface S07_AXI + 0 + + + S08_HAS_DATA_FIFO + Enable Data FIFO on interface S08_AXI + 0 + + + S09_HAS_DATA_FIFO + Enable Data FIFO on interface S09_AXI + 0 + + + S10_HAS_DATA_FIFO + Enable Data FIFO on interface S10_AXI + 0 + + + S11_HAS_DATA_FIFO + Enable Data FIFO on interface S11_AXI + 0 + + + S12_HAS_DATA_FIFO + Enable Data FIFO on interface S12_AXI + 0 + + + S13_HAS_DATA_FIFO + Enable Data FIFO on interface S13_AXI + 0 + + + S14_HAS_DATA_FIFO + Enable Data FIFO on interface S14_AXI + 0 + + + S15_HAS_DATA_FIFO + Enable Data FIFO on interface S15_AXI + 0 + + + M00_ISSUANCE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_ISSUANCE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_ISSUANCE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_ISSUANCE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_ISSUANCE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_ISSUANCE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_ISSUANCE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_ISSUANCE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_ISSUANCE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_ISSUANCE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_ISSUANCE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_ISSUANCE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_ISSUANCE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_ISSUANCE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_ISSUANCE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_ISSUANCE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_ISSUANCE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_ISSUANCE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_ISSUANCE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_ISSUANCE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_ISSUANCE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_ISSUANCE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_ISSUANCE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_ISSUANCE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_ISSUANCE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_ISSUANCE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_ISSUANCE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_ISSUANCE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_ISSUANCE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_ISSUANCE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_ISSUANCE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_ISSUANCE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_ISSUANCE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_ISSUANCE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_ISSUANCE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_ISSUANCE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_ISSUANCE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_ISSUANCE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_ISSUANCE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_ISSUANCE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_ISSUANCE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_ISSUANCE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_ISSUANCE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_ISSUANCE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_ISSUANCE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_ISSUANCE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_ISSUANCE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_ISSUANCE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_ISSUANCE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_ISSUANCE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_ISSUANCE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_ISSUANCE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_ISSUANCE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_ISSUANCE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_ISSUANCE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_ISSUANCE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_ISSUANCE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_ISSUANCE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_ISSUANCE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_ISSUANCE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_ISSUANCE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_ISSUANCE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_ISSUANCE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_ISSUANCE + Incicates whether M63_AXI connects to a secure slave + 0 + + + M00_SECURE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_SECURE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_SECURE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_SECURE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_SECURE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_SECURE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_SECURE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_SECURE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_SECURE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_SECURE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_SECURE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_SECURE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_SECURE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_SECURE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_SECURE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_SECURE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_SECURE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_SECURE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_SECURE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_SECURE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_SECURE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_SECURE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_SECURE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_SECURE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_SECURE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_SECURE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_SECURE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_SECURE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_SECURE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_SECURE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_SECURE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_SECURE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_SECURE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_SECURE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_SECURE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_SECURE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_SECURE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_SECURE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_SECURE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_SECURE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_SECURE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_SECURE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_SECURE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_SECURE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_SECURE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_SECURE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_SECURE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_SECURE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_SECURE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_SECURE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_SECURE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_SECURE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_SECURE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_SECURE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_SECURE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_SECURE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_SECURE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_SECURE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_SECURE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_SECURE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_SECURE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_SECURE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_SECURE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_SECURE + Incicates whether M63_AXI connects to a secure slave + 0 + + + Component_Name + z_turn_ps_7_axi_periph_0 + + + + + + /AXI_Infrastructure + /Embedded_Processing/AXI_Infrastructure + + AXI Interconnect + level_2 + http://www.xilinx.com + 6 + + xilinx.com:ip:axi_interconnect:2.0 + + 2015-06-23T16:14:23Z + + + + + + + 2015.2 + + + + + \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.upgrade_log b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.upgrade_log new file mode 100644 index 0000000..d7048c3 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.upgrade_log @@ -0,0 +1,16 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +| Date : Fri Jul 10 13:44:16 2015 +| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7z020clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'z_turn_ps_7_axi_periph_1' + +1. Summary +---------- + +SUCCESS in the update of z_turn_ps_7_axi_periph_1 (xilinx.com:ip:axi_interconnect:2.1 (Rev. 6)) to current project options. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.xci b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.xci new file mode 100644 index 0000000..dddb5af --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.xci @@ -0,0 +1,341 @@ + + + xilinx.com + xci + unknown + 1.0 + + + z_turn_ps_7_axi_periph_1 + + + 1 + 1 + 0 + 0 + 0 + 32 + 0 + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + z_turn_ps_7_axi_periph_0 + zynq + xc7z020 + clg400 + -1 + C + + VERILOG + MIXED + TRUE + TRUE + + TRUE + 2015.2 + 6 + GLOBAL + + . + ../../../../ipshared + IP_Integrator_AppCore + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.xml new file mode 100644 index 0000000..deed3d3 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.xml @@ -0,0 +1,4459 @@ + + + xilinx.com + customized_ip + z_turn_ps_7_axi_periph_1 + 1.0 + + + + choices_0 + 0 + 1 + 2 + + + choices_1 + 0 + 1 + + + choices_2 + 0 + 1 + + + choices_3 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choices_4 + 2 + 4 + 8 + 16 + 32 + 64 + + + choices_5 + 2 + 4 + 8 + 16 + 32 + 64 + + + choices_6 + 0 + 1 + 3 + 4 + + + choices_7 + 0 + 1 + 3 + 4 + + + choices_8 + 0 + 1 + 3 + 4 + + + choices_9 + 0 + 1 + 3 + 4 + + + choices_10 + 0 + 1 + 3 + 4 + + + choices_11 + 0 + 1 + 3 + 4 + + + choices_12 + 0 + 1 + 3 + 4 + + + choices_13 + 0 + 1 + 3 + 4 + + + choices_14 + 0 + 1 + 3 + 4 + + + choices_15 + 0 + 1 + 3 + 4 + + + choices_16 + 0 + 1 + 3 + 4 + + + choices_17 + 0 + 1 + 3 + 4 + + + choices_18 + 0 + 1 + 3 + 4 + + + choices_19 + 0 + 1 + 3 + 4 + + + choices_20 + 0 + 1 + 3 + 4 + + + choices_21 + 0 + 1 + 3 + 4 + + + choices_22 + 0 + 1 + 3 + 4 + + + choices_23 + 0 + 1 + 3 + 4 + + + choices_24 + 0 + 1 + 3 + 4 + + + choices_25 + 0 + 1 + 3 + 4 + + + choices_26 + 0 + 1 + 3 + 4 + + + choices_27 + 0 + 1 + 3 + 4 + + + choices_28 + 0 + 1 + 3 + 4 + + + choices_29 + 0 + 1 + 3 + 4 + + + choices_30 + 0 + 1 + 3 + 4 + + + choices_31 + 0 + 1 + 3 + 4 + + + choices_32 + 0 + 1 + 3 + 4 + + + choices_33 + 0 + 1 + 3 + 4 + + + choices_34 + 0 + 1 + 3 + 4 + + + choices_35 + 0 + 1 + 3 + 4 + + + choices_36 + 0 + 1 + 3 + 4 + + + choices_37 + 0 + 1 + 3 + 4 + + + choices_38 + 0 + 1 + 3 + 4 + + + choices_39 + 0 + 1 + 3 + 4 + + + choices_40 + 0 + 1 + 3 + 4 + + + choices_41 + 0 + 1 + 3 + 4 + + + choices_42 + 0 + 1 + 3 + 4 + + + choices_43 + 0 + 1 + 3 + 4 + + + choices_44 + 0 + 1 + 3 + 4 + + + choices_45 + 0 + 1 + 3 + 4 + + + choices_46 + 0 + 1 + 3 + 4 + + + choices_47 + 0 + 1 + 3 + 4 + + + choices_48 + 0 + 1 + 3 + 4 + + + choices_49 + 0 + 1 + 3 + 4 + + + choices_50 + 0 + 1 + 3 + 4 + + + choices_51 + 0 + 1 + 3 + 4 + + + choices_52 + 0 + 1 + 3 + 4 + + + choices_53 + 0 + 1 + 3 + 4 + + + choices_54 + 0 + 1 + 3 + 4 + + + choices_55 + 0 + 1 + 3 + 4 + + + choices_56 + 0 + 1 + 3 + 4 + + + choices_57 + 0 + 1 + 3 + 4 + + + choices_58 + 0 + 1 + 3 + 4 + + + choices_59 + 0 + 1 + 3 + 4 + + + choices_60 + 0 + 1 + 3 + 4 + + + choices_61 + 0 + 1 + 3 + 4 + + + choices_62 + 0 + 1 + 3 + 4 + + + choices_63 + 0 + 1 + 3 + 4 + + + choices_64 + 0 + 1 + 3 + 4 + + + choices_65 + 0 + 1 + 3 + 4 + + + choices_66 + 0 + 1 + 3 + 4 + + + choices_67 + 0 + 1 + 3 + 4 + + + choices_68 + 0 + 1 + 3 + 4 + + + choices_69 + 0 + 1 + 3 + 4 + + + choices_70 + 0 + 1 + 2 + + + choices_71 + 0 + 1 + 2 + + + choices_72 + 0 + 1 + 2 + + + choices_73 + 0 + 1 + 2 + + + choices_74 + 0 + 1 + 2 + + + choices_75 + 0 + 1 + 2 + + + choices_76 + 0 + 1 + 2 + + + choices_77 + 0 + 1 + 2 + + + choices_78 + 0 + 1 + 2 + + + choices_79 + 0 + 1 + 2 + + + choices_80 + 0 + 1 + 2 + + + choices_81 + 0 + 1 + 2 + + + choices_82 + 0 + 1 + 2 + + + choices_83 + 0 + 1 + 2 + + + choices_84 + 0 + 1 + 2 + + + choices_85 + 0 + 1 + 2 + + + choices_86 + 0 + 1 + 2 + + + choices_87 + 0 + 1 + 2 + + + choices_88 + 0 + 1 + 2 + + + choices_89 + 0 + 1 + 2 + + + choices_90 + 0 + 1 + 2 + + + choices_91 + 0 + 1 + 2 + + + choices_92 + 0 + 1 + 2 + + + choices_93 + 0 + 1 + 2 + + + choices_94 + 0 + 1 + 2 + + + choices_95 + 0 + 1 + 2 + + + choices_96 + 0 + 1 + 2 + + + choices_97 + 0 + 1 + 2 + + + choices_98 + 0 + 1 + 2 + + + choices_99 + 0 + 1 + 2 + + + choices_100 + 0 + 1 + 2 + + + choices_101 + 0 + 1 + 2 + + + choices_102 + 0 + 1 + 2 + + + choices_103 + 0 + 1 + 2 + + + choices_104 + 0 + 1 + 2 + + + choices_105 + 0 + 1 + 2 + + + choices_106 + 0 + 1 + 2 + + + choices_107 + 0 + 1 + 2 + + + choices_108 + 0 + 1 + 2 + + + choices_109 + 0 + 1 + 2 + + + choices_110 + 0 + 1 + 2 + + + choices_111 + 0 + 1 + 2 + + + choices_112 + 0 + 1 + 2 + + + choices_113 + 0 + 1 + 2 + + + choices_114 + 0 + 1 + 2 + + + choices_115 + 0 + 1 + 2 + + + choices_116 + 0 + 1 + 2 + + + choices_117 + 0 + 1 + 2 + + + choices_118 + 0 + 1 + 2 + + + choices_119 + 0 + 1 + 2 + + + choices_120 + 0 + 1 + 2 + + + choices_121 + 0 + 1 + 2 + + + choices_122 + 0 + 1 + 2 + + + choices_123 + 0 + 1 + 2 + + + choices_124 + 0 + 1 + 2 + + + choices_125 + 0 + 1 + 2 + + + choices_126 + 0 + 1 + 2 + + + choices_127 + 0 + 1 + 2 + + + choices_128 + 0 + 1 + 2 + + + choices_129 + 0 + 1 + 2 + + + choices_130 + 0 + 1 + 2 + + + choices_131 + 0 + 1 + 2 + + + choices_132 + 0 + 1 + 2 + + + choices_133 + 0 + 1 + 2 + + + choices_134 + 0 + 1 + 3 + 4 + + + choices_135 + 0 + 1 + 3 + 4 + + + choices_136 + 0 + 1 + 3 + 4 + + + choices_137 + 0 + 1 + 3 + 4 + + + choices_138 + 0 + 1 + 3 + 4 + + + choices_139 + 0 + 1 + 3 + 4 + + + choices_140 + 0 + 1 + 3 + 4 + + + choices_141 + 0 + 1 + 3 + 4 + + + choices_142 + 0 + 1 + 3 + 4 + + + choices_143 + 0 + 1 + 3 + 4 + + + choices_144 + 0 + 1 + 3 + 4 + + + choices_145 + 0 + 1 + 3 + 4 + + + choices_146 + 0 + 1 + 3 + 4 + + + choices_147 + 0 + 1 + 3 + 4 + + + choices_148 + 0 + 1 + 3 + 4 + + + choices_149 + 0 + 1 + 3 + 4 + + + choices_150 + 0 + 1 + 2 + + + choices_151 + 0 + 1 + 2 + + + choices_152 + 0 + 1 + 2 + + + choices_153 + 0 + 1 + 2 + + + choices_154 + 0 + 1 + 2 + + + choices_155 + 0 + 1 + 2 + + + choices_156 + 0 + 1 + 2 + + + choices_157 + 0 + 1 + 2 + + + choices_158 + 0 + 1 + 2 + + + choices_159 + 0 + 1 + 2 + + + choices_160 + 0 + 1 + 2 + + + choices_161 + 0 + 1 + 2 + + + choices_162 + 0 + 1 + 2 + + + choices_163 + 0 + 1 + 2 + + + choices_164 + 0 + 1 + 2 + + + choices_165 + 0 + 1 + 2 + + + choices_166 + 0 + 1 + + + choices_167 + 0 + 1 + + + choices_168 + 0 + 1 + + + choices_169 + 0 + 1 + + + choices_170 + 0 + 1 + + + choices_171 + 0 + 1 + + + choices_172 + 0 + 1 + + + choices_173 + 0 + 1 + + + choices_174 + 0 + 1 + + + choices_175 + 0 + 1 + + + choices_176 + 0 + 1 + + + choices_177 + 0 + 1 + + + choices_178 + 0 + 1 + + + choices_179 + 0 + 1 + + + choices_180 + 0 + 1 + + + choices_181 + 0 + 1 + + + choices_182 + 0 + 1 + + + choices_183 + 0 + 1 + + + choices_184 + 0 + 1 + + + choices_185 + 0 + 1 + + + choices_186 + 0 + 1 + + + choices_187 + 0 + 1 + + + choices_188 + 0 + 1 + + + choices_189 + 0 + 1 + + + choices_190 + 0 + 1 + + + choices_191 + 0 + 1 + + + choices_192 + 0 + 1 + + + choices_193 + 0 + 1 + + + choices_194 + 0 + 1 + + + choices_195 + 0 + 1 + + + choices_196 + 0 + 1 + + + choices_197 + 0 + 1 + + + choices_198 + 0 + 1 + + + choices_199 + 0 + 1 + + + choices_200 + 0 + 1 + + + choices_201 + 0 + 1 + + + choices_202 + 0 + 1 + + + choices_203 + 0 + 1 + + + choices_204 + 0 + 1 + + + choices_205 + 0 + 1 + + + choices_206 + 0 + 1 + + + choices_207 + 0 + 1 + + + choices_208 + 0 + 1 + + + choices_209 + 0 + 1 + + + choices_210 + 0 + 1 + + + choices_211 + 0 + 1 + + + choices_212 + 0 + 1 + + + choices_213 + 0 + 1 + + + choices_214 + 0 + 1 + + + choices_215 + 0 + 1 + + + choices_216 + 0 + 1 + + + choices_217 + 0 + 1 + + + choices_218 + 0 + 1 + + + choices_219 + 0 + 1 + + + choices_220 + 0 + 1 + + + choices_221 + 0 + 1 + + + choices_222 + 0 + 1 + + + choices_223 + 0 + 1 + + + choices_224 + 0 + 1 + + + choices_225 + 0 + 1 + + + choices_226 + 0 + 1 + + + choices_227 + 0 + 1 + + + choices_228 + 0 + 1 + + + choices_229 + 0 + 1 + + + choices_230 + 0 + 1 + + + choices_231 + 0 + 1 + + + choices_232 + 0 + 1 + + + choices_233 + 0 + 1 + + + choices_234 + 0 + 1 + + + choices_235 + 0 + 1 + + + choices_236 + 0 + 1 + + + choices_237 + 0 + 1 + + + choices_238 + 0 + 1 + + + choices_239 + 0 + 1 + + + choices_240 + 0 + 1 + + + choices_241 + 0 + 1 + + + choices_242 + 0 + 1 + + + choices_243 + 0 + 1 + + + choices_244 + 0 + 1 + + + choices_245 + 0 + 1 + + + choices_246 + 0 + 1 + + + choices_247 + 0 + 1 + + + choices_248 + 0 + 1 + + + choices_249 + 0 + 1 + + + choices_250 + 0 + 1 + + + choices_251 + 0 + 1 + + + choices_252 + 0 + 1 + + + choices_253 + 0 + 1 + + + choices_254 + 0 + 1 + + + choices_255 + 0 + 1 + + + choices_256 + 0 + 1 + + + choices_257 + 0 + 1 + + + choices_258 + 0 + 1 + + + choices_259 + 0 + 1 + + + choices_260 + 0 + 1 + + + choices_261 + 0 + 1 + + + choices_262 + 0 + 1 + + + choices_263 + 0 + 1 + + + choices_264 + 0 + 1 + + + choices_265 + 0 + 1 + + + choices_266 + 0 + 1 + + + choices_267 + 0 + 1 + + + choices_268 + 0 + 1 + + + choices_269 + 0 + 1 + + + choices_270 + 0 + 1 + + + choices_271 + 0 + 1 + + + choices_272 + 0 + 1 + + + choices_273 + 0 + 1 + + + choices_274 + 0 + 1 + + + choices_275 + 0 + 1 + + + choices_276 + 0 + 1 + + + choices_277 + 0 + 1 + + + choices_278 + 0 + 1 + + + choices_279 + 0 + 1 + + + choices_280 + 0 + 1 + + + choices_281 + 0 + 1 + + + choices_282 + 0 + 1 + + + choices_283 + 0 + 1 + + + choices_284 + 0 + 1 + + + choices_285 + 0 + 1 + + + choices_286 + 0 + 1 + + + choices_287 + 0 + 1 + + + choices_288 + 0 + 1 + + + choices_289 + 0 + 1 + + + choices_290 + 0 + 1 + + + choices_291 + 0 + 1 + + + choices_292 + 0 + 1 + + + choices_293 + 0 + 1 + + + The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices + + + NUM_SI + Number of Slave Interfaces + 1 + + + NUM_MI + Number of Master Interfaces + 1 + + + STRATEGY + Interconnect Optimization Strategy + 0 + + + ENABLE_ADVANCED_OPTIONS + Enable Advanced Configuration Options + 0 + + + ENABLE_PROTOCOL_CHECKERS + Enable Protocol Checkers and mark interfaces for debug + 0 + + + XBAR_DATA_WIDTH + Data Width of the AXI Crossbar + 32 + + + PCHK_WAITS + Maximum number of idle cycles for READY monitoring + 0 + + + PCHK_MAX_RD_BURSTS + Maximum outstanding READ Transactions per ID + 2 + + + PCHK_MAX_WR_BURSTS + Maximum outstanding WRITE Transactions per ID + 2 + + + SYNCHRONIZATION_STAGES + Synchronization Stages + 2 + + + M00_HAS_REGSLICE + Enable Register Slice on interface M00_AXI + 0 + + + M01_HAS_REGSLICE + Enable Register Slice on interface M01_AXI + 0 + + + M02_HAS_REGSLICE + Enable Register Slice on interface M02_AXI + 0 + + + M03_HAS_REGSLICE + Enable Register Slice on interface M03_AXI + 0 + + + M04_HAS_REGSLICE + Enable Register Slice on interface M04_AXI + 0 + + + M05_HAS_REGSLICE + Enable Register Slice on interface M05_AXI + 0 + + + M06_HAS_REGSLICE + Enable Register Slice on interface M06_AXI + 0 + + + M07_HAS_REGSLICE + Enable Register Slice on interface M07_AXI + 0 + + + M08_HAS_REGSLICE + Enable Register Slice on interface M08_AXI + 0 + + + M09_HAS_REGSLICE + Enable Register Slice on interface M09_AXI + 0 + + + M10_HAS_REGSLICE + Enable Register Slice on interface M10_AXI + 0 + + + M11_HAS_REGSLICE + Enable Register Slice on interface M11_AXI + 0 + + + M12_HAS_REGSLICE + Enable Register Slice on interface M12_AXI + 0 + + + M13_HAS_REGSLICE + Enable Register Slice on interface M13_AXI + 0 + + + M14_HAS_REGSLICE + Enable Register Slice on interface M14_AXI + 0 + + + M15_HAS_REGSLICE + Enable Register Slice on interface M15_AXI + 0 + + + M16_HAS_REGSLICE + Enable Register Slice on interface M16_AXI + 0 + + + M17_HAS_REGSLICE + Enable Register Slice on interface M17_AXI + 0 + + + M18_HAS_REGSLICE + Enable Register Slice on interface M18_AXI + 0 + + + M19_HAS_REGSLICE + Enable Register Slice on interface M19_AXI + 0 + + + M20_HAS_REGSLICE + Enable Register Slice on interface M20_AXI + 0 + + + M21_HAS_REGSLICE + Enable Register Slice on interface M21_AXI + 0 + + + M22_HAS_REGSLICE + Enable Register Slice on interface M22_AXI + 0 + + + M23_HAS_REGSLICE + Enable Register Slice on interface M23_AXI + 0 + + + M24_HAS_REGSLICE + Enable Register Slice on interface M24_AXI + 0 + + + M25_HAS_REGSLICE + Enable Register Slice on interface M25_AXI + 0 + + + M26_HAS_REGSLICE + Enable Register Slice on interface M26_AXI + 0 + + + M27_HAS_REGSLICE + Enable Register Slice on interface M27_AXI + 0 + + + M28_HAS_REGSLICE + Enable Register Slice on interface M28_AXI + 0 + + + M29_HAS_REGSLICE + Enable Register Slice on interface M29_AXI + 0 + + + M30_HAS_REGSLICE + Enable Register Slice on interface M30_AXI + 0 + + + M31_HAS_REGSLICE + Enable Register Slice on interface M31_AXI + 0 + + + M32_HAS_REGSLICE + Enable Register Slice on interface M32_AXI + 0 + + + M33_HAS_REGSLICE + Enable Register Slice on interface M33_AXI + 0 + + + M34_HAS_REGSLICE + Enable Register Slice on interface M34_AXI + 0 + + + M35_HAS_REGSLICE + Enable Register Slice on interface M35_AXI + 0 + + + M36_HAS_REGSLICE + Enable Register Slice on interface M36_AXI + 0 + + + M37_HAS_REGSLICE + Enable Register Slice on interface M37_AXI + 0 + + + M38_HAS_REGSLICE + Enable Register Slice on interface M38_AXI + 0 + + + M39_HAS_REGSLICE + Enable Register Slice on interface M39_AXI + 0 + + + M40_HAS_REGSLICE + Enable Register Slice on interface M40_AXI + 0 + + + M41_HAS_REGSLICE + Enable Register Slice on interface M41_AXI + 0 + + + M42_HAS_REGSLICE + Enable Register Slice on interface M42_AXI + 0 + + + M43_HAS_REGSLICE + Enable Register Slice on interface M43_AXI + 0 + + + M44_HAS_REGSLICE + Enable Register Slice on interface M44_AXI + 0 + + + M45_HAS_REGSLICE + Enable Register Slice on interface M45_AXI + 0 + + + M46_HAS_REGSLICE + Enable Register Slice on interface M46_AXI + 0 + + + M47_HAS_REGSLICE + Enable Register Slice on interface M47_AXI + 0 + + + M48_HAS_REGSLICE + Enable Register Slice on interface M48_AXI + 0 + + + M49_HAS_REGSLICE + Enable Register Slice on interface M49_AXI + 0 + + + M50_HAS_REGSLICE + Enable Register Slice on interface M50_AXI + 0 + + + M51_HAS_REGSLICE + Enable Register Slice on interface M51_AXI + 0 + + + M52_HAS_REGSLICE + Enable Register Slice on interface M52_AXI + 0 + + + M53_HAS_REGSLICE + Enable Register Slice on interface M53_AXI + 0 + + + M54_HAS_REGSLICE + Enable Register Slice on interface M54_AXI + 0 + + + M55_HAS_REGSLICE + Enable Register Slice on interface M55_AXI + 0 + + + M56_HAS_REGSLICE + Enable Register Slice on interface M56_AXI + 0 + + + M57_HAS_REGSLICE + Enable Register Slice on interface M57_AXI + 0 + + + M58_HAS_REGSLICE + Enable Register Slice on interface M58_AXI + 0 + + + M59_HAS_REGSLICE + Enable Register Slice on interface M59_AXI + 0 + + + M60_HAS_REGSLICE + Enable Register Slice on interface M60_AXI + 0 + + + M61_HAS_REGSLICE + Enable Register Slice on interface M61_AXI + 0 + + + M62_HAS_REGSLICE + Enable Register Slice on interface M62_AXI + 0 + + + M63_HAS_REGSLICE + Enable Register Slice on interface M63_AXI + 0 + + + M00_HAS_DATA_FIFO + Enable Data FIFO on interface M00_AXI + 0 + + + M01_HAS_DATA_FIFO + Enable Data FIFO on interface M01_AXI + 0 + + + M02_HAS_DATA_FIFO + Enable Data FIFO on interface M02_AXI + 0 + + + M03_HAS_DATA_FIFO + Enable Data FIFO on interface M03_AXI + 0 + + + M04_HAS_DATA_FIFO + Enable Data FIFO on interface M04_AXI + 0 + + + M05_HAS_DATA_FIFO + Enable Data FIFO on interface M05_AXI + 0 + + + M06_HAS_DATA_FIFO + Enable Data FIFO on interface M06_AXI + 0 + + + M07_HAS_DATA_FIFO + Enable Data FIFO on interface M07_AXI + 0 + + + M08_HAS_DATA_FIFO + Enable Data FIFO on interface M08_AXI + 0 + + + M09_HAS_DATA_FIFO + Enable Data FIFO on interface M09_AXI + 0 + + + M10_HAS_DATA_FIFO + Enable Data FIFO on interface M10_AXI + 0 + + + M11_HAS_DATA_FIFO + Enable Data FIFO on interface M11_AXI + 0 + + + M12_HAS_DATA_FIFO + Enable Data FIFO on interface M12_AXI + 0 + + + M13_HAS_DATA_FIFO + Enable Data FIFO on interface M13_AXI + 0 + + + M14_HAS_DATA_FIFO + Enable Data FIFO on interface M14_AXI + 0 + + + M15_HAS_DATA_FIFO + Enable Data FIFO on interface M15_AXI + 0 + + + M16_HAS_DATA_FIFO + Enable Data FIFO on interface M16_AXI + 0 + + + M17_HAS_DATA_FIFO + Enable Data FIFO on interface M17_AXI + 0 + + + M18_HAS_DATA_FIFO + Enable Data FIFO on interface M18_AXI + 0 + + + M19_HAS_DATA_FIFO + Enable Data FIFO on interface M19_AXI + 0 + + + M20_HAS_DATA_FIFO + Enable Data FIFO on interface M20_AXI + 0 + + + M21_HAS_DATA_FIFO + Enable Data FIFO on interface M21_AXI + 0 + + + M22_HAS_DATA_FIFO + Enable Data FIFO on interface M22_AXI + 0 + + + M23_HAS_DATA_FIFO + Enable Data FIFO on interface M23_AXI + 0 + + + M24_HAS_DATA_FIFO + Enable Data FIFO on interface M24_AXI + 0 + + + M25_HAS_DATA_FIFO + Enable Data FIFO on interface M25_AXI + 0 + + + M26_HAS_DATA_FIFO + Enable Data FIFO on interface M26_AXI + 0 + + + M27_HAS_DATA_FIFO + Enable Data FIFO on interface M27_AXI + 0 + + + M28_HAS_DATA_FIFO + Enable Data FIFO on interface M28_AXI + 0 + + + M29_HAS_DATA_FIFO + Enable Data FIFO on interface M29_AXI + 0 + + + M30_HAS_DATA_FIFO + Enable Data FIFO on interface M30_AXI + 0 + + + M31_HAS_DATA_FIFO + Enable Data FIFO on interface M31_AXI + 0 + + + M32_HAS_DATA_FIFO + Enable Data FIFO on interface M32_AXI + 0 + + + M33_HAS_DATA_FIFO + Enable Data FIFO on interface M33_AXI + 0 + + + M34_HAS_DATA_FIFO + Enable Data FIFO on interface M34_AXI + 0 + + + M35_HAS_DATA_FIFO + Enable Data FIFO on interface M35_AXI + 0 + + + M36_HAS_DATA_FIFO + Enable Data FIFO on interface M36_AXI + 0 + + + M37_HAS_DATA_FIFO + Enable Data FIFO on interface M37_AXI + 0 + + + M38_HAS_DATA_FIFO + Enable Data FIFO on interface M38_AXI + 0 + + + M39_HAS_DATA_FIFO + Enable Data FIFO on interface M39_AXI + 0 + + + M40_HAS_DATA_FIFO + Enable Data FIFO on interface M40_AXI + 0 + + + M41_HAS_DATA_FIFO + Enable Data FIFO on interface M41_AXI + 0 + + + M42_HAS_DATA_FIFO + Enable Data FIFO on interface M42_AXI + 0 + + + M43_HAS_DATA_FIFO + Enable Data FIFO on interface M43_AXI + 0 + + + M44_HAS_DATA_FIFO + Enable Data FIFO on interface M44_AXI + 0 + + + M45_HAS_DATA_FIFO + Enable Data FIFO on interface M45_AXI + 0 + + + M46_HAS_DATA_FIFO + Enable Data FIFO on interface M46_AXI + 0 + + + M47_HAS_DATA_FIFO + Enable Data FIFO on interface M47_AXI + 0 + + + M48_HAS_DATA_FIFO + Enable Data FIFO on interface M48_AXI + 0 + + + M49_HAS_DATA_FIFO + Enable Data FIFO on interface M49_AXI + 0 + + + M50_HAS_DATA_FIFO + Enable Data FIFO on interface M50_AXI + 0 + + + M51_HAS_DATA_FIFO + Enable Data FIFO on interface M51_AXI + 0 + + + M52_HAS_DATA_FIFO + Enable Data FIFO on interface M52_AXI + 0 + + + M53_HAS_DATA_FIFO + Enable Data FIFO on interface M53_AXI + 0 + + + M54_HAS_DATA_FIFO + Enable Data FIFO on interface M54_AXI + 0 + + + M55_HAS_DATA_FIFO + Enable Data FIFO on interface M55_AXI + 0 + + + M56_HAS_DATA_FIFO + Enable Data FIFO on interface M56_AXI + 0 + + + M57_HAS_DATA_FIFO + Enable Data FIFO on interface M57_AXI + 0 + + + M58_HAS_DATA_FIFO + Enable Data FIFO on interface M58_AXI + 0 + + + M59_HAS_DATA_FIFO + Enable Data FIFO on interface M59_AXI + 0 + + + M60_HAS_DATA_FIFO + Enable Data FIFO on interface M60_AXI + 0 + + + M61_HAS_DATA_FIFO + Enable Data FIFO on interface M61_AXI + 0 + + + M62_HAS_DATA_FIFO + Enable Data FIFO on interface M62_AXI + 0 + + + M63_HAS_DATA_FIFO + Enable Data FIFO on interface M63_AXI + 0 + + + S00_HAS_REGSLICE + Enable Register Slice on interface S00_AXI + 0 + + + S01_HAS_REGSLICE + Enable Register Slice on interface S01_AXI + 0 + + + S02_HAS_REGSLICE + Enable Register Slice on interface S02_AXI + 0 + + + S03_HAS_REGSLICE + Enable Register Slice on interface S03_AXI + 0 + + + S04_HAS_REGSLICE + Enable Register Slice on interface S04_AXI + 0 + + + S05_HAS_REGSLICE + Enable Register Slice on interface S05_AXI + 0 + + + S06_HAS_REGSLICE + Enable Register Slice on interface S06_AXI + 0 + + + S07_HAS_REGSLICE + Enable Register Slice on interface S07_AXI + 0 + + + S08_HAS_REGSLICE + Enable Register Slice on interface S08_AXI + 0 + + + S09_HAS_REGSLICE + Enable Register Slice on interface S09_AXI + 0 + + + S10_HAS_REGSLICE + Enable Register Slice on interface S10_AXI + 0 + + + S11_HAS_REGSLICE + Enable Register Slice on interface S11_AXI + 0 + + + S12_HAS_REGSLICE + Enable Register Slice on interface S12_AXI + 0 + + + S13_HAS_REGSLICE + Enable Register Slice on interface S13_AXI + 0 + + + S14_HAS_REGSLICE + Enable Register Slice on interface S14_AXI + 0 + + + S15_HAS_REGSLICE + Enable Register Slice on interface S15_AXI + 0 + + + S00_HAS_DATA_FIFO + Enable Data FIFO on interface S00_AXI + 0 + + + S01_HAS_DATA_FIFO + Enable Data FIFO on interface S01_AXI + 0 + + + S02_HAS_DATA_FIFO + Enable Data FIFO on interface S02_AXI + 0 + + + S03_HAS_DATA_FIFO + Enable Data FIFO on interface S03_AXI + 0 + + + S04_HAS_DATA_FIFO + Enable Data FIFO on interface S04_AXI + 0 + + + S05_HAS_DATA_FIFO + Enable Data FIFO on interface S05_AXI + 0 + + + S06_HAS_DATA_FIFO + Enable Data FIFO on interface S06_AXI + 0 + + + S07_HAS_DATA_FIFO + Enable Data FIFO on interface S07_AXI + 0 + + + S08_HAS_DATA_FIFO + Enable Data FIFO on interface S08_AXI + 0 + + + S09_HAS_DATA_FIFO + Enable Data FIFO on interface S09_AXI + 0 + + + S10_HAS_DATA_FIFO + Enable Data FIFO on interface S10_AXI + 0 + + + S11_HAS_DATA_FIFO + Enable Data FIFO on interface S11_AXI + 0 + + + S12_HAS_DATA_FIFO + Enable Data FIFO on interface S12_AXI + 0 + + + S13_HAS_DATA_FIFO + Enable Data FIFO on interface S13_AXI + 0 + + + S14_HAS_DATA_FIFO + Enable Data FIFO on interface S14_AXI + 0 + + + S15_HAS_DATA_FIFO + Enable Data FIFO on interface S15_AXI + 0 + + + M00_ISSUANCE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_ISSUANCE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_ISSUANCE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_ISSUANCE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_ISSUANCE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_ISSUANCE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_ISSUANCE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_ISSUANCE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_ISSUANCE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_ISSUANCE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_ISSUANCE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_ISSUANCE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_ISSUANCE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_ISSUANCE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_ISSUANCE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_ISSUANCE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_ISSUANCE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_ISSUANCE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_ISSUANCE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_ISSUANCE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_ISSUANCE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_ISSUANCE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_ISSUANCE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_ISSUANCE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_ISSUANCE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_ISSUANCE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_ISSUANCE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_ISSUANCE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_ISSUANCE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_ISSUANCE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_ISSUANCE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_ISSUANCE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_ISSUANCE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_ISSUANCE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_ISSUANCE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_ISSUANCE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_ISSUANCE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_ISSUANCE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_ISSUANCE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_ISSUANCE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_ISSUANCE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_ISSUANCE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_ISSUANCE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_ISSUANCE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_ISSUANCE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_ISSUANCE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_ISSUANCE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_ISSUANCE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_ISSUANCE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_ISSUANCE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_ISSUANCE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_ISSUANCE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_ISSUANCE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_ISSUANCE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_ISSUANCE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_ISSUANCE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_ISSUANCE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_ISSUANCE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_ISSUANCE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_ISSUANCE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_ISSUANCE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_ISSUANCE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_ISSUANCE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_ISSUANCE + Incicates whether M63_AXI connects to a secure slave + 0 + + + M00_SECURE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_SECURE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_SECURE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_SECURE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_SECURE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_SECURE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_SECURE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_SECURE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_SECURE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_SECURE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_SECURE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_SECURE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_SECURE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_SECURE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_SECURE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_SECURE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_SECURE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_SECURE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_SECURE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_SECURE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_SECURE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_SECURE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_SECURE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_SECURE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_SECURE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_SECURE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_SECURE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_SECURE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_SECURE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_SECURE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_SECURE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_SECURE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_SECURE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_SECURE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_SECURE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_SECURE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_SECURE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_SECURE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_SECURE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_SECURE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_SECURE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_SECURE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_SECURE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_SECURE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_SECURE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_SECURE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_SECURE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_SECURE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_SECURE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_SECURE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_SECURE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_SECURE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_SECURE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_SECURE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_SECURE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_SECURE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_SECURE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_SECURE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_SECURE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_SECURE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_SECURE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_SECURE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_SECURE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_SECURE + Incicates whether M63_AXI connects to a secure slave + 0 + + + Component_Name + z_turn_ps_7_axi_periph_0 + + + + + + /AXI_Infrastructure + /Embedded_Processing/AXI_Infrastructure + + AXI Interconnect + level_2 + http://www.xilinx.com + 6 + + xilinx.com:ip:axi_interconnect:2.0 + + 2015-06-23T16:14:23Z + + + + + + + 2015.2 + + + + + \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/doc/proc_sys_reset_v5_0_changelog.txt b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/doc/proc_sys_reset_v5_0_changelog.txt new file mode 100644 index 0000000..d8c5a93 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/doc/proc_sys_reset_v5_0_changelog.txt @@ -0,0 +1,104 @@ +2015.2: + * Version 5.0 (Rev. 7) + * No changes + +2015.1: + * Version 5.0 (Rev. 7) + * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk + * Supported devices and production status are now determined automatically, to simplify support for future devices + +2014.4.1: + * Version 5.0 (Rev. 6) + * No changes + +2014.4: + * Version 5.0 (Rev. 6) + * No changes + +2014.3: + * Version 5.0 (Rev. 6) + * Modified to use new sub-cores in place of proc_common,no functional changes + * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability + * Updated core to use utils.tcl, needed for board flow from common location + +2014.2: + * Version 5.0 (Rev. 5) + * Enhanced support for IP Integrator + * Board flow related updates, no functional changes + +2014.1: + * Version 5.0 (Rev. 4) + * Internal device family name change, no functional changes + +2013.4: + * Version 5.0 (Rev. 3) + * Added exdes.xdc file + * Changed the associated resets for slowest_sync_clk + * Kintex UltraScale Pre-Production support + +2013.3: + * Version 5.0 (Rev. 2) + * Changed board flow specific parameter name as per new requirements + * Added example design and demonstration testbench + * Reduced warnings in synthesis and simulation + * Enhanced support for IP Integrator + * Added support for Cadence IES and Synopsys VCS simulators + * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability + * Support for 7-series devices at Production status + +2013.2: + * Version 5.0 (Rev. 1) + * Added BETA support for future devices. + * No other RTL updates + +2013.1: + * Version 5.0 + * Updated version for 2013.1 + * Updated bd.tcl for board flow + * No other RTL updates + +(c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/sim/z_turn_rst_ps_7_166M_0.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/sim/z_turn_rst_ps_7_166M_0.vhd new file mode 100644 index 0000000..867916e --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/sim/z_turn_rst_ps_7_166M_0.vhd @@ -0,0 +1,138 @@ +-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 +-- IP Revision: 7 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY proc_sys_reset_v5_0; +USE proc_sys_reset_v5_0.proc_sys_reset; + +ENTITY z_turn_rst_ps_7_166M_0 IS + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END z_turn_rst_ps_7_166M_0; + +ARCHITECTURE z_turn_rst_ps_7_166M_0_arch OF z_turn_rst_ps_7_166M_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : string; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_rst_ps_7_166M_0_arch: ARCHITECTURE IS "yes"; + + COMPONENT proc_sys_reset IS + GENERIC ( + C_FAMILY : STRING; + C_EXT_RST_WIDTH : INTEGER; + C_AUX_RST_WIDTH : INTEGER; + C_EXT_RESET_HIGH : STD_LOGIC; + C_AUX_RESET_HIGH : STD_LOGIC; + C_NUM_BUS_RST : INTEGER; + C_NUM_PERP_RST : INTEGER; + C_NUM_INTERCONNECT_ARESETN : INTEGER; + C_NUM_PERP_ARESETN : INTEGER + ); + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT proc_sys_reset; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; + ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; +BEGIN + U0 : proc_sys_reset + GENERIC MAP ( + C_FAMILY => "zynq", + C_EXT_RST_WIDTH => 4, + C_AUX_RST_WIDTH => 4, + C_EXT_RESET_HIGH => '0', + C_AUX_RESET_HIGH => '0', + C_NUM_BUS_RST => 1, + C_NUM_PERP_RST => 1, + C_NUM_INTERCONNECT_ARESETN => 1, + C_NUM_PERP_ARESETN => 1 + ) + PORT MAP ( + slowest_sync_clk => slowest_sync_clk, + ext_reset_in => ext_reset_in, + aux_reset_in => aux_reset_in, + mb_debug_sys_rst => mb_debug_sys_rst, + dcm_locked => dcm_locked, + mb_reset => mb_reset, + bus_struct_reset => bus_struct_reset, + peripheral_reset => peripheral_reset, + interconnect_aresetn => interconnect_aresetn, + peripheral_aresetn => peripheral_aresetn + ); +END z_turn_rst_ps_7_166M_0_arch; diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/synth/z_turn_rst_ps_7_166M_0.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/synth/z_turn_rst_ps_7_166M_0.vhd new file mode 100644 index 0000000..3479bc5 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/synth/z_turn_rst_ps_7_166M_0.vhd @@ -0,0 +1,144 @@ +-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 +-- IP Revision: 7 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY proc_sys_reset_v5_0; +USE proc_sys_reset_v5_0.proc_sys_reset; + +ENTITY z_turn_rst_ps_7_166M_0 IS + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END z_turn_rst_ps_7_166M_0; + +ARCHITECTURE z_turn_rst_ps_7_166M_0_arch OF z_turn_rst_ps_7_166M_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : string; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_rst_ps_7_166M_0_arch: ARCHITECTURE IS "yes"; + + COMPONENT proc_sys_reset IS + GENERIC ( + C_FAMILY : STRING; + C_EXT_RST_WIDTH : INTEGER; + C_AUX_RST_WIDTH : INTEGER; + C_EXT_RESET_HIGH : STD_LOGIC; + C_AUX_RESET_HIGH : STD_LOGIC; + C_NUM_BUS_RST : INTEGER; + C_NUM_PERP_RST : INTEGER; + C_NUM_INTERCONNECT_ARESETN : INTEGER; + C_NUM_PERP_ARESETN : INTEGER + ); + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT proc_sys_reset; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF z_turn_rst_ps_7_166M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_rst_ps_7_166M_0_arch : ARCHITECTURE IS "z_turn_rst_ps_7_166M_0,proc_sys_reset,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF z_turn_rst_ps_7_166M_0_arch: ARCHITECTURE IS "z_turn_rst_ps_7_166M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; + ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; +BEGIN + U0 : proc_sys_reset + GENERIC MAP ( + C_FAMILY => "zynq", + C_EXT_RST_WIDTH => 4, + C_AUX_RST_WIDTH => 4, + C_EXT_RESET_HIGH => '0', + C_AUX_RESET_HIGH => '0', + C_NUM_BUS_RST => 1, + C_NUM_PERP_RST => 1, + C_NUM_INTERCONNECT_ARESETN => 1, + C_NUM_PERP_ARESETN => 1 + ) + PORT MAP ( + slowest_sync_clk => slowest_sync_clk, + ext_reset_in => ext_reset_in, + aux_reset_in => aux_reset_in, + mb_debug_sys_rst => mb_debug_sys_rst, + dcm_locked => dcm_locked, + mb_reset => mb_reset, + bus_struct_reset => bus_struct_reset, + peripheral_reset => peripheral_reset, + interconnect_aresetn => interconnect_aresetn, + peripheral_aresetn => peripheral_aresetn + ); +END z_turn_rst_ps_7_166M_0_arch; diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.upgrade_log b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.upgrade_log new file mode 100644 index 0000000..9bb29c8 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.upgrade_log @@ -0,0 +1,16 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +| Date : Fri Jul 10 13:44:17 2015 +| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7z020clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'z_turn_rst_ps_7_166M_0' + +1. Summary +---------- + +SUCCESS in the update of z_turn_rst_ps_7_166M_0 (xilinx.com:ip:proc_sys_reset:5.0 (Rev. 7)) to current project options. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.veo b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.veo new file mode 100644 index 0000000..a0c569d --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.veo @@ -0,0 +1,74 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 +// IP Revision: 7 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +z_turn_rst_ps_7_166M_0 your_instance_name ( + .slowest_sync_clk(slowest_sync_clk), // input wire slowest_sync_clk + .ext_reset_in(ext_reset_in), // input wire ext_reset_in + .aux_reset_in(aux_reset_in), // input wire aux_reset_in + .mb_debug_sys_rst(mb_debug_sys_rst), // input wire mb_debug_sys_rst + .dcm_locked(dcm_locked), // input wire dcm_locked + .mb_reset(mb_reset), // output wire mb_reset + .bus_struct_reset(bus_struct_reset), // output wire [0 : 0] bus_struct_reset + .peripheral_reset(peripheral_reset), // output wire [0 : 0] peripheral_reset + .interconnect_aresetn(interconnect_aresetn), // output wire [0 : 0] interconnect_aresetn + .peripheral_aresetn(peripheral_aresetn) // output wire [0 : 0] peripheral_aresetn +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file z_turn_rst_ps_7_166M_0.v when simulating +// the core, z_turn_rst_ps_7_166M_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.xci b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.xci new file mode 100644 index 0000000..959686b --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.xci @@ -0,0 +1,66 @@ + + + xilinx.com + xci + unknown + 1.0 + + + z_turn_rst_ps_7_166M_0 + + + 1 + 1 + 1 + 1 + 0 + 0 + 4 + 4 + z_turn_rst_ps_7_166M_0 + false + Custom + zynq + 4 + 4 + 0 + 0 + 1 + 1 + 1 + 1 + 50000000 + z_turn_processing_system7_0_0_FCLK_CLK1 + zynq + xc7z020 + clg400 + -1 + C + + VERILOG + MIXED + TRUE + TRUE + + TRUE + 2015.2 + 7 + OUT_OF_CONTEXT + + . + ../../../../ipshared + IP_Integrator + + + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.xdc b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.xdc new file mode 100644 index 0000000..0d284d0 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.xdc @@ -0,0 +1,49 @@ + +# file: z_turn_rst_ps_7_166M_0.xdc +# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +set_false_path -to [get_pins -hier *cdc_to*/D] diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.xml new file mode 100644 index 0000000..98de275 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.xml @@ -0,0 +1,1204 @@ + + + xilinx.com + customized_ip + z_turn_rst_ps_7_166M_0 + 1.0 + + + clock + Clock + + + + + + + CLK + + + slowest_sync_clk + + + + + + ASSOCIATED_RESET + mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset + + + FREQ_HZ + Slowest Sync clock frequency + Slowest Synchronous clock frequency + 50000000 + + + CLK_DOMAIN + z_turn_processing_system7_0_0_FCLK_CLK1 + + + + + ext_reset + Ext_Reset + + + + + + + RST + + + ext_reset_in + + + + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + + required + + + + + + + + aux_reset + aux_reset + + + + + + + RST + + + aux_reset_in + + + + + + dbg_reset + DBG_Reset + + + + + + + RST + + + mb_debug_sys_rst + + + + + + POLARITY + ACTIVE_HIGH + + + + + mb_rst + MB_rst + + + + + + + RST + + + mb_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PROCESSOR + + + + + bus_struct_reset + bus_struct_reset + + + + + + + RST + + + bus_struct_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + interconnect_low_rst + interconnect_low_rst + + + + + + + RST + + + interconnect_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + INTERCONNECT + + + + + peripheral_high_rst + peripheral_high_rst + + + + + + + RST + + + peripheral_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + + + peripheral_low_rst + peripheral_low_rst + + + + + + + RST + + + peripheral_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + PERIPHERAL + + + + + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + customizationCRC + c4626279 + + + customizationCRCversion + 5 + + + boundaryCRC + db2c5124 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:43 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + + xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + customizationCRC + c4626279 + + + customizationCRCversion + 5 + + + boundaryCRC + db2c5124 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:43 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + xilinx_synthesisconstraints_view_fileset + + + + customizationCRC + c4626279 + + + customizationCRCversion + 5 + + + boundaryCRC + db2c5124 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:43 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + customizationCRC + c4626279 + + + customizationCRCversion + 5 + + + boundaryCRC + db2c5124 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:43 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + customizationCRC + e72ca2db + + + customizationCRCversion + 5 + + + boundaryCRC + db2c5124 + + + boundaryCRCversion + 1 + + + GENtimestamp + Wed Jul 08 07:19:55 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + + xilinx_vhdlsimulationwrapper_view_fileset + + + + customizationCRC + e72ca2db + + + customizationCRCversion + 5 + + + boundaryCRC + db2c5124 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:43 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + customizationCRC + c4626279 + + + customizationCRCversion + 5 + + + boundaryCRC + db2c5124 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:43 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + customizationCRC + c4626279 + + + customizationCRCversion + 5 + + + boundaryCRC + db2c5124 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:43 UTC 2015 + + + StaleAtRelink + false + + + + + + + slowest_sync_clk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + ext_reset_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + aux_reset_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + mb_debug_sys_rst + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + dcm_locked + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + mb_reset + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + bus_struct_reset + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + peripheral_reset + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + interconnect_aresetn + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + peripheral_aresetn + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + + + C_FAMILY + zynq + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RESET_HIGH + Ext Reset High + 0 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + + + + choices_0 + Custom + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + z_turn_rst_ps_7_166M_0.veo + verilogTemplate + + + + xilinx_vhdlsynthesis_view_fileset + + ../../../../ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/upcnt_n.vhd + vhdlSource + proc_sys_reset_v5_0 + + + ../../../../ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/sequence.vhd + vhdlSource + proc_sys_reset_v5_0 + + + ../../../../ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/lpf.vhd + vhdlSource + proc_sys_reset_v5_0 + + + ../../../../ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/proc_sys_reset.vhd + vhdlSource + proc_sys_reset_v5_0 + + + z_turn_rst_ps_7_166M_0.xdc + xdc + + + + xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + ../../../../ipshared/xilinx.com/lib_cdc_v1_0/ea79928f/hdl/src/vhdl/cdc_sync.vhd + vhdlSource + lib_cdc_v1_0 + + + + + + + + + + + xilinx_synthesisconstraints_view_fileset + + z_turn_rst_ps_7_166M_0_ooc.xdc + xdc + USED_IN_synthesis + USED_IN_implementation + USED_IN_out_of_context + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/z_turn_rst_ps_7_166M_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../../../ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/upcnt_n.vhd + vhdlSource + proc_sys_reset_v5_0 + + + ../../../../ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/sequence.vhd + vhdlSource + proc_sys_reset_v5_0 + + + ../../../../ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/lpf.vhd + vhdlSource + proc_sys_reset_v5_0 + + + ../../../../ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/proc_sys_reset.vhd + vhdlSource + proc_sys_reset_v5_0 + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + ../../../../ipshared/xilinx.com/lib_cdc_v1_0/ea79928f/hdl/src/vhdl/cdc_sync.vhd + vhdlSource + lib_cdc_v1_0 + + + + + + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/z_turn_rst_ps_7_166M_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_implementation_view_fileset + + z_turn_rst_ps_7_166M_0_board.xdc + xdc + USED_IN_synthesis + USED_IN_implementation + USED_IN_board + + + + xilinx_versioninformation_view_fileset + + doc/proc_sys_reset_v5_0_changelog.txt + text + + + + Processor Reset System + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_EXT_RESET_HIGH + Ext Reset High + 0 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + Component_Name + z_turn_rst_ps_7_166M_0 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + RESET_BOARD_INTERFACE + Custom + + + + + + /Embedded_Processing/Clock_&_Reset + + Processor System Reset + level_2 + http://www.xilinx.com + 7 + + xilinx.com:ip:proc_sys_reset:4.00.a + + 2015-06-23T16:14:01Z + + + + + + + + + 2015.2 + + + + + + + + \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0_board.xdc b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0_board.xdc new file mode 100644 index 0000000..3422a8e --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0_board.xdc @@ -0,0 +1,2 @@ +#--------------------Physical Constraints----------------- + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0_ooc.xdc b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0_ooc.xdc new file mode 100644 index 0000000..af238a2 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0_ooc.xdc @@ -0,0 +1,58 @@ +# (c) Copyright 2012-2015 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# DO NOT MODIFY THIS FILE. +# ######################################################### +# +# This XDC is used only in OOC mode for synthesis, implementation +# +# ######################################################### + + +create_clock -period 20 -name slowest_sync_clk [get_ports slowest_sync_clk] +set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports slowest_sync_clk] + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/doc/util_vector_logic_v2_0_changelog.txt b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/doc/util_vector_logic_v2_0_changelog.txt new file mode 100644 index 0000000..c29ccd1 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/doc/util_vector_logic_v2_0_changelog.txt @@ -0,0 +1,56 @@ +2014.4: +* Version 2.0 +* Changed the port ordering from (0 to C_SIZE-1) to (C_SIZE-1 downto 0) +* Updated the vhdl library name from util_vector_logic_v1_0 to util_vector_logic_v2_0 + +2014.1: + * Version 1.0 (Rev. 2) + * Updated the vhdl library name from work to util_vector_logic_v1_0 + + + (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/sim/z_turn_util_vector_logic_0_0.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/sim/z_turn_util_vector_logic_0_0.vhd new file mode 100644 index 0000000..0a7713b --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/sim/z_turn_util_vector_logic_0_0.vhd @@ -0,0 +1,92 @@ +-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 +-- IP Revision: 0 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY util_vector_logic_v2_0; +USE util_vector_logic_v2_0.util_vector_logic; + +ENTITY z_turn_util_vector_logic_0_0 IS + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END z_turn_util_vector_logic_0_0; + +ARCHITECTURE z_turn_util_vector_logic_0_0_arch OF z_turn_util_vector_logic_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : string; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes"; + + COMPONENT util_vector_logic IS + GENERIC ( + C_OPERATION : STRING; + C_SIZE : INTEGER + ); + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT util_vector_logic; +BEGIN + U0 : util_vector_logic + GENERIC MAP ( + C_OPERATION => "not", + C_SIZE => 1 + ) + PORT MAP ( + Op1 => Op1, + Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + Res => Res + ); +END z_turn_util_vector_logic_0_0_arch; diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/synth/z_turn_util_vector_logic_0_0.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/synth/z_turn_util_vector_logic_0_0.vhd new file mode 100644 index 0000000..206bd25 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/synth/z_turn_util_vector_logic_0_0.vhd @@ -0,0 +1,98 @@ +-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 +-- IP Revision: 0 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY util_vector_logic_v2_0; +USE util_vector_logic_v2_0.util_vector_logic; + +ENTITY z_turn_util_vector_logic_0_0 IS + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END z_turn_util_vector_logic_0_0; + +ARCHITECTURE z_turn_util_vector_logic_0_0_arch OF z_turn_util_vector_logic_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : string; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes"; + + COMPONENT util_vector_logic IS + GENERIC ( + C_OPERATION : STRING; + C_SIZE : INTEGER + ); + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT util_vector_logic; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2015.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_util_vector_logic_0_0_arch : ARCHITECTURE IS "z_turn_util_vector_logic_0_0,util_vector_logic,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "z_turn_util_vector_logic_0_0,util_vector_logic,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_OPERATION=not,C_SIZE=1}"; +BEGIN + U0 : util_vector_logic + GENERIC MAP ( + C_OPERATION => "not", + C_SIZE => 1 + ) + PORT MAP ( + Op1 => Op1, + Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + Res => Res + ); +END z_turn_util_vector_logic_0_0_arch; diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.upgrade_log b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.upgrade_log new file mode 100644 index 0000000..7c1bd9d --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.upgrade_log @@ -0,0 +1,16 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +| Date : Fri Jul 10 13:44:18 2015 +| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7z020clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'z_turn_util_vector_logic_0_0' + +1. Summary +---------- + +SUCCESS in the update of z_turn_util_vector_logic_0_0 (xilinx.com:ip:util_vector_logic:2.0) to current project options. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.veo b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.veo new file mode 100644 index 0000000..09e2f30 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.veo @@ -0,0 +1,66 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:util_vector_logic:2.0 +// IP Revision: 0 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +z_turn_util_vector_logic_0_0 your_instance_name ( + .Op1(Op1), // input wire [0 : 0] Op1 + .Res(Res) // output wire [0 : 0] Res +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file z_turn_util_vector_logic_0_0.v when simulating +// the core, z_turn_util_vector_logic_0_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.xci b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.xci new file mode 100644 index 0000000..eb28ce7 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.xci @@ -0,0 +1,47 @@ + + + xilinx.com + xci + unknown + 1.0 + + + z_turn_util_vector_logic_0_0 + + + 1 + not + z_turn_util_vector_logic_0_0 + not + 1 + zynq + xc7z020 + clg400 + -1 + C + + VERILOG + MIXED + TRUE + TRUE + + TRUE + 2015.2 + 0 + OUT_OF_CONTEXT + + . + ../../../../ipshared + IP_Integrator + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.xml new file mode 100644 index 0000000..353913b --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.xml @@ -0,0 +1,443 @@ + + + xilinx.com + customized_ip + z_turn_util_vector_logic_0_0 + 1.0 + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + + xilinx_vhdlsynthesis_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 03:52:31 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + customizationCRC + e54c2ed1 + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 03:52:31 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + + xilinx_vhdlsimulationwrapper_view_fileset + + + + customizationCRC + e54c2ed1 + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + + + Op1 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + Op2 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + optional + false + + + + + + Res + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_OPERATION + C Operation + not + + + C_SIZE + C Size + 1 + + + + + + choices_0 + and + or + xor + not + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + z_turn_util_vector_logic_0_0.veo + verilogTemplate + + + + xilinx_vhdlsynthesis_view_fileset + + ../../../../ipshared/xilinx.com/util_vector_logic_v2_0/5ac42227/hdl/util_vector_logic.vhd + vhdlSource + util_vector_logic_v2_0 + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/z_turn_util_vector_logic_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../../../ipshared/xilinx.com/util_vector_logic_v2_0/5ac42227/hdl/util_vector_logic.vhd + vhdlSource + util_vector_logic_v2_0 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/z_turn_util_vector_logic_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/util_vector_logic_v2_0_changelog.txt + text + + + + Performs bitwise logic operations on two n-bit inputs to produce a single n-bit output + + + C_SIZE + C Size + 1 + + + C_OPERATION + C Operation + not + + + Component_Name + z_turn_util_vector_logic_0_0 + + + + + + aartix7 + artix7 + artix7l + azynq + kintex7l + qartix7 + qkintex7 + qkintex7l + qvirtex7 + qzynq + virtex7 + zynq + kintex7 + kintexu + virtexu + + + /BaseIP + + Utility Vector Logic + + IPI + + Xilinx + http://www.xilinx.com + 0 + 2014-10-03T23:01:11Z + + + + + + + + 2014.4.0 + + + + + + + \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/doc/util_vector_logic_v2_0_changelog.txt b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/doc/util_vector_logic_v2_0_changelog.txt new file mode 100644 index 0000000..c29ccd1 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/doc/util_vector_logic_v2_0_changelog.txt @@ -0,0 +1,56 @@ +2014.4: +* Version 2.0 +* Changed the port ordering from (0 to C_SIZE-1) to (C_SIZE-1 downto 0) +* Updated the vhdl library name from util_vector_logic_v1_0 to util_vector_logic_v2_0 + +2014.1: + * Version 1.0 (Rev. 2) + * Updated the vhdl library name from work to util_vector_logic_v1_0 + + + (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/sim/z_turn_util_vector_logic_0_1.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/sim/z_turn_util_vector_logic_0_1.vhd new file mode 100644 index 0000000..4923f2b --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/sim/z_turn_util_vector_logic_0_1.vhd @@ -0,0 +1,92 @@ +-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 +-- IP Revision: 0 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY util_vector_logic_v2_0; +USE util_vector_logic_v2_0.util_vector_logic; + +ENTITY z_turn_util_vector_logic_0_1 IS + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END z_turn_util_vector_logic_0_1; + +ARCHITECTURE z_turn_util_vector_logic_0_1_arch OF z_turn_util_vector_logic_0_1 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : string; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "yes"; + + COMPONENT util_vector_logic IS + GENERIC ( + C_OPERATION : STRING; + C_SIZE : INTEGER + ); + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT util_vector_logic; +BEGIN + U0 : util_vector_logic + GENERIC MAP ( + C_OPERATION => "not", + C_SIZE => 1 + ) + PORT MAP ( + Op1 => Op1, + Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + Res => Res + ); +END z_turn_util_vector_logic_0_1_arch; diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/synth/z_turn_util_vector_logic_0_1.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/synth/z_turn_util_vector_logic_0_1.vhd new file mode 100644 index 0000000..8a8f9a9 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/synth/z_turn_util_vector_logic_0_1.vhd @@ -0,0 +1,98 @@ +-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 +-- IP Revision: 0 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY util_vector_logic_v2_0; +USE util_vector_logic_v2_0.util_vector_logic; + +ENTITY z_turn_util_vector_logic_0_1 IS + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END z_turn_util_vector_logic_0_1; + +ARCHITECTURE z_turn_util_vector_logic_0_1_arch OF z_turn_util_vector_logic_0_1 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : string; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "yes"; + + COMPONENT util_vector_logic IS + GENERIC ( + C_OPERATION : STRING; + C_SIZE : INTEGER + ); + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT util_vector_logic; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2015.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_util_vector_logic_0_1_arch : ARCHITECTURE IS "z_turn_util_vector_logic_0_1,util_vector_logic,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "z_turn_util_vector_logic_0_1,util_vector_logic,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_OPERATION=not,C_SIZE=1}"; +BEGIN + U0 : util_vector_logic + GENERIC MAP ( + C_OPERATION => "not", + C_SIZE => 1 + ) + PORT MAP ( + Op1 => Op1, + Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + Res => Res + ); +END z_turn_util_vector_logic_0_1_arch; diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.upgrade_log b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.upgrade_log new file mode 100644 index 0000000..5b8c4cf --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.upgrade_log @@ -0,0 +1,16 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +| Date : Fri Jul 10 13:44:21 2015 +| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7z020clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'z_turn_util_vector_logic_0_1' + +1. Summary +---------- + +SUCCESS in the update of z_turn_util_vector_logic_0_1 (xilinx.com:ip:util_vector_logic:2.0) to current project options. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.veo b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.veo new file mode 100644 index 0000000..e48254c --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.veo @@ -0,0 +1,66 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:util_vector_logic:2.0 +// IP Revision: 0 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +z_turn_util_vector_logic_0_1 your_instance_name ( + .Op1(Op1), // input wire [0 : 0] Op1 + .Res(Res) // output wire [0 : 0] Res +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file z_turn_util_vector_logic_0_1.v when simulating +// the core, z_turn_util_vector_logic_0_1. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.xci b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.xci new file mode 100644 index 0000000..0eabad4 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.xci @@ -0,0 +1,47 @@ + + + xilinx.com + xci + unknown + 1.0 + + + z_turn_util_vector_logic_0_1 + + + 1 + not + z_turn_util_vector_logic_0_1 + not + 1 + zynq + xc7z020 + clg400 + -1 + C + + VERILOG + MIXED + TRUE + TRUE + + TRUE + 2015.2 + 0 + OUT_OF_CONTEXT + + . + ../../../../ipshared + IP_Integrator + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.xml new file mode 100644 index 0000000..f8f2bba --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.xml @@ -0,0 +1,443 @@ + + + xilinx.com + customized_ip + z_turn_util_vector_logic_0_1 + 1.0 + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + + xilinx_vhdlsynthesis_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 03:52:31 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + customizationCRC + e54c2ed1 + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 03:52:31 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + + xilinx_vhdlsimulationwrapper_view_fileset + + + + customizationCRC + e54c2ed1 + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + + + Op1 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + Op2 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + optional + false + + + + + + Res + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_OPERATION + C Operation + not + + + C_SIZE + C Size + 1 + + + + + + choices_0 + and + or + xor + not + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + z_turn_util_vector_logic_0_1.veo + verilogTemplate + + + + xilinx_vhdlsynthesis_view_fileset + + ../../../../ipshared/xilinx.com/util_vector_logic_v2_0/5ac42227/hdl/util_vector_logic.vhd + vhdlSource + util_vector_logic_v2_0 + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/z_turn_util_vector_logic_0_1.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../../../ipshared/xilinx.com/util_vector_logic_v2_0/5ac42227/hdl/util_vector_logic.vhd + vhdlSource + util_vector_logic_v2_0 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/z_turn_util_vector_logic_0_1.vhd + vhdlSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/util_vector_logic_v2_0_changelog.txt + text + + + + Performs bitwise logic operations on two n-bit inputs to produce a single n-bit output + + + C_SIZE + C Size + 1 + + + C_OPERATION + C Operation + not + + + Component_Name + z_turn_util_vector_logic_0_1 + + + + + + aartix7 + artix7 + artix7l + azynq + kintex7l + qartix7 + qkintex7 + qkintex7l + qvirtex7 + qzynq + virtex7 + zynq + kintex7 + kintexu + virtexu + + + /BaseIP + + Utility Vector Logic + + IPI + + Xilinx + http://www.xilinx.com + 0 + 2014-10-03T23:01:11Z + + + + + + + + 2014.4.0 + + + + + + + \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/doc/util_vector_logic_v2_0_changelog.txt b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/doc/util_vector_logic_v2_0_changelog.txt new file mode 100644 index 0000000..c29ccd1 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/doc/util_vector_logic_v2_0_changelog.txt @@ -0,0 +1,56 @@ +2014.4: +* Version 2.0 +* Changed the port ordering from (0 to C_SIZE-1) to (C_SIZE-1 downto 0) +* Updated the vhdl library name from util_vector_logic_v1_0 to util_vector_logic_v2_0 + +2014.1: + * Version 1.0 (Rev. 2) + * Updated the vhdl library name from work to util_vector_logic_v1_0 + + + (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/sim/z_turn_util_vector_logic_1_0.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/sim/z_turn_util_vector_logic_1_0.vhd new file mode 100644 index 0000000..fdef930 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/sim/z_turn_util_vector_logic_1_0.vhd @@ -0,0 +1,92 @@ +-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 +-- IP Revision: 0 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY util_vector_logic_v2_0; +USE util_vector_logic_v2_0.util_vector_logic; + +ENTITY z_turn_util_vector_logic_1_0 IS + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END z_turn_util_vector_logic_1_0; + +ARCHITECTURE z_turn_util_vector_logic_1_0_arch OF z_turn_util_vector_logic_1_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : string; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "yes"; + + COMPONENT util_vector_logic IS + GENERIC ( + C_OPERATION : STRING; + C_SIZE : INTEGER + ); + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT util_vector_logic; +BEGIN + U0 : util_vector_logic + GENERIC MAP ( + C_OPERATION => "not", + C_SIZE => 1 + ) + PORT MAP ( + Op1 => Op1, + Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + Res => Res + ); +END z_turn_util_vector_logic_1_0_arch; diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/synth/z_turn_util_vector_logic_1_0.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/synth/z_turn_util_vector_logic_1_0.vhd new file mode 100644 index 0000000..57a667f --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/synth/z_turn_util_vector_logic_1_0.vhd @@ -0,0 +1,98 @@ +-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 +-- IP Revision: 0 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY util_vector_logic_v2_0; +USE util_vector_logic_v2_0.util_vector_logic; + +ENTITY z_turn_util_vector_logic_1_0 IS + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END z_turn_util_vector_logic_1_0; + +ARCHITECTURE z_turn_util_vector_logic_1_0_arch OF z_turn_util_vector_logic_1_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : string; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "yes"; + + COMPONENT util_vector_logic IS + GENERIC ( + C_OPERATION : STRING; + C_SIZE : INTEGER + ); + PORT ( + Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT util_vector_logic; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2015.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_util_vector_logic_1_0_arch : ARCHITECTURE IS "z_turn_util_vector_logic_1_0,util_vector_logic,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "z_turn_util_vector_logic_1_0,util_vector_logic,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_OPERATION=not,C_SIZE=1}"; +BEGIN + U0 : util_vector_logic + GENERIC MAP ( + C_OPERATION => "not", + C_SIZE => 1 + ) + PORT MAP ( + Op1 => Op1, + Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + Res => Res + ); +END z_turn_util_vector_logic_1_0_arch; diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.upgrade_log b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.upgrade_log new file mode 100644 index 0000000..7c83933 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.upgrade_log @@ -0,0 +1,16 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +| Date : Fri Jul 10 13:44:22 2015 +| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7z020clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'z_turn_util_vector_logic_1_0' + +1. Summary +---------- + +SUCCESS in the update of z_turn_util_vector_logic_1_0 (xilinx.com:ip:util_vector_logic:2.0) to current project options. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.veo b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.veo new file mode 100644 index 0000000..4090d08 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.veo @@ -0,0 +1,66 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:util_vector_logic:2.0 +// IP Revision: 0 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +z_turn_util_vector_logic_1_0 your_instance_name ( + .Op1(Op1), // input wire [0 : 0] Op1 + .Res(Res) // output wire [0 : 0] Res +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file z_turn_util_vector_logic_1_0.v when simulating +// the core, z_turn_util_vector_logic_1_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.xci b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.xci new file mode 100644 index 0000000..a09eb1e --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.xci @@ -0,0 +1,47 @@ + + + xilinx.com + xci + unknown + 1.0 + + + z_turn_util_vector_logic_1_0 + + + 1 + not + z_turn_util_vector_logic_1_0 + not + 1 + zynq + xc7z020 + clg400 + -1 + C + + VERILOG + MIXED + TRUE + TRUE + + TRUE + 2015.2 + 0 + OUT_OF_CONTEXT + + . + ../../../../ipshared + IP_Integrator + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.xml new file mode 100644 index 0000000..dc7a4b3 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.xml @@ -0,0 +1,443 @@ + + + xilinx.com + customized_ip + z_turn_util_vector_logic_1_0 + 1.0 + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + + xilinx_vhdlsynthesis_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 03:52:31 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + customizationCRC + e54c2ed1 + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 03:52:31 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + + xilinx_vhdlsimulationwrapper_view_fileset + + + + customizationCRC + e54c2ed1 + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + customizationCRC + 41518b0e + + + customizationCRCversion + 5 + + + boundaryCRC + 2cb6a31c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + + + Op1 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + Op2 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + optional + false + + + + + + Res + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_OPERATION + C Operation + not + + + C_SIZE + C Size + 1 + + + + + + choices_0 + and + or + xor + not + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + z_turn_util_vector_logic_1_0.veo + verilogTemplate + + + + xilinx_vhdlsynthesis_view_fileset + + ../../../../ipshared/xilinx.com/util_vector_logic_v2_0/5ac42227/hdl/util_vector_logic.vhd + vhdlSource + util_vector_logic_v2_0 + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/z_turn_util_vector_logic_1_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../../../ipshared/xilinx.com/util_vector_logic_v2_0/5ac42227/hdl/util_vector_logic.vhd + vhdlSource + util_vector_logic_v2_0 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/z_turn_util_vector_logic_1_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/util_vector_logic_v2_0_changelog.txt + text + + + + Performs bitwise logic operations on two n-bit inputs to produce a single n-bit output + + + C_SIZE + C Size + 1 + + + C_OPERATION + C Operation + not + + + Component_Name + z_turn_util_vector_logic_1_0 + + + + + + aartix7 + artix7 + artix7l + azynq + kintex7l + qartix7 + qkintex7 + qkintex7l + qvirtex7 + qzynq + virtex7 + zynq + kintex7 + kintexu + virtexu + + + /BaseIP + + Utility Vector Logic + + IPI + + Xilinx + http://www.xilinx.com + 0 + 2014-10-03T23:01:11Z + + + + + + + + 2014.4.0 + + + + + + + \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/doc/xlconcat_v2_1_changelog.txt b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/doc/xlconcat_v2_1_changelog.txt new file mode 100644 index 0000000..d07a13b --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/doc/xlconcat_v2_1_changelog.txt @@ -0,0 +1,64 @@ +2014.4 + * Version 2.1 (Rev.1) + * Add Auto/Manual button for Inxx Width in GUI dialog. + +2014.2 + * Version 2.1 + * upgrade input sources from 16 to 32. + +2014.1: + * Version 2.0 + * Version 1.0 of the xlconcat block reverses the order in + * which input signals are concatenated. Version 2.0 + * preserves the order of input signals on the output. + * The upgrade from 1.0 to 2.0 will change input connections + * in order to preserve the overall the signal order on output. + + + (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/sim/z_turn_xlconcat_0_0.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/sim/z_turn_xlconcat_0_0.v new file mode 100644 index 0000000..e6ec994 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/sim/z_turn_xlconcat_0_0.v @@ -0,0 +1,164 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module z_turn_xlconcat_0_0 ( + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + dout +); + +input wire [0 : 0] In0; +input wire [0 : 0] In1; +input wire [0 : 0] In2; +input wire [0 : 0] In3; +input wire [0 : 0] In4; +input wire [0 : 0] In5; +input wire [0 : 0] In6; +input wire [0 : 0] In7; +input wire [0 : 0] In8; +input wire [0 : 0] In9; +input wire [0 : 0] In10; +input wire [0 : 0] In11; +input wire [0 : 0] In12; +input wire [0 : 0] In13; +input wire [0 : 0] In14; +input wire [0 : 0] In15; +output wire [15 : 0] dout; + + xlconcat #( + .IN0_WIDTH(1), + .IN1_WIDTH(1), + .IN2_WIDTH(1), + .IN3_WIDTH(1), + .IN4_WIDTH(1), + .IN5_WIDTH(1), + .IN6_WIDTH(1), + .IN7_WIDTH(1), + .IN8_WIDTH(1), + .IN9_WIDTH(1), + .IN10_WIDTH(1), + .IN11_WIDTH(1), + .IN12_WIDTH(1), + .IN13_WIDTH(1), + .IN14_WIDTH(1), + .IN15_WIDTH(1), + .IN16_WIDTH(1), + .IN17_WIDTH(1), + .IN18_WIDTH(1), + .IN19_WIDTH(1), + .IN20_WIDTH(1), + .IN21_WIDTH(1), + .IN22_WIDTH(1), + .IN23_WIDTH(1), + .IN24_WIDTH(1), + .IN25_WIDTH(1), + .IN26_WIDTH(1), + .IN27_WIDTH(1), + .IN28_WIDTH(1), + .IN29_WIDTH(1), + .IN30_WIDTH(1), + .IN31_WIDTH(1), + .dout_width(16), + .NUM_PORTS(16) + ) inst ( + .In0(In0), + .In1(In1), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In16(1'B0), + .In17(1'B0), + .In18(1'B0), + .In19(1'B0), + .In20(1'B0), + .In21(1'B0), + .In22(1'B0), + .In23(1'B0), + .In24(1'B0), + .In25(1'B0), + .In26(1'B0), + .In27(1'B0), + .In28(1'B0), + .In29(1'B0), + .In30(1'B0), + .In31(1'B0), + .dout(dout) + ); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/synth/z_turn_xlconcat_0_0.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/synth/z_turn_xlconcat_0_0.v new file mode 100644 index 0000000..14ff4ec --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/synth/z_turn_xlconcat_0_0.v @@ -0,0 +1,165 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +(* X_CORE_INFO = "xlconcat,Vivado 2015.2" *) +(* CHECK_LICENSE_TYPE = "z_turn_xlconcat_0_0,xlconcat,{}" *) +(* CORE_GENERATION_INFO = "z_turn_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=16,NUM_PORTS=16}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module z_turn_xlconcat_0_0 ( + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + dout +); + +input wire [0 : 0] In0; +input wire [0 : 0] In1; +input wire [0 : 0] In2; +input wire [0 : 0] In3; +input wire [0 : 0] In4; +input wire [0 : 0] In5; +input wire [0 : 0] In6; +input wire [0 : 0] In7; +input wire [0 : 0] In8; +input wire [0 : 0] In9; +input wire [0 : 0] In10; +input wire [0 : 0] In11; +input wire [0 : 0] In12; +input wire [0 : 0] In13; +input wire [0 : 0] In14; +input wire [0 : 0] In15; +output wire [15 : 0] dout; + + xlconcat #( + .IN0_WIDTH(1), + .IN1_WIDTH(1), + .IN2_WIDTH(1), + .IN3_WIDTH(1), + .IN4_WIDTH(1), + .IN5_WIDTH(1), + .IN6_WIDTH(1), + .IN7_WIDTH(1), + .IN8_WIDTH(1), + .IN9_WIDTH(1), + .IN10_WIDTH(1), + .IN11_WIDTH(1), + .IN12_WIDTH(1), + .IN13_WIDTH(1), + .IN14_WIDTH(1), + .IN15_WIDTH(1), + .IN16_WIDTH(1), + .IN17_WIDTH(1), + .IN18_WIDTH(1), + .IN19_WIDTH(1), + .IN20_WIDTH(1), + .IN21_WIDTH(1), + .IN22_WIDTH(1), + .IN23_WIDTH(1), + .IN24_WIDTH(1), + .IN25_WIDTH(1), + .IN26_WIDTH(1), + .IN27_WIDTH(1), + .IN28_WIDTH(1), + .IN29_WIDTH(1), + .IN30_WIDTH(1), + .IN31_WIDTH(1), + .dout_width(16), + .NUM_PORTS(16) + ) inst ( + .In0(In0), + .In1(In1), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In16(1'B0), + .In17(1'B0), + .In18(1'B0), + .In19(1'B0), + .In20(1'B0), + .In21(1'B0), + .In22(1'B0), + .In23(1'B0), + .In24(1'B0), + .In25(1'B0), + .In26(1'B0), + .In27(1'B0), + .In28(1'B0), + .In29(1'B0), + .In30(1'B0), + .In31(1'B0), + .dout(dout) + ); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.upgrade_log b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.upgrade_log new file mode 100644 index 0000000..00a29dc --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.upgrade_log @@ -0,0 +1,16 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +| Date : Fri Jul 10 13:44:23 2015 +| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7z020clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'z_turn_xlconcat_0_0' + +1. Summary +---------- + +SUCCESS in the update of z_turn_xlconcat_0_0 (xilinx.com:ip:xlconcat:2.1 (Rev. 1)) to current project options. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.veo b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.veo new file mode 100644 index 0000000..e553f93 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.veo @@ -0,0 +1,81 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +z_turn_xlconcat_0_0 your_instance_name ( + .In0(In0), // input wire [0 : 0] In0 + .In1(In1), // input wire [0 : 0] In1 + .In2(In2), // input wire [0 : 0] In2 + .In3(In3), // input wire [0 : 0] In3 + .In4(In4), // input wire [0 : 0] In4 + .In5(In5), // input wire [0 : 0] In5 + .In6(In6), // input wire [0 : 0] In6 + .In7(In7), // input wire [0 : 0] In7 + .In8(In8), // input wire [0 : 0] In8 + .In9(In9), // input wire [0 : 0] In9 + .In10(In10), // input wire [0 : 0] In10 + .In11(In11), // input wire [0 : 0] In11 + .In12(In12), // input wire [0 : 0] In12 + .In13(In13), // input wire [0 : 0] In13 + .In14(In14), // input wire [0 : 0] In14 + .In15(In15), // input wire [0 : 0] In15 + .dout(dout) // output wire [15 : 0] dout +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file z_turn_xlconcat_0_0.v when simulating +// the core, z_turn_xlconcat_0_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.xci b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.xci new file mode 100644 index 0000000..b231c0e --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.xci @@ -0,0 +1,126 @@ + + + xilinx.com + xci + unknown + 1.0 + + + z_turn_xlconcat_0_0 + + + 16 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + z_turn_xlconcat_0_0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 16 + 16 + zynq + xc7z020 + clg400 + -1 + C + + VERILOG + MIXED + TRUE + TRUE + + TRUE + 2015.2 + 1 + OUT_OF_CONTEXT + + . + ../../../../ipshared + IP_Integrator + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.xml new file mode 100644 index 0000000..64abb91 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.xml @@ -0,0 +1,1936 @@ + + + xilinx.com + customized_ip + z_turn_xlconcat_0_0 + 1.0 + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + customizationCRC + e59d4259 + + + customizationCRCversion + 5 + + + boundaryCRC + c92f259f + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:43 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + + xilinx_verilogsynthesis_view_fileset + + + + customizationCRC + e59d4259 + + + customizationCRCversion + 5 + + + boundaryCRC + c92f259f + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 03 07:51:34 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + + xilinx_verilogsynthesiswrapper_view_fileset + + + + customizationCRC + e59d4259 + + + customizationCRCversion + 5 + + + boundaryCRC + c92f259f + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:43 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + + xilinx_verilogbehavioralsimulation_view_fileset + + + + customizationCRC + 0686b6b9 + + + customizationCRCversion + 5 + + + boundaryCRC + c92f259f + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 03 07:51:34 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + + xilinx_verilogsimulationwrapper_view_fileset + + + + customizationCRC + 0686b6b9 + + + customizationCRCversion + 5 + + + boundaryCRC + c92f259f + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:43 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + customizationCRC + e59d4259 + + + customizationCRCversion + 5 + + + boundaryCRC + c92f259f + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:43 UTC 2015 + + + StaleAtRelink + false + + + + + + + In0 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In1 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In2 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In3 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In4 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In5 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In6 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In7 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In8 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In9 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In10 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In11 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In12 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In13 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In14 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In15 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In16 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In17 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In18 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In19 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In20 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In21 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In22 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In23 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In24 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In25 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In26 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In27 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In28 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In29 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In30 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In31 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + dout + + out + + 15 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + IN0_WIDTH + In0 Width + 1 + + + IN1_WIDTH + In1 Width + 1 + + + IN2_WIDTH + In2 Width + 1 + + + IN3_WIDTH + In3 Width + 1 + + + IN4_WIDTH + In4 Width + 1 + + + IN5_WIDTH + In5 Width + 1 + + + IN6_WIDTH + In6 Width + 1 + + + IN7_WIDTH + In7 Width + 1 + + + IN8_WIDTH + In8 Width + 1 + + + IN9_WIDTH + In9 Width + 1 + + + IN10_WIDTH + In10 Width + 1 + + + IN11_WIDTH + In11 Width + 1 + + + IN12_WIDTH + In12 Width + 1 + + + IN13_WIDTH + In13 Width + 1 + + + IN14_WIDTH + In14 Width + 1 + + + IN15_WIDTH + In15 Width + 1 + + + IN16_WIDTH + In16 Width + 1 + + + IN17_WIDTH + In17 Width + 1 + + + IN18_WIDTH + In18 Width + 1 + + + IN19_WIDTH + In19 Width + 1 + + + IN20_WIDTH + In20 Width + 1 + + + IN21_WIDTH + In21 Width + 1 + + + IN22_WIDTH + In22 Width + 1 + + + IN23_WIDTH + In23 Width + 1 + + + IN24_WIDTH + In24 Width + 1 + + + IN25_WIDTH + In25 Width + 1 + + + IN26_WIDTH + In26 Width + 1 + + + IN27_WIDTH + In27 Width + 1 + + + IN28_WIDTH + In28 Width + 1 + + + IN29_WIDTH + In29 Width + 1 + + + IN30_WIDTH + In30 Width + 1 + + + IN31_WIDTH + In31 Width + 1 + + + dout_width + Dout Width + 16 + + + NUM_PORTS + Number of Ports + 16 + + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + z_turn_xlconcat_0_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_view_fileset + + ../../../../ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.v + verilogSource + work + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/z_turn_xlconcat_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../../../ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.v + verilogSource + work + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/z_turn_xlconcat_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/xlconcat_v2_1_changelog.txt + text + + + + Concatenates up to 32 ports into a single port + + + NUM_PORTS + Number of Ports + 16 + + + IN0_WIDTH + In0 Width + 1 + + + IN1_WIDTH + In1 Width + 1 + + + IN2_WIDTH + In2 Width + 1 + + + IN3_WIDTH + In3 Width + 1 + + + IN4_WIDTH + In4 Width + 1 + + + IN5_WIDTH + In5 Width + 1 + + + IN6_WIDTH + In6 Width + 1 + + + IN7_WIDTH + In7 Width + 1 + + + IN8_WIDTH + In8 Width + 1 + + + IN9_WIDTH + In9 Width + 1 + + + IN10_WIDTH + In10 Width + 1 + + + IN11_WIDTH + In11 Width + 1 + + + IN12_WIDTH + In12 Width + 1 + + + IN13_WIDTH + In13 Width + 1 + + + IN14_WIDTH + In14 Width + 1 + + + IN15_WIDTH + In15 Width + 1 + + + IN16_WIDTH + In16 Width + 1 + + + IN17_WIDTH + In17 Width + 1 + + + Component_Name + z_turn_xlconcat_0_0 + + + IN18_WIDTH + In18 Width + 1 + + + IN19_WIDTH + In19 Width + 1 + + + IN20_WIDTH + In20 Width + 1 + + + IN21_WIDTH + In21 Width + 1 + + + IN22_WIDTH + In22 Width + 1 + + + IN23_WIDTH + In23 Width + 1 + + + IN24_WIDTH + In24 Width + 1 + + + IN25_WIDTH + In25 Width + 1 + + + IN26_WIDTH + In26 Width + 1 + + + IN27_WIDTH + In27 Width + 1 + + + IN28_WIDTH + In28 Width + 1 + + + IN29_WIDTH + In29 Width + 1 + + + IN30_WIDTH + In30 Width + 1 + + + IN31_WIDTH + In31 Width + 1 + + + dout_width + Dout Width + 16 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + virtexu + kintexu + + + /Basic_Elements + + Concat + + IPI + + http://www.xilinx.com + 1 + 2014-10-09T21:18:16Z + + + + + + + + + + + + + + + + + + + + + + 2014.4 + + + + + + + \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/doc/xlconcat_v2_1_changelog.txt b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/doc/xlconcat_v2_1_changelog.txt new file mode 100644 index 0000000..d07a13b --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/doc/xlconcat_v2_1_changelog.txt @@ -0,0 +1,64 @@ +2014.4 + * Version 2.1 (Rev.1) + * Add Auto/Manual button for Inxx Width in GUI dialog. + +2014.2 + * Version 2.1 + * upgrade input sources from 16 to 32. + +2014.1: + * Version 2.0 + * Version 1.0 of the xlconcat block reverses the order in + * which input signals are concatenated. Version 2.0 + * preserves the order of input signals on the output. + * The upgrade from 1.0 to 2.0 will change input connections + * in order to preserve the overall the signal order on output. + + + (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/sim/z_turn_xlconcat_0_1.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/sim/z_turn_xlconcat_0_1.v new file mode 100644 index 0000000..d24b6a8 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/sim/z_turn_xlconcat_0_1.v @@ -0,0 +1,136 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module z_turn_xlconcat_0_1 ( + In0, + In1, + dout +); + +input wire [31 : 0] In0; +input wire [31 : 0] In1; +output wire [63 : 0] dout; + + xlconcat #( + .IN0_WIDTH(32), + .IN1_WIDTH(32), + .IN2_WIDTH(1), + .IN3_WIDTH(1), + .IN4_WIDTH(1), + .IN5_WIDTH(1), + .IN6_WIDTH(1), + .IN7_WIDTH(1), + .IN8_WIDTH(1), + .IN9_WIDTH(1), + .IN10_WIDTH(1), + .IN11_WIDTH(1), + .IN12_WIDTH(1), + .IN13_WIDTH(1), + .IN14_WIDTH(1), + .IN15_WIDTH(1), + .IN16_WIDTH(1), + .IN17_WIDTH(1), + .IN18_WIDTH(1), + .IN19_WIDTH(1), + .IN20_WIDTH(1), + .IN21_WIDTH(1), + .IN22_WIDTH(1), + .IN23_WIDTH(1), + .IN24_WIDTH(1), + .IN25_WIDTH(1), + .IN26_WIDTH(1), + .IN27_WIDTH(1), + .IN28_WIDTH(1), + .IN29_WIDTH(1), + .IN30_WIDTH(1), + .IN31_WIDTH(1), + .dout_width(64), + .NUM_PORTS(2) + ) inst ( + .In0(In0), + .In1(In1), + .In2(1'B0), + .In3(1'B0), + .In4(1'B0), + .In5(1'B0), + .In6(1'B0), + .In7(1'B0), + .In8(1'B0), + .In9(1'B0), + .In10(1'B0), + .In11(1'B0), + .In12(1'B0), + .In13(1'B0), + .In14(1'B0), + .In15(1'B0), + .In16(1'B0), + .In17(1'B0), + .In18(1'B0), + .In19(1'B0), + .In20(1'B0), + .In21(1'B0), + .In22(1'B0), + .In23(1'B0), + .In24(1'B0), + .In25(1'B0), + .In26(1'B0), + .In27(1'B0), + .In28(1'B0), + .In29(1'B0), + .In30(1'B0), + .In31(1'B0), + .dout(dout) + ); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/synth/z_turn_xlconcat_0_1.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/synth/z_turn_xlconcat_0_1.v new file mode 100644 index 0000000..d0fc1a3 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/synth/z_turn_xlconcat_0_1.v @@ -0,0 +1,137 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +(* X_CORE_INFO = "xlconcat,Vivado 2015.2" *) +(* CHECK_LICENSE_TYPE = "z_turn_xlconcat_0_1,xlconcat,{}" *) +(* CORE_GENERATION_INFO = "z_turn_xlconcat_0_1,xlconcat,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=32,IN1_WIDTH=32,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=64,NUM_PORTS=2}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module z_turn_xlconcat_0_1 ( + In0, + In1, + dout +); + +input wire [31 : 0] In0; +input wire [31 : 0] In1; +output wire [63 : 0] dout; + + xlconcat #( + .IN0_WIDTH(32), + .IN1_WIDTH(32), + .IN2_WIDTH(1), + .IN3_WIDTH(1), + .IN4_WIDTH(1), + .IN5_WIDTH(1), + .IN6_WIDTH(1), + .IN7_WIDTH(1), + .IN8_WIDTH(1), + .IN9_WIDTH(1), + .IN10_WIDTH(1), + .IN11_WIDTH(1), + .IN12_WIDTH(1), + .IN13_WIDTH(1), + .IN14_WIDTH(1), + .IN15_WIDTH(1), + .IN16_WIDTH(1), + .IN17_WIDTH(1), + .IN18_WIDTH(1), + .IN19_WIDTH(1), + .IN20_WIDTH(1), + .IN21_WIDTH(1), + .IN22_WIDTH(1), + .IN23_WIDTH(1), + .IN24_WIDTH(1), + .IN25_WIDTH(1), + .IN26_WIDTH(1), + .IN27_WIDTH(1), + .IN28_WIDTH(1), + .IN29_WIDTH(1), + .IN30_WIDTH(1), + .IN31_WIDTH(1), + .dout_width(64), + .NUM_PORTS(2) + ) inst ( + .In0(In0), + .In1(In1), + .In2(1'B0), + .In3(1'B0), + .In4(1'B0), + .In5(1'B0), + .In6(1'B0), + .In7(1'B0), + .In8(1'B0), + .In9(1'B0), + .In10(1'B0), + .In11(1'B0), + .In12(1'B0), + .In13(1'B0), + .In14(1'B0), + .In15(1'B0), + .In16(1'B0), + .In17(1'B0), + .In18(1'B0), + .In19(1'B0), + .In20(1'B0), + .In21(1'B0), + .In22(1'B0), + .In23(1'B0), + .In24(1'B0), + .In25(1'B0), + .In26(1'B0), + .In27(1'B0), + .In28(1'B0), + .In29(1'B0), + .In30(1'B0), + .In31(1'B0), + .dout(dout) + ); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.upgrade_log b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.upgrade_log new file mode 100644 index 0000000..c751b41 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.upgrade_log @@ -0,0 +1,16 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +| Date : Fri Jul 10 13:44:23 2015 +| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7z020clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'z_turn_xlconcat_0_1' + +1. Summary +---------- + +SUCCESS in the update of z_turn_xlconcat_0_1 (xilinx.com:ip:xlconcat:2.1 (Rev. 1)) to current project options. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.veo b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.veo new file mode 100644 index 0000000..4683bb4 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.veo @@ -0,0 +1,67 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +z_turn_xlconcat_0_1 your_instance_name ( + .In0(In0), // input wire [31 : 0] In0 + .In1(In1), // input wire [31 : 0] In1 + .dout(dout) // output wire [63 : 0] dout +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file z_turn_xlconcat_0_1.v when simulating +// the core, z_turn_xlconcat_0_1. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.xci b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.xci new file mode 100644 index 0000000..c087e8c --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.xci @@ -0,0 +1,111 @@ + + + xilinx.com + xci + unknown + 1.0 + + + z_turn_xlconcat_0_1 + + + 2 + 32 + 32 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + z_turn_xlconcat_0_1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 64 + 32 + 32 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 64 + 2 + zynq + xc7z020 + clg400 + -1 + C + + VERILOG + MIXED + TRUE + TRUE + + TRUE + 2015.2 + 1 + OUT_OF_CONTEXT + + . + ../../../../ipshared + IP_Integrator + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.xml new file mode 100644 index 0000000..52bfdca --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.xml @@ -0,0 +1,1906 @@ + + + xilinx.com + customized_ip + z_turn_xlconcat_0_1 + 1.0 + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + customizationCRC + 4a7a1063 + + + customizationCRCversion + 5 + + + boundaryCRC + 445d2e6d + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + + xilinx_verilogsynthesis_view_fileset + + + + customizationCRC + 4a7a1063 + + + customizationCRCversion + 5 + + + boundaryCRC + 445d2e6d + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 03 07:51:34 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + + xilinx_verilogsynthesiswrapper_view_fileset + + + + customizationCRC + 4a7a1063 + + + customizationCRCversion + 5 + + + boundaryCRC + 445d2e6d + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + + xilinx_verilogbehavioralsimulation_view_fileset + + + + customizationCRC + 4ef8d8e5 + + + customizationCRCversion + 5 + + + boundaryCRC + 445d2e6d + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 03 07:51:34 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + + xilinx_verilogsimulationwrapper_view_fileset + + + + customizationCRC + 4ef8d8e5 + + + customizationCRCversion + 5 + + + boundaryCRC + 445d2e6d + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + customizationCRC + 4a7a1063 + + + customizationCRCversion + 5 + + + boundaryCRC + 445d2e6d + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + + + In0 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In1 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In2 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In3 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In4 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In5 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In6 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In7 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In8 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In9 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In10 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In11 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In12 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In13 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In14 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In15 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In16 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In17 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In18 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In19 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In20 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In21 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In22 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In23 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In24 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In25 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In26 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In27 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In28 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In29 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In30 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In31 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + dout + + out + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + IN0_WIDTH + In0 Width + 32 + + + IN1_WIDTH + In1 Width + 32 + + + IN2_WIDTH + In2 Width + 1 + + + IN3_WIDTH + In3 Width + 1 + + + IN4_WIDTH + In4 Width + 1 + + + IN5_WIDTH + In5 Width + 1 + + + IN6_WIDTH + In6 Width + 1 + + + IN7_WIDTH + In7 Width + 1 + + + IN8_WIDTH + In8 Width + 1 + + + IN9_WIDTH + In9 Width + 1 + + + IN10_WIDTH + In10 Width + 1 + + + IN11_WIDTH + In11 Width + 1 + + + IN12_WIDTH + In12 Width + 1 + + + IN13_WIDTH + In13 Width + 1 + + + IN14_WIDTH + In14 Width + 1 + + + IN15_WIDTH + In15 Width + 1 + + + IN16_WIDTH + In16 Width + 1 + + + IN17_WIDTH + In17 Width + 1 + + + IN18_WIDTH + In18 Width + 1 + + + IN19_WIDTH + In19 Width + 1 + + + IN20_WIDTH + In20 Width + 1 + + + IN21_WIDTH + In21 Width + 1 + + + IN22_WIDTH + In22 Width + 1 + + + IN23_WIDTH + In23 Width + 1 + + + IN24_WIDTH + In24 Width + 1 + + + IN25_WIDTH + In25 Width + 1 + + + IN26_WIDTH + In26 Width + 1 + + + IN27_WIDTH + In27 Width + 1 + + + IN28_WIDTH + In28 Width + 1 + + + IN29_WIDTH + In29 Width + 1 + + + IN30_WIDTH + In30 Width + 1 + + + IN31_WIDTH + In31 Width + 1 + + + dout_width + Dout Width + 64 + + + NUM_PORTS + Number of Ports + 2 + + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + z_turn_xlconcat_0_1.veo + verilogTemplate + + + + xilinx_verilogsynthesis_view_fileset + + ../../../../ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.v + verilogSource + work + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/z_turn_xlconcat_0_1.v + verilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../../../ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.v + verilogSource + work + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/z_turn_xlconcat_0_1.v + verilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/xlconcat_v2_1_changelog.txt + text + + + + Concatenates up to 32 ports into a single port + + + NUM_PORTS + Number of Ports + 2 + + + IN0_WIDTH + In0 Width + 32 + + + IN1_WIDTH + In1 Width + 32 + + + IN2_WIDTH + In2 Width + 1 + + + IN3_WIDTH + In3 Width + 1 + + + IN4_WIDTH + In4 Width + 1 + + + IN5_WIDTH + In5 Width + 1 + + + IN6_WIDTH + In6 Width + 1 + + + IN7_WIDTH + In7 Width + 1 + + + IN8_WIDTH + In8 Width + 1 + + + IN9_WIDTH + In9 Width + 1 + + + IN10_WIDTH + In10 Width + 1 + + + IN11_WIDTH + In11 Width + 1 + + + IN12_WIDTH + In12 Width + 1 + + + IN13_WIDTH + In13 Width + 1 + + + IN14_WIDTH + In14 Width + 1 + + + IN15_WIDTH + In15 Width + 1 + + + IN16_WIDTH + In16 Width + 1 + + + IN17_WIDTH + In17 Width + 1 + + + Component_Name + z_turn_xlconcat_0_1 + + + IN18_WIDTH + In18 Width + 1 + + + IN19_WIDTH + In19 Width + 1 + + + IN20_WIDTH + In20 Width + 1 + + + IN21_WIDTH + In21 Width + 1 + + + IN22_WIDTH + In22 Width + 1 + + + IN23_WIDTH + In23 Width + 1 + + + IN24_WIDTH + In24 Width + 1 + + + IN25_WIDTH + In25 Width + 1 + + + IN26_WIDTH + In26 Width + 1 + + + IN27_WIDTH + In27 Width + 1 + + + IN28_WIDTH + In28 Width + 1 + + + IN29_WIDTH + In29 Width + 1 + + + IN30_WIDTH + In30 Width + 1 + + + IN31_WIDTH + In31 Width + 1 + + + dout_width + Dout Width + 64 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + virtexu + kintexu + + + /Basic_Elements + + Concat + + IPI + + http://www.xilinx.com + 1 + 2014-10-09T21:18:16Z + + + + + + + 2014.4 + + + + + + + \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/doc/xlconcat_v2_1_changelog.txt b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/doc/xlconcat_v2_1_changelog.txt new file mode 100644 index 0000000..d07a13b --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/doc/xlconcat_v2_1_changelog.txt @@ -0,0 +1,64 @@ +2014.4 + * Version 2.1 (Rev.1) + * Add Auto/Manual button for Inxx Width in GUI dialog. + +2014.2 + * Version 2.1 + * upgrade input sources from 16 to 32. + +2014.1: + * Version 2.0 + * Version 1.0 of the xlconcat block reverses the order in + * which input signals are concatenated. Version 2.0 + * preserves the order of input signals on the output. + * The upgrade from 1.0 to 2.0 will change input connections + * in order to preserve the overall the signal order on output. + + + (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/sim/z_turn_xlconcat_0_2.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/sim/z_turn_xlconcat_0_2.v new file mode 100644 index 0000000..ee0b169 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/sim/z_turn_xlconcat_0_2.v @@ -0,0 +1,196 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module z_turn_xlconcat_0_2 ( + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + In16, + In17, + In18, + In19, + In20, + In21, + In22, + In23, + In24, + In25, + In26, + In27, + In28, + In29, + In30, + In31, + dout +); + +input wire [0 : 0] In0; +input wire [0 : 0] In1; +input wire [0 : 0] In2; +input wire [0 : 0] In3; +input wire [0 : 0] In4; +input wire [0 : 0] In5; +input wire [0 : 0] In6; +input wire [0 : 0] In7; +input wire [0 : 0] In8; +input wire [0 : 0] In9; +input wire [0 : 0] In10; +input wire [0 : 0] In11; +input wire [0 : 0] In12; +input wire [0 : 0] In13; +input wire [0 : 0] In14; +input wire [0 : 0] In15; +input wire [0 : 0] In16; +input wire [0 : 0] In17; +input wire [0 : 0] In18; +input wire [0 : 0] In19; +input wire [0 : 0] In20; +input wire [0 : 0] In21; +input wire [0 : 0] In22; +input wire [0 : 0] In23; +input wire [0 : 0] In24; +input wire [0 : 0] In25; +input wire [0 : 0] In26; +input wire [0 : 0] In27; +input wire [0 : 0] In28; +input wire [0 : 0] In29; +input wire [0 : 0] In30; +input wire [0 : 0] In31; +output wire [31 : 0] dout; + + xlconcat #( + .IN0_WIDTH(1), + .IN1_WIDTH(1), + .IN2_WIDTH(1), + .IN3_WIDTH(1), + .IN4_WIDTH(1), + .IN5_WIDTH(1), + .IN6_WIDTH(1), + .IN7_WIDTH(1), + .IN8_WIDTH(1), + .IN9_WIDTH(1), + .IN10_WIDTH(1), + .IN11_WIDTH(1), + .IN12_WIDTH(1), + .IN13_WIDTH(1), + .IN14_WIDTH(1), + .IN15_WIDTH(1), + .IN16_WIDTH(1), + .IN17_WIDTH(1), + .IN18_WIDTH(1), + .IN19_WIDTH(1), + .IN20_WIDTH(1), + .IN21_WIDTH(1), + .IN22_WIDTH(1), + .IN23_WIDTH(1), + .IN24_WIDTH(1), + .IN25_WIDTH(1), + .IN26_WIDTH(1), + .IN27_WIDTH(1), + .IN28_WIDTH(1), + .IN29_WIDTH(1), + .IN30_WIDTH(1), + .IN31_WIDTH(1), + .dout_width(32), + .NUM_PORTS(32) + ) inst ( + .In0(In0), + .In1(In1), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In16(In16), + .In17(In17), + .In18(In18), + .In19(In19), + .In20(In20), + .In21(In21), + .In22(In22), + .In23(In23), + .In24(In24), + .In25(In25), + .In26(In26), + .In27(In27), + .In28(In28), + .In29(In29), + .In30(In30), + .In31(In31), + .dout(dout) + ); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/synth/z_turn_xlconcat_0_2.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/synth/z_turn_xlconcat_0_2.v new file mode 100644 index 0000000..18d861a --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/synth/z_turn_xlconcat_0_2.v @@ -0,0 +1,197 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +(* X_CORE_INFO = "xlconcat,Vivado 2015.2" *) +(* CHECK_LICENSE_TYPE = "z_turn_xlconcat_0_2,xlconcat,{}" *) +(* CORE_GENERATION_INFO = "z_turn_xlconcat_0_2,xlconcat,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=32,NUM_PORTS=32}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module z_turn_xlconcat_0_2 ( + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + In16, + In17, + In18, + In19, + In20, + In21, + In22, + In23, + In24, + In25, + In26, + In27, + In28, + In29, + In30, + In31, + dout +); + +input wire [0 : 0] In0; +input wire [0 : 0] In1; +input wire [0 : 0] In2; +input wire [0 : 0] In3; +input wire [0 : 0] In4; +input wire [0 : 0] In5; +input wire [0 : 0] In6; +input wire [0 : 0] In7; +input wire [0 : 0] In8; +input wire [0 : 0] In9; +input wire [0 : 0] In10; +input wire [0 : 0] In11; +input wire [0 : 0] In12; +input wire [0 : 0] In13; +input wire [0 : 0] In14; +input wire [0 : 0] In15; +input wire [0 : 0] In16; +input wire [0 : 0] In17; +input wire [0 : 0] In18; +input wire [0 : 0] In19; +input wire [0 : 0] In20; +input wire [0 : 0] In21; +input wire [0 : 0] In22; +input wire [0 : 0] In23; +input wire [0 : 0] In24; +input wire [0 : 0] In25; +input wire [0 : 0] In26; +input wire [0 : 0] In27; +input wire [0 : 0] In28; +input wire [0 : 0] In29; +input wire [0 : 0] In30; +input wire [0 : 0] In31; +output wire [31 : 0] dout; + + xlconcat #( + .IN0_WIDTH(1), + .IN1_WIDTH(1), + .IN2_WIDTH(1), + .IN3_WIDTH(1), + .IN4_WIDTH(1), + .IN5_WIDTH(1), + .IN6_WIDTH(1), + .IN7_WIDTH(1), + .IN8_WIDTH(1), + .IN9_WIDTH(1), + .IN10_WIDTH(1), + .IN11_WIDTH(1), + .IN12_WIDTH(1), + .IN13_WIDTH(1), + .IN14_WIDTH(1), + .IN15_WIDTH(1), + .IN16_WIDTH(1), + .IN17_WIDTH(1), + .IN18_WIDTH(1), + .IN19_WIDTH(1), + .IN20_WIDTH(1), + .IN21_WIDTH(1), + .IN22_WIDTH(1), + .IN23_WIDTH(1), + .IN24_WIDTH(1), + .IN25_WIDTH(1), + .IN26_WIDTH(1), + .IN27_WIDTH(1), + .IN28_WIDTH(1), + .IN29_WIDTH(1), + .IN30_WIDTH(1), + .IN31_WIDTH(1), + .dout_width(32), + .NUM_PORTS(32) + ) inst ( + .In0(In0), + .In1(In1), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In16(In16), + .In17(In17), + .In18(In18), + .In19(In19), + .In20(In20), + .In21(In21), + .In22(In22), + .In23(In23), + .In24(In24), + .In25(In25), + .In26(In26), + .In27(In27), + .In28(In28), + .In29(In29), + .In30(In30), + .In31(In31), + .dout(dout) + ); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.upgrade_log b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.upgrade_log new file mode 100644 index 0000000..80e061c --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.upgrade_log @@ -0,0 +1,16 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +| Date : Fri Jul 10 13:44:24 2015 +| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7z020clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'z_turn_xlconcat_0_2' + +1. Summary +---------- + +SUCCESS in the update of z_turn_xlconcat_0_2 (xilinx.com:ip:xlconcat:2.1 (Rev. 1)) to current project options. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.veo b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.veo new file mode 100644 index 0000000..b82707d --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.veo @@ -0,0 +1,97 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +z_turn_xlconcat_0_2 your_instance_name ( + .In0(In0), // input wire [0 : 0] In0 + .In1(In1), // input wire [0 : 0] In1 + .In2(In2), // input wire [0 : 0] In2 + .In3(In3), // input wire [0 : 0] In3 + .In4(In4), // input wire [0 : 0] In4 + .In5(In5), // input wire [0 : 0] In5 + .In6(In6), // input wire [0 : 0] In6 + .In7(In7), // input wire [0 : 0] In7 + .In8(In8), // input wire [0 : 0] In8 + .In9(In9), // input wire [0 : 0] In9 + .In10(In10), // input wire [0 : 0] In10 + .In11(In11), // input wire [0 : 0] In11 + .In12(In12), // input wire [0 : 0] In12 + .In13(In13), // input wire [0 : 0] In13 + .In14(In14), // input wire [0 : 0] In14 + .In15(In15), // input wire [0 : 0] In15 + .In16(In16), // input wire [0 : 0] In16 + .In17(In17), // input wire [0 : 0] In17 + .In18(In18), // input wire [0 : 0] In18 + .In19(In19), // input wire [0 : 0] In19 + .In20(In20), // input wire [0 : 0] In20 + .In21(In21), // input wire [0 : 0] In21 + .In22(In22), // input wire [0 : 0] In22 + .In23(In23), // input wire [0 : 0] In23 + .In24(In24), // input wire [0 : 0] In24 + .In25(In25), // input wire [0 : 0] In25 + .In26(In26), // input wire [0 : 0] In26 + .In27(In27), // input wire [0 : 0] In27 + .In28(In28), // input wire [0 : 0] In28 + .In29(In29), // input wire [0 : 0] In29 + .In30(In30), // input wire [0 : 0] In30 + .In31(In31), // input wire [0 : 0] In31 + .dout(dout) // output wire [31 : 0] dout +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file z_turn_xlconcat_0_2.v when simulating +// the core, z_turn_xlconcat_0_2. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.xci b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.xci new file mode 100644 index 0000000..6e2f621 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.xci @@ -0,0 +1,142 @@ + + + xilinx.com + xci + unknown + 1.0 + + + z_turn_xlconcat_0_2 + + + 32 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + z_turn_xlconcat_0_2 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 32 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 32 + 32 + zynq + xc7z020 + clg400 + -1 + C + + VERILOG + MIXED + TRUE + TRUE + + TRUE + 2015.2 + 1 + OUT_OF_CONTEXT + + . + ../../../../ipshared + IP_Integrator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.xml new file mode 100644 index 0000000..8cea8f6 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.xml @@ -0,0 +1,1968 @@ + + + xilinx.com + customized_ip + z_turn_xlconcat_0_2 + 1.0 + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + customizationCRC + d42439e7 + + + customizationCRCversion + 5 + + + boundaryCRC + cfd21d2c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + + xilinx_verilogsynthesis_view_fileset + + + + customizationCRC + d42439e7 + + + customizationCRCversion + 5 + + + boundaryCRC + cfd21d2c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 03 07:51:34 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + + xilinx_verilogsynthesiswrapper_view_fileset + + + + customizationCRC + d42439e7 + + + customizationCRCversion + 5 + + + boundaryCRC + cfd21d2c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + + xilinx_verilogbehavioralsimulation_view_fileset + + + + customizationCRC + 05a2bdc2 + + + customizationCRCversion + 5 + + + boundaryCRC + cfd21d2c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 03 07:51:34 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + + xilinx_verilogsimulationwrapper_view_fileset + + + + customizationCRC + 05a2bdc2 + + + customizationCRCversion + 5 + + + boundaryCRC + cfd21d2c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + customizationCRC + d42439e7 + + + customizationCRCversion + 5 + + + boundaryCRC + cfd21d2c + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + + + In0 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In1 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In2 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In3 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In4 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In5 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In6 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In7 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In8 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In9 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In10 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In11 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In12 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In13 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In14 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In15 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In16 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In17 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In18 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In19 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In20 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In21 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In22 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In23 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In24 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In25 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In26 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In27 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In28 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In29 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In30 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In31 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + dout + + out + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + IN0_WIDTH + In0 Width + 1 + + + IN1_WIDTH + In1 Width + 1 + + + IN2_WIDTH + In2 Width + 1 + + + IN3_WIDTH + In3 Width + 1 + + + IN4_WIDTH + In4 Width + 1 + + + IN5_WIDTH + In5 Width + 1 + + + IN6_WIDTH + In6 Width + 1 + + + IN7_WIDTH + In7 Width + 1 + + + IN8_WIDTH + In8 Width + 1 + + + IN9_WIDTH + In9 Width + 1 + + + IN10_WIDTH + In10 Width + 1 + + + IN11_WIDTH + In11 Width + 1 + + + IN12_WIDTH + In12 Width + 1 + + + IN13_WIDTH + In13 Width + 1 + + + IN14_WIDTH + In14 Width + 1 + + + IN15_WIDTH + In15 Width + 1 + + + IN16_WIDTH + In16 Width + 1 + + + IN17_WIDTH + In17 Width + 1 + + + IN18_WIDTH + In18 Width + 1 + + + IN19_WIDTH + In19 Width + 1 + + + IN20_WIDTH + In20 Width + 1 + + + IN21_WIDTH + In21 Width + 1 + + + IN22_WIDTH + In22 Width + 1 + + + IN23_WIDTH + In23 Width + 1 + + + IN24_WIDTH + In24 Width + 1 + + + IN25_WIDTH + In25 Width + 1 + + + IN26_WIDTH + In26 Width + 1 + + + IN27_WIDTH + In27 Width + 1 + + + IN28_WIDTH + In28 Width + 1 + + + IN29_WIDTH + In29 Width + 1 + + + IN30_WIDTH + In30 Width + 1 + + + IN31_WIDTH + In31 Width + 1 + + + dout_width + Dout Width + 32 + + + NUM_PORTS + Number of Ports + 32 + + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + z_turn_xlconcat_0_2.veo + verilogTemplate + + + + xilinx_verilogsynthesis_view_fileset + + ../../../../ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.v + verilogSource + work + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/z_turn_xlconcat_0_2.v + verilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../../../ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.v + verilogSource + work + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/z_turn_xlconcat_0_2.v + verilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/xlconcat_v2_1_changelog.txt + text + + + + Concatenates up to 32 ports into a single port + + + NUM_PORTS + Number of Ports + 32 + + + IN0_WIDTH + In0 Width + 1 + + + IN1_WIDTH + In1 Width + 1 + + + IN2_WIDTH + In2 Width + 1 + + + IN3_WIDTH + In3 Width + 1 + + + IN4_WIDTH + In4 Width + 1 + + + IN5_WIDTH + In5 Width + 1 + + + IN6_WIDTH + In6 Width + 1 + + + IN7_WIDTH + In7 Width + 1 + + + IN8_WIDTH + In8 Width + 1 + + + IN9_WIDTH + In9 Width + 1 + + + IN10_WIDTH + In10 Width + 1 + + + IN11_WIDTH + In11 Width + 1 + + + IN12_WIDTH + In12 Width + 1 + + + IN13_WIDTH + In13 Width + 1 + + + IN14_WIDTH + In14 Width + 1 + + + IN15_WIDTH + In15 Width + 1 + + + IN16_WIDTH + In16 Width + 1 + + + IN17_WIDTH + In17 Width + 1 + + + Component_Name + z_turn_xlconcat_0_2 + + + IN18_WIDTH + In18 Width + 1 + + + IN19_WIDTH + In19 Width + 1 + + + IN20_WIDTH + In20 Width + 1 + + + IN21_WIDTH + In21 Width + 1 + + + IN22_WIDTH + In22 Width + 1 + + + IN23_WIDTH + In23 Width + 1 + + + IN24_WIDTH + In24 Width + 1 + + + IN25_WIDTH + In25 Width + 1 + + + IN26_WIDTH + In26 Width + 1 + + + IN27_WIDTH + In27 Width + 1 + + + IN28_WIDTH + In28 Width + 1 + + + IN29_WIDTH + In29 Width + 1 + + + IN30_WIDTH + In30 Width + 1 + + + IN31_WIDTH + In31 Width + 1 + + + dout_width + Dout Width + 32 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + virtexu + kintexu + + + /Basic_Elements + + Concat + + IPI + + http://www.xilinx.com + 1 + 2014-10-09T21:18:16Z + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2014.4 + + + + + + + \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/doc/xlconcat_v2_1_changelog.txt b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/doc/xlconcat_v2_1_changelog.txt new file mode 100644 index 0000000..d07a13b --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/doc/xlconcat_v2_1_changelog.txt @@ -0,0 +1,64 @@ +2014.4 + * Version 2.1 (Rev.1) + * Add Auto/Manual button for Inxx Width in GUI dialog. + +2014.2 + * Version 2.1 + * upgrade input sources from 16 to 32. + +2014.1: + * Version 2.0 + * Version 1.0 of the xlconcat block reverses the order in + * which input signals are concatenated. Version 2.0 + * preserves the order of input signals on the output. + * The upgrade from 1.0 to 2.0 will change input connections + * in order to preserve the overall the signal order on output. + + + (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/sim/z_turn_xlconcat_1_0.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/sim/z_turn_xlconcat_1_0.v new file mode 100644 index 0000000..8d58a8c --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/sim/z_turn_xlconcat_1_0.v @@ -0,0 +1,190 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module z_turn_xlconcat_1_0 ( + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + In16, + In17, + In18, + In19, + In20, + In21, + In22, + In23, + In24, + In25, + In26, + In27, + In28, + dout +); + +input wire [0 : 0] In0; +input wire [0 : 0] In1; +input wire [0 : 0] In2; +input wire [0 : 0] In3; +input wire [0 : 0] In4; +input wire [0 : 0] In5; +input wire [0 : 0] In6; +input wire [0 : 0] In7; +input wire [0 : 0] In8; +input wire [0 : 0] In9; +input wire [0 : 0] In10; +input wire [0 : 0] In11; +input wire [0 : 0] In12; +input wire [0 : 0] In13; +input wire [0 : 0] In14; +input wire [0 : 0] In15; +input wire [0 : 0] In16; +input wire [0 : 0] In17; +input wire [0 : 0] In18; +input wire [0 : 0] In19; +input wire [0 : 0] In20; +input wire [0 : 0] In21; +input wire [0 : 0] In22; +input wire [0 : 0] In23; +input wire [3 : 0] In24; +input wire [0 : 0] In25; +input wire [0 : 0] In26; +input wire [0 : 0] In27; +input wire [0 : 0] In28; +output wire [31 : 0] dout; + + xlconcat #( + .IN0_WIDTH(1), + .IN1_WIDTH(1), + .IN2_WIDTH(1), + .IN3_WIDTH(1), + .IN4_WIDTH(1), + .IN5_WIDTH(1), + .IN6_WIDTH(1), + .IN7_WIDTH(1), + .IN8_WIDTH(1), + .IN9_WIDTH(1), + .IN10_WIDTH(1), + .IN11_WIDTH(1), + .IN12_WIDTH(1), + .IN13_WIDTH(1), + .IN14_WIDTH(1), + .IN15_WIDTH(1), + .IN16_WIDTH(1), + .IN17_WIDTH(1), + .IN18_WIDTH(1), + .IN19_WIDTH(1), + .IN20_WIDTH(1), + .IN21_WIDTH(1), + .IN22_WIDTH(1), + .IN23_WIDTH(1), + .IN24_WIDTH(4), + .IN25_WIDTH(1), + .IN26_WIDTH(1), + .IN27_WIDTH(1), + .IN28_WIDTH(1), + .IN29_WIDTH(1), + .IN30_WIDTH(1), + .IN31_WIDTH(1), + .dout_width(32), + .NUM_PORTS(29) + ) inst ( + .In0(In0), + .In1(In1), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In16(In16), + .In17(In17), + .In18(In18), + .In19(In19), + .In20(In20), + .In21(In21), + .In22(In22), + .In23(In23), + .In24(In24), + .In25(In25), + .In26(In26), + .In27(In27), + .In28(In28), + .In29(1'B0), + .In30(1'B0), + .In31(1'B0), + .dout(dout) + ); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/synth/z_turn_xlconcat_1_0.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/synth/z_turn_xlconcat_1_0.v new file mode 100644 index 0000000..9aabf15 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/synth/z_turn_xlconcat_1_0.v @@ -0,0 +1,191 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +(* X_CORE_INFO = "xlconcat,Vivado 2015.2" *) +(* CHECK_LICENSE_TYPE = "z_turn_xlconcat_1_0,xlconcat,{}" *) +(* CORE_GENERATION_INFO = "z_turn_xlconcat_1_0,xlconcat,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=4,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=32,NUM_PORTS=29}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module z_turn_xlconcat_1_0 ( + In0, + In1, + In2, + In3, + In4, + In5, + In6, + In7, + In8, + In9, + In10, + In11, + In12, + In13, + In14, + In15, + In16, + In17, + In18, + In19, + In20, + In21, + In22, + In23, + In24, + In25, + In26, + In27, + In28, + dout +); + +input wire [0 : 0] In0; +input wire [0 : 0] In1; +input wire [0 : 0] In2; +input wire [0 : 0] In3; +input wire [0 : 0] In4; +input wire [0 : 0] In5; +input wire [0 : 0] In6; +input wire [0 : 0] In7; +input wire [0 : 0] In8; +input wire [0 : 0] In9; +input wire [0 : 0] In10; +input wire [0 : 0] In11; +input wire [0 : 0] In12; +input wire [0 : 0] In13; +input wire [0 : 0] In14; +input wire [0 : 0] In15; +input wire [0 : 0] In16; +input wire [0 : 0] In17; +input wire [0 : 0] In18; +input wire [0 : 0] In19; +input wire [0 : 0] In20; +input wire [0 : 0] In21; +input wire [0 : 0] In22; +input wire [0 : 0] In23; +input wire [3 : 0] In24; +input wire [0 : 0] In25; +input wire [0 : 0] In26; +input wire [0 : 0] In27; +input wire [0 : 0] In28; +output wire [31 : 0] dout; + + xlconcat #( + .IN0_WIDTH(1), + .IN1_WIDTH(1), + .IN2_WIDTH(1), + .IN3_WIDTH(1), + .IN4_WIDTH(1), + .IN5_WIDTH(1), + .IN6_WIDTH(1), + .IN7_WIDTH(1), + .IN8_WIDTH(1), + .IN9_WIDTH(1), + .IN10_WIDTH(1), + .IN11_WIDTH(1), + .IN12_WIDTH(1), + .IN13_WIDTH(1), + .IN14_WIDTH(1), + .IN15_WIDTH(1), + .IN16_WIDTH(1), + .IN17_WIDTH(1), + .IN18_WIDTH(1), + .IN19_WIDTH(1), + .IN20_WIDTH(1), + .IN21_WIDTH(1), + .IN22_WIDTH(1), + .IN23_WIDTH(1), + .IN24_WIDTH(4), + .IN25_WIDTH(1), + .IN26_WIDTH(1), + .IN27_WIDTH(1), + .IN28_WIDTH(1), + .IN29_WIDTH(1), + .IN30_WIDTH(1), + .IN31_WIDTH(1), + .dout_width(32), + .NUM_PORTS(29) + ) inst ( + .In0(In0), + .In1(In1), + .In2(In2), + .In3(In3), + .In4(In4), + .In5(In5), + .In6(In6), + .In7(In7), + .In8(In8), + .In9(In9), + .In10(In10), + .In11(In11), + .In12(In12), + .In13(In13), + .In14(In14), + .In15(In15), + .In16(In16), + .In17(In17), + .In18(In18), + .In19(In19), + .In20(In20), + .In21(In21), + .In22(In22), + .In23(In23), + .In24(In24), + .In25(In25), + .In26(In26), + .In27(In27), + .In28(In28), + .In29(1'B0), + .In30(1'B0), + .In31(1'B0), + .dout(dout) + ); +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.upgrade_log b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.upgrade_log new file mode 100644 index 0000000..3d73b0f --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.upgrade_log @@ -0,0 +1,16 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 +| Date : Fri Jul 10 13:44:25 2015 +| Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7z020clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'z_turn_xlconcat_1_0' + +1. Summary +---------- + +SUCCESS in the update of z_turn_xlconcat_1_0 (xilinx.com:ip:xlconcat:2.1 (Rev. 1)) to current project options. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.veo b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.veo new file mode 100644 index 0000000..6b48581 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.veo @@ -0,0 +1,94 @@ +// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 1 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +z_turn_xlconcat_1_0 your_instance_name ( + .In0(In0), // input wire [0 : 0] In0 + .In1(In1), // input wire [0 : 0] In1 + .In2(In2), // input wire [0 : 0] In2 + .In3(In3), // input wire [0 : 0] In3 + .In4(In4), // input wire [0 : 0] In4 + .In5(In5), // input wire [0 : 0] In5 + .In6(In6), // input wire [0 : 0] In6 + .In7(In7), // input wire [0 : 0] In7 + .In8(In8), // input wire [0 : 0] In8 + .In9(In9), // input wire [0 : 0] In9 + .In10(In10), // input wire [0 : 0] In10 + .In11(In11), // input wire [0 : 0] In11 + .In12(In12), // input wire [0 : 0] In12 + .In13(In13), // input wire [0 : 0] In13 + .In14(In14), // input wire [0 : 0] In14 + .In15(In15), // input wire [0 : 0] In15 + .In16(In16), // input wire [0 : 0] In16 + .In17(In17), // input wire [0 : 0] In17 + .In18(In18), // input wire [0 : 0] In18 + .In19(In19), // input wire [0 : 0] In19 + .In20(In20), // input wire [0 : 0] In20 + .In21(In21), // input wire [0 : 0] In21 + .In22(In22), // input wire [0 : 0] In22 + .In23(In23), // input wire [0 : 0] In23 + .In24(In24), // input wire [3 : 0] In24 + .In25(In25), // input wire [0 : 0] In25 + .In26(In26), // input wire [0 : 0] In26 + .In27(In27), // input wire [0 : 0] In27 + .In28(In28), // input wire [0 : 0] In28 + .dout(dout) // output wire [31 : 0] dout +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file z_turn_xlconcat_1_0.v when simulating +// the core, z_turn_xlconcat_1_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.xci b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.xci new file mode 100644 index 0000000..30158f5 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.xci @@ -0,0 +1,139 @@ + + + xilinx.com + xci + unknown + 1.0 + + + z_turn_xlconcat_1_0 + + + 29 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + z_turn_xlconcat_1_0 + 1 + 1 + 1 + 1 + 1 + 1 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 32 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 32 + 29 + zynq + xc7z020 + clg400 + -1 + C + + VERILOG + MIXED + TRUE + TRUE + + TRUE + 2015.2 + 1 + OUT_OF_CONTEXT + + . + ../../../../ipshared + IP_Integrator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.xml new file mode 100644 index 0000000..59f4b12 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.xml @@ -0,0 +1,1962 @@ + + + xilinx.com + customized_ip + z_turn_xlconcat_1_0 + 1.0 + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + customizationCRC + 5fb472c2 + + + customizationCRCversion + 5 + + + boundaryCRC + d2a88554 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + + xilinx_verilogsynthesis_view_fileset + + + + customizationCRC + 5fb472c2 + + + customizationCRCversion + 5 + + + boundaryCRC + d2a88554 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 03 07:51:34 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + + xilinx_verilogsynthesiswrapper_view_fileset + + + + customizationCRC + 5fb472c2 + + + customizationCRCversion + 5 + + + boundaryCRC + d2a88554 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + + xilinx_verilogbehavioralsimulation_view_fileset + + + + customizationCRC + 3a7189c7 + + + customizationCRCversion + 5 + + + boundaryCRC + d2a88554 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 03 07:51:34 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + + xilinx_verilogsimulationwrapper_view_fileset + + + + customizationCRC + 3a7189c7 + + + customizationCRCversion + 5 + + + boundaryCRC + d2a88554 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + customizationCRC + 5fb472c2 + + + customizationCRCversion + 5 + + + boundaryCRC + d2a88554 + + + boundaryCRCversion + 1 + + + GENtimestamp + Fri Jul 10 05:48:45 UTC 2015 + + + StaleAtRelink + false + + + + + + + In0 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In1 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In2 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In3 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In4 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In5 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In6 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In7 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In8 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In9 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In10 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In11 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In12 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In13 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In14 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In15 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In16 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In17 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In18 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In19 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In20 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In21 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In22 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In23 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In24 + + in + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In25 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In26 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In27 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In28 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + In29 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In30 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + In31 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + dout + + out + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + IN0_WIDTH + In0 Width + 1 + + + IN1_WIDTH + In1 Width + 1 + + + IN2_WIDTH + In2 Width + 1 + + + IN3_WIDTH + In3 Width + 1 + + + IN4_WIDTH + In4 Width + 1 + + + IN5_WIDTH + In5 Width + 1 + + + IN6_WIDTH + In6 Width + 1 + + + IN7_WIDTH + In7 Width + 1 + + + IN8_WIDTH + In8 Width + 1 + + + IN9_WIDTH + In9 Width + 1 + + + IN10_WIDTH + In10 Width + 1 + + + IN11_WIDTH + In11 Width + 1 + + + IN12_WIDTH + In12 Width + 1 + + + IN13_WIDTH + In13 Width + 1 + + + IN14_WIDTH + In14 Width + 1 + + + IN15_WIDTH + In15 Width + 1 + + + IN16_WIDTH + In16 Width + 1 + + + IN17_WIDTH + In17 Width + 1 + + + IN18_WIDTH + In18 Width + 1 + + + IN19_WIDTH + In19 Width + 1 + + + IN20_WIDTH + In20 Width + 1 + + + IN21_WIDTH + In21 Width + 1 + + + IN22_WIDTH + In22 Width + 1 + + + IN23_WIDTH + In23 Width + 1 + + + IN24_WIDTH + In24 Width + 4 + + + IN25_WIDTH + In25 Width + 1 + + + IN26_WIDTH + In26 Width + 1 + + + IN27_WIDTH + In27 Width + 1 + + + IN28_WIDTH + In28 Width + 1 + + + IN29_WIDTH + In29 Width + 1 + + + IN30_WIDTH + In30 Width + 1 + + + IN31_WIDTH + In31 Width + 1 + + + dout_width + Dout Width + 32 + + + NUM_PORTS + Number of Ports + 29 + + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + z_turn_xlconcat_1_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_view_fileset + + ../../../../ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.v + verilogSource + work + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/z_turn_xlconcat_1_0.v + verilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../../../ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.v + verilogSource + work + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/z_turn_xlconcat_1_0.v + verilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/xlconcat_v2_1_changelog.txt + text + + + + Concatenates up to 32 ports into a single port + + + NUM_PORTS + Number of Ports + 29 + + + IN0_WIDTH + In0 Width + 1 + + + IN1_WIDTH + In1 Width + 1 + + + IN2_WIDTH + In2 Width + 1 + + + IN3_WIDTH + In3 Width + 1 + + + IN4_WIDTH + In4 Width + 1 + + + IN5_WIDTH + In5 Width + 1 + + + IN6_WIDTH + In6 Width + 1 + + + IN7_WIDTH + In7 Width + 1 + + + IN8_WIDTH + In8 Width + 1 + + + IN9_WIDTH + In9 Width + 1 + + + IN10_WIDTH + In10 Width + 1 + + + IN11_WIDTH + In11 Width + 1 + + + IN12_WIDTH + In12 Width + 1 + + + IN13_WIDTH + In13 Width + 1 + + + IN14_WIDTH + In14 Width + 1 + + + IN15_WIDTH + In15 Width + 1 + + + IN16_WIDTH + In16 Width + 1 + + + IN17_WIDTH + In17 Width + 1 + + + Component_Name + z_turn_xlconcat_1_0 + + + IN18_WIDTH + In18 Width + 1 + + + IN19_WIDTH + In19 Width + 1 + + + IN20_WIDTH + In20 Width + 1 + + + IN21_WIDTH + In21 Width + 1 + + + IN22_WIDTH + In22 Width + 1 + + + IN23_WIDTH + In23 Width + 1 + + + IN24_WIDTH + In24 Width + 4 + + + IN25_WIDTH + In25 Width + 1 + + + IN26_WIDTH + In26 Width + 1 + + + IN27_WIDTH + In27 Width + 1 + + + IN28_WIDTH + In28 Width + 1 + + + IN29_WIDTH + In29 Width + 1 + + + IN30_WIDTH + In30 Width + 1 + + + IN31_WIDTH + In31 Width + 1 + + + dout_width + Dout Width + 32 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + virtexu + kintexu + + + /Basic_Elements + + Concat + + IPI + + http://www.xilinx.com + 1 + 2014-10-09T21:18:16Z + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2014.4 + + + + + + + \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ui/bd_24d8caf0.ui b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ui/bd_24d8caf0.ui new file mode 100644 index 0000000..0d2ad77 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ui/bd_24d8caf0.ui @@ -0,0 +1,17 @@ +{ + guistr: "# # String gsaved with Nlview 6.4.12 2014-12-16 bk=1.3272 VDI=35 GEI=35 GUI=JA:1.6 +# -string -flagsOSRD +preplace port M_ACLK -pg 1 -y 60 -defaultsOSRD +preplace port S_ACLK -pg 1 -y 20 -defaultsOSRD +preplace port S_AXI -pg 1 -y 40 -defaultsOSRD +preplace port M_AXI -pg 1 -y 60 -defaultsOSRD +preplace portBus M_ARESETN -pg 1 -y 80 -defaultsOSRD +preplace portBus S_ARESETN -pg 1 -y 100 -defaultsOSRD +preplace inst s00_data_fifo -pg 1 -lvl 1 -y 60 -defaultsOSRD +preplace netloc s00_data_fifo_to_s00_couplers 1 1 1 N +preplace netloc M_ACLK_1 1 0 1 NJ +preplace netloc M_ARESETN_1 1 0 1 NJ +preplace netloc s00_couplers_to_s00_data_fifo 1 0 1 NJ +levelinfo -pg 1 130 240 350 +", +} diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ui/bd_35e35d22.ui b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ui/bd_35e35d22.ui new file mode 100644 index 0000000..75b3a50 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ui/bd_35e35d22.ui @@ -0,0 +1,78 @@ +{ + commentid: "", + guistr: "# # String gsaved with Nlview 6.4.12 2014-12-16 bk=1.3272 VDI=35 GEI=35 GUI=JA:1.6 +# -string -flagsOSRD +preplace port I2S_FSYNC_IN -pg 1 -y 80 -defaultsOSRD +preplace port I2S_DIN -pg 1 -y 180 -defaultsOSRD +preplace port DDR -pg 1 -y 470 -defaultsOSRD +preplace port MEMS_INTn -pg 1 -y 260 -defaultsOSRD +preplace port HDMI_INTn -pg 1 -y 340 -defaultsOSRD +preplace port IO_B34_LP11 -pg 1 -y 160 -defaultsOSRD +preplace port LCD_VSYNC -pg 1 -y 380 -defaultsOSRD +preplace port IO_B34_LN8 -pg 1 -y 140 -defaultsOSRD +preplace port I2S_SCLK -pg 1 -y 70 -defaultsOSRD +preplace port LCD_HSYNC -pg 1 -y 400 -defaultsOSRD +preplace port BP -pg 1 -y 210 -defaultsOSRD +preplace port IO_B34_LN11 -pg 1 -y 100 -defaultsOSRD +preplace port LCD_PCLK -pg 1 -y 340 -defaultsOSRD +preplace port LCD_DE -pg 1 -y 360 -defaultsOSRD +preplace port IIC_0 -pg 1 -y 710 -defaultsOSRD +preplace port FIXED_IO -pg 1 -y 490 -defaultsOSRD +preplace port IO_B34_LP6 -pg 1 -y 60 -defaultsOSRD +preplace port I2S_DOUT -pg 1 -y 110 -defaultsOSRD +preplace port IO_B34_LP8 -pg 1 -y 120 -defaultsOSRD +preplace port I2S_FSYNC_OUT -pg 1 -y 90 -defaultsOSRD +preplace portBus IO_B35_LP -pg 1 -y 360 -defaultsOSRD +preplace portBus IO_B34_LN -pg 1 -y 40 -defaultsOSRD +preplace portBus IO_B34_LP -pg 1 -y 20 -defaultsOSRD +preplace portBus LCD_DATA -pg 1 -y 420 -defaultsOSRD +preplace portBus SW -pg 1 -y 210 -defaultsOSRD +preplace portBus LEDS -pg 1 -y 230 -defaultsOSRD +preplace portBus IO_B35_LN -pg 1 -y 390 -defaultsOSRD +preplace inst z_turn_ps_7_axi_periph_0 -pg 1 -lvl 7 -y 500 -defaultsOSRD +preplace inst ps7 -pg 1 -lvl 5 -y 820 -defaultsOSRD +preplace inst z_turn_ps_7_axi_periph_1 -pg 1 -lvl 7 -y 800 -defaultsOSRD -resize 200 196 +preplace inst xlconcat_0 -pg 1 -lvl 2 -y 430 -defaultsOSRD +preplace inst util_vector_logic_0 -pg 1 -lvl 3 -y 430 -defaultsOSRD +preplace inst proc_sys_reset_0 -pg 1 -lvl 6 -y 230 -defaultsOSRD -resize 280 140 +preplace inst xlconcat_1 -pg 1 -lvl 1 -y 510 -defaultsOSRD -resize 160 205 +preplace inst util_vector_logic_1 -pg 1 -lvl 3 -y 510 -defaultsOSRD -resize 140 60 +preplace inst proc_sys_reset_1 -pg 1 -lvl 6 -y 440 -defaultsOSRD +preplace inst xlconcat_2 -pg 1 -lvl 1 -y 980 -defaultsOSRD -resize 160 205 +preplace inst xlconcat -pg 1 -lvl 4 -y 580 -defaultsOSRD +preplace inst util_vector_logic_2 -pg 1 -lvl 3 -y 610 -defaultsOSRD -resize 140 60 +preplace inst proc_sys_reset_2 -pg 1 -lvl 6 -y 760 -defaultsOSRD -resize 280 140 +preplace inst proc_sys_reset_3 -pg 1 -lvl 6 -y 990 -defaultsOSRD -resize 280 140 +preplace netloc ps_7_FIXED_IO 1 5 3 2140 870 NJ 930 NJ +preplace netloc MEMS_INTn_1 1 0 3 NJ 260 NJ 260 610 +preplace netloc ps_7_FCLK_CLK0 1 4 3 1460 370 2110 350 2600 +preplace netloc ps_7_FCLK_CLK1 1 5 1 2090 +preplace netloc proc_sys_reset2_peripheral_aresetn 1 6 1 2540 +preplace netloc proc_sys_reset2_interconnect_aresetn 1 6 1 N +preplace netloc ps_7_FCLK_RESET1_N 1 5 1 2150 +preplace netloc xlconcat_1_dout 1 1 1 360 +preplace netloc util_vector_logic_0_Res 1 3 1 N +preplace netloc ps_7_FCLK_RESET0_N 1 5 1 2100 +preplace netloc ps_7_FCLK_CLK2 1 4 3 1470 1080 2180 550 2570 +preplace netloc ps_7_FCLK_CLK3 1 5 1 N +preplace netloc HDMI_INTn_1 1 0 3 NJ 340 NJ 490 620 +preplace netloc ps_7_M_AXI_GP0 1 5 2 2130 850 NJ +preplace netloc ps_7_FCLK_RESET3_N 1 5 1 2190 +preplace netloc ps_7_FCLK_RESET2_N 1 5 1 2170 +preplace netloc rst_ps_7_166M_peripheral_aresetn 1 6 1 2580 +preplace netloc xlconcat_0_dout 1 4 1 1450 +preplace netloc ps_7_DDR 1 5 3 2160 860 NJ 920 NJ +preplace netloc ps7_IIC_0 1 5 3 2120 880 NJ 940 NJ +preplace netloc util_vector_logic_2_Res 1 3 1 1110 +preplace netloc util_vector_logic_1_Res 1 3 1 1100 +preplace netloc io2axis_M00_AXI 1 4 4 1470 560 NJ 560 NJ 680 2940 +preplace netloc xlconcat_2_dout 1 1 1 380 +preplace netloc SW_1 1 0 1 160 +preplace netloc xlconcat_0_dout1 1 2 4 NJ 560 NJ 380 NJ 380 2080 +preplace netloc rst_ps_7_166M_interconnect_aresetn 1 6 1 2590 +levelinfo -pg 1 140 260 500 990 1350 1880 2350 2800 2990 +", +} +{ + da_axi4_cnt: "1", +} \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/z_turn.bd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/z_turn.bd new file mode 100644 index 0000000..95c5863 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/z_turn.bd @@ -0,0 +1,1685 @@ + + + + + xilinx.com + BlockDiagram + z_turn + 1.00.a + + + isTop + true + + + + + DDR + + + + + + FIXED_IO + + + + + + IIC_0 + + + + + + DATA.IO_B35_LP + Data + Data + + + + + + + DATA + + + IO_B35_LP + + + + + + LAYERED_METADATA + undef + + + + + + + + + + DATA.IO_B35_LN + Data + Data + + + + + + + DATA + + + IO_B35_LN + + + + + + LAYERED_METADATA + undef + + + + + + + + + + DATA.LCD_DATA + Data + Data + + + + + + + DATA + + + LCD_DATA + + + + + + LAYERED_METADATA + undef + + + + + + + + + + CLK.LCD_PCLK + Clk + Clock + + + + + + + CLK + + + LCD_PCLK + + + + + + FREQ_HZ + 100000000 + + + + + + + + PHASE + 0.000 + + + + + + + + + + CLK.I2S_SCLK + Clk + Clock + + + + + + + CLK + + + I2S_SCLK + + + + + + FREQ_HZ + 100000000 + + + + + + + + PHASE + 0.000 + + + + + + + + + + CLK.IO_B34_LP11 + Clk + Clock + + + + + + + CLK + + + IO_B34_LP11 + + + + + + FREQ_HZ + 50000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + z_turn_IO_B34_LP11 + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + IO_B35_LP + + in + + 24 + 1 + + + + + IO_B35_LN + + in + + 24 + 1 + + + + + LCD_DATA + + out + + 15 + 0 + + + + + LCD_VSYNC + + out + + + + LCD_HSYNC + + out + + + + LCD_DE + + out + + + + LCD_PCLK + + out + + + + I2S_SCLK + + out + + + + I2S_FSYNC_OUT + + out + + + + I2S_DOUT + + out + + + + IO_B34_LP + + in + + 5 + 1 + + + + + IO_B34_LN + + in + + 5 + 1 + + + + + I2S_DIN + + in + + + + I2S_FSYNC_IN + + in + + + + IO_B34_LP6 + + in + + + + IO_B34_LP8 + + in + + + + IO_B34_LN8 + + in + + + + IO_B34_LP11 + + in + + + + IO_B34_LN11 + + in + + + + LEDS + + out + + 2 + 0 + + + + + BP + + out + + + + HDMI_INTn + + in + + + + MEMS_INTn + + in + + + + SW + + in + + 3 + 0 + + + + + + + + + xilinx.com + BlockDiagram + z_turn_imp + 1.00.a + + + proc_sys_reset_2 + + + z_turn_proc_sys_reset1_0 + + + + proc_sys_reset_3 + + + z_turn_proc_sys_reset_1_0 + + + + proc_sys_reset_0 + + + z_turn_proc_sys_reset_3_0 + + + + ps7 + + + z_turn_processing_system7_0_0 + 166.667 + 100 + 200 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + LVCMOS 1.8V + MT41K256M16 RE-15E + 1 + 1 + 1 + 1 + MIO 16 .. 27 + 1 + 0 + 1 + 1 + MIO 46 + 1 + MIO 47 + 0 + 0 + 1 + 1 + MIO 14 .. 15 + 0 + 1 + 1 + MIO 51 + 0 + 1 + 1 + MIO 12 .. 13 + 0 + 1 + 1 + disabled + + + + z_turn_ps_7_axi_periph_0 + + + z_turn_ps_7_axi_periph_0 + 1 + 0 + xilinx.com:ip:axi_interconnect:2.1 + + + + z_turn_ps_7_axi_periph_1 + + + z_turn_ps_7_axi_periph_1 + 1 + 0 + xilinx.com:ip:axi_interconnect:2.1 + + + + proc_sys_reset_1 + + + z_turn_rst_ps_7_166M_0 + + + + util_vector_logic_0 + + + z_turn_util_vector_logic_0_0 + 1 + not + + + + util_vector_logic_1 + + + z_turn_util_vector_logic_0_1 + 1 + not + + + + util_vector_logic_2 + + + z_turn_util_vector_logic_1_0 + 1 + not + + + + xlconcat + + + z_turn_xlconcat_0_0 + 16 + + + + xlconcat_0 + + + z_turn_xlconcat_0_1 + 32 + 32 + + + + xlconcat_1 + + + z_turn_xlconcat_0_2 + 32 + + + + xlconcat_2 + + + z_turn_xlconcat_1_0 + 29 + 4 + 1 + + + + + + ps_7_M_AXI_GP0 + + + + + io2axis_M00_AXI + + + + + + + xlconcat_0_dout + + + + + ps_7_FCLK_CLK0 + + + + + + + + + rst_ps_7_166M_peripheral_aresetn + + + + + + rst_ps_7_166M_interconnect_aresetn + + + + + ps_7_FCLK_CLK2 + + + + + + + + + ps_7_FCLK_RESET1_N + + + + + ps_7_FCLK_RESET2_N + + + + + proc_sys_reset2_interconnect_aresetn + + + + + proc_sys_reset2_peripheral_aresetn + + + + + + ps_7_FCLK_RESET0_N + + + + + ps_7_FCLK_RESET3_N + + + + + ps_7_FCLK_CLK3 + + + + + ps_7_FCLK_CLK1 + + + + + util_vector_logic_0_Res + + + + + HDMI_INTn_1 + + + + + util_vector_logic_1_Res + + + + + MEMS_INTn_1 + + + + + + util_vector_logic_2_Res + + + + + xlconcat_1_dout + + + + + xlconcat_2_dout + + + + + xlconcat_0_dout1 + + + + + SW_1 + + + + + + + + + + + + + + + + + + + xilinx.com + BlockDiagram/z_turn_imp + z_turn_ps_7_axi_periph_1 + 1.00.a + + + S00_AXI + + + + + + M00_AXI + + + + + + CLK.ACLK + Clk + Clock + + + + + + + CLK + + + ACLK + + + + + + RST.ARESETN + Reset + Reset + + + + + + + RST + + + ARESETN + + + + + + CLK.S00_ACLK + Clk + Clock + + + + + + + CLK + + + S00_ACLK + + + + + + ASSOCIATED_BUSIF + S00_AXI + + + + + + + + ASSOCIATED_RESET + S00_ARESETN + + + + + + + + + + RST.S00_ARESETN + Reset + Reset + + + + + + + RST + + + S00_ARESETN + + + + + + CLK.M00_ACLK + Clk + Clock + + + + + + + CLK + + + M00_ACLK + + + + + + ASSOCIATED_BUSIF + M00_AXI + + + + + + + + ASSOCIATED_RESET + M00_ARESETN + + + + + + + + + + RST.M00_ARESETN + Reset + Reset + + + + + + + RST + + + M00_ARESETN + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + ACLK + + in + + + + ARESETN + + in + + 0 + 0 + + + + + S00_ACLK + + in + + + + S00_ARESETN + + in + + 0 + 0 + + + + + M00_ACLK + + in + + + + M00_ARESETN + + in + + 0 + 0 + + + + + + + + + xilinx.com + BlockDiagram/z_turn_imp + z_turn_ps_7_axi_periph_1_imp + 1.00.a + + + s00_couplers + + + + + + + z_turn_ps_7_axi_periph_1_ACLK_net + + + + + z_turn_ps_7_axi_periph_1_ARESETN_net + + + + + S00_ACLK_1 + + + + + S00_ARESETN_1 + + + + + + + + + + + + + + + + xilinx.com + BlockDiagram/z_turn_imp/z_turn_ps_7_axi_periph_1_imp + s00_couplers + 1.00.a + + + M_AXI + + + + + + S_AXI + + + + + + CLK.M_ACLK + Clk + Clock + + + + + + + CLK + + + M_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXI + + + + + + + + ASSOCIATED_RESET + M_ARESETN + + + + + + + + + + RST.M_ARESETN + Reset + Reset + + + + + + + RST + + + M_ARESETN + + + + + + CLK.S_ACLK + Clk + Clock + + + + + + + CLK + + + S_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + + + + + + ASSOCIATED_RESET + S_ARESETN + + + + + + + + + + RST.S_ARESETN + Reset + Reset + + + + + + + RST + + + S_ARESETN + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M_ACLK + + in + + + + M_ARESETN + + in + + 0 + 0 + + + + + S_ACLK + + in + + + + S_ARESETN + + in + + 0 + 0 + + + + + + + + + xilinx.com + BlockDiagram/z_turn_imp/z_turn_ps_7_axi_periph_1_imp + s00_couplers_imp + 1.00.a + + + + + + + + + + + xilinx.com + BlockDiagram/z_turn_imp + z_turn_ps_7_axi_periph_0 + 1.00.a + + + S00_AXI + + + + + + M00_AXI + + + + + + CLK.ACLK + Clk + Clock + + + + + + + CLK + + + ACLK + + + + + + RST.ARESETN + Reset + Reset + + + + + + + RST + + + ARESETN + + + + + + CLK.S00_ACLK + Clk + Clock + + + + + + + CLK + + + S00_ACLK + + + + + + ASSOCIATED_BUSIF + S00_AXI + + + + + + + + ASSOCIATED_RESET + S00_ARESETN + + + + + + + + + + RST.S00_ARESETN + Reset + Reset + + + + + + + RST + + + S00_ARESETN + + + + + + CLK.M00_ACLK + Clk + Clock + + + + + + + CLK + + + M00_ACLK + + + + + + ASSOCIATED_BUSIF + M00_AXI + + + + + + + + ASSOCIATED_RESET + M00_ARESETN + + + + + + + + + + RST.M00_ARESETN + Reset + Reset + + + + + + + RST + + + M00_ARESETN + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + ACLK + + in + + + + ARESETN + + in + + 0 + 0 + + + + + S00_ACLK + + in + + + + S00_ARESETN + + in + + 0 + 0 + + + + + M00_ACLK + + in + + + + M00_ARESETN + + in + + 0 + 0 + + + + + + + + + xilinx.com + BlockDiagram/z_turn_imp + z_turn_ps_7_axi_periph_0_imp + 1.00.a + + + s00_couplers + + + + + + + z_turn_ps_7_axi_periph_0_ACLK_net + + + + + z_turn_ps_7_axi_periph_0_ARESETN_net + + + + + S00_ACLK_1 + + + + + S00_ARESETN_1 + + + + + + + + + + + + + + + + xilinx.com + BlockDiagram/z_turn_imp/z_turn_ps_7_axi_periph_0_imp + s00_couplers + 1.00.a + + + M_AXI + + + + + + S_AXI + + + + + + CLK.M_ACLK + Clk + Clock + + + + + + + CLK + + + M_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXI + + + + + + + + ASSOCIATED_RESET + M_ARESETN + + + + + + + + + + RST.M_ARESETN + Reset + Reset + + + + + + + RST + + + M_ARESETN + + + + + + CLK.S_ACLK + Clk + Clock + + + + + + + CLK + + + S_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + + + + + + ASSOCIATED_RESET + S_ARESETN + + + + + + + + + + RST.S_ARESETN + Reset + Reset + + + + + + + RST + + + S_ARESETN + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M_ACLK + + in + + + + M_ARESETN + + in + + 0 + 0 + + + + + S_ACLK + + in + + + + S_ARESETN + + in + + 0 + 0 + + + + + + + + + xilinx.com + BlockDiagram/z_turn_imp/z_turn_ps_7_axi_periph_0_imp + s00_couplers_imp + 1.00.a + + + + + + + + + + + xilinx.com + Addressing/ps7 + processing_system7 + 5.5 + + + Data + 4G + 32 + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/z_turn.bxml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/z_turn.bxml new file mode 100644 index 0000000..0d2ca58 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/z_turn.bxml @@ -0,0 +1,252 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/z_turn_ooc.xdc b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/z_turn_ooc.xdc new file mode 100644 index 0000000..8fd1446 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/z_turn_ooc.xdc @@ -0,0 +1,15 @@ +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# This constraints file is not used in normal top-down synthesis (default flow +# of Vivado) +################################################################################ +create_clock -name IO_B34_LP11 -period 20 [get_ports IO_B34_LP11] +create_clock -name ps7_FCLK_CLK0 -period 5.9999998080000063 [get_pins ps7/FCLK_CLK0] +create_clock -name ps7_FCLK_CLK1 -period 20 [get_pins ps7/FCLK_CLK1] +create_clock -name ps7_FCLK_CLK2 -period 10 [get_pins ps7/FCLK_CLK2] +create_clock -name ps7_FCLK_CLK3 -period 5 [get_pins ps7/FCLK_CLK3] + +################################################################################ \ No newline at end of file diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/lib_cdc_v1_0/ea79928f/hdl/src/vhdl/cdc_sync.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/lib_cdc_v1_0/ea79928f/hdl/src/vhdl/cdc_sync.vhd new file mode 100644 index 0000000..3286567 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/lib_cdc_v1_0/ea79928f/hdl/src/vhdl/cdc_sync.vhd @@ -0,0 +1,1261 @@ + +--Generic Help +--C_CDC_TYPE : Defines the type of CDC needed +-- 0 means pulse synchronizer. Used to transfer one clock pulse +-- from prmry domain to scndry domain. +-- 1 means level synchronizer. Used to transfer level signal. +-- 2 means level synchronizer with ack. Used to transfer level +-- signal. Input signal should change only when prmry_ack is detected +-- +--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal +-- Set to 0 when incoming signal is purely floped signal. +-- +--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases +-- it might be needed. +-- 0 means reset not needed for sync flops +-- 1 means reset needed for sync flops. i +-- In this case prmry_resetn should be in prmry clock, +-- while scndry_reset should be in scndry clock. +-- +--C_SINGLE_BIT : CDC should normally be done for single bit signals only. +-- However, based on design buses can also be CDC'ed. +-- 0 means it is a bus. In this case input be connected to prmry_vect_in. +-- Output is on scndry_vect_out. +-- 1 means it is a single bit. In this case input be connected to prmry_in. +-- Output is on scndry_out. +-- +--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 +-- +--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. +-- Value of 0, 1 is allowed only for level CDC. +-- Min value for Pulse CDC is 2 +-- +--Whenever this file is used following XDC constraint has to be added + +-- set_false_path -to [get_pins -hier *cdc_to*/D] + + +--IO Ports +-- +-- prmry_aclk : clock of originating domain (source domain) +-- prmry_resetn : sync reset of originating clock domain (source domain) +-- prmry_in : input signal bit. This should be a pure flop output without +-- any combi logic. This is source. +-- prmry_vect_in : bus signal. From Source domain. +-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. +-- Used only when C_CDC_TYPE = 2 +-- scndry_aclk : destination clock. +-- scndry_resetn : sync reset of destination domain +-- scndry_out : sync'ed output in destination domain. Single bit. +-- scndry_vect_out : sync'ed output in destination domain. bus. + + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_misc.all; +library unisim; +use unisim.vcomponents.FDR; + + + +entity cdc_sync is + generic ( + C_CDC_TYPE : integer range 0 to 2 := 1 ; + -- 0 is pulse synch + -- 1 is level synch + -- 2 is ack based level sync + C_RESET_STATE : integer range 0 to 1 := 0 ; + -- 0 is reset not needed + -- 1 is reset needed + C_SINGLE_BIT : integer range 0 to 1 := 1 ; + -- 0 is bus input + -- 1 is single bit input + C_FLOP_INPUT : integer range 0 to 1 := 0 ; + C_VECTOR_WIDTH : integer range 0 to 64 := 32 ; + C_MTBF_STAGES : integer range 0 to 6 := 2 + -- Vector Data witdth + ); + + port ( + prmry_aclk : in std_logic ; -- + prmry_resetn : in std_logic ; -- + prmry_in : in std_logic ; -- + prmry_vect_in : in std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) ; -- + prmry_ack : out std_logic ; + -- + scndry_aclk : in std_logic ; -- + scndry_resetn : in std_logic ; -- + -- + -- Primary to Secondary Clock Crossing -- + scndry_out : out std_logic ; -- + -- + scndry_vect_out : out std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) -- + + ); + +end cdc_sync; + +------------------------------------------------------------------------------- +-- Architecture +------------------------------------------------------------------------------- +architecture implementation of cdc_sync is + +attribute DowngradeIPIdentifiedWarnings : string; +attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; + +--attribute DONT_TOUCH : STRING; +--attribute KEEP : STRING; +--attribute DONT_TOUCH of implementation : architecture is "yes"; +signal prmry_resetn1 : std_logic := '0'; +signal scndry_resetn1 : std_logic := '0'; +signal prmry_reset2 : std_logic := '0'; +signal scndry_reset2 : std_logic := '0'; +--attribute KEEP of prmry_resetn1 : signal is "true"; +--attribute KEEP of scndry_resetn1 : signal is "true"; + +------------------------------------------------------------------------------- +-- Functions +------------------------------------------------------------------------------- + +-- No Functions Declared + +------------------------------------------------------------------------------- +-- Constants Declarations +------------------------------------------------------------------------------- + +-- No Constants Declared + +------------------------------------------------------------------------------- +-- Begin architecture logic +------------------------------------------------------------------------------- +begin + +HAS_RESET : if C_RESET_STATE = 1 generate +begin +prmry_resetn1 <= prmry_resetn; +scndry_resetn1 <= scndry_resetn; + +end generate HAS_RESET; + +HAS_NO_RESET : if C_RESET_STATE = 0 generate +begin + +prmry_resetn1 <= '1'; +scndry_resetn1 <= '1'; + +end generate HAS_NO_RESET; + +prmry_reset2 <= not prmry_resetn1; +scndry_reset2 <= not scndry_resetn1; + + +-- Generate PULSE clock domain crossing +GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate + +-- Primary to Secondary +signal s_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; +signal s_out_d2 : std_logic := '0'; +signal s_out_d3 : std_logic := '0'; +signal s_out_d4 : std_logic := '0'; +signal s_out_d5 : std_logic := '0'; +signal s_out_d6 : std_logic := '0'; +signal s_out_d7 : std_logic := '0'; +signal s_out_re : std_logic := '0'; +signal prmry_in_xored : std_logic := '0'; +signal p_in_d1_cdc_from : std_logic := '0'; + +signal srst_d1 : std_logic := '0'; +signal srst_d2 : std_logic := '0'; +signal srst_d3 : std_logic := '0'; +signal srst_d4 : std_logic := '0'; +signal srst_d5 : std_logic := '0'; +signal srst_d6 : std_logic := '0'; +signal srst_d7 : std_logic := '0'; + + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Pulse Clock Crossing ** + --** PRIMARY TO SECONDARY OPEN-ENDED ** + --***************************************************************************** + +scndry_vect_out <= (others => '0'); +prmry_ack <= '0'; + +prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; + +--------------------------------------REG_P_IN : process(prmry_aclk) +-------------------------------------- begin +-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +-------------------------------------- p_in_d1_cdc_from <= '0'; +-------------------------------------- else +-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; +-------------------------------------- end if; +-------------------------------------- end if; +-------------------------------------- end process REG_P_IN; + + + +REG_P_IN_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_in_d1_cdc_from, + C => prmry_aclk, + D => prmry_in_xored, + R => prmry_reset2 + ); + + + + + +REG_P_IN2_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d1_cdc_to, + C => scndry_aclk, + D => p_in_d1_cdc_from, + R => scndry_reset2 + ); + + + +------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) +------------------------------------ begin +------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then +------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------------ s_out_d2 <= '0'; +------------------------------------ s_out_d3 <= '0'; +------------------------------------ s_out_d4 <= '0'; +------------------------------------ s_out_d5 <= '0'; +------------------------------------ s_out_d6 <= '0'; +------------------------------------ s_out_d7 <= '0'; +------------------------------------ scndry_out <= '0'; +------------------------------------ else +------------------------------------ s_out_d2 <= s_out_d1_cdc_to; +------------------------------------ s_out_d3 <= s_out_d2; +------------------------------------ s_out_d4 <= s_out_d3; +------------------------------------ s_out_d5 <= s_out_d4; +------------------------------------ s_out_d6 <= s_out_d5; +------------------------------------ s_out_d7 <= s_out_d6; +------------------------------------ scndry_out <= s_out_re; +------------------------------------ end if; +------------------------------------ end if; +------------------------------------ end process P_IN_CROSS2SCNDRY; + + + + +P_IN_CROSS2SCNDRY_s_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d2, + C => scndry_aclk, + D => s_out_d1_cdc_to, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d3, + C => scndry_aclk, + D => s_out_d2, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d4, + C => scndry_aclk, + D => s_out_d3, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d5, + C => scndry_aclk, + D => s_out_d4, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d6, + C => scndry_aclk, + D => s_out_d5, + R => scndry_reset2 + ); + + + +P_IN_CROSS2SCNDRY_s_out_d7 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d7, + C => scndry_aclk, + D => s_out_d6, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_scndry_out : component FDR + generic map(INIT => '0' + )port map ( + Q => scndry_out, + C => scndry_aclk, + D => s_out_re, + R => scndry_reset2 + ); + +s_rst_d1 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d1, + C => scndry_aclk, + D => '1', + R => scndry_reset2 + ); +s_rst_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d2, + C => scndry_aclk, + D => srst_d1, + R => scndry_reset2 + ); +s_rst_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d3, + C => scndry_aclk, + D => srst_d2, + R => scndry_reset2 + ); + +s_rst_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d4, + C => scndry_aclk, + D => srst_d3, + R => scndry_reset2 + ); + + +s_rst_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d5, + C => scndry_aclk, + D => srst_d4, + R => scndry_reset2 + ); + +s_rst_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d6, + C => scndry_aclk, + D => srst_d5, + R => scndry_reset2 + ); + +s_rst_d7 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d7, + C => scndry_aclk, + D => srst_d6, + R => scndry_reset2 + ); + +MTBF_2 : if C_MTBF_STAGES = 2 generate +begin + s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3); + +end generate MTBF_2; + +MTBF_3 : if C_MTBF_STAGES = 3 generate +begin + s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4); + +end generate MTBF_3; + +MTBF_4 : if C_MTBF_STAGES = 4 generate +begin + s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5); + +end generate MTBF_4; + +MTBF_5 : if C_MTBF_STAGES = 5 generate +begin + s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6); + +end generate MTBF_5; + +MTBF_6 : if C_MTBF_STAGES = 6 generate +begin + s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7); + +end generate MTBF_6; + + -- Feed secondary pulse out + +end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; + + +-- Generate LEVEL clock domain crossing with reset state = 0 +GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate +begin +-- Primary to Secondary + +SINGLE_BIT : if C_SINGLE_BIT = 1 generate + +signal p_level_in_d1_cdc_from : std_logic := '0'; +signal p_level_in_int : std_logic := '0'; +signal s_level_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; +signal s_level_out_d2 : std_logic := '0'; +signal s_level_out_d3 : std_logic := '0'; +signal s_level_out_d4 : std_logic := '0'; +signal s_level_out_d5 : std_logic := '0'; +signal s_level_out_d6 : std_logic := '0'; + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic + +scndry_vect_out <= (others => '0'); +prmry_ack <= '0'; + + +INPUT_FLOP : if C_FLOP_INPUT = 1 generate +begin + +---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) +---------------------------------- begin +---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +---------------------------------- p_level_in_d1_cdc_from <= '0'; +---------------------------------- else +---------------------------------- p_level_in_d1_cdc_from <= prmry_in; +---------------------------------- end if; +---------------------------------- end if; +---------------------------------- end process REG_PLEVEL_IN; + + +REG_PLEVEL_IN_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_in_d1_cdc_from, + C => prmry_aclk, + D => prmry_in, + R => prmry_reset2 + ); + + + p_level_in_int <= p_level_in_d1_cdc_from; + +end generate INPUT_FLOP; + + +NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate +begin + + p_level_in_int <= prmry_in; + +end generate NO_INPUT_FLOP; + + +CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d1_cdc_to, + C => scndry_aclk, + D => p_level_in_int, + R => scndry_reset2 + ); + + +------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) +------------------------------ begin +------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then +------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------ s_level_out_d2 <= '0'; +------------------------------ s_level_out_d3 <= '0'; +------------------------------ s_level_out_d4 <= '0'; +------------------------------ s_level_out_d5 <= '0'; +------------------------------ s_level_out_d6 <= '0'; +------------------------------ else +------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; +------------------------------ s_level_out_d3 <= s_level_out_d2; +------------------------------ s_level_out_d4 <= s_level_out_d3; +------------------------------ s_level_out_d5 <= s_level_out_d4; +------------------------------ s_level_out_d6 <= s_level_out_d5; +------------------------------ end if; +------------------------------ end if; +------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; + + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d2, + C => scndry_aclk, + D => s_level_out_d1_cdc_to, + R => scndry_reset2 + ); + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d3, + C => scndry_aclk, + D => s_level_out_d2, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d4, + C => scndry_aclk, + D => s_level_out_d3, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d5, + C => scndry_aclk, + D => s_level_out_d4, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d6, + C => scndry_aclk, + D => s_level_out_d5, + R => scndry_reset2 + ); + + + + + + + +MTBF_L1 : if C_MTBF_STAGES = 1 generate +begin + scndry_out <= s_level_out_d1_cdc_to; + + +end generate MTBF_L1; + +MTBF_L2 : if C_MTBF_STAGES = 2 generate +begin + + scndry_out <= s_level_out_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_out <= s_level_out_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_out <= s_level_out_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_out <= s_level_out_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_out <= s_level_out_d6; + + +end generate MTBF_L6; + +end generate SINGLE_BIT; + + + +MULTI_BIT : if C_SINGLE_BIT = 0 generate + +signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); +signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; +signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic + +scndry_out <= '0'; +prmry_ack <= '0'; + + +INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate +begin + + + +----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) +----------------------------------- begin +----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); +----------------------------------- else +----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; +----------------------------------- end if; +----------------------------------- end if; +----------------------------------- end process REG_PLEVEL_IN; + +FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate +begin + +REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_in_bus_d1_cdc_from (i), + C => prmry_aclk, + D => prmry_vect_in (i), + R => prmry_reset2 + ); +end generate FOR_REG_PLEVEL_IN; + + + + + + p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; + +end generate INPUT_FLOP_BUS; + + +NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate +begin + +p_level_in_bus_int <= prmry_vect_in; + +end generate NO_INPUT_FLOP_BUS; + +FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d1_cdc_to (i), + C => scndry_aclk, + D => p_level_in_bus_int (i), + R => scndry_reset2 + ); +end generate FOR_IN_cdc_to; + +----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) +----------------------------------------- begin +----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then +----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +----------------------------------------- s_level_out_bus_d2 <= (others => '0'); +----------------------------------------- s_level_out_bus_d3 <= (others => '0'); +----------------------------------------- s_level_out_bus_d4 <= (others => '0'); +----------------------------------------- s_level_out_bus_d5 <= (others => '0'); +----------------------------------------- s_level_out_bus_d6 <= (others => '0'); +----------------------------------------- else +----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; +----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; +----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; +----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; +----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; +----------------------------------------- end if; +----------------------------------------- end if; +----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; + + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d2 (i), + C => scndry_aclk, + D => s_level_out_bus_d1_cdc_to (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d3 (i), + C => scndry_aclk, + D => s_level_out_bus_d2 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d4 (i), + C => scndry_aclk, + D => s_level_out_bus_d3 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; + + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d5 (i), + C => scndry_aclk, + D => s_level_out_bus_d4 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d6 (i), + C => scndry_aclk, + D => s_level_out_bus_d5 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; + + + +MTBF_L1 : if C_MTBF_STAGES = 1 generate +begin + + scndry_vect_out <= s_level_out_bus_d1_cdc_to; + + +end generate MTBF_L1; + +MTBF_L2 : if C_MTBF_STAGES = 2 generate +begin + + scndry_vect_out <= s_level_out_bus_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_vect_out <= s_level_out_bus_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_vect_out <= s_level_out_bus_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_vect_out <= s_level_out_bus_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_vect_out <= s_level_out_bus_d6; + + +end generate MTBF_L6; + +end generate MULTI_BIT; + + +end generate GENERATE_LEVEL_P_S_CDC; + + +GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate +-- Primary to Secondary + + +signal p_level_in_d1_cdc_from : std_logic := '0'; +signal p_level_in_int : std_logic := '0'; +signal s_level_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; +signal s_level_out_d2 : std_logic := '0'; +signal s_level_out_d3 : std_logic := '0'; +signal s_level_out_d4 : std_logic := '0'; +signal s_level_out_d5 : std_logic := '0'; +signal s_level_out_d6 : std_logic := '0'; +signal p_level_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; +signal p_level_out_d2 : std_logic := '0'; +signal p_level_out_d3 : std_logic := '0'; +signal p_level_out_d4 : std_logic := '0'; +signal p_level_out_d5 : std_logic := '0'; +signal p_level_out_d6 : std_logic := '0'; +signal p_level_out_d7 : std_logic := '0'; +signal scndry_out_int : std_logic := '0'; +signal prmry_pulse_ack : std_logic := '0'; + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; + + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic +scndry_vect_out <= (others => '0'); + + +INPUT_FLOP : if C_FLOP_INPUT = 1 generate +begin + +------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) +------------------------------------------ begin +------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then +------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------------------ p_level_in_d1_cdc_from <= '0'; +------------------------------------------ else +------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; +------------------------------------------ end if; +------------------------------------------ end if; +------------------------------------------ end process REG_PLEVEL_IN; + + + +REG_PLEVEL_IN_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_in_d1_cdc_from, + C => prmry_aclk, + D => prmry_in, + R => prmry_reset2 + ); + + + p_level_in_int <= p_level_in_d1_cdc_from; + +end generate INPUT_FLOP; + + +NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate +begin + + p_level_in_int <= prmry_in; + +end generate NO_INPUT_FLOP; + + +CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d1_cdc_to, + C => scndry_aclk, + D => p_level_in_int, + R => scndry_reset2 + ); + + +------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) +------------------------------------------------ begin +------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then +------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------------------------ s_level_out_d2 <= '0'; +------------------------------------------------ s_level_out_d3 <= '0'; +------------------------------------------------ s_level_out_d4 <= '0'; +------------------------------------------------ s_level_out_d5 <= '0'; +------------------------------------------------ s_level_out_d6 <= '0'; +------------------------------------------------ else +------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; +------------------------------------------------ s_level_out_d3 <= s_level_out_d2; +------------------------------------------------ s_level_out_d4 <= s_level_out_d3; +------------------------------------------------ s_level_out_d5 <= s_level_out_d4; +------------------------------------------------ s_level_out_d6 <= s_level_out_d5; +------------------------------------------------ end if; +------------------------------------------------ end if; +------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; + + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d2, + C => scndry_aclk, + D => s_level_out_d1_cdc_to, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d3, + C => scndry_aclk, + D => s_level_out_d2, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d4, + C => scndry_aclk, + D => s_level_out_d3, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d5, + C => scndry_aclk, + D => s_level_out_d4, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d6, + C => scndry_aclk, + D => s_level_out_d5, + R => scndry_reset2 + ); + + + + + + + + +--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) +--------------------------------------------------- begin +--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +--------------------------------------------------- p_level_out_d1_cdc_to <= '0'; +--------------------------------------------------- p_level_out_d2 <= '0'; +--------------------------------------------------- p_level_out_d3 <= '0'; +--------------------------------------------------- p_level_out_d4 <= '0'; +--------------------------------------------------- p_level_out_d5 <= '0'; +--------------------------------------------------- p_level_out_d6 <= '0'; +--------------------------------------------------- p_level_out_d7 <= '0'; +--------------------------------------------------- prmry_ack <= '0'; +--------------------------------------------------- else +--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; +--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; +--------------------------------------------------- p_level_out_d3 <= p_level_out_d2; +--------------------------------------------------- p_level_out_d4 <= p_level_out_d3; +--------------------------------------------------- p_level_out_d5 <= p_level_out_d4; +--------------------------------------------------- p_level_out_d6 <= p_level_out_d5; +--------------------------------------------------- p_level_out_d7 <= p_level_out_d6; +--------------------------------------------------- prmry_ack <= prmry_pulse_ack; +--------------------------------------------------- end if; +--------------------------------------------------- end if; +--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; + + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d1_cdc_to, + C => prmry_aclk, + D => scndry_out_int, + R => prmry_reset2 + ); + + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d2, + C => prmry_aclk, + D => p_level_out_d1_cdc_to, + R => prmry_reset2 + ); + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d3, + C => prmry_aclk, + D => p_level_out_d2, + R => prmry_reset2 + ); + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d4, + C => prmry_aclk, + D => p_level_out_d3, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d5, + C => prmry_aclk, + D => p_level_out_d4, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d6, + C => prmry_aclk, + D => p_level_out_d5, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d7, + C => prmry_aclk, + D => p_level_out_d6, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR + generic map(INIT => '0' + )port map ( + Q => prmry_ack, + C => prmry_aclk, + D => prmry_pulse_ack, + R => prmry_reset2 + ); + + + + + + + + + + + + + + + +MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate +begin + + scndry_out_int <= s_level_out_d2; + --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; + prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_out_int <= s_level_out_d3; + --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; + prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_out_int <= s_level_out_d4; + --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; + prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_out_int <= s_level_out_d5; + --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; + prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_out_int <= s_level_out_d6; + --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; + prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; + + +end generate MTBF_L6; + + scndry_out <= scndry_out_int; + + +end generate GENERATE_LEVEL_ACK_P_S_CDC; + + +end implementation; + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/lpf.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/lpf.vhd new file mode 100644 index 0000000..e7a05b5 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/lpf.vhd @@ -0,0 +1,444 @@ +------------------------------------------------------------------------------- +-- lpf - entity/architecture pair +------------------------------------------------------------------------------- +-- +-- ************************************************************************ +-- ** DISCLAIMER OF LIABILITY ** +-- ** ** +-- ** This file contains proprietary and confidential information of ** +-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** +-- ** from Xilinx, and may be used, copied and/or disclosed only ** +-- ** pursuant to the terms of a valid license agreement with Xilinx. ** +-- ** ** +-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** +-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** +-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** +-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** +-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** +-- ** does not warrant that functions included in the Materials will ** +-- ** meet the requirements of Licensee, or that the operation of the ** +-- ** Materials will be uninterrupted or error-free, or that defects ** +-- ** in the Materials will be corrected. Furthermore, Xilinx does ** +-- ** not warrant or make any representations regarding use, or the ** +-- ** results of the use, of the Materials in terms of correctness, ** +-- ** accuracy, reliability or otherwise. ** +-- ** ** +-- ** Xilinx products are not designed or intended to be fail-safe, ** +-- ** or for use in any application requiring fail-safe performance, ** +-- ** such as life-support or safety devices or systems, Class III ** +-- ** medical devices, nuclear facilities, applications related to ** +-- ** the deployment of airbags, or any other applications that could ** +-- ** lead to death, personal injury or severe property or ** +-- ** environmental damage (individually and collectively, "critical ** +-- ** applications"). Customer assumes the sole risk and liability ** +-- ** of any use of Xilinx products in critical applications, ** +-- ** subject only to applicable laws and regulations governing ** +-- ** limitations on product liability. ** +-- ** ** +-- ** Copyright 2012 Xilinx, Inc. ** +-- ** All rights reserved. ** +-- ** ** +-- ** This disclaimer and copyright notice must be retained as part ** +-- ** of this file at all times. ** +-- ************************************************************************ +-- +------------------------------------------------------------------------------- +-- Filename: lpf.vhd +-- Version: v4.00a +-- Description: Parameterizeable top level processor reset module. +-- VHDL-Standard: VHDL'93 +------------------------------------------------------------------------------- +-- Structure: This section should show the hierarchical structure of the +-- designs.Separate lines with blank lines if necessary to improve +-- readability. +-- +-- proc_sys_reset.vhd +-- upcnt_n.vhd +-- lpf.vhd +-- sequence.vhd +------------------------------------------------------------------------------- +-- Author: Kurt Conover +-- History: +-- Kurt Conover 11/08/01 -- First Release +-- +-- KC 02/25/2002 -- Added Dcm_locked as an input +-- -- Added Power on reset srl_time_out +-- +-- KC 08/26/2003 -- Added attribute statements for power on +-- reset SRL +-- +-- ~~~~~~~ +-- SK 03/11/10 +-- ^^^^^^^ +-- 1. Updated the core so support the active low "Interconnect_aresetn" and +-- "Peripheral_aresetn" signals. +-- ^^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_arith.all; +library lib_cdc_v1_0; +--use lib_cdc_v1_0.all; +library Unisim; + use Unisim.all; +------------------------------------------------------------------------------- +-- Port Declaration +------------------------------------------------------------------------------- +-- Definition of Generics: +-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting +-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting +-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low +-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low +-- +-- Definition of Ports: +-- Slowest_sync_clk -- Clock +-- External_System_Reset -- External Reset Input +-- Auxiliary_System_Reset -- Auxiliary Reset Input +-- Dcm_locked -- DCM Locked, hold system in reset until 1 +-- Lpf_reset -- Low Pass Filtered Output +-- +------------------------------------------------------------------------------- +entity lpf is + generic( + C_EXT_RST_WIDTH : Integer; + C_AUX_RST_WIDTH : Integer; + C_EXT_RESET_HIGH : std_logic; + C_AUX_RESET_HIGH : std_logic + ); + + port( + MB_Debug_Sys_Rst : in std_logic; + Dcm_locked : in std_logic; + External_System_Reset : in std_logic; + Auxiliary_System_Reset : in std_logic; + Slowest_Sync_Clk : in std_logic; + Lpf_reset : out std_logic + ); + +end lpf; + +architecture imp of lpf is + +component SRL16 is +-- synthesis translate_off + generic ( + INIT : bit_vector ); +-- synthesis translate_on + port (D : in std_logic; + CLK : in std_logic; + A0 : in std_logic; + A1 : in std_logic; + A2 : in std_logic; + A3 : in std_logic; + Q : out std_logic); +end component SRL16; + + +constant CLEAR : std_logic := '0'; + +signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset +signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1) + := (others => '0'); -- LPF DFF + +signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset +signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1) + := (others => '0'); -- LPF DFF + +signal exr_and : std_logic := '0'; -- varible input width "and" gate +signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate + +signal asr_and : std_logic := '0'; -- varible input width "and" gate +signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate + +signal lpf_int : std_logic := '0'; -- internal Lpf_reset +signal lpf_exr : std_logic := '0'; +signal lpf_asr : std_logic := '0'; + +signal srl_time_out : std_logic; + +attribute INIT : string; +attribute INIT of POR_SRL_I: label is "FFFF"; + + +begin + + Lpf_reset <= lpf_int; + +------------------------------------------------------------------------------- +-- Power On Reset Generation +------------------------------------------------------------------------------- +-- This generates a reset for the first 16 clocks after a power up +------------------------------------------------------------------------------- + POR_SRL_I: SRL16 +-- synthesis translate_off + generic map ( + INIT => X"FFFF") +-- synthesis translate_on + port map ( + D => '0', + CLK => Slowest_sync_clk, + A0 => '1', + A1 => '1', + A2 => '1', + A3 => '1', + Q => srl_time_out); + +------------------------------------------------------------------------------- +-- LPF_OUTPUT_PROCESS +------------------------------------------------------------------------------- +-- This generates the reset pulse and the count enable to core reset counter +-- +--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate +--begin +LPF_OUTPUT_PROCESS: process (Slowest_sync_clk) +begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked; + end if; +end process LPF_OUTPUT_PROCESS; +--end generate ACTIVE_HIGH_LPF_EXT; + +--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate +--begin +--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- lpf_int <= not (lpf_exr or +-- lpf_asr or +-- srl_time_out)or +-- not Dcm_locked; +-- end if; +-- end process; +--end generate ACTIVE_LOW_LPF_EXT; + +EXR_OUTPUT_PROCESS: process (Slowest_sync_clk) +begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if exr_and = '1' then + lpf_exr <= '1'; + elsif (exr_and = '0' and exr_nand = '1') then + lpf_exr <= '0'; + end if; + end if; +end process EXR_OUTPUT_PROCESS; + +ASR_OUTPUT_PROCESS: process (Slowest_sync_clk) +begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if asr_and = '1' then + lpf_asr <= '1'; + elsif (asr_and = '0' and asr_nand = '1') then + lpf_asr <= '0'; + end if; + end if; +end process ASR_OUTPUT_PROCESS; +------------------------------------------------------------------------------- +-- This If-generate selects an active high input for External System Reset +------------------------------------------------------------------------------- +ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate +begin + ----------------------------------- +exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst; + +ACT_HI_EXT: entity lib_cdc_v1_0.cdc_sync + generic map ( + C_CDC_TYPE => 1, + C_RESET_STATE => 0, + C_SINGLE_BIT => 1, + C_FLOP_INPUT => 0, + C_VECTOR_WIDTH => 2, + C_MTBF_STAGES => 4 + ) + port map( + prmry_aclk => '1', + prmry_resetn => '1',--S_AXI_ARESETN, + prmry_in => exr_d1, + prmry_ack => open, + scndry_out => exr_lpf(0), + scndry_aclk => Slowest_Sync_Clk, + scndry_resetn => '1', --S_AXIS_ARESETN, + prmry_vect_in => "00", + scndry_vect_out => open + ); + +----------------------------------- +end generate ACTIVE_HIGH_EXT; +------------------------------------------------------------------------------- +-- This If-generate selects an active low input for External System Reset +------------------------------------------------------------------------------- +ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate +begin +exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst; + ------------------------------------- + +ACT_LO_EXT: entity lib_cdc_v1_0.cdc_sync + generic map ( + C_CDC_TYPE => 1, + C_RESET_STATE => 0, + C_SINGLE_BIT => 1, + C_FLOP_INPUT => 0, + C_VECTOR_WIDTH => 2, + C_MTBF_STAGES => 4 + ) + port map( + prmry_aclk => '1', + prmry_resetn => '1',--S_AXI_ARESETN, + prmry_in => exr_d1, + prmry_ack => open, + scndry_out => exr_lpf(0), + scndry_aclk => Slowest_Sync_Clk, + scndry_resetn => '1', --S_AXIS_ARESETN, + prmry_vect_in => "00", + scndry_vect_out => open + ); +------------------------------------- +end generate ACTIVE_LOW_EXT; + +------------------------------------------------------------------------------- +-- This If-generate selects an active high input for Auxiliary System Reset +------------------------------------------------------------------------------- +ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate +begin +asr_d1 <= Auxiliary_System_Reset; +------------------------------------- + +ACT_HI_AUX: entity lib_cdc_v1_0.cdc_sync + generic map ( + C_CDC_TYPE => 1, + C_RESET_STATE => 0, + C_SINGLE_BIT => 1, + C_FLOP_INPUT => 0, + C_VECTOR_WIDTH => 2, + C_MTBF_STAGES => 4 + ) + port map( + prmry_aclk => '1', + prmry_resetn => '1',--S_AXI_ARESETN, + prmry_in => asr_d1, + prmry_ack => open, + scndry_out => asr_lpf(0), + scndry_aclk => Slowest_Sync_Clk, + scndry_resetn => '1', --S_AXIS_ARESETN, + prmry_vect_in => "00", + scndry_vect_out => open + ); + ------------------------------------- +end generate ACTIVE_HIGH_AUX; +------------------------------------------------------------------------------- +-- This If-generate selects an active low input for Auxiliary System Reset +------------------------------------------------------------------------------- +ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate +begin + ------------------------------------- +asr_d1 <= not Auxiliary_System_Reset; + +ACT_LO_AUX: entity lib_cdc_v1_0.cdc_sync + generic map ( + C_CDC_TYPE => 1, + C_RESET_STATE => 0, + C_SINGLE_BIT => 1, + C_FLOP_INPUT => 0, + C_VECTOR_WIDTH => 2, + C_MTBF_STAGES => 4 + ) + port map( + prmry_aclk => '1', + prmry_resetn => '1',--S_AXI_ARESETN, + prmry_in => asr_d1, + prmry_ack => open, + scndry_out => asr_lpf(0), + scndry_aclk => Slowest_Sync_Clk, + scndry_resetn => '1', --S_AXIS_ARESETN, + prmry_vect_in => "00", + scndry_vect_out => open + ); + ------------------------------------- +end generate ACTIVE_LOW_AUX; + +------------------------------------------------------------------------------- +-- This For-generate creates the low pass filter D-Flip Flops +------------------------------------------------------------------------------- +EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate +begin + ---------------------------------------- + EXT_LPF_DFF : process (Slowest_Sync_Clk) + begin + if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then + exr_lpf(i) <= exr_lpf(i-1); + end if; + end process; + ---------------------------------------- +end generate EXT_LPF; +------------------------------------------------------------------------------------------ +-- Implement the 'AND' function on the for the LPF +------------------------------------------------------------------------------------------ +EXT_LPF_AND : process (exr_lpf) +Variable loop_and : std_logic; +Variable loop_nand : std_logic; +Begin + loop_and := '1'; + loop_nand := '1'; + for j in 0 to C_EXT_RST_WIDTH - 1 loop + loop_and := loop_and and exr_lpf(j); + loop_nand := loop_nand and not exr_lpf(j); + End loop; + + exr_and <= loop_and; + exr_nand <= loop_nand; + +end process; + +------------------------------------------------------------------------------- +-- This For-generate creates the low pass filter D-Flip Flops +------------------------------------------------------------------------------- +AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate +begin + ---------------------------------------- + AUX_LPF_DFF : process (Slowest_Sync_Clk) + begin + if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then + asr_lpf(k) <= asr_lpf(k-1); + end if; + end process; + ---------------------------------------- +end generate AUX_LPF; +------------------------------------------------------------------------------------------ +-- Implement the 'AND' function on the for the LPF +------------------------------------------------------------------------------------------ +AUX_LPF_AND : process (asr_lpf) +Variable aux_loop_and : std_logic; +Variable aux_loop_nand : std_logic; +Begin + aux_loop_and := '1'; + aux_loop_nand := '1'; + for m in 0 to C_AUX_RST_WIDTH - 1 loop + aux_loop_and := aux_loop_and and asr_lpf(m); + aux_loop_nand := aux_loop_nand and not asr_lpf(m); + End loop; + + asr_and <= aux_loop_and; + asr_nand <= aux_loop_nand; + +end process; + +end imp; + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/proc_sys_reset.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/proc_sys_reset.vhd new file mode 100644 index 0000000..f2aae81 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/proc_sys_reset.vhd @@ -0,0 +1,455 @@ +------------------------------------------------------------------------------- +-- proc_sys_reset - entity/architecture pair +------------------------------------------------------------------------------- +-- +-- ************************************************************************ +-- ** DISCLAIMER OF LIABILITY ** +-- ** ** +-- ** This file contains proprietary and confidential information of ** +-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** +-- ** from Xilinx, and may be used, copied and/or disclosed only ** +-- ** pursuant to the terms of a valid license agreement with Xilinx. ** +-- ** ** +-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** +-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** +-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** +-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** +-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** +-- ** does not warrant that functions included in the Materials will ** +-- ** meet the requirements of Licensee, or that the operation of the ** +-- ** Materials will be uninterrupted or error-free, or that defects ** +-- ** in the Materials will be corrected. Furthermore, Xilinx does ** +-- ** not warrant or make any representations regarding use, or the ** +-- ** results of the use, of the Materials in terms of correctness, ** +-- ** accuracy, reliability or otherwise. ** +-- ** ** +-- ** Xilinx products are not designed or intended to be fail-safe, ** +-- ** or for use in any application requiring fail-safe performance, ** +-- ** such as life-support or safety devices or systems, Class III ** +-- ** medical devices, nuclear facilities, applications related to ** +-- ** the deployment of airbags, or any other applications that could ** +-- ** lead to death, personal injury or severe property or ** +-- ** environmental damage (individually and collectively, "critical ** +-- ** applications"). Customer assumes the sole risk and liability ** +-- ** of any use of Xilinx products in critical applications, ** +-- ** subject only to applicable laws and regulations governing ** +-- ** limitations on product liability. ** +-- ** ** +-- ** Copyright 2012 Xilinx, Inc. ** +-- ** All rights reserved. ** +-- ** ** +-- ** This disclaimer and copyright notice must be retained as part ** +-- ** of this file at all times. ** +-- ************************************************************************ +-- +------------------------------------------------------------------------------- +-- Filename: proc_sys_reset.vhd +-- Version: v4.00a +-- Description: Parameterizeable top level processor reset module. +-- VHDL-Standard: VHDL'93 +------------------------------------------------------------------------------- +-- Structure: This section should show the hierarchical structure of the +-- designs.Separate lines with blank lines if necessary to improve +-- readability. +-- +-- proc_sys_reset.vhd +-- upcnt_n.vhd +-- lpf.vhd +-- sequence.vhd +------------------------------------------------------------------------------- +-- Author: rolandp +-- History: +-- kc 11/07/01 -- First version +-- +-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to +-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to +-- C_AUX_RESET_HIGH to match generics used in +-- MicroBlaze. Added the DCM Lock as an input +-- to keep reset active until after the Lock +-- is valid. +-- lcw 10/11/2004 -- Updated for NCSim +-- Ravi 09/14/2006 -- Added Attributes for synthesis +-- rolandp 04/16/2007 -- version 2.00a +-- ~~~~~~~ +-- SK 03/11/10 +-- ^^^^^^^ +-- 1. Updated the core so support the active low "Interconnect_aresetn" and +-- "Peripheral_aresetn" signals. +-- ^^^^^^^ +-- ~~~~~~~ +-- SK 05/12/11 +-- ^^^^^^^ +-- 1. Updated the core so remove the support for PPC related functionality. +-- ^^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_cmb" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; +library unisim; + use unisim.vcomponents.all; +library proc_sys_reset_v5_0; + use proc_sys_reset_v5_0.all; + +------------------------------------------------------------------------------- +-- Port Declaration +------------------------------------------------------------------------------- +-- Definition of Generics: +-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting +-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting + +-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low +-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low + +-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate +-- C_NUM_PERP_RST -- Number of Peripheral resets to generate +-- +-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect +-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral + +-- Definition of Ports: +-- slowest_sync_clk -- Clock +-- ext_reset_in -- External Reset Input +-- aux_reset_in -- Auxiliary Reset Input +-- mb_debug_sys_rst -- MDM Reset Input +-- dcm_locked -- DCM Locked, hold system in reset until 1 +-- mb_reset -- MB core reset out +-- bus_struct_reset -- Bus structure reset out +-- peripheral_reset -- Peripheral reset out + +-- interconnect_aresetn -- Interconnect Bus structure registered rst out +-- peripheral_aresetn -- Active Low Peripheral registered reset out +------------------------------------------------------------------------------- + +entity proc_sys_reset is + generic ( + C_FAMILY : string := "virtex7"; + C_EXT_RST_WIDTH : integer := 4; + C_AUX_RST_WIDTH : integer := 4; + C_EXT_RESET_HIGH : std_logic := '0'; -- High active input + C_AUX_RESET_HIGH : std_logic := '1'; -- High active input + C_NUM_BUS_RST : integer := 1; + C_NUM_PERP_RST : integer := 1; + + C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010 + C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010 + ); + port ( + slowest_sync_clk : in std_logic; + + ext_reset_in : in std_logic; + aux_reset_in : in std_logic; + + -- from MDM + mb_debug_sys_rst : in std_logic; + -- DCM locked information + dcm_locked : in std_logic := '1'; + + -- -- from PPC + -- Core_Reset_Req_0 : in std_logic; + -- Chip_Reset_Req_0 : in std_logic; + -- System_Reset_Req_0 : in std_logic; + -- Core_Reset_Req_1 : in std_logic; + -- Chip_Reset_Req_1 : in std_logic; + -- System_Reset_Req_1 : in std_logic; + + -- RstcPPCresetcore_0 : out std_logic := '0'; + -- RstcPPCresetchip_0 : out std_logic := '0'; + -- RstcPPCresetsys_0 : out std_logic := '0'; + -- RstcPPCresetcore_1 : out std_logic := '0'; + -- RstcPPCresetchip_1 : out std_logic := '0'; + -- RstcPPCresetsys_1 : out std_logic := '0'; + + -- to Microblaze active high reset + mb_reset : out std_logic := '0'; + -- active high resets + bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1) + := (others => '0'); + peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1) + := (others => '0'); + -- active low resets + interconnect_aresetn : out + std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1)) + := (others => '1'); + peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1)) + := (others => '1') + ); + +end entity proc_sys_reset; + +------------------------------------------------------------------------------- +-- Architecture +------------------------------------------------------------------------------- +architecture imp of proc_sys_reset is + +------------------------------------------------------------------------------- +-- Constant Declarations +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- Signal and Type Declarations +-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req +-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req +-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req +-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req +-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req +-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req + +signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable +signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable + +signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0 +signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1 + +signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output +signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output + +signal lpf_reset : std_logic; -- Low pass filtered ext or aux + +--signal Chip_Reset_Req : std_logic := '0'; +--signal System_Reset_Req : std_logic := '0'; + +signal Bsr_out : std_logic; +signal Pr_out : std_logic; + +-- signal Core_out : std_logic; +-- signal Chip_out : std_logic; +-- signal Sys_out : std_logic; +signal MB_out : std_logic; + +------------------------------------------------------------------------------- +-- Attributes to synthesis +------------------------------------------------------------------------------- + +attribute equivalent_register_removal: string; +attribute equivalent_register_removal of bus_struct_reset : signal is "no"; +attribute equivalent_register_removal of peripheral_reset : signal is "no"; + +attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; +attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; + +begin +------------------------------------------------------------------------------- + +-- --------------------- +-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze +-- --------------------- +-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate +-- begin + MB_Reset_PROCESS: process (slowest_sync_clk) + begin + if (slowest_sync_clk'event and slowest_sync_clk = '1') then + mb_reset <= MB_out; + end if; + end process; +-- ---------------------------------------------------------------------------- +-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s) +-- ---------------------------------------------------------------------------- + BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate + BSR_DFF : process (slowest_sync_clk) + begin + if (slowest_sync_clk'event and slowest_sync_clk = '1') then + bus_struct_reset(i) <= Bsr_out; + end if; + end process; + end generate BSR_OUT_DFF; + +-- --------------------------------------------------------------------------- +-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s) +-- --------------------------------------------------------------------------- + ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate + BSR_DFF : process (slowest_sync_clk) + begin + if (slowest_sync_clk'event and slowest_sync_clk = '1') then + interconnect_aresetn(i) <= not (Bsr_out); + end if; + end process; + end generate ACTIVE_LOW_BSR_OUT_DFF; +------------------------------------------------------------------------------- + +-- ---------------------------------------------------------------------------- +-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s) +-- ---------------------------------------------------------------------------- + PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate + PR_DFF : process (slowest_sync_clk) + begin + if (slowest_sync_clk'event and slowest_sync_clk = '1') then + peripheral_reset(i) <= Pr_out; + end if; + end process; + end generate PR_OUT_DFF; + +-- ---------------------------------------------------------------------------- +-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s) +-- ---------------------------------------------------------------------------- + ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate + ACTIVE_LOW_PR_DFF : process (slowest_sync_clk) + begin + if (slowest_sync_clk'event and slowest_sync_clk = '1') then + peripheral_aresetn(i) <= not(Pr_out); + end if; + end process; + end generate ACTIVE_LOW_PR_OUT_DFF; +------------------------------------------------------------------------------- +-- This process defines the RstcPPCreset and MB_Reset outputs +------------------------------------------------------------------------------- + -- Rstc_output_PROCESS_0: process (Slowest_sync_clk) + -- begin + -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + -- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and + -- core_cnt_0(1) and core_cnt_0(0)) + -- or Core_out; + -- RstcPPCresetchip_0 <= Chip_out; + -- RstcPPCresetsys_0 <= Sys_out; + -- end if; + -- end process; + + -- Rstc_output_PROCESS_1: process (Slowest_sync_clk) + -- begin + -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + -- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and + -- core_cnt_1(1) and core_cnt_1(0)) + -- or Core_out; + -- RstcPPCresetchip_1 <= Chip_out; + -- RstcPPCresetsys_1 <= Sys_out; + -- end if; + -- end process; + +------------------------------------------------------------------------------- + +--------------------------------------------------------------------------------- +---- This process delays signals so the the edge can be detected and used +---- Double register to sync up with slowest_sync_clk +--------------------------------------------------------------------------------- +-- DELAY_PROCESS_0: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- core_reset_req_0_d1 <= Core_Reset_Req_0; +-- core_reset_req_0_d2 <= core_reset_req_0_d1; +-- core_reset_req_0_d3 <= core_reset_req_0_d2; +-- end if; +-- end process; +-- +-- DELAY_PROCESS_1: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- core_reset_req_1_d1 <= Core_Reset_Req_1; +-- core_reset_req_1_d2 <= core_reset_req_1_d1; +-- core_reset_req_1_d3 <= core_reset_req_1_d2; +-- end if; +-- end process; + + +-- ** -- ------------------------------------------------------------------------------- +-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a +-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks +-- ** -- ------------------------------------------------------------------------------- +-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0.UPCNT_N +-- ** -- generic map (C_SIZE => 4) +-- ** -- port map( +-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0); +-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC; +-- ** -- Load => '0', -- in STD_LOGIC; +-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC; +-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC; +-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) +-- ** -- ); +-- ** -- +-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0.UPCNT_N +-- ** -- generic map (C_SIZE => 4) +-- ** -- port map( +-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0); +-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC; +-- ** -- Load => '0', -- in STD_LOGIC; +-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC; +-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC; +-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) +-- ** -- ); +-- ** -- +-- ** -- ------------------------------------------------------------------------------- +-- ** -- -- CORE_RESET_PROCESS +-- ** -- ------------------------------------------------------------------------------- +-- ** -- -- This generates the reset pulse and the count enable to core reset counter +-- ** -- -- +-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk) +-- ** -- begin +-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1)); +-- ** -- --or not core_req_edge_0; +-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3); +-- ** -- end if; +-- ** -- end process; +-- ** -- +-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk) +-- ** -- begin +-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1)); +-- ** -- --or not core_req_edge_1; +-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3); +-- ** -- end if; +-- ** -- end process; + +------------------------------------------------------------------------------- +-- This instantiates a low pass filter to filter both External and Auxiliary +-- Reset Inputs. +------------------------------------------------------------------------------- + EXT_LPF : entity proc_sys_reset_v5_0.LPF + generic map ( + C_EXT_RST_WIDTH => C_EXT_RST_WIDTH, + C_AUX_RST_WIDTH => C_AUX_RST_WIDTH, + C_EXT_RESET_HIGH => C_EXT_RESET_HIGH, + C_AUX_RESET_HIGH => C_AUX_RESET_HIGH + ) + port map( + MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic + Dcm_locked => dcm_locked, -- in std_logic + External_System_Reset => ext_reset_in, -- in std_logic + Auxiliary_System_Reset => aux_reset_in, -- in std_logic + Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic + Lpf_reset => lpf_reset -- out std_logic + ); + +------------------------------------------------------------------------------- +-- This instantiates the sequencer +-- This controls the time between resets becoming inactive +------------------------------------------------------------------------------- + + -- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1; + + -- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1; + + SEQ : entity proc_sys_reset_v5_0.SEQUENCE + --generic map ( + -- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH + --) + port map( + Lpf_reset => lpf_reset, -- in std_logic + --System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic + --Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic + Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic + Bsr_out => Bsr_out, -- out std_logic + Pr_out => Pr_out, -- out std_logic + --Core_out => open, -- Core_out, -- out std_logic + --Chip_out => open, -- Chip_out, -- out std_logic + --Sys_out => open, -- Sys_out, -- out std_logic + MB_out => MB_out); -- out std_logic + +end imp; + +--END_SINGLE_FILE_TAG diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/sequence.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/sequence.vhd new file mode 100644 index 0000000..61b0461 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/sequence.vhd @@ -0,0 +1,521 @@ +------------------------------------------------------------------------------- +-- sequence - entity/architecture pair +------------------------------------------------------------------------------- +-- +-- ************************************************************************ +-- ** DISCLAIMER OF LIABILITY ** +-- ** ** +-- ** This file contains proprietary and confidential information of ** +-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** +-- ** from Xilinx, and may be used, copied and/or disclosed only ** +-- ** pursuant to the terms of a valid license agreement with Xilinx. ** +-- ** ** +-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** +-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** +-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** +-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** +-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** +-- ** does not warrant that functions included in the Materials will ** +-- ** meet the requirements of Licensee, or that the operation of the ** +-- ** Materials will be uninterrupted or error-free, or that defects ** +-- ** in the Materials will be corrected. Furthermore, Xilinx does ** +-- ** not warrant or make any representations regarding use, or the ** +-- ** results of the use, of the Materials in terms of correctness, ** +-- ** accuracy, reliability or otherwise. ** +-- ** ** +-- ** Xilinx products are not designed or intended to be fail-safe, ** +-- ** or for use in any application requiring fail-safe performance, ** +-- ** such as life-support or safety devices or systems, Class III ** +-- ** medical devices, nuclear facilities, applications related to ** +-- ** the deployment of airbags, or any other applications that could ** +-- ** lead to death, personal injury or severe property or ** +-- ** environmental damage (individually and collectively, "critical ** +-- ** applications"). Customer assumes the sole risk and liability ** +-- ** of any use of Xilinx products in critical applications, ** +-- ** subject only to applicable laws and regulations governing ** +-- ** limitations on product liability. ** +-- ** ** +-- ** Copyright 2012 Xilinx, Inc. ** +-- ** All rights reserved. ** +-- ** ** +-- ** This disclaimer and copyright notice must be retained as part ** +-- ** of this file at all times. ** +-- ************************************************************************ +-- +------------------------------------------------------------------------------- +-- Filename: proc_sys_reset.vhd +-- Version: v4.00a +-- Description: Parameterizeable top level processor reset module. +-- VHDL-Standard: VHDL'93 +------------------------------------------------------------------------------- +-- Structure: This section should show the hierarchical structure of the +-- designs.Separate lines with blank lines if necessary to improve +-- readability. +-- -- proc_sys_reset.vhd +-- -- upcnt_n.vhd +-- -- lpf.vhd +-- -- sequence.vhd +------------------------------------------------------------------------------- +-- Filename: sequence.vhd +-- +-- Description: +-- This file control the sequencing coming out of a reset. +-- The sequencing is as follows: +-- Bus_Struct_Reset comes out of reset first. Either when the +-- external or auxiliary reset goes inactive or 16 clocks +-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC +-- System_Reset_Request. +-- Peripheral_Reset comes out of reset 16 clocks after +-- Bus_Struct_Reset. +-- The PPC resetcore, comes out of reset +-- 16 clocks after Peripheral_Reset. +-- The PPC resetchip and resetsystem come out of reset +-- at the same time as Bus_Struct_Reset. +------------------------------------------------------------------------------- +-- Author: Kurt Conover +-- History: +-- Kurt Conover 11/12/01 -- First Release +-- LC Whittle 10/11/2004 -- Update for NCSim +-- rolandp 04/16/2007 -- v2.00a +-- +-- ~~~~~~~ +-- SK 03/11/10 +-- ^^^^^^^ +-- 1. Updated the core so support the active low "Interconnect_aresetn" and +-- "Peripheral_aresetn" signals. +-- ^^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library unisim; +use unisim.vcomponents.all; +library proc_sys_reset_v5_0; + +------------------------------------------------------------------------------- +-- Port Declaration +------------------------------------------------------------------------------- +-- Definition of Generics: +-- +-- Definition of Ports: +-- Lpf_reset -- Low Pass Filtered in +-- System_Reset_Req -- System Reset Request +-- Chip_Reset_Req -- Chip Reset Request +-- Slowest_Sync_Clk -- Clock +-- Bsr_out -- Bus Structure Reset out +-- Pr_out -- Peripheral Reset out +-- Core_out -- Core reset out +-- Chip_out -- Chip reset out +-- Sys_out -- System reset out +-- MB_out -- MB reset out +-- +------------------------------------------------------------------------------- +entity sequence is + port( + Lpf_reset : in std_logic; + -- System_Reset_Req : in std_logic; + -- Chip_Reset_Req : in std_logic; + Slowest_Sync_Clk : in std_logic; + Bsr_out : out std_logic; + Pr_out : out std_logic; + -- Core_out : out std_logic; + -- Chip_out : out std_logic; + -- Sys_out : out std_logic; + MB_out : out std_logic + ); +end sequence; + +architecture imp of sequence is + +constant CLEAR : std_logic := '0'; +constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12 +constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25 +constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28 +constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41 +constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44 +constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57 +constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP; +constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS; +constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP; +constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS; + +signal bsr : std_logic := '0'; +signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0'); +signal pr : std_logic := '0'; +signal pr_dec : std_logic_vector(2 downto 0) := (others => '0'); +signal Core : std_logic := '0'; +signal core_dec : std_logic_vector(2 downto 0) := (others => '0'); +signal Chip : std_logic := '0'; +signal chip_dec : std_logic_vector(2 downto 0) := (others => '0'); +signal Sys : std_logic := '0'; +signal sys_dec : std_logic_vector(2 downto 0) := (others => '0'); +signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req +signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req +signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req +signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req +signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req +signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req +signal seq_cnt : std_logic_vector(5 downto 0); +signal seq_cnt_en : std_logic := '0'; +signal seq_clr : std_logic := '0'; + +signal ris_edge : std_logic := '0'; +signal sys_edge : std_logic := '0'; +signal from_sys : std_logic; + +------------------------------------------------------------------------------- +-- Component Declarations +------------------------------------------------------------------------------- + +begin + + Pr_out <= pr; + Bsr_out <= bsr; + MB_out <= core; + -- Core_out <= core; + -- Chip_out <= chip or sys; + -- Sys_out <= sys; + +------------------------------------------------------------------------------- +-- This process remembers that the reset was caused be +-- System_Reset_Req +------------------------------------------------------------------------------- + SYS_FROM_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + --if Lpf_reset='1' or system_reset_req_d3='1' then + if (Lpf_reset = '1') then + from_sys <= '1'; + --elsif Chip_Reset_Req_d3='1' then + -- from_sys <= '0'; + elsif (Core = '0') then + from_sys <='0'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- This instantiates a counter to control the sequencing +------------------------------------------------------------------------------- + SEQ_COUNTER : entity proc_sys_reset_v5_0.UPCNT_N + generic map (C_SIZE => 6) + port map( + Data => "000000", + Cnt_en => seq_cnt_en, + Load => '0', + Clr => seq_clr, + Clk => Slowest_sync_clk, + Qout => seq_cnt + ); + +------------------------------------------------------------------------------- +-- SEQ_CNT_EN_PROCESS +------------------------------------------------------------------------------- +-- This generates the reset pulse and the count enable to core reset counter +-- count until all outputs are inactive +------------------------------------------------------------------------------- + SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if (Lpf_reset='1' --or + --System_Reset_Req_d3='1' or + --Chip_Reset_Req_d3='1' or + --ris_edge = '1' + ) then + seq_cnt_en <= '1'; + elsif (Core='0') then -- Core always present and always last + seq_cnt_en <= '0'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- SEQ_CLR_PROCESS +------------------------------------------------------------------------------- +-- This generates the reset to the sequence counter +-- Clear the counter on a rising edge of chip or system request or low pass +-- filter output +------------------------------------------------------------------------------- + SEQ_CLR_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + -- if ris_edge = '1' or Lpf_reset = '1' then + if (Lpf_reset = '1') then + seq_clr <= '0'; + else + seq_clr <= '1'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- This process defines the Peripheral_Reset output signal +------------------------------------------------------------------------------- + PR_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + --if ris_edge = '1' or Lpf_reset = '1' then + if (Lpf_reset = '1') then + pr <= '1'; + elsif (pr_dec(2) = '1') then + pr <= '0'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- This process decodes the sequence counter for PR to use +------------------------------------------------------------------------------- + PR_DECODE_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if ( + (seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0') + or + (seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1') + ) then + pr_dec(0) <= '1'; + else + pr_dec(0) <= '0'; + end if; + if ( + (seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0') + or + (seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1') + )then + pr_dec(1) <= '1'; + else + pr_dec(1) <= '0'; + end if; + pr_dec(2) <= pr_dec(1) and pr_dec(0); + end if; + end process; + +------------------------------------------------------------------------------- +-- This process defines the Bus_Struct_Reset output signal +------------------------------------------------------------------------------- + BSR_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + --if ris_edge = '1' or Lpf_reset = '1' then + if (Lpf_reset = '1') then + bsr <= '1'; + elsif (bsr_dec(2) = '1') then + bsr <= '0'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- This process decodes the sequence counter for BSR to use +------------------------------------------------------------------------------- + BSR_DECODE_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if ( + (seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0') + or + (seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1') + )then + bsr_dec(0) <= '1'; + else + bsr_dec(0) <= '0'; + end if; + if ( + (seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0') + or + (seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1') + )then + bsr_dec(1) <= '1'; + else + bsr_dec(1) <= '0'; + end if; + bsr_dec(2) <= bsr_dec(1) and bsr_dec(0); + end if; + end process; + + +------------------------------------------------------------------------------- +-- This process defines the Peripheral_Reset output signal +------------------------------------------------------------------------------- + CORE_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + -- if ris_edge = '1' or Lpf_reset = '1' then + if (Lpf_reset = '1') then + core <= '1'; + elsif (core_dec(2) = '1') then + core <= '0'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- This process decodes the sequence counter for PR to use +------------------------------------------------------------------------------- + CORE_DECODE_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if ( + (seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0') + or + (seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1') + )then + core_dec(0) <= '1'; + else + core_dec(0) <= '0'; + end if; + if ( + (seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0') + or + (seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1') + )then + core_dec(1) <= '1'; + else + core_dec(1) <= '0'; + end if; + core_dec(2) <= core_dec(1) and core_dec(0); + end if; + end process; + +--------------------------------------------------------------------------------- +---- This process defines the Chip output signal +--------------------------------------------------------------------------------- +-- CHIP_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- -- if ris_edge = '1' or Lpf_reset = '1' then +-- if Lpf_reset = '1' then +-- chip <= '1'; +-- elsif chip_dec(2) = '1' then +-- chip <= '0'; +-- end if; +-- end if; +-- end process; +-- +--------------------------------------------------------------------------------- +---- This process decodes the sequence counter for Chip to use +---- sys is overlapping the chip reset and thus no need to decode this here +--------------------------------------------------------------------------------- +-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then +-- chip_dec(0) <= '1'; +-- else +-- chip_dec(0) <= '0'; +-- end if; +-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then +-- chip_dec(1) <= '1'; +-- else +-- chip_dec(1) <= '0'; +-- end if; +-- chip_dec(2) <= chip_dec(1) and chip_dec(0); +-- end if; +-- end process; + +--------------------------------------------------------------------------------- +---- This process defines the Sys output signal +--------------------------------------------------------------------------------- +-- SYS_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- if sys_edge = '1' or Lpf_reset = '1' then +-- sys <= '1'; +-- elsif sys_dec(2) = '1' then +-- sys <= '0'; +-- end if; +-- end if; +-- end process; +-- +--------------------------------------------------------------------------------- +---- This process decodes the sequence counter for Sys to use +--------------------------------------------------------------------------------- +-- SYS_DECODE_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or +-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then +-- sys_dec(0) <= '1'; +-- else +-- sys_dec(0) <= '0'; +-- end if; +-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or +-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then +-- sys_dec(1) <= '1'; +-- else +-- sys_dec(1) <= '0'; +-- end if; +-- sys_dec(2) <= sys_dec(1) and sys_dec(0); +-- end if; +-- end process; +-- +--------------------------------------------------------------------------------- +---- This process delays signals so the the edge can be detected and used +--------------------------------------------------------------------------------- +-- DELAY_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- chip_reset_req_d1 <= Chip_Reset_Req ; +-- chip_reset_req_d2 <= chip_Reset_Req_d1 ; +-- chip_reset_req_d3 <= chip_Reset_Req_d2 ; +-- system_reset_req_d1 <= System_Reset_Req; +-- system_reset_req_d2 <= system_Reset_Req_d1; +-- system_reset_req_d3 <= system_Reset_Req_d2; +-- end if; +-- end process; + +------------------------------------------------------------------------------- +-- This process creates a signal that goes high on the rising edge of either +-- Chip_Reset_Req or System_Reset_Req +------------------------------------------------------------------------------- +-- RIS_EDGE_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge +-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then +-- ris_edge <= '1'; +-- else +-- ris_edge <='0'; +-- end if; +-- end if; +-- end process; + +------------------------------------------------------------------------------- +-- This process creates a signal that goes high on the rising edge of +-- System_Reset_Req +------------------------------------------------------------------------------- +-- SYS_EDGE_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then +-- sys_edge <= '1'; +-- else +-- sys_edge <='0'; +-- end if; +-- end if; +-- end process; + + + +end architecture imp; + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/upcnt_n.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/upcnt_n.vhd new file mode 100644 index 0000000..4afed3c --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/upcnt_n.vhd @@ -0,0 +1,153 @@ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- upcnt_n - entity/architecture pair +------------------------------------------------------------------------------- +-- +-- ************************************************************************ +-- ** DISCLAIMER OF LIABILITY ** +-- ** ** +-- ** This file contains proprietary and confidential information of ** +-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** +-- ** from Xilinx, and may be used, copied and/or disclosed only ** +-- ** pursuant to the terms of a valid license agreement with Xilinx. ** +-- ** ** +-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** +-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** +-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** +-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** +-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** +-- ** does not warrant that functions included in the Materials will ** +-- ** meet the requirements of Licensee, or that the operation of the ** +-- ** Materials will be uninterrupted or error-free, or that defects ** +-- ** in the Materials will be corrected. Furthermore, Xilinx does ** +-- ** not warrant or make any representations regarding use, or the ** +-- ** results of the use, of the Materials in terms of correctness, ** +-- ** accuracy, reliability or otherwise. ** +-- ** ** +-- ** Xilinx products are not designed or intended to be fail-safe, ** +-- ** or for use in any application requiring fail-safe performance, ** +-- ** such as life-support or safety devices or systems, Class III ** +-- ** medical devices, nuclear facilities, applications related to ** +-- ** the deployment of airbags, or any other applications that could ** +-- ** lead to death, personal injury or severe property or ** +-- ** environmental damage (individually and collectively, "critical ** +-- ** applications"). Customer assumes the sole risk and liability ** +-- ** of any use of Xilinx products in critical applications, ** +-- ** subject only to applicable laws and regulations governing ** +-- ** limitations on product liability. ** +-- ** ** +-- ** Copyright 2010 Xilinx, Inc. ** +-- ** All rights reserved. ** +-- ** ** +-- ** This disclaimer and copyright notice must be retained as part ** +-- ** of this file at all times. ** +-- ************************************************************************ +-- +------------------------------------------------------------------------------- +-- Filename: upcnt_n.vhd +-- Version: v4.00a +-- Description: Parameterizeable top level processor reset module. +-- VHDL-Standard: VHDL'93 +------------------------------------------------------------------------------- +-- Structure: This section should show the hierarchical structure of the +-- designs.Separate lines with blank lines if necessary to improve +-- readability. +-- +-- proc_sys_reset.vhd +-- upcnt_n.vhd +-- lpf.vhd +-- sequence.vhd +------------------------------------------------------------------------------- +-- Author: Kurt Conover +-- History: +-- Kurt Conover 11/07/01 -- First Release +-- +-- ~~~~~~~ +-- SK 03/11/10 +-- ^^^^^^^ +-- 1. Updated the core so support the active low "Interconnect_aresetn" and +-- "Peripheral_aresetn" signals. +-- ^^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +------------------------------------------------------------------------------- +-- Port Declaration +------------------------------------------------------------------------------- +-- Definition of Generics: +-- C_SIZE -- Number of bits in counter +-- +-- +-- Definition of Ports: +-- Data -- parallel data input +-- Cnt_en -- count enable +-- Load -- Load Data +-- Clr -- reset +-- Clk -- Clock +-- Qout -- Count output +-- +------------------------------------------------------------------------------- +entity upcnt_n is + generic( + C_SIZE : Integer + ); + + port( + Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0); + Cnt_en : in STD_LOGIC; + Load : in STD_LOGIC; + Clr : in STD_LOGIC; + Clk : in STD_LOGIC; + Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) + ); + +end upcnt_n; + +architecture imp of upcnt_n is + +constant CLEAR : std_logic := '0'; + +signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1'); + +begin + process(Clk) + begin + + if (Clk'event) and Clk = '1' then + -- Clear output register + if (Clr = CLEAR) then + q_int <= (others => '0'); + -- Load in start value + elsif (Load = '1') then + q_int <= UNSIGNED(Data); + -- If count enable is high + elsif Cnt_en = '1' then + q_int <= q_int + 1; + end if; + end if; + end process; + + Qout <= STD_LOGIC_VECTOR(q_int); + +end imp; + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_afi_slave.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_afi_slave.v new file mode 100644 index 0000000..dcc7214 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_afi_slave.v @@ -0,0 +1,978 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_afi_slave.v + * + * Date : 2012-11 + * + * Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM + * from Cadence. + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_afi_slave ( + S_RESETN, + + S_ARREADY, + S_AWREADY, + S_BVALID, + S_RLAST, + S_RVALID, + S_WREADY, + S_BRESP, + S_RRESP, + S_RDATA, + S_BID, + S_RID, + S_ACLK, + S_ARVALID, + S_AWVALID, + S_BREADY, + S_RREADY, + S_WLAST, + S_WVALID, + S_ARBURST, + S_ARLOCK, + S_ARSIZE, + S_AWBURST, + S_AWLOCK, + S_AWSIZE, + S_ARPROT, + S_AWPROT, + S_ARADDR, + S_AWADDR, + S_WDATA, + S_ARCACHE, + S_ARLEN, + S_AWCACHE, + S_AWLEN, + S_WSTRB, + S_ARID, + S_AWID, + S_WID, + + S_AWQOS, + S_ARQOS, + + SW_CLK, + WR_DATA_ACK_OCM, + WR_DATA_ACK_DDR, + WR_ADDR, + WR_DATA, + WR_BYTES, + WR_DATA_VALID_OCM, + WR_DATA_VALID_DDR, + WR_QOS, + + RD_REQ_DDR, + RD_REQ_OCM, + RD_ADDR, + RD_DATA_OCM, + RD_DATA_DDR, + RD_BYTES, + RD_QOS, + RD_DATA_VALID_OCM, + RD_DATA_VALID_DDR, + S_RDISSUECAP1_EN, + S_WRISSUECAP1_EN, + S_RCOUNT, + S_WCOUNT, + S_RACOUNT, + S_WACOUNT + +); + parameter enable_this_port = 0; + parameter slave_name = "Slave"; + parameter data_bus_width = 32; + parameter address_bus_width = 32; + parameter id_bus_width = 6; + parameter slave_base_address = 0; + parameter slave_high_address = 4; + parameter max_outstanding_transactions = 8; + parameter exclusive_access_supported = 0; + + `include "processing_system7_bfm_v2_0_local_params.v" + + /* Local parameters only for this module */ + /* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles. + This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported. + 1-bit extra width than the no.of.bits needed to represent the outstanding transactions + Extra bit helps in generating the empty and full flags + */ + parameter int_cntr_width = clogb2(max_outstanding_transactions)+1; + + /* RESP data */ + parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; + parameter rsp_lsb = 0; + parameter rsp_msb = axi_rsp_width-1; + parameter rsp_id_lsb = rsp_msb + 1; + parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1; + + input S_RESETN; + + output S_ARREADY; + output S_AWREADY; + output S_BVALID; + output S_RLAST; + output S_RVALID; + output S_WREADY; + output [axi_rsp_width-1:0] S_BRESP; + output [axi_rsp_width-1:0] S_RRESP; + output [data_bus_width-1:0] S_RDATA; + output [id_bus_width-1:0] S_BID; + output [id_bus_width-1:0] S_RID; + input S_ACLK; + input S_ARVALID; + input S_AWVALID; + input S_BREADY; + input S_RREADY; + input S_WLAST; + input S_WVALID; + input [axi_brst_type_width-1:0] S_ARBURST; + input [axi_lock_width-1:0] S_ARLOCK; + input [axi_size_width-1:0] S_ARSIZE; + input [axi_brst_type_width-1:0] S_AWBURST; + input [axi_lock_width-1:0] S_AWLOCK; + input [axi_size_width-1:0] S_AWSIZE; + input [axi_prot_width-1:0] S_ARPROT; + input [axi_prot_width-1:0] S_AWPROT; + input [address_bus_width-1:0] S_ARADDR; + input [address_bus_width-1:0] S_AWADDR; + input [data_bus_width-1:0] S_WDATA; + input [axi_cache_width-1:0] S_ARCACHE; + input [axi_cache_width-1:0] S_ARLEN; + + input [axi_qos_width-1:0] S_ARQOS; + + input [axi_cache_width-1:0] S_AWCACHE; + input [axi_len_width-1:0] S_AWLEN; + + input [axi_qos_width-1:0] S_AWQOS; + input [(data_bus_width/8)-1:0] S_WSTRB; + input [id_bus_width-1:0] S_ARID; + input [id_bus_width-1:0] S_AWID; + input [id_bus_width-1:0] S_WID; + + input SW_CLK; + input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; + output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; + output [max_burst_bits-1:0] WR_DATA; + output [addr_width-1:0] WR_ADDR; + output [max_transfer_bytes_width:0] WR_BYTES; + output reg RD_REQ_OCM, RD_REQ_DDR; + output reg [addr_width-1:0] RD_ADDR; + input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM; + output reg[max_transfer_bytes_width:0] RD_BYTES; + input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR; + output [axi_qos_width-1:0] WR_QOS; + output reg [axi_qos_width-1:0] RD_QOS; + + input S_RDISSUECAP1_EN; + input S_WRISSUECAP1_EN; + + output [7:0] S_RCOUNT; + output [7:0] S_WCOUNT; + output [2:0] S_RACOUNT; + output [5:0] S_WACOUNT; + + wire net_ARVALID; + wire net_AWVALID; + wire net_WVALID; + + real s_aclk_period; + + cdn_axi3_slave_bfm #(slave_name, + data_bus_width, + address_bus_width, + id_bus_width, + slave_base_address, + (slave_high_address- slave_base_address), + max_outstanding_transactions, + 0, ///MEMORY_MODEL_MODE, + exclusive_access_supported) + slave (.ACLK (S_ACLK), + .ARESETn (S_RESETN), /// confirm this + // Write Address Channel + .AWID (S_AWID), + .AWADDR (S_AWADDR), + .AWLEN (S_AWLEN), + .AWSIZE (S_AWSIZE), + .AWBURST (S_AWBURST), + .AWLOCK (S_AWLOCK), + .AWCACHE (S_AWCACHE), + .AWPROT (S_AWPROT), + .AWVALID (net_AWVALID), + .AWREADY (S_AWREADY), + // Write Data Channel Signals. + .WID (S_WID), + .WDATA (S_WDATA), + .WSTRB (S_WSTRB), + .WLAST (S_WLAST), + .WVALID (net_WVALID), + .WREADY (S_WREADY), + // Write Response Channel Signals. + .BID (S_BID), + .BRESP (S_BRESP), + .BVALID (S_BVALID), + .BREADY (S_BREADY), + // Read Address Channel Signals. + .ARID (S_ARID), + .ARADDR (S_ARADDR), + .ARLEN (S_ARLEN), + .ARSIZE (S_ARSIZE), + .ARBURST (S_ARBURST), + .ARLOCK (S_ARLOCK), + .ARCACHE (S_ARCACHE), + .ARPROT (S_ARPROT), + .ARVALID (net_ARVALID), + .ARREADY (S_ARREADY), + // Read Data Channel Signals. + .RID (S_RID), + .RDATA (S_RDATA), + .RRESP (S_RRESP), + .RLAST (S_RLAST), + .RVALID (S_RVALID), + .RREADY (S_RREADY)); + + + wire wr_intr_fifo_full; + reg temp_wr_intr_fifo_full; + + /* Interconnect WR_FIFO model instance */ + processing_system7_bfm_v2_0_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR); + + /* Register the async 'full' signal to S_ACLK clock */ + always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full; + + /* Latency type and Debug/Error Control */ + reg[1:0] latency_type = RANDOM_CASE; + reg DEBUG_INFO = 1; + reg STOP_ON_ERROR = 1'b1; + + /* Internal nets/regs for calling slave BFM API's*/ + reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1]; + reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0; + wire wr_fifo_empty; + + /* Store the awvalid receive time --- necessary for calculating the bresp latency */ + reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0; + real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received + reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received + + /* Address Write Channel handshake*/ + reg[int_cntr_width-1:0] aw_cnt = 0;// + + /* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1]; + reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1]; + reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1]; + reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1]; + reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1]; + reg aw_flag [0:max_outstanding_transactions-1]; + reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1]; + reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1]; + reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1]; + wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached) + + /* internal fifos to store burst write data, ID & strobes*/ + reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1]; + reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer + reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received + wire wd_fifo_full; + + /* Write Data Channel and Write Response handshake signals*/ + reg [int_cntr_width-1:0] wd_cnt = 0; + reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data; + reg [addr_width-1:0] aligned_wr_addr; + reg [max_burst_bytes_width:0] valid_data_bytes; + reg [int_cntr_width-1:0] wr_bresp_cnt = 0; + reg [axi_rsp_width-1:0] bresp; + reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response + reg enable_write_bresp; + reg [int_cntr_width-1:0] rd_bresp_cnt = 0; + integer wr_latency_count; + reg wr_delayed; + wire bresp_fifo_empty; + + /* keep track of count values */ + reg[7:0] wcount; + reg[5:0] wacount; + + /* Qos*/ + reg [axi_qos_width-1:0] ar_qos, aw_qos; + + initial begin + if(DEBUG_INFO) begin + if(enable_this_port) + $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name); + else + $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name); + end + end + /*--------------------------------------------------------------------------------*/ + + /* Store the Clock cycle time period */ + + always@(S_RESETN) + begin + if(S_RESETN) begin + @(posedge S_ACLK); + s_aclk_period = $time; + @(posedge S_ACLK); + s_aclk_period = $time - s_aclk_period; + end + end + /*--------------------------------------------------------------------------------*/ + + initial slave.set_disable_reset_value_checks(1); + initial begin + repeat(2) @(posedge S_ACLK); + if(!enable_this_port) begin + slave.set_channel_level_info(0); + slave.set_function_level_info(0); + end + slave.RESPONSE_TIMEOUT = 0; + end + /*--------------------------------------------------------------------------------*/ + + /* Set Latency type to be used */ + task set_latency_type; + input[1:0] lat; + begin + if(enable_this_port) + latency_type = lat; + else begin + //if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + /* Set ARQoS to be used */ + task set_arqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) + ar_qos = qos; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set AWQoS to be used */ + task set_awqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) + aw_qos = qos; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* get the wr latency number */ + function [31:0] get_wr_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : get_wr_lat_number = afi_wr_min; + AVG_CASE : get_wr_lat_number = afi_wr_avg; + WORST_CASE : get_wr_lat_number = afi_wr_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min); + 2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg); + default : get_wr_lat_number = ($random()%60+ afi_wr_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* get the rd latency number */ + function [31:0] get_rd_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : get_rd_lat_number = afi_rd_min; + AVG_CASE : get_rd_lat_number = afi_rd_avg; + WORST_CASE : get_rd_lat_number = afi_rd_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min); + 2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg); + default : get_rd_lat_number = ($random()%60+ afi_rd_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + /* Check for any WRITE/READs when this port is disabled */ + always@(S_AWVALID or S_WVALID or S_ARVALID) + begin + if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name); + $stop; + end + end + + /*--------------------------------------------------------------------------------*/ + + assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0; + assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0; + assign net_WVALID = enable_this_port ? S_WVALID : 1'b0; + + assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0; + assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0; + assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0; + + assign S_WCOUNT = wcount; + assign S_WACOUNT = wacount; + + // FIFO_STATUS (only if AFI port) 1- full + function automatic wrfifo_full ; + input [axi_len_width:0] fifo_space_exp; + integer fifo_space_left; + begin + fifo_space_left = afi_fifo_locations - wcount; + if(fifo_space_left < fifo_space_exp) + wrfifo_full = 1; + else + wrfifo_full = 0; + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* Store the awvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID ) + begin + if(!S_RESETN) + aw_time_cnt = 0; + else begin + if(S_AWVALID) begin + awvalid_receive_time[aw_time_cnt] = $time; + awvalid_flag[aw_time_cnt] = 1'b1; + aw_time_cnt = aw_time_cnt + 1; + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_AWVALID && S_AWREADY) begin + if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos; + else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS; + end + end + + /* Address Write Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + aw_cnt = 0; + wacount = 0; + end else begin + if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin + slave.RECEIVE_WRITE_ADDRESS(0, + id_invalid, + awaddr[aw_cnt[int_cntr_width-2:0]], + awlen[aw_cnt[int_cntr_width-2:0]], + awsize[aw_cnt[int_cntr_width-2:0]], + awbrst[aw_cnt[int_cntr_width-2:0]], + awlock[aw_cnt[int_cntr_width-2:0]], + awcache[aw_cnt[int_cntr_width-2:0]], + awprot[aw_cnt[int_cntr_width-2:0]], + awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID. + aw_flag[aw_cnt[int_cntr_width-2:0]] = 1'b1; + aw_cnt = aw_cnt + 1; + wacount = wacount + 1; + end // if (!aw_fifo_full) + end /// if else + end /// always + /*--------------------------------------------------------------------------------*/ + + /* Write Data Channel Handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wd_cnt = 0; + end else begin + if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin + if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin + slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); + wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1; + wd_cnt = wd_cnt + 1; + end + end else begin + if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin + slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); + wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1; + wd_cnt = wd_cnt + 1; + end + end /// if + end /// else + end /// always + /*--------------------------------------------------------------------------------*/ + + /* Align the wrap data for write transaction */ + task automatic get_wrap_aligned_wr_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + output [addr_width-1:0] start_addr; /// aligned start address + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8)); + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data << 8; + temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8]; + wrp_data = wrp_data << 8; + wrp_bytes = wrp_bytes - 1; + end + wrp_bytes = addr - start_addr; + wrp_data = b_data << (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Calculate the Response for each read/write transaction */ + function [axi_rsp_width-1:0] calculate_resp; + input [addr_width-1:0] awaddr; + input [axi_prot_width-1:0] awprot; + reg [axi_rsp_width-1:0] rsp; + begin + rsp = AXI_OK; + /* Address Decode */ + if(decode_address(awaddr) === INVALID_MEM_TYPE) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr); + end + else if(decode_address(awaddr) === REG_MEM) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr); + end + if(secure_access_enabled && awprot[1]) + rsp = AXI_DEC_ERR; // decode error + calculate_resp = rsp; + end + endfunction + /*--------------------------------------------------------------------------------*/ + reg[max_burst_bits-1:0] temp_wr_data; + /* Store the Write response for each write transaction */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wr_fifo_wr_ptr = 0; + wcount = 0; + end else begin + enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]]; + /* calculate bresp only when AWVALID && WLAST is received */ + if(enable_write_bresp) begin + aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0; + wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0; + + bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]); + /* Fill AFI_WR_data FIFO */ + if(bresp === AXI_OK ) begin + if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data + get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address + end else begin + aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]]; + aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ; + end + valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]; + end else + valid_data_bytes = 0; + temp_wr_data = aligned_wr_data; + wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes}; + wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1; + wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1; + end + end // else + end // always + /*--------------------------------------------------------------------------------*/ + + /* Send Write Response Channel handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + rd_bresp_cnt = 0; + wr_latency_count = get_wr_lat_number(1); + wr_delayed = 0; + bresp_time_cnt = 0; + end else begin + wr_delayed = 1'b0; + if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count)) + wr_delayed = 1; + if(!bresp_fifo_empty && wr_delayed) begin + slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID + fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response + ); + wr_delayed = 0; + awvalid_flag[bresp_time_cnt] = 1'b0; + bresp_time_cnt = bresp_time_cnt+1; + rd_bresp_cnt = rd_bresp_cnt + 1; + wr_latency_count = get_wr_lat_number(1); + end + end // else + end//always + /*--------------------------------------------------------------------------------*/ + + /* Write Response Channel handshake */ + reg wr_int_state; + /* Reading from the wr_fifo and sending to Interconnect fifo*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wr_int_state = 1'b0; + wr_bresp_cnt = 0; + wr_fifo_rd_ptr = 0; + end else begin + case(wr_int_state) + 1'b0 : begin + wr_int_state = 1'b0; + if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin + wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes + wr_int_state = 1'b1; + /* start filling the write response fifo at the same time */ + fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp + wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length + wacount = wacount - 1; + wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1; + wr_bresp_cnt = wr_bresp_cnt+1; + end + end + 1'b1 : begin + wr_int_state = 0; + end + endcase + end + end + /*--------------------------------------------------------------------------------*/ +/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/ + +/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/ + +/* READ CHANNELS */ +/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */ + reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0; + real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received + reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received + reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info + +/* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1]; + reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1]; + reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1]; + reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1]; + reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1]; + reg ar_flag [0:max_outstanding_transactions-1]; + reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1]; + reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1]; + reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1]; + wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached) + + reg [int_cntr_width-1:0] wr_rresp_cnt = 0; + reg [axi_rsp_width-1:0] rresp; + reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response + reg enable_write_rresp; + + /* Send Read Response & Data Channel handshake */ + integer rd_latency_count; + reg rd_delayed; + + reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes + reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0; + wire read_fifo_full; + + reg [7:0] rcount; + reg [2:0] racount; + + wire rd_intr_fifo_full, rd_intr_fifo_empty; + wire read_fifo_empty; + + /* signals to communicate with interconnect RD_FIFO model */ + reg rd_req, invalid_rd_req; + + /* REad control Info + 56:25 : Address (32) + 24:22 : Size (3) + 21:20 : BRST (2) + 19:16 : LEN (4) + 15:10 : RID (6) + 9:8 : RRSP (2) + 7:0 : byte cnt (8) + */ + reg [rd_info_bits-1:0] read_control_info; + reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data; + reg temp_rd_intr_fifo_empty; + + processing_system7_bfm_v2_0_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR); + + assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0; + assign S_RCOUNT = rcount; + assign S_RACOUNT = racount; + + /* Register the asynch signal empty coming from Interconnect READ FIFO */ + always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty; + + // FIFO_STATUS (only if AFI port) 1- full + function automatic rdfifo_full ; + input [axi_len_width:0] fifo_space_exp; + integer fifo_space_left; + begin + fifo_space_left = afi_fifo_locations - rcount; + if(fifo_space_left < fifo_space_exp) + rdfifo_full = 1; + else + rdfifo_full = 0; + end + endfunction + + /* Store the arvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID ) + begin + if(!S_RESETN) + ar_time_cnt = 0; + else begin + if(S_ARVALID) begin + arvalid_receive_time[ar_time_cnt] = $time; + arvalid_flag[ar_time_cnt] = 1'b1; + ar_time_cnt = ar_time_cnt + 1; + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_ARVALID && S_ARREADY) begin + if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos; + else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS; + end + end + + /* Address Read Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + ar_cnt = 0; + racount = 0; + end else begin + if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full + slave.RECEIVE_READ_ADDRESS(0, + id_invalid, + araddr[ar_cnt[int_cntr_width-2:0]], + arlen[ar_cnt[int_cntr_width-2:0]], + arsize[ar_cnt[int_cntr_width-2:0]], + arbrst[ar_cnt[int_cntr_width-2:0]], + arlock[ar_cnt[int_cntr_width-2:0]], + arcache[ar_cnt[int_cntr_width-2:0]], + arprot[ar_cnt[int_cntr_width-2:0]], + arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID. + ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1; + ar_cnt = ar_cnt+1; + racount = racount + 1; + end /// if(!ar_fifo_full) + end /// if else + end /// always*/ + + /*--------------------------------------------------------------------------------*/ + + /* Align Wrap data for read transaction*/ + task automatic get_wrap_aligned_rd_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [addr_width-1:0] start_addr; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data >> 8; + temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0]; + wrp_data = wrp_data >> 8; + wrp_bytes = wrp_bytes - 1; + end + temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8)); + wrp_bytes = addr - start_addr; + wrp_data = b_data >> (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1; + reg rd_fifo_state; + reg [addr_width-1:0] temp_read_address; + reg [max_burst_bytes_width:0] temp_rd_valid_bytes; + /* get the data from memory && also calculate the rresp*/ + always@(negedge S_RESETN or posedge SW_CLK) + begin + if(!S_RESETN)begin + wr_rresp_cnt =0; + rd_fifo_state = RD_DATA_REQ; + temp_rd_valid_bytes = 0; + temp_read_address = 0; + RD_REQ_DDR = 1'b0; + RD_REQ_OCM = 1'b0; + rd_req = 0; + invalid_rd_req= 0; + RD_QOS = 0; + end else begin + case(rd_fifo_state) + RD_DATA_REQ : begin + rd_fifo_state = RD_DATA_REQ; + RD_REQ_DDR = 1'b0; + RD_REQ_OCM = 1'b0; + invalid_rd_req = 0; + if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition + ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0; + rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]); + temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8; + + if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin + temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes; + else + temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]]; + + if(rresp === AXI_OK) begin + case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]); + OCM_MEM : RD_REQ_OCM = 1; + DDR_MEM : RD_REQ_DDR = 1; + default : invalid_rd_req = 1; + endcase + end else + invalid_rd_req = 1; + RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]]; + RD_BYTES = temp_rd_valid_bytes; + RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]]; + rd_fifo_state = WAIT_RD_VALID; + rd_req = 1; + racount = racount - 1; + read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes }; + wr_rresp_cnt = wr_rresp_cnt + 1; + end + end + WAIT_RD_VALID : begin + rd_fifo_state = WAIT_RD_VALID; + rd_req = 0; + if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin + RD_REQ_DDR = 1'b0; + RD_REQ_OCM = 1'b0; + invalid_rd_req = 0; + rd_fifo_state = RD_DATA_REQ; + end + end + endcase + end /// else + end /// always + /*--------------------------------------------------------------------------------*/ + + /* thread to fill in the AFI RD_FIFO */ + reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes + reg tmp_state; + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN)begin + rd_fifo_wr_ptr = 0; + rcount = 0; + tmp_state = 0; + end else begin + case(tmp_state) + 0 : begin + tmp_state = 0; + if(!temp_rd_intr_fifo_empty) begin + rd_intr_fifo.read_mem(temp_rd_data); + tmp_state = 1; + end + end + 1 : begin + tmp_state = 1; + if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin + read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data; + rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1; + rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length + tmp_state = 0; + end + end + endcase + end + end + /*--------------------------------------------------------------------------------*/ + + reg[max_burst_bytes_width:0] rd_v_b; + reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes + reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data; + reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp; + + /* Read Data Channel handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN)begin + rd_fifo_rd_ptr = 0; + rd_latency_count = get_rd_lat_number(1); + rd_delayed = 0; + rresp_time_cnt = 0; + rd_v_b = 0; + end else begin + if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin + rd_delayed = 1; + end + if(!read_fifo_empty && rd_delayed)begin + rd_delayed = 0; + arvalid_flag[rresp_time_cnt] = 1'b0; + tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]]; + rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]); + temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb]; + if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin + get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b); + temp_read_data = aligned_rd_data; + end + temp_read_rsp = 0; + repeat(axi_burst_len) begin + temp_read_rsp = temp_read_rsp >> axi_rsp_width; + temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb]; + end + slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb], + tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], + tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb], + tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb], + tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb], + temp_read_data, + temp_read_rsp); + rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ; + rresp_time_cnt = rresp_time_cnt+1; + rd_latency_count = get_rd_lat_number(1); + rd_fifo_rd_ptr = rd_fifo_rd_ptr+1; + end + end /// else + end /// always +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_apis.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_apis.v new file mode 100644 index 0000000..a12c3b1 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_apis.v @@ -0,0 +1,825 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_apis.v + * + * Date : 2012-11 + * + * Description : Set of Zynq BFM APIs that are used for writing tests. + * + *****************************************************************************/ + + /* API for setting the STOP_ON_ERROR*/ + task automatic set_stop_on_error; + input LEVEL; + begin + $display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL); + STOP_ON_ERROR = LEVEL; + M_AXI_GP0.master.set_stop_on_error(LEVEL); + M_AXI_GP1.master.set_stop_on_error(LEVEL); + S_AXI_GP0.slave.set_stop_on_error(LEVEL); + S_AXI_GP1.slave.set_stop_on_error(LEVEL); + S_AXI_HP0.slave.set_stop_on_error(LEVEL); + S_AXI_HP1.slave.set_stop_on_error(LEVEL); + S_AXI_HP2.slave.set_stop_on_error(LEVEL); + S_AXI_HP3.slave.set_stop_on_error(LEVEL); + S_AXI_ACP.slave.set_stop_on_error(LEVEL); + M_AXI_GP0.STOP_ON_ERROR = LEVEL; + M_AXI_GP1.STOP_ON_ERROR = LEVEL; + S_AXI_GP0.STOP_ON_ERROR = LEVEL; + S_AXI_GP1.STOP_ON_ERROR = LEVEL; + S_AXI_HP0.STOP_ON_ERROR = LEVEL; + S_AXI_HP1.STOP_ON_ERROR = LEVEL; + S_AXI_HP2.STOP_ON_ERROR = LEVEL; + S_AXI_HP3.STOP_ON_ERROR = LEVEL; + S_AXI_ACP.STOP_ON_ERROR = LEVEL; + + end + endtask + + /* API for setting the verbosity for channel level info*/ + task automatic set_channel_level_info; + input [1023:0] name; + input LEVEL; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO, name , LEVEL); + case(name) + "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL); + "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL); + "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL); + "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL); + "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL); + "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL); + "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL); + "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL); + "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL); + "ALL" : begin + M_AXI_GP0.master.set_channel_level_info(LEVEL); + M_AXI_GP1.master.set_channel_level_info(LEVEL); + S_AXI_GP0.slave.set_channel_level_info(LEVEL); + S_AXI_GP1.slave.set_channel_level_info(LEVEL); + S_AXI_HP0.slave.set_channel_level_info(LEVEL); + S_AXI_HP1.slave.set_channel_level_info(LEVEL); + S_AXI_HP2.slave.set_channel_level_info(LEVEL); + S_AXI_HP3.slave.set_channel_level_info(LEVEL); + S_AXI_ACP.slave.set_channel_level_info(LEVEL); + end + default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for setting the verbosity for function level info*/ + task automatic set_function_level_info; + input [1023:0] name; + input LEVEL; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO, name , LEVEL); + case(name) + "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL); + "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL); + "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL); + "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL); + "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL); + "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL); + "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL); + "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL); + "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL); + "ALL" : begin + M_AXI_GP0.master.set_function_level_info(LEVEL); + M_AXI_GP1.master.set_function_level_info(LEVEL); + S_AXI_GP0.slave.set_function_level_info(LEVEL); + S_AXI_GP1.slave.set_function_level_info(LEVEL); + S_AXI_HP0.slave.set_function_level_info(LEVEL); + S_AXI_HP1.slave.set_function_level_info(LEVEL); + S_AXI_HP2.slave.set_function_level_info(LEVEL); + S_AXI_HP3.slave.set_function_level_info(LEVEL); + S_AXI_ACP.slave.set_function_level_info(LEVEL); + end + default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for setting the Message verbosity */ + task automatic set_debug_level_info; + input LEVEL; + begin + $display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO, LEVEL); + DEBUG_INFO = LEVEL; + M_AXI_GP0.DEBUG_INFO = LEVEL; + M_AXI_GP1.DEBUG_INFO = LEVEL; + S_AXI_GP0.DEBUG_INFO = LEVEL; + S_AXI_GP1.DEBUG_INFO = LEVEL; + S_AXI_HP0.DEBUG_INFO = LEVEL; + S_AXI_HP1.DEBUG_INFO = LEVEL; + S_AXI_HP2.DEBUG_INFO = LEVEL; + S_AXI_HP3.DEBUG_INFO = LEVEL; + S_AXI_ACP.DEBUG_INFO = LEVEL; + end + endtask + + /* API for setting ARQos Values */ + task automatic set_arqos; + input [1023:0] name; + input [axi_qos_width-1:0] value; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO, name , value); + case(name) + "S_AXI_GP0" : S_AXI_GP0.set_arqos(value); + "S_AXI_GP1" : S_AXI_GP1.set_arqos(value); + "S_AXI_HP0" : S_AXI_HP0.set_arqos(value); + "S_AXI_HP1" : S_AXI_HP1.set_arqos(value); + "S_AXI_HP2" : S_AXI_HP2.set_arqos(value); + "S_AXI_HP3" : S_AXI_HP3.set_arqos(value); + "S_AXI_ACP" : S_AXI_ACP.set_arqos(value); + default : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for setting AWQos Values */ + task automatic set_awqos; + input [1023:0] name; + input [axi_qos_width-1:0] value; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO, name , value); + case(name) + "S_AXI_GP0" : S_AXI_GP0.set_awqos(value); + "S_AXI_GP1" : S_AXI_GP1.set_awqos(value); + "S_AXI_HP0" : S_AXI_HP0.set_awqos(value); + "S_AXI_HP1" : S_AXI_HP1.set_awqos(value); + "S_AXI_HP2" : S_AXI_HP2.set_awqos(value); + "S_AXI_HP3" : S_AXI_HP3.set_awqos(value); + "S_AXI_ACP" : S_AXI_ACP.set_awqos(value); + default : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for soft reset control */ + task automatic fpga_soft_reset; + input[data_width-1:0] reset_ctrl; + begin + if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO, reset_ctrl); + gen_rst.fpga_soft_reset(reset_ctrl); + end + endtask + + /* API for pre-loading memories from (DDR/OCM model) */ + task automatic pre_load_mem_from_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] no_of_bytes; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + succ = $fopen(file_name,"r"); + if(succ == 0) begin + $display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name); + if(STOP_ON_ERROR) $stop; + end + else if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); + else + ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + DDR_MEM : begin + ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* API for pre-loading memories (DDR/OCM) */ + task automatic pre_load_mem; + input [1:0] data_type; + input [addr_width-1:0] start_addr; + input [int_width-1:0] no_of_bytes; + reg [1:0] mem_type; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes); + else + ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes); + end + DDR_MEM : begin + ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + end + endtask + + /* API for backdoor write to memories (DDR/OCM) */ + task automatic write_mem; + input [max_burst_bits-1 :0] data; + input [addr_width-1:0] start_addr; + input [max_burst_bytes_width:0] no_of_bytes; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.write_mem(data,start_addr,no_of_bytes); + else + ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO, start_addr, no_of_bytes); + end + DDR_MEM : begin + ddrc.ddr.write_mem(data,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* read_memory */ + task automatic read_mem; + input [addr_width-1:0] start_addr; + input [max_burst_bytes_width :0] no_of_bytes; + output[max_burst_bits-1 :0] data; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.read_mem(data,start_addr,no_of_bytes); + else + ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO, start_addr, no_of_bytes); + end + DDR_MEM : begin + ddrc.ddr.read_mem(data,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* API for backdoor read to memories (DDR/OCM) */ + task automatic peek_mem_to_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] no_of_bytes; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes); + else + ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + DDR_MEM : begin + ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* API to read interrupt status */ + task automatic read_interrupt; + output[irq_width-1:0] irq_status; + begin + irq_status = IRQ_F2P; + if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO, irq_status); + end + endtask + + /* API to wait on interrup */ + task automatic wait_interrupt; + input [3:0] irq; + output[irq_width-1:0] irq_status; + begin + if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO, irq); + + case(irq) + 0 : wait(IRQ_F2P[0] === 1'b1); + 1 : wait(IRQ_F2P[1] === 1'b1); + 2 : wait(IRQ_F2P[2] === 1'b1); + 3 : wait(IRQ_F2P[3] === 1'b1); + 4 : wait(IRQ_F2P[4] === 1'b1); + 5 : wait(IRQ_F2P[5] === 1'b1); + 6 : wait(IRQ_F2P[6] === 1'b1); + 7 : wait(IRQ_F2P[7] === 1'b1); + 8 : wait(IRQ_F2P[8] === 1'b1); + 8 : wait(IRQ_F2P[9] === 1'b1); + 10: wait(IRQ_F2P[10] === 1'b1); + 11: wait(IRQ_F2P[11] === 1'b1); + 12: wait(IRQ_F2P[12] === 1'b1); + 13: wait(IRQ_F2P[13] === 1'b1); + 14: wait(IRQ_F2P[14] === 1'b1); + 15: wait(IRQ_F2P[15] === 1'b1); + default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR); + endcase + if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO, irq); + irq_status = IRQ_F2P; + end + endtask + + /* API to wait for a certain match pattern*/ + task automatic wait_mem_update; + input[addr_width-1:0] address; + input[data_width-1:0] data_in; + output[data_width-1:0] data_out; + reg[data_width-1:0] datao; + begin + if(mem_update_key) begin + mem_update_key = 0; + if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in); + if(check_addr_aligned(address)) begin + ddrc.ddr.wait_mem_update(address, datao); + if(datao != data_in)begin + $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao); + $stop; + end else + $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO, address, data_in); + data_out = datao; + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR, address); + if(STOP_ON_ERROR) $stop; + end + mem_update_key = 1; + end else + $display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); + end + endtask + + + /* API to initiate a WRITE transaction on one of the AXI-Master ports*/ + task automatic write_from_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] wr_size; + output [axi_rsp_width-1:0] response; + integer succ; + begin + succ = $fopen(file_name,"r"); + if(succ == 0) begin + $display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name); + if(STOP_ON_ERROR) $stop; + end + else if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(check_addr_aligned(start_addr)) begin + $fclose(succ); + case(start_addr[31:30]) + GP_M0 : begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name); + M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + end + GP_M1 : begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name); + M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + end + default : begin + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr); + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + end + endtask + + /* API to initiate a READ transaction on one of the AXI-Master ports*/ + task automatic read_to_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] rd_size; + output [axi_rsp_width-1:0] response; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR , start_addr); + if(STOP_ON_ERROR) $stop; + end else if(check_addr_aligned(start_addr)) begin + case(start_addr[31:30]) + GP_M0 : begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name); + M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + end + GP_M1 : begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name); + M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + end + default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr); + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + end + endtask + + /* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/ + task automatic write_data; + input [addr_width-1:0] start_addr; + input [max_transfer_bytes_width:0] wr_size; + input [(max_transfer_bytes*8)-1:0] w_data; + output [axi_rsp_width-1:0] response; + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(wr_size > max_transfer_bytes) begin + $display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size); + M_AXI_GP0.write_data(start_addr,wr_size,w_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size); + M_AXI_GP1.write_data(start_addr,wr_size,w_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); + end + endtask + + /* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/ + task automatic read_data; + input [addr_width-1:0] start_addr; + input [max_transfer_bytes_width:0] rd_size; + output[(max_transfer_bytes*8)-1:0] rd_data; + output [axi_rsp_width-1:0] response; + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(rd_size > max_transfer_bytes) begin + $display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size); + M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size); + M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr); + end + endtask + +/* Hooks to call to BFM APIs */ + task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr); + end + endtask + + task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + reg[511:0] rsp; /// string for response + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr); + end + endtask + + task automatic read_burst; + input [addr_width-1:0] start_addr; + input [axi_len_width-1:0] len; + input [axi_size_width-1:0] siz; + input [axi_brst_type_width-1:0] burst; + input [axi_lock_width-1:0] lck; + input [axi_cache_width-1:0] cache; + input [axi_prot_width-1:0] prot; + output [(axi_mgp_data_width*axi_burst_len)-1:0] data; + output [(axi_rsp_width*axi_burst_len)-1:0] response; + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr); + M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr); + M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr); + end + endtask + + task automatic wait_reg_update; + input [addr_width-1:0] addr; + input [data_width-1:0] data_i; + input [data_width-1:0] mask_i; + input [int_width-1:0] time_interval; + input [int_width-1:0] time_out; + output [data_width-1:0] data_o; + + reg upd_done0; + reg upd_done1; + begin + if(!check_master_address(addr)) begin + $display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR, addr); + if(STOP_ON_ERROR) $stop; + end else if(addr[31:30] === GP_M0) begin + if(reg_update_key_0) begin + reg_update_key_0 = 0; + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); + M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0); + if(DEBUG_INFO && upd_done0) + $display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr); + reg_update_key_0 = 1; + end else + $display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); + end else if(addr[31:30] === GP_M1) begin + if(reg_update_key_1) begin + reg_update_key_1 = 0; + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); + M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1); + if(DEBUG_INFO && upd_done1) + $display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr); + reg_update_key_1 = 1; + end else + $display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr); + end + endtask + +/* API to read register map */ + task read_register_map; + input [addr_width-1:0] start_addr; + input [max_regs_width:0] no_of_registers; + output[max_burst_bits-1 :0] data; + reg [max_regs_width:0] no_of_regs; + begin + no_of_regs = no_of_registers; + if(no_of_registers > 32) begin + $display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr); + no_of_regs = 32; + end + if(check_addr_aligned(start_addr)) begin + if(decode_address(start_addr) == REG_MEM) begin + if(DEBUG_INFO) $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO, start_addr,no_of_regs ); + regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes + if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, start_addr, data ); + end else begin + $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr); + end + end else begin + data = 0; + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr); + end + end + endtask + +/* API to read single register */ + task read_register; + input [addr_width-1:0] addr; + output[data_width-1:0] data; + begin + if(check_addr_aligned(addr)) begin + if(decode_address(addr) == REG_MEM) begin + if(DEBUG_INFO) $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO, addr ); + regc.regm.get_data(addr >> 2, data); + if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, addr, data ); + end else begin + $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr); + end + end else begin + data = 0; + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr); + end + + end + endtask + + /* API to set the AXI-Slave profile*/ + task automatic set_slave_profile; + input[1023:0] name; + input[1:0] latency ; + begin + if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO, name); + case(name) + "S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency); + "S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency); + "S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency); + "S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency); + "S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency); + "S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency); + "S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency); + "ALL" : begin + S_AXI_GP0.set_latency_type(latency); + S_AXI_GP1.set_latency_type(latency); + S_AXI_HP0.set_latency_type(latency); + S_AXI_HP1.set_latency_type(latency); + S_AXI_HP2.set_latency_type(latency); + S_AXI_HP3.set_latency_type(latency); + S_AXI_ACP.set_latency_type(latency); + end + endcase + end + endtask + + +/*------------------------------ LOCAL APIs ------------------------------------------------ */ + + /* local API for address decoding*/ + function automatic [1:0] decode_address; + input [addr_width-1:0] address; + begin + if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr )) + decode_address = OCM_MEM; /// OCM + else if(address >= ddr_start_addr && address <= ddr_end_addr) + decode_address = DDR_MEM; /// DDR + else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr) + decode_address = OCM_MEM; /// OCM + else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr) + decode_address = REG_MEM; /// Register Map + else + decode_address = INVALID_MEM_TYPE; /// ERROR in Address + end + endfunction + + /* local API for checking address is 32-bit (4-byte) aligned */ + function automatic check_addr_aligned; + input [addr_width-1:0] address; + begin + if((address%4) !=0 ) begin // + check_addr_aligned = 0; ///not_aligned + end else + check_addr_aligned = 1; + end + endfunction + + /* local API to check address for GP Masters */ + function check_master_address; + input [addr_width-1:0] address; + begin + if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr) + check_master_address = 1'b1; + else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr) + check_master_address = 1'b1; + else + check_master_address = 1'b0; /// ERROR in Address + end + endfunction + + /* Response decode */ + function automatic [511:0] get_resp; + input[axi_rsp_width-1:0] response; + begin + case(response) + 2'b00 : get_resp = "OKAY"; + 2'b01 : get_resp = "EXOKAY"; + 2'b10 : get_resp = "SLVERR"; + 2'b11 : get_resp = "DECERR"; + endcase + end + endfunction diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v new file mode 100644 index 0000000..c5577b7 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v @@ -0,0 +1,151 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_arb_hp0_1.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between RD/WR requests from 2 ports. + * Used for modelling the Top_Interconnect switch. + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_arb_hp0_1( + sw_clk, + rstn, + w_qos_hp0, + r_qos_hp0, + w_qos_hp1, + r_qos_hp1, + + wr_ack_ddr_hp0, + wr_data_hp0, + wr_addr_hp0, + wr_bytes_hp0, + wr_dv_ddr_hp0, + rd_req_ddr_hp0, + rd_addr_hp0, + rd_bytes_hp0, + rd_data_ddr_hp0, + rd_dv_ddr_hp0, + + wr_ack_ddr_hp1, + wr_data_hp1, + wr_addr_hp1, + wr_bytes_hp1, + wr_dv_ddr_hp1, + rd_req_ddr_hp1, + rd_addr_hp1, + rd_bytes_hp1, + rd_data_ddr_hp1, + rd_dv_ddr_hp1, + + ddr_wr_ack, + ddr_wr_dv, + ddr_rd_req, + ddr_rd_dv, + ddr_rd_qos, + ddr_wr_qos, + + ddr_wr_addr, + ddr_wr_data, + ddr_wr_bytes, + ddr_rd_addr, + ddr_rd_data, + ddr_rd_bytes + +); +`include "processing_system7_bfm_v2_0_local_params.v" +input sw_clk; +input rstn; +input [axi_qos_width-1:0] w_qos_hp0; +input [axi_qos_width-1:0] r_qos_hp0; +input [axi_qos_width-1:0] w_qos_hp1; +input [axi_qos_width-1:0] r_qos_hp1; +input [axi_qos_width-1:0] ddr_rd_qos; +input [axi_qos_width-1:0] ddr_wr_qos; + +output wr_ack_ddr_hp0; +input [max_burst_bits-1:0] wr_data_hp0; +input [addr_width-1:0] wr_addr_hp0; +input [max_burst_bytes_width:0] wr_bytes_hp0; +output wr_dv_ddr_hp0; + +input rd_req_ddr_hp0; +input [addr_width-1:0] rd_addr_hp0; +input [max_burst_bytes_width:0] rd_bytes_hp0; +output [max_burst_bits-1:0] rd_data_ddr_hp0; +output rd_dv_ddr_hp0; + +output wr_ack_ddr_hp1; +input [max_burst_bits-1:0] wr_data_hp1; +input [addr_width-1:0] wr_addr_hp1; +input [max_burst_bytes_width:0] wr_bytes_hp1; +output wr_dv_ddr_hp1; + +input rd_req_ddr_hp1; +input [addr_width-1:0] rd_addr_hp1; +input [max_burst_bytes_width:0] rd_bytes_hp1; +output [max_burst_bits-1:0] rd_data_ddr_hp1; +output rd_dv_ddr_hp1; + +input ddr_wr_ack; +output ddr_wr_dv; +output [addr_width-1:0]ddr_wr_addr; +output [max_burst_bits-1:0]ddr_wr_data; +output [max_burst_bytes_width:0]ddr_wr_bytes; + +input ddr_rd_dv; +input [max_burst_bits-1:0] ddr_rd_data; +output ddr_rd_req; +output [addr_width-1:0] ddr_rd_addr; +output [max_burst_bytes_width:0] ddr_rd_bytes; + + + + +processing_system7_bfm_v2_0_arb_wr ddr_hp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_hp0), + .qos2(w_qos_hp1), + .prt_dv1(wr_dv_ddr_hp0), + .prt_dv2(wr_dv_ddr_hp1), + .prt_data1(wr_data_hp0), + .prt_data2(wr_data_hp1), + .prt_addr1(wr_addr_hp0), + .prt_addr2(wr_addr_hp1), + .prt_bytes1(wr_bytes_hp0), + .prt_bytes2(wr_bytes_hp1), + .prt_ack1(wr_ack_ddr_hp0), + .prt_ack2(wr_ack_ddr_hp1), + .prt_req(ddr_wr_dv), + .prt_qos(ddr_wr_qos), + .prt_data(ddr_wr_data), + .prt_addr(ddr_wr_addr), + .prt_bytes(ddr_wr_bytes), + .prt_ack(ddr_wr_ack) +); + +processing_system7_bfm_v2_0_arb_rd ddr_hp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_hp0), + .qos2(r_qos_hp1), + .prt_req1(rd_req_ddr_hp0), + .prt_req2(rd_req_ddr_hp1), + .prt_data1(rd_data_ddr_hp0), + .prt_data2(rd_data_ddr_hp1), + .prt_addr1(rd_addr_hp0), + .prt_addr2(rd_addr_hp1), + .prt_bytes1(rd_bytes_hp0), + .prt_bytes2(rd_bytes_hp1), + .prt_dv1(rd_dv_ddr_hp0), + .prt_dv2(rd_dv_ddr_hp1), + .prt_qos(ddr_rd_qos), + .prt_req(ddr_rd_req), + .prt_data(ddr_rd_data), + .prt_addr(ddr_rd_addr), + .prt_bytes(ddr_rd_bytes), + .prt_dv(ddr_rd_dv) +); + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v new file mode 100644 index 0000000..809d558 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v @@ -0,0 +1,151 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_arb_hp2_3.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between RD/WR requests from 2 ports. + * Used for modelling the Top_Interconnect switch. + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_arb_hp2_3( + sw_clk, + rstn, + w_qos_hp2, + r_qos_hp2, + w_qos_hp3, + r_qos_hp3, + + wr_ack_ddr_hp2, + wr_data_hp2, + wr_addr_hp2, + wr_bytes_hp2, + wr_dv_ddr_hp2, + rd_req_ddr_hp2, + rd_addr_hp2, + rd_bytes_hp2, + rd_data_ddr_hp2, + rd_dv_ddr_hp2, + + wr_ack_ddr_hp3, + wr_data_hp3, + wr_addr_hp3, + wr_bytes_hp3, + wr_dv_ddr_hp3, + rd_req_ddr_hp3, + rd_addr_hp3, + rd_bytes_hp3, + rd_data_ddr_hp3, + rd_dv_ddr_hp3, + + ddr_wr_ack, + ddr_wr_dv, + ddr_rd_req, + ddr_rd_dv, + ddr_rd_qos, + ddr_wr_qos, + + ddr_wr_addr, + ddr_wr_data, + ddr_wr_bytes, + ddr_rd_addr, + ddr_rd_data, + ddr_rd_bytes + +); +`include "processing_system7_bfm_v2_0_local_params.v" +input sw_clk; +input rstn; +input [axi_qos_width-1:0] w_qos_hp2; +input [axi_qos_width-1:0] r_qos_hp2; +input [axi_qos_width-1:0] w_qos_hp3; +input [axi_qos_width-1:0] r_qos_hp3; +input [axi_qos_width-1:0] ddr_rd_qos; +input [axi_qos_width-1:0] ddr_wr_qos; + +output wr_ack_ddr_hp2; +input [max_burst_bits-1:0] wr_data_hp2; +input [addr_width-1:0] wr_addr_hp2; +input [max_burst_bytes_width:0] wr_bytes_hp2; +output wr_dv_ddr_hp2; + +input rd_req_ddr_hp2; +input [addr_width-1:0] rd_addr_hp2; +input [max_burst_bytes_width:0] rd_bytes_hp2; +output [max_burst_bits-1:0] rd_data_ddr_hp2; +output rd_dv_ddr_hp2; + +output wr_ack_ddr_hp3; +input [max_burst_bits-1:0] wr_data_hp3; +input [addr_width-1:0] wr_addr_hp3; +input [max_burst_bytes_width:0] wr_bytes_hp3; +output wr_dv_ddr_hp3; + +input rd_req_ddr_hp3; +input [addr_width-1:0] rd_addr_hp3; +input [max_burst_bytes_width:0] rd_bytes_hp3; +output [max_burst_bits-1:0] rd_data_ddr_hp3; +output rd_dv_ddr_hp3; + +input ddr_wr_ack; +output ddr_wr_dv; +output [addr_width-1:0]ddr_wr_addr; +output [max_burst_bits-1:0]ddr_wr_data; +output [max_burst_bytes_width:0]ddr_wr_bytes; + +input ddr_rd_dv; +input [max_burst_bits-1:0] ddr_rd_data; +output ddr_rd_req; +output [addr_width-1:0] ddr_rd_addr; +output [max_burst_bytes_width:0] ddr_rd_bytes; + + + + +processing_system7_bfm_v2_0_arb_wr ddr_hp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_hp2), + .qos2(w_qos_hp3), + .prt_dv1(wr_dv_ddr_hp2), + .prt_dv2(wr_dv_ddr_hp3), + .prt_data1(wr_data_hp2), + .prt_data2(wr_data_hp3), + .prt_addr1(wr_addr_hp2), + .prt_addr2(wr_addr_hp3), + .prt_bytes1(wr_bytes_hp2), + .prt_bytes2(wr_bytes_hp3), + .prt_ack1(wr_ack_ddr_hp2), + .prt_ack2(wr_ack_ddr_hp3), + .prt_req(ddr_wr_dv), + .prt_qos(ddr_wr_qos), + .prt_data(ddr_wr_data), + .prt_addr(ddr_wr_addr), + .prt_bytes(ddr_wr_bytes), + .prt_ack(ddr_wr_ack) +); + +processing_system7_bfm_v2_0_arb_rd ddr_hp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_hp2), + .qos2(r_qos_hp3), + .prt_req1(rd_req_ddr_hp2), + .prt_req2(rd_req_ddr_hp3), + .prt_data1(rd_data_ddr_hp2), + .prt_data2(rd_data_ddr_hp3), + .prt_addr1(rd_addr_hp2), + .prt_addr2(rd_addr_hp3), + .prt_bytes1(rd_bytes_hp2), + .prt_bytes2(rd_bytes_hp3), + .prt_dv1(rd_dv_ddr_hp2), + .prt_dv2(rd_dv_ddr_hp3), + .prt_req(ddr_rd_req), + .prt_qos(ddr_rd_qos), + .prt_data(ddr_rd_data), + .prt_addr(ddr_rd_addr), + .prt_bytes(ddr_rd_bytes), + .prt_dv(ddr_rd_dv) +); + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_rd.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_rd.v new file mode 100644 index 0000000..7c791e5 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_rd.v @@ -0,0 +1,154 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_arb_rd.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 2 read requests from 2 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_arb_rd( + rstn, + sw_clk, + + qos1, + qos2, + + prt_req1, + prt_req2, + prt_bytes1, + prt_bytes2, + prt_addr1, + prt_addr2, + prt_data1, + prt_data2, + prt_dv1, + prt_dv2, + + prt_req, + prt_qos, + prt_addr, + prt_bytes, + prt_data, + prt_dv + +); +`include "processing_system7_bfm_v2_0_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2; +input prt_req1, prt_req2; +input [addr_width-1:0] prt_addr1, prt_addr2; +input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2; +output reg prt_dv1, prt_dv2; +output reg [max_burst_bits-1:0] prt_data1,prt_data2; + +output reg prt_req; +output reg [axi_qos_width-1:0] prt_qos; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +input [max_burst_bits-1:0] prt_data; +input prt_dv; + +parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11; +reg [1:0] state; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_req = 0; + if(prt_req1 && !prt_req2) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(!prt_req1 && prt_req2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req1 && prt_req2) begin + if(qos1 > qos2) begin + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else if(qos1 < qos2) begin + prt_req = 1; + prt_addr = prt_addr2; + prt_qos = qos2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req1:begin + state = serv_req1; + prt_dv2 = 1'b0; + if(prt_dv) begin + prt_dv1 = 1'b1; + prt_data1 = prt_data; + prt_req = 0; + if(prt_req2) begin + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + state = wait_dv_low; + //state = wait_req; + end + end + end + serv_req2:begin + state = serv_req2; + prt_dv1 = 1'b0; + if(prt_dv) begin + prt_dv2 = 1'b1; + prt_data2 = prt_data; + prt_req = 0; + if(prt_req1) begin + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else begin + state = wait_dv_low; + //state = wait_req; + end + end + end + + wait_dv_low:begin + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + state = wait_dv_low; + if(!prt_dv) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_rd_4.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_rd_4.v new file mode 100644 index 0000000..0f44158 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_rd_4.v @@ -0,0 +1,254 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_arb_rd_4.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 4 read requests from 4 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_arb_rd_4( + rstn, + sw_clk, + + qos1, + qos2, + qos3, + qos4, + + prt_req1, + prt_req2, + prt_req3, + prt_req4, + + prt_data1, + prt_data2, + prt_data3, + prt_data4, + + prt_addr1, + prt_addr2, + prt_addr3, + prt_addr4, + + prt_bytes1, + prt_bytes2, + prt_bytes3, + prt_bytes4, + + prt_dv1, + prt_dv2, + prt_dv3, + prt_dv4, + + prt_qos, + prt_req, + prt_data, + prt_addr, + prt_bytes, + prt_dv + +); +`include "processing_system7_bfm_v2_0_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2,qos3,qos4; +input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv; +output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4; +input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4; +input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4; +output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req; +input [max_burst_bits-1:0] prt_data; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +output reg [axi_qos_width-1:0] prt_qos; + +parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101; +reg [2:0] state; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + prt_req = 1'b0; + if(prt_req1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_req2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_req4) begin + prt_req = 1; + prt_addr = prt_addr4; + prt_qos = qos4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + serv_req1:begin + state = serv_req1; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + if(prt_dv)begin + prt_dv1 = 1'b1; + prt_data1 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req2) begin + state = serv_req2; + prt_qos = qos2; + prt_req = 1; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req3) begin + state = serv_req3; + prt_qos = qos3; + prt_req = 1; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_req4) begin + prt_req = 1; + prt_qos = qos4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + end + serv_req2:begin + state = serv_req2; + prt_dv1 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + if(prt_dv)begin + prt_dv2 = 1'b1; + prt_data2 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_req4) begin + state = serv_req4; + prt_req = 1; + prt_qos = qos4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_req1) begin + prt_req = 1; + prt_addr = prt_addr1; + prt_qos = qos1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req3:begin + state = serv_req3; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv4 = 1'b0; + if(prt_dv)begin + prt_dv3 = 1'b1; + prt_data3 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req4) begin + state = serv_req4; + prt_qos = qos4; + prt_req = 1; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_req1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_req2) begin + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end + end + end + serv_req4:begin + state = serv_req4; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + if(prt_dv)begin + prt_dv4 = 1'b1; + prt_data4 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req1) begin + state = serv_req1; + prt_qos = qos1; + prt_req = 1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_req2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req3) begin + prt_req = 1; + prt_addr = prt_addr3; + prt_qos = qos3; + prt_bytes = prt_bytes3; + state = serv_req3; + end + end + end + wait_dv_low:begin + state = wait_dv_low; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + if(!prt_dv) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_wr.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_wr.v new file mode 100644 index 0000000..6af1e2b --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_wr.v @@ -0,0 +1,152 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_arb_wr.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 2 write requests from 2 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_arb_wr( + rstn, + sw_clk, + qos1, + qos2, + prt_dv1, + prt_dv2, + prt_data1, + prt_data2, + prt_addr1, + prt_addr2, + prt_bytes1, + prt_bytes2, + prt_ack1, + prt_ack2, + prt_qos, + prt_req, + prt_data, + prt_addr, + prt_bytes, + prt_ack + +); +`include "processing_system7_bfm_v2_0_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2; +input [max_burst_bits-1:0] prt_data1,prt_data2; +input [addr_width-1:0] prt_addr1,prt_addr2; +input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2; +input prt_dv1, prt_dv2, prt_ack; +output reg prt_ack1,prt_ack2,prt_req; +output reg [max_burst_bits-1:0] prt_data; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +output reg [axi_qos_width-1:0] prt_qos; + +parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11; +reg [1:0] state,temp_state; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_req = 1'b0; + if(prt_dv1 && !prt_dv2) begin + state = serv_req1; + prt_req = 1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + prt_qos = qos1; + end else if(!prt_dv1 && prt_dv2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv1 && prt_dv2) begin + if(qos1 > qos2) begin + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else if(qos1 < qos2) begin + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req1:begin + state = serv_req1; + prt_ack2 = 1'b0; + if(prt_ack) begin + prt_ack1 = 1'b1; + prt_req = 0; + if(prt_dv2) begin + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + // state = wait_req; + state = wait_ack_low; + end + end + end + serv_req2:begin + state = serv_req2; + prt_ack1 = 1'b0; + if(prt_ack) begin + prt_ack2 = 1'b1; + prt_req = 0; + if(prt_dv1) begin + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else begin + state = wait_ack_low; + // state = wait_req; + end + end + end + wait_ack_low:begin + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + state = wait_ack_low; + if(!prt_ack) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_wr_4.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_wr_4.v new file mode 100644 index 0000000..4409478 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_wr_4.v @@ -0,0 +1,265 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_arb_wr_4.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 4 write requests from 4 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_arb_wr_4( + rstn, + sw_clk, + + qos1, + qos2, + qos3, + qos4, + + prt_dv1, + prt_dv2, + prt_dv3, + prt_dv4, + + prt_data1, + prt_data2, + prt_data3, + prt_data4, + + prt_addr1, + prt_addr2, + prt_addr3, + prt_addr4, + + prt_bytes1, + prt_bytes2, + prt_bytes3, + prt_bytes4, + + prt_ack1, + prt_ack2, + prt_ack3, + prt_ack4, + + prt_qos, + prt_req, + prt_data, + prt_addr, + prt_bytes, + prt_ack + +); +`include "processing_system7_bfm_v2_0_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2,qos3,qos4; +input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4; +input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4; +input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4; +input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack; +output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req; +output reg [max_burst_bits-1:0] prt_data; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +output reg [axi_qos_width-1:0] prt_qos; +parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101; +reg [2:0] state; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + prt_req = 0; + if(prt_dv1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_dv2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + prt_data = prt_data3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_dv4) begin + prt_req = 1; + prt_qos = qos4; + prt_data = prt_data4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + serv_req1:begin + state = serv_req1; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + if(prt_ack)begin + prt_ack1 = 1'b1; + //state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv2) begin + state = serv_req2; + prt_qos = qos2; + prt_req = 1; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + prt_data = prt_data3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_dv4) begin + prt_req = 1; + prt_qos = qos4; + prt_data = prt_data4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + end + serv_req2:begin + state = serv_req2; + prt_ack1 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + if(prt_ack)begin + prt_ack2 = 1'b1; + //state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv3) begin + state = serv_req3; + prt_qos = qos3; + prt_req = 1; + prt_data = prt_data3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_dv4) begin + state = serv_req4; + prt_req = 1; + prt_qos = qos4; + prt_data = prt_data4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_dv1) begin + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req3:begin + state = serv_req3; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack4 = 1'b0; + if(prt_ack)begin + prt_ack3 = 1'b1; +// state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv4) begin + state = serv_req4; + prt_qos = qos4; + prt_req = 1; + prt_data = prt_data4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_dv1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_dv2) begin + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end + end + end + serv_req4:begin + state = serv_req4; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + if(prt_ack)begin + prt_ack4 = 1'b1; + //state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_dv2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv3) begin + prt_req = 1; + prt_qos = qos3; + prt_data = prt_data3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + state = serv_req3; + end + end + end + wait_ack_low:begin + state = wait_ack_low; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + if(!prt_ack) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_acp.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_acp.v new file mode 100644 index 0000000..3d31167 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_acp.v @@ -0,0 +1,93 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_axi_acp.v + * + * Date : 2012-11 + * + * Description : Connections for ACP port + * + *****************************************************************************/ + +/* AXI Slave ACP */ + processing_system7_bfm_v2_0_axi_slave #( C_USE_S_AXI_ACP, // enable + axi_acp_name, // name + axi_acp_data_width, // data width + addr_width, /// address width + axi_acp_id_width, // ID width + C_S_AXI_ACP_BASEADDR, // slave base address + C_S_AXI_ACP_HIGHADDR,// slave size + axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes + axi_slv_excl_support, // Exclusive access support + axi_acp_wr_outstanding, + axi_acp_rd_outstanding) + S_AXI_ACP(.S_RESETN (net_axi_acp_rstn), + .S_ACLK (S_AXI_ACP_ACLK), + // Write Address Channel + .S_AWID (S_AXI_ACP_AWID), + .S_AWADDR (S_AXI_ACP_AWADDR), + .S_AWLEN (S_AXI_ACP_AWLEN), + .S_AWSIZE (S_AXI_ACP_AWSIZE), + .S_AWBURST (S_AXI_ACP_AWBURST), + .S_AWLOCK (S_AXI_ACP_AWLOCK), + .S_AWCACHE (S_AXI_ACP_AWCACHE), + .S_AWPROT (S_AXI_ACP_AWPROT), + .S_AWVALID (S_AXI_ACP_AWVALID), + .S_AWREADY (S_AXI_ACP_AWREADY), + // Write Data Channel Signals. + .S_WID (S_AXI_ACP_WID), + .S_WDATA (S_AXI_ACP_WDATA), + .S_WSTRB (S_AXI_ACP_WSTRB), + .S_WLAST (S_AXI_ACP_WLAST), + .S_WVALID (S_AXI_ACP_WVALID), + .S_WREADY (S_AXI_ACP_WREADY), + // Write Response Channel Signals. + .S_BID (S_AXI_ACP_BID), + .S_BRESP (S_AXI_ACP_BRESP), + .S_BVALID (S_AXI_ACP_BVALID), + .S_BREADY (S_AXI_ACP_BREADY), + // Read Address Channel Signals. + .S_ARID (S_AXI_ACP_ARID), + .S_ARADDR (S_AXI_ACP_ARADDR), + .S_ARLEN (S_AXI_ACP_ARLEN), + .S_ARSIZE (S_AXI_ACP_ARSIZE), + .S_ARBURST (S_AXI_ACP_ARBURST), + .S_ARLOCK (S_AXI_ACP_ARLOCK), + .S_ARCACHE (S_AXI_ACP_ARCACHE), + .S_ARPROT (S_AXI_ACP_ARPROT), + .S_ARVALID (S_AXI_ACP_ARVALID), + .S_ARREADY (S_AXI_ACP_ARREADY), + // Read Data Channel Signals. + .S_RID (S_AXI_ACP_RID), + .S_RDATA (S_AXI_ACP_RDATA), + .S_RRESP (S_AXI_ACP_RRESP), + .S_RLAST (S_AXI_ACP_RLAST), + .S_RVALID (S_AXI_ACP_RVALID), + .S_RREADY (S_AXI_ACP_RREADY), + // Side band signals + .S_AWQOS (S_AXI_ACP_AWQOS), + .S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals + + .SW_CLK (net_sw_clk), +/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/ + .WR_DATA_ACK_DDR (ddr_wr_ack_port0), + .WR_DATA_ACK_OCM (ocm_wr_ack_port0), + .WR_DATA (net_wr_data_acp), + .WR_ADDR (net_wr_addr_acp), + .WR_BYTES (net_wr_bytes_acp), + .WR_DATA_VALID_DDR (ddr_wr_dv_port0), + .WR_DATA_VALID_OCM (ocm_wr_dv_port0), + .WR_QOS (net_wr_qos_acp), + + .RD_REQ_DDR (ddr_rd_req_port0), + .RD_REQ_OCM (ocm_rd_req_port0), + .RD_REQ_REG (reg_rd_req_port0), + .RD_ADDR (net_rd_addr_acp), + .RD_DATA_DDR (ddr_rd_data_port0), + .RD_DATA_OCM (ocm_rd_data_port0), + .RD_DATA_REG (reg_rd_data_port0), + .RD_BYTES (net_rd_bytes_acp), + .RD_DATA_VALID_DDR (ddr_rd_dv_port0), + .RD_DATA_VALID_OCM (ocm_rd_dv_port0), + .RD_DATA_VALID_REG (reg_rd_dv_port0), + .RD_QOS (net_rd_qos_acp) + +); diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_gp.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_gp.v new file mode 100644 index 0000000..145bf89 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_gp.v @@ -0,0 +1,309 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_axi_gp.v + * + * Date : 2012-11 + * + * Description : Connections for AXI GP ports + * + *****************************************************************************/ + + /* IDs for Masters + // l2m1 (CPU000) + 12'b11_000_000_00_00 + 12'b11_010_000_00_00 + 12'b11_011_000_00_00 + 12'b11_100_000_00_00 + 12'b11_101_000_00_00 + 12'b11_110_000_00_00 + 12'b11_111_000_00_00 + // l2m1 (CPU001) + 12'b11_000_001_00_00 + 12'b11_010_001_00_00 + 12'b11_011_001_00_00 + 12'b11_100_001_00_00 + 12'b11_101_001_00_00 + 12'b11_110_001_00_00 + 12'b11_111_001_00_00 + */ + +/* AXI -Master GP0 */ + processing_system7_bfm_v2_0_axi_master #(C_USE_M_AXI_GP0, // enable + axi_mgp0_name,// name + axi_mgp_data_width, /// Data Width + addr_width, /// Address width + axi_mgp_id_width, //// ID Width + axi_mgp_outstanding, //// Outstanding transactions + axi_mst_excl_support, // EXCL Access Support + axi_mgp_wr_id, //WR_ID + axi_mgp_rd_id) //RD_ID + M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn), + .M_ACLK (M_AXI_GP0_ACLK), + // Write Address Channel + .M_AWID (M_AXI_GP0_AWID_FULL), + .M_AWADDR (M_AXI_GP0_AWADDR), + .M_AWLEN (M_AXI_GP0_AWLEN), + .M_AWSIZE (M_AXI_GP0_AWSIZE), + .M_AWBURST (M_AXI_GP0_AWBURST), + .M_AWLOCK (M_AXI_GP0_AWLOCK), + .M_AWCACHE (M_AXI_GP0_AWCACHE), + .M_AWPROT (M_AXI_GP0_AWPROT), + .M_AWVALID (M_AXI_GP0_AWVALID), + .M_AWREADY (M_AXI_GP0_AWREADY), + // Write Data Channel Signals. + .M_WID (M_AXI_GP0_WID_FULL), + .M_WDATA (M_AXI_GP0_WDATA), + .M_WSTRB (M_AXI_GP0_WSTRB), + .M_WLAST (M_AXI_GP0_WLAST), + .M_WVALID (M_AXI_GP0_WVALID), + .M_WREADY (M_AXI_GP0_WREADY), + // Write Response Channel Signals. + .M_BID (M_AXI_GP0_BID_FULL), + .M_BRESP (M_AXI_GP0_BRESP), + .M_BVALID (M_AXI_GP0_BVALID), + .M_BREADY (M_AXI_GP0_BREADY), + // Read Address Channel Signals. + .M_ARID (M_AXI_GP0_ARID_FULL), + .M_ARADDR (M_AXI_GP0_ARADDR), + .M_ARLEN (M_AXI_GP0_ARLEN), + .M_ARSIZE (M_AXI_GP0_ARSIZE), + .M_ARBURST (M_AXI_GP0_ARBURST), + .M_ARLOCK (M_AXI_GP0_ARLOCK), + .M_ARCACHE (M_AXI_GP0_ARCACHE), + .M_ARPROT (M_AXI_GP0_ARPROT), + .M_ARVALID (M_AXI_GP0_ARVALID), + .M_ARREADY (M_AXI_GP0_ARREADY), + // Read Data Channel Signals. + .M_RID (M_AXI_GP0_RID_FULL), + .M_RDATA (M_AXI_GP0_RDATA), + .M_RRESP (M_AXI_GP0_RRESP), + .M_RLAST (M_AXI_GP0_RLAST), + .M_RVALID (M_AXI_GP0_RVALID), + .M_RREADY (M_AXI_GP0_RREADY), + // Side band signals + .M_AWQOS (M_AXI_GP0_AWQOS), + .M_ARQOS (M_AXI_GP0_ARQOS) + ); + + /* AXI Master GP1 */ + processing_system7_bfm_v2_0_axi_master #(C_USE_M_AXI_GP1, // enable + axi_mgp1_name,// name + axi_mgp_data_width, /// Data Width + addr_width, /// Address width + axi_mgp_id_width, //// ID Width + axi_mgp_outstanding, //// Outstanding transactions + axi_mst_excl_support, // EXCL Access Support + axi_mgp_wr_id, //WR_ID + axi_mgp_rd_id) //RD_ID + M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn), + .M_ACLK (M_AXI_GP1_ACLK), + // Write Address Channel + .M_AWID (M_AXI_GP1_AWID_FULL), + .M_AWADDR (M_AXI_GP1_AWADDR), + .M_AWLEN (M_AXI_GP1_AWLEN), + .M_AWSIZE (M_AXI_GP1_AWSIZE), + .M_AWBURST (M_AXI_GP1_AWBURST), + .M_AWLOCK (M_AXI_GP1_AWLOCK), + .M_AWCACHE (M_AXI_GP1_AWCACHE), + .M_AWPROT (M_AXI_GP1_AWPROT), + .M_AWVALID (M_AXI_GP1_AWVALID), + .M_AWREADY (M_AXI_GP1_AWREADY), + // Write Data Channel Signals. + .M_WID (M_AXI_GP1_WID_FULL), + .M_WDATA (M_AXI_GP1_WDATA), + .M_WSTRB (M_AXI_GP1_WSTRB), + .M_WLAST (M_AXI_GP1_WLAST), + .M_WVALID (M_AXI_GP1_WVALID), + .M_WREADY (M_AXI_GP1_WREADY), + // Write Response Channel Signals. + .M_BID (M_AXI_GP1_BID_FULL), + .M_BRESP (M_AXI_GP1_BRESP), + .M_BVALID (M_AXI_GP1_BVALID), + .M_BREADY (M_AXI_GP1_BREADY), + // Read Address Channel Signals. + .M_ARID (M_AXI_GP1_ARID_FULL), + .M_ARADDR (M_AXI_GP1_ARADDR), + .M_ARLEN (M_AXI_GP1_ARLEN), + .M_ARSIZE (M_AXI_GP1_ARSIZE), + .M_ARBURST (M_AXI_GP1_ARBURST), + .M_ARLOCK (M_AXI_GP1_ARLOCK), + .M_ARCACHE (M_AXI_GP1_ARCACHE), + .M_ARPROT (M_AXI_GP1_ARPROT), + .M_ARVALID (M_AXI_GP1_ARVALID), + .M_ARREADY (M_AXI_GP1_ARREADY), + // Read Data Channel Signals. + .M_RID (M_AXI_GP1_RID_FULL), + .M_RDATA (M_AXI_GP1_RDATA), + .M_RRESP (M_AXI_GP1_RRESP), + .M_RLAST (M_AXI_GP1_RLAST), + .M_RVALID (M_AXI_GP1_RVALID), + .M_RREADY (M_AXI_GP1_RREADY), + // Side band signals + .M_AWQOS (M_AXI_GP1_AWQOS), + .M_ARQOS (M_AXI_GP1_ARQOS) + ); + +/* AXI Slave GP0 */ + processing_system7_bfm_v2_0_axi_slave #(C_USE_S_AXI_GP0, /// enable + axi_sgp0_name, //name + axi_sgp_data_width, /// data width + addr_width, /// address width + axi_sgp_id_width, /// ID width + C_S_AXI_GP0_BASEADDR,//// base address + C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr) + axi_sgp_outstanding, // outstanding transactions + axi_slv_excl_support, // exclusive access not supported + axi_sgp_wr_outstanding, + axi_sgp_rd_outstanding) + S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn), + .S_ACLK (S_AXI_GP0_ACLK), + // Write Address Channel + .S_AWID (S_AXI_GP0_AWID), + .S_AWADDR (S_AXI_GP0_AWADDR), + .S_AWLEN (S_AXI_GP0_AWLEN), + .S_AWSIZE (S_AXI_GP0_AWSIZE), + .S_AWBURST (S_AXI_GP0_AWBURST), + .S_AWLOCK (S_AXI_GP0_AWLOCK), + .S_AWCACHE (S_AXI_GP0_AWCACHE), + .S_AWPROT (S_AXI_GP0_AWPROT), + .S_AWVALID (S_AXI_GP0_AWVALID), + .S_AWREADY (S_AXI_GP0_AWREADY), + // Write Data Channel Signals. + .S_WID (S_AXI_GP0_WID), + .S_WDATA (S_AXI_GP0_WDATA), + .S_WSTRB (S_AXI_GP0_WSTRB), + .S_WLAST (S_AXI_GP0_WLAST), + .S_WVALID (S_AXI_GP0_WVALID), + .S_WREADY (S_AXI_GP0_WREADY), + // Write Response Channel Signals. + .S_BID (S_AXI_GP0_BID), + .S_BRESP (S_AXI_GP0_BRESP), + .S_BVALID (S_AXI_GP0_BVALID), + .S_BREADY (S_AXI_GP0_BREADY), + // Read Address Channel Signals. + .S_ARID (S_AXI_GP0_ARID), + .S_ARADDR (S_AXI_GP0_ARADDR), + .S_ARLEN (S_AXI_GP0_ARLEN), + .S_ARSIZE (S_AXI_GP0_ARSIZE), + .S_ARBURST (S_AXI_GP0_ARBURST), + .S_ARLOCK (S_AXI_GP0_ARLOCK), + .S_ARCACHE (S_AXI_GP0_ARCACHE), + .S_ARPROT (S_AXI_GP0_ARPROT), + .S_ARVALID (S_AXI_GP0_ARVALID), + .S_ARREADY (S_AXI_GP0_ARREADY), + // Read Data Channel Signals. + .S_RID (S_AXI_GP0_RID), + .S_RDATA (S_AXI_GP0_RDATA), + .S_RRESP (S_AXI_GP0_RRESP), + .S_RLAST (S_AXI_GP0_RLAST), + .S_RVALID (S_AXI_GP0_RVALID), + .S_RREADY (S_AXI_GP0_RREADY), + // Side band signals + .S_AWQOS (S_AXI_GP0_AWQOS), + .S_ARQOS (S_AXI_GP0_ARQOS), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0), + .WR_DATA (net_wr_data_gp0), + .WR_ADDR (net_wr_addr_gp0), + .WR_BYTES (net_wr_bytes_gp0), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_gp0), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_gp0), + .WR_QOS (net_wr_qos_gp0), + .RD_REQ_DDR (net_rd_req_ddr_gp0), + .RD_REQ_OCM (net_rd_req_ocm_gp0), + .RD_REQ_REG (net_rd_req_reg_gp0), + .RD_ADDR (net_rd_addr_gp0), + .RD_DATA_DDR (net_rd_data_ddr_gp0), + .RD_DATA_OCM (net_rd_data_ocm_gp0), + .RD_DATA_REG (net_rd_data_reg_gp0), + .RD_BYTES (net_rd_bytes_gp0), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0), + .RD_DATA_VALID_REG (net_rd_dv_reg_gp0), + .RD_QOS (net_rd_qos_gp0) + +); + +/* AXI Slave GP1 */ + processing_system7_bfm_v2_0_axi_slave #(C_USE_S_AXI_GP1, /// enable + axi_sgp1_name, //name + axi_sgp_data_width, /// data width + addr_width, /// address width + axi_sgp_id_width, /// ID width + C_S_AXI_GP1_BASEADDR,//// base address + C_S_AXI_GP1_HIGHADDR,/// HIGh_addr + axi_sgp_outstanding, // outstanding transactions + axi_slv_excl_support, // exclusive access + axi_sgp_wr_outstanding, + axi_sgp_rd_outstanding) + S_AXI_GP1(.S_RESETN (net_axi_gp1_rstn), + .S_ACLK (S_AXI_GP1_ACLK), + // Write Address Channel + .S_AWID (S_AXI_GP1_AWID), + .S_AWADDR (S_AXI_GP1_AWADDR), + .S_AWLEN (S_AXI_GP1_AWLEN), + .S_AWSIZE (S_AXI_GP1_AWSIZE), + .S_AWBURST (S_AXI_GP1_AWBURST), + .S_AWLOCK (S_AXI_GP1_AWLOCK), + .S_AWCACHE (S_AXI_GP1_AWCACHE), + .S_AWPROT (S_AXI_GP1_AWPROT), + .S_AWVALID (S_AXI_GP1_AWVALID), + .S_AWREADY (S_AXI_GP1_AWREADY), + // Write Data Channel Signals. + .S_WID (S_AXI_GP1_WID), + .S_WDATA (S_AXI_GP1_WDATA), + .S_WSTRB (S_AXI_GP1_WSTRB), + .S_WLAST (S_AXI_GP1_WLAST), + .S_WVALID (S_AXI_GP1_WVALID), + .S_WREADY (S_AXI_GP1_WREADY), + // Write Response Channel Signals. + .S_BID (S_AXI_GP1_BID), + .S_BRESP (S_AXI_GP1_BRESP), + .S_BVALID (S_AXI_GP1_BVALID), + .S_BREADY (S_AXI_GP1_BREADY), + // Read Address Channel Signals. + .S_ARID (S_AXI_GP1_ARID), + .S_ARADDR (S_AXI_GP1_ARADDR), + .S_ARLEN (S_AXI_GP1_ARLEN), + .S_ARSIZE (S_AXI_GP1_ARSIZE), + .S_ARBURST (S_AXI_GP1_ARBURST), + .S_ARLOCK (S_AXI_GP1_ARLOCK), + .S_ARCACHE (S_AXI_GP1_ARCACHE), + .S_ARPROT (S_AXI_GP1_ARPROT), + .S_ARVALID (S_AXI_GP1_ARVALID), + .S_ARREADY (S_AXI_GP1_ARREADY), + // Read Data Channel Signals. + .S_RID (S_AXI_GP1_RID), + .S_RDATA (S_AXI_GP1_RDATA), + .S_RRESP (S_AXI_GP1_RRESP), + .S_RLAST (S_AXI_GP1_RLAST), + .S_RVALID (S_AXI_GP1_RVALID), + .S_RREADY (S_AXI_GP1_RREADY), + // Side band signals + .S_AWQOS (S_AXI_GP1_AWQOS), + .S_ARQOS (S_AXI_GP1_ARQOS), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1), + .WR_DATA (net_wr_data_gp1), + .WR_ADDR (net_wr_addr_gp1), + .WR_BYTES (net_wr_bytes_gp1), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_gp1), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_gp1), + .WR_QOS (net_wr_qos_gp1), + .RD_REQ_OCM (net_rd_req_ocm_gp1), + .RD_REQ_DDR (net_rd_req_ddr_gp1), + .RD_REQ_REG (net_rd_req_reg_gp1), + .RD_ADDR (net_rd_addr_gp1), + .RD_DATA_DDR (net_rd_data_ddr_gp1), + .RD_DATA_OCM (net_rd_data_ocm_gp1), + .RD_DATA_REG (net_rd_data_reg_gp1), + .RD_BYTES (net_rd_bytes_gp1), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1), + .RD_DATA_VALID_REG (net_rd_dv_reg_gp1), + .RD_QOS (net_rd_qos_gp1) + +); diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_hp.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_hp.v new file mode 100644 index 0000000..bb1ad62 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_hp.v @@ -0,0 +1,346 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_axi_hp.v + * + * Date : 2012-11 + * + * Description : Connections for AXI HP ports + * + *****************************************************************************/ + +/* AXI Slave HP0 */ + processing_system7_bfm_v2_0_afi_slave #( C_USE_S_AXI_HP0, // enable + axi_hp0_name, // name + C_S_AXI_HP0_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP0_BASEADDR, // slave base address + C_S_AXI_HP0_HIGHADDR, // slave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn), + .S_ACLK (S_AXI_HP0_ACLK), + // Write Address channel + .S_AWID (S_AXI_HP0_AWID), + .S_AWADDR (S_AXI_HP0_AWADDR), + .S_AWLEN (S_AXI_HP0_AWLEN), + .S_AWSIZE (S_AXI_HP0_AWSIZE), + .S_AWBURST (S_AXI_HP0_AWBURST), + .S_AWLOCK (S_AXI_HP0_AWLOCK), + .S_AWCACHE (S_AXI_HP0_AWCACHE), + .S_AWPROT (S_AXI_HP0_AWPROT), + .S_AWVALID (S_AXI_HP0_AWVALID), + .S_AWREADY (S_AXI_HP0_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP0_WID), + .S_WDATA (S_AXI_HP0_WDATA), + .S_WSTRB (S_AXI_HP0_WSTRB), + .S_WLAST (S_AXI_HP0_WLAST), + .S_WVALID (S_AXI_HP0_WVALID), + .S_WREADY (S_AXI_HP0_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP0_BID), + .S_BRESP (S_AXI_HP0_BRESP), + .S_BVALID (S_AXI_HP0_BVALID), + .S_BREADY (S_AXI_HP0_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP0_ARID), + .S_ARADDR (S_AXI_HP0_ARADDR), + .S_ARLEN (S_AXI_HP0_ARLEN), + .S_ARSIZE (S_AXI_HP0_ARSIZE), + .S_ARBURST (S_AXI_HP0_ARBURST), + .S_ARLOCK (S_AXI_HP0_ARLOCK), + .S_ARCACHE (S_AXI_HP0_ARCACHE), + .S_ARPROT (S_AXI_HP0_ARPROT), + .S_ARVALID (S_AXI_HP0_ARVALID), + .S_ARREADY (S_AXI_HP0_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP0_RID), + .S_RDATA (S_AXI_HP0_RDATA), + .S_RRESP (S_AXI_HP0_RRESP), + .S_RLAST (S_AXI_HP0_RLAST), + .S_RVALID (S_AXI_HP0_RVALID), + .S_RREADY (S_AXI_HP0_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP0_AWQOS), + .S_ARQOS (S_AXI_HP0_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP0_RCOUNT), + .S_WCOUNT (S_AXI_HP0_WCOUNT), + .S_RACOUNT (S_AXI_HP0_RACOUNT), + .S_WACOUNT (S_AXI_HP0_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0), + .WR_DATA (net_wr_data_hp0), + .WR_ADDR (net_wr_addr_hp0), + .WR_BYTES (net_wr_bytes_hp0), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp0), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp0), + .WR_QOS (net_wr_qos_hp0), + .RD_REQ_DDR (net_rd_req_ddr_hp0), + .RD_REQ_OCM (net_rd_req_ocm_hp0), + .RD_ADDR (net_rd_addr_hp0), + .RD_DATA_DDR (net_rd_data_ddr_hp0), + .RD_DATA_OCM (net_rd_data_ocm_hp0), + .RD_BYTES (net_rd_bytes_hp0), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0), + .RD_QOS (net_rd_qos_hp0) + ); + +/* AXI Slave HP1 */ + processing_system7_bfm_v2_0_afi_slave #( C_USE_S_AXI_HP1, // enable + axi_hp1_name, // name + C_S_AXI_HP1_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP1_BASEADDR, // slave base address + C_S_AXI_HP1_HIGHADDR, // Slave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn), + .S_ACLK (S_AXI_HP1_ACLK), + // Write Address channel + .S_AWID (S_AXI_HP1_AWID), + .S_AWADDR (S_AXI_HP1_AWADDR), + .S_AWLEN (S_AXI_HP1_AWLEN), + .S_AWSIZE (S_AXI_HP1_AWSIZE), + .S_AWBURST (S_AXI_HP1_AWBURST), + .S_AWLOCK (S_AXI_HP1_AWLOCK), + .S_AWCACHE (S_AXI_HP1_AWCACHE), + .S_AWPROT (S_AXI_HP1_AWPROT), + .S_AWVALID (S_AXI_HP1_AWVALID), + .S_AWREADY (S_AXI_HP1_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP1_WID), + .S_WDATA (S_AXI_HP1_WDATA), + .S_WSTRB (S_AXI_HP1_WSTRB), + .S_WLAST (S_AXI_HP1_WLAST), + .S_WVALID (S_AXI_HP1_WVALID), + .S_WREADY (S_AXI_HP1_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP1_BID), + .S_BRESP (S_AXI_HP1_BRESP), + .S_BVALID (S_AXI_HP1_BVALID), + .S_BREADY (S_AXI_HP1_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP1_ARID), + .S_ARADDR (S_AXI_HP1_ARADDR), + .S_ARLEN (S_AXI_HP1_ARLEN), + .S_ARSIZE (S_AXI_HP1_ARSIZE), + .S_ARBURST (S_AXI_HP1_ARBURST), + .S_ARLOCK (S_AXI_HP1_ARLOCK), + .S_ARCACHE (S_AXI_HP1_ARCACHE), + .S_ARPROT (S_AXI_HP1_ARPROT), + .S_ARVALID (S_AXI_HP1_ARVALID), + .S_ARREADY (S_AXI_HP1_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP1_RID), + .S_RDATA (S_AXI_HP1_RDATA), + .S_RRESP (S_AXI_HP1_RRESP), + .S_RLAST (S_AXI_HP1_RLAST), + .S_RVALID (S_AXI_HP1_RVALID), + .S_RREADY (S_AXI_HP1_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP1_AWQOS), + .S_ARQOS (S_AXI_HP1_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP1_RCOUNT), + .S_WCOUNT (S_AXI_HP1_WCOUNT), + .S_RACOUNT (S_AXI_HP1_RACOUNT), + .S_WACOUNT (S_AXI_HP1_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1), + .WR_DATA (net_wr_data_hp1), + .WR_ADDR (net_wr_addr_hp1), + .WR_BYTES (net_wr_bytes_hp1), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1), + .WR_QOS (net_wr_qos_hp1), + .RD_REQ_DDR (net_rd_req_ddr_hp1), + .RD_REQ_OCM (net_rd_req_ocm_hp1), + .RD_ADDR (net_rd_addr_hp1), + .RD_DATA_DDR (net_rd_data_ddr_hp1), + .RD_DATA_OCM (net_rd_data_ocm_hp1), + .RD_BYTES (net_rd_bytes_hp1), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1), + .RD_QOS (net_rd_qos_hp1) + + ); + +/* AXI Slave HP2 */ + processing_system7_bfm_v2_0_afi_slave #( C_USE_S_AXI_HP2, // enable + axi_hp2_name, // name + C_S_AXI_HP2_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP2_BASEADDR, // slave base address + C_S_AXI_HP2_HIGHADDR, // SLave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn), + .S_ACLK (S_AXI_HP2_ACLK), + // Write Address channel + .S_AWID (S_AXI_HP2_AWID), + .S_AWADDR (S_AXI_HP2_AWADDR), + .S_AWLEN (S_AXI_HP2_AWLEN), + .S_AWSIZE (S_AXI_HP2_AWSIZE), + .S_AWBURST (S_AXI_HP2_AWBURST), + .S_AWLOCK (S_AXI_HP2_AWLOCK), + .S_AWCACHE (S_AXI_HP2_AWCACHE), + .S_AWPROT (S_AXI_HP2_AWPROT), + .S_AWVALID (S_AXI_HP2_AWVALID), + .S_AWREADY (S_AXI_HP2_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP2_WID), + .S_WDATA (S_AXI_HP2_WDATA), + .S_WSTRB (S_AXI_HP2_WSTRB), + .S_WLAST (S_AXI_HP2_WLAST), + .S_WVALID (S_AXI_HP2_WVALID), + .S_WREADY (S_AXI_HP2_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP2_BID), + .S_BRESP (S_AXI_HP2_BRESP), + .S_BVALID (S_AXI_HP2_BVALID), + .S_BREADY (S_AXI_HP2_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP2_ARID), + .S_ARADDR (S_AXI_HP2_ARADDR), + .S_ARLEN (S_AXI_HP2_ARLEN), + .S_ARSIZE (S_AXI_HP2_ARSIZE), + .S_ARBURST (S_AXI_HP2_ARBURST), + .S_ARLOCK (S_AXI_HP2_ARLOCK), + .S_ARCACHE (S_AXI_HP2_ARCACHE), + .S_ARPROT (S_AXI_HP2_ARPROT), + .S_ARVALID (S_AXI_HP2_ARVALID), + .S_ARREADY (S_AXI_HP2_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP2_RID), + .S_RDATA (S_AXI_HP2_RDATA), + .S_RRESP (S_AXI_HP2_RRESP), + .S_RLAST (S_AXI_HP2_RLAST), + .S_RVALID (S_AXI_HP2_RVALID), + .S_RREADY (S_AXI_HP2_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP2_AWQOS), + .S_ARQOS (S_AXI_HP2_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP2_RCOUNT), + .S_WCOUNT (S_AXI_HP2_WCOUNT), + .S_RACOUNT (S_AXI_HP2_RACOUNT), + .S_WACOUNT (S_AXI_HP2_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2), + .WR_DATA (net_wr_data_hp2), + .WR_ADDR (net_wr_addr_hp2), + .WR_BYTES (net_wr_bytes_hp2), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp2), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp2), + .WR_QOS (net_wr_qos_hp2), + .RD_REQ_DDR (net_rd_req_ddr_hp2), + .RD_REQ_OCM (net_rd_req_ocm_hp2), + .RD_ADDR (net_rd_addr_hp2), + .RD_DATA_DDR (net_rd_data_ddr_hp2), + .RD_DATA_OCM (net_rd_data_ocm_hp2), + .RD_BYTES (net_rd_bytes_hp2), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2), + .RD_QOS (net_rd_qos_hp2) + + ); + +/* AXI Slave HP3 */ + processing_system7_bfm_v2_0_afi_slave #( C_USE_S_AXI_HP3, // enable + axi_hp3_name, // name + C_S_AXI_HP3_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP3_BASEADDR, // slave base address + C_S_AXI_HP3_HIGHADDR, // SLave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn), + .S_ACLK (S_AXI_HP3_ACLK), + // Write ADDRESS CHANNEL + .S_AWID (S_AXI_HP3_AWID), + .S_AWADDR (S_AXI_HP3_AWADDR), + .S_AWLEN (S_AXI_HP3_AWLEN), + .S_AWSIZE (S_AXI_HP3_AWSIZE), + .S_AWBURST (S_AXI_HP3_AWBURST), + .S_AWLOCK (S_AXI_HP3_AWLOCK), + .S_AWCACHE (S_AXI_HP3_AWCACHE), + .S_AWPROT (S_AXI_HP3_AWPROT), + .S_AWVALID (S_AXI_HP3_AWVALID), + .S_AWREADY (S_AXI_HP3_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP3_WID), + .S_WDATA (S_AXI_HP3_WDATA), + .S_WSTRB (S_AXI_HP3_WSTRB), + .S_WLAST (S_AXI_HP3_WLAST), + .S_WVALID (S_AXI_HP3_WVALID), + .S_WREADY (S_AXI_HP3_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP3_BID), + .S_BRESP (S_AXI_HP3_BRESP), + .S_BVALID (S_AXI_HP3_BVALID), + .S_BREADY (S_AXI_HP3_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP3_ARID), + .S_ARADDR (S_AXI_HP3_ARADDR), + .S_ARLEN (S_AXI_HP3_ARLEN), + .S_ARSIZE (S_AXI_HP3_ARSIZE), + .S_ARBURST (S_AXI_HP3_ARBURST), + .S_ARLOCK (S_AXI_HP3_ARLOCK), + .S_ARCACHE (S_AXI_HP3_ARCACHE), + .S_ARPROT (S_AXI_HP3_ARPROT), + .S_ARVALID (S_AXI_HP3_ARVALID), + .S_ARREADY (S_AXI_HP3_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP3_RID), + .S_RDATA (S_AXI_HP3_RDATA), + .S_RRESP (S_AXI_HP3_RRESP), + .S_RLAST (S_AXI_HP3_RLAST), + .S_RVALID (S_AXI_HP3_RVALID), + .S_RREADY (S_AXI_HP3_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP3_AWQOS), + .S_ARQOS (S_AXI_HP3_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP3_RCOUNT), + .S_WCOUNT (S_AXI_HP3_WCOUNT), + .S_RACOUNT (S_AXI_HP3_RACOUNT), + .S_WACOUNT (S_AXI_HP3_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3), + .WR_DATA (net_wr_data_hp3), + .WR_ADDR (net_wr_addr_hp3), + .WR_BYTES (net_wr_bytes_hp3), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp3), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp3), + .WR_QOS (net_wr_qos_hp3), + .RD_REQ_DDR (net_rd_req_ddr_hp3), + .RD_REQ_OCM (net_rd_req_ocm_hp3), + .RD_ADDR (net_rd_addr_hp3), + .RD_DATA_DDR (net_rd_data_ddr_hp3), + .RD_DATA_OCM (net_rd_data_ocm_hp3), + .RD_BYTES (net_rd_bytes_hp3), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3), + .RD_QOS (net_rd_qos_hp3) + ); diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_master.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_master.v new file mode 100644 index 0000000..f60070c --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_master.v @@ -0,0 +1,679 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_axi_master.v + * + * Date : 2012-11 + * + * Description : Model that acts as PS AXI Master port interface. + * It uses AXI3 Master BFM + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_axi_master ( + M_RESETN, + M_ARVALID, + M_AWVALID, + M_BREADY, + M_RREADY, + M_WLAST, + M_WVALID, + M_ARID, + M_AWID, + M_WID, + M_ARBURST, + M_ARLOCK, + M_ARSIZE, + M_AWBURST, + M_AWLOCK, + M_AWSIZE, + M_ARPROT, + M_AWPROT, + M_ARADDR, + M_AWADDR, + M_WDATA, + M_ARCACHE, + M_ARLEN, + M_AWCACHE, + M_AWLEN, + M_ARQOS, // not connected to AXI BFM + M_AWQOS, // not connected to AXI BFM + M_WSTRB, + M_ACLK, + M_ARREADY, + M_AWREADY, + M_BVALID, + M_RLAST, + M_RVALID, + M_WREADY, + M_BID, + M_RID, + M_BRESP, + M_RRESP, + M_RDATA + +); + parameter enable_this_port = 0; + parameter master_name = "Master"; + parameter data_bus_width = 32; + parameter address_bus_width = 32; + parameter id_bus_width = 6; + parameter max_outstanding_transactions = 8; + parameter exclusive_access_supported = 0; + parameter EXCL_ID = 12'hC00; + `include "processing_system7_bfm_v2_0_local_params.v" + /* IDs for Masters + // l2m1 (CPU000) + 12'b11_000_000_00_00 + 12'b11_010_000_00_00 + 12'b11_011_000_00_00 + 12'b11_100_000_00_00 + 12'b11_101_000_00_00 + 12'b11_110_000_00_00 + 12'b11_111_000_00_00 + // l2m1 (CPU001) + 12'b11_000_001_00_00 + 12'b11_010_001_00_00 + 12'b11_011_001_00_00 + 12'b11_100_001_00_00 + 12'b11_101_001_00_00 + 12'b11_110_001_00_00 + 12'b11_111_001_00_00 + */ + + input M_RESETN; + + output M_ARVALID; + output M_AWVALID; + output M_BREADY; + output M_RREADY; + output M_WLAST; + output M_WVALID; + output [id_bus_width-1:0] M_ARID; + output [id_bus_width-1:0] M_AWID; + output [id_bus_width-1:0] M_WID; + output [axi_brst_type_width-1:0] M_ARBURST; + output [axi_lock_width-1:0] M_ARLOCK; + output [axi_size_width-1:0] M_ARSIZE; + output [axi_brst_type_width-1:0] M_AWBURST; + output [axi_lock_width-1:0] M_AWLOCK; + output [axi_size_width-1:0] M_AWSIZE; + output [axi_prot_width-1:0] M_ARPROT; + output [axi_prot_width-1:0] M_AWPROT; + output [address_bus_width-1:0] M_ARADDR; + output [address_bus_width-1:0] M_AWADDR; + output [data_bus_width-1:0] M_WDATA; + output [axi_cache_width-1:0] M_ARCACHE; + output [axi_len_width-1:0] M_ARLEN; + output [axi_qos_width-1:0] M_ARQOS; // not connected to AXI BFM + output [axi_cache_width-1:0] M_AWCACHE; + output [axi_len_width-1:0] M_AWLEN; + output [axi_qos_width-1:0] M_AWQOS; // not connected to AXI BFM + output [(data_bus_width/8)-1:0] M_WSTRB; + input M_ACLK; + input M_ARREADY; + input M_AWREADY; + input M_BVALID; + input M_RLAST; + input M_RVALID; + input M_WREADY; + input [id_bus_width-1:0] M_BID; + input [id_bus_width-1:0] M_RID; + input [axi_rsp_width-1:0] M_BRESP; + input [axi_rsp_width-1:0] M_RRESP; + input [data_bus_width-1:0] M_RDATA; + + wire net_RESETN; + wire net_RVALID; + wire net_BVALID; + reg DEBUG_INFO = 1'b1; + reg STOP_ON_ERROR = 1'b1; + + integer use_id_no = 0; + + assign M_ARQOS = 'b0; + assign M_AWQOS = 'b0; + assign net_RESETN = M_RESETN; //ENABLE_THIS_PORT ? M_RESETN : 1'b0; + assign net_RVALID = enable_this_port ? M_RVALID : 1'b0; + assign net_BVALID = enable_this_port ? M_BVALID : 1'b0; + + initial begin + if(DEBUG_INFO) begin + if(enable_this_port) + $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, master_name); + else + $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, master_name); + end + end + + initial master.set_disable_reset_value_checks(1); + initial begin + repeat(2) @(posedge M_ACLK); + if(!enable_this_port) begin + master.set_channel_level_info(0); + master.set_function_level_info(0); + end + master.RESPONSE_TIMEOUT = 0; + end + + cdn_axi3_master_bfm #(master_name, + data_bus_width, + address_bus_width, + id_bus_width, + max_outstanding_transactions, + exclusive_access_supported) + + master (.ACLK (M_ACLK), + .ARESETn (net_RESETN), /// confirm this + // Write Address Channel + .AWID (M_AWID), + .AWADDR (M_AWADDR), + .AWLEN (M_AWLEN), + .AWSIZE (M_AWSIZE), + .AWBURST (M_AWBURST), + .AWLOCK (M_AWLOCK), + .AWCACHE (M_AWCACHE), + .AWPROT (M_AWPROT), + .AWVALID (M_AWVALID), + .AWREADY (M_AWREADY), + // Write Data Channel Signals. + .WID (M_WID), + .WDATA (M_WDATA), + .WSTRB (M_WSTRB), + .WLAST (M_WLAST), + .WVALID (M_WVALID), + .WREADY (M_WREADY), + // Write Response Channel Signals. + .BID (M_BID), + .BRESP (M_BRESP), + .BVALID (net_BVALID), + .BREADY (M_BREADY), + // Read Address Channel Signals. + .ARID (M_ARID), + .ARADDR (M_ARADDR), + .ARLEN (M_ARLEN), + .ARSIZE (M_ARSIZE), + .ARBURST (M_ARBURST), + .ARLOCK (M_ARLOCK), + .ARCACHE (M_ARCACHE), + .ARPROT (M_ARPROT), + .ARVALID (M_ARVALID), + .ARREADY (M_ARREADY), + // Read Data Channel Signals. + .RID (M_RID), + .RDATA (M_RDATA), + .RRESP (M_RRESP), + .RLAST (M_RLAST), + .RVALID (net_RVALID), + .RREADY (M_RREADY)); + + +/* Call to BFM APIs */ +task automatic read_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,output [(axi_mgp_data_width*axi_burst_len)-1:0] data, output [(axi_rsp_width*axi_burst_len)-1:0] response); + if(enable_this_port)begin + if(lck !== AXI_NRML) + master.READ_BURST(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,response); + else + master.READ_BURST(get_id(1),addr,len,siz,burst,lck,cache,prot,data,response); + end else begin + $display("[%0d] : %0s : %0s : Port is disabled. 'read_burst' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end +endtask + +task automatic write_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + if(enable_this_port)begin + if(lck !== AXI_NRML) + master.WRITE_BURST(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response); + else + master.WRITE_BURST(get_id(1),addr,len,siz,burst,lck,cache,prot,data,datasize,response); + end else begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_burst' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end +endtask + +task automatic write_burst_concurrent(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + if(enable_this_port)begin + if(lck !== AXI_NRML) + master.WRITE_BURST_CONCURRENT(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response); + else + master.WRITE_BURST_CONCURRENT(get_id(1),addr,len,siz,burst,lck,cache,prot,data,datasize,response); + end else begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_burst_concurrent' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end +endtask + +/* local */ +function automatic[id_bus_width-1:0] get_id; +input dummy; +begin + case(use_id_no) + // l2m1 (CPU000) + 0 : get_id = 12'b11_000_000_00_00; + 1 : get_id = 12'b11_010_000_00_00; + 2 : get_id = 12'b11_011_000_00_00; + 3 : get_id = 12'b11_100_000_00_00; + 4 : get_id = 12'b11_101_000_00_00; + 5 : get_id = 12'b11_110_000_00_00; + 6 : get_id = 12'b11_111_000_00_00; + // l2m1 (CPU001) + 7 : get_id = 12'b11_000_001_00_00; + 8 : get_id = 12'b11_010_001_00_00; + 9 : get_id = 12'b11_011_001_00_00; + 10 : get_id = 12'b11_100_001_00_00; + 11 : get_id = 12'b11_101_001_00_00; + 12 : get_id = 12'b11_110_001_00_00; + 13 : get_id = 12'b11_111_001_00_00; + endcase + if(use_id_no == 13) + use_id_no = 0; + else + use_id_no = use_id_no+1; +end +endfunction + +/* Write data from file */ +task automatic write_from_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] wr_size; +output [axi_rsp_width-1:0] response; +reg [axi_rsp_width-1:0] wresp,rwrsp; +reg [addr_width-1:0] addr; +reg [(axi_burst_len*data_bus_width)-1 : 0] wr_data; +integer bytes; +integer trnsfr_bytes; +integer wr_fd; +integer succ; +integer trnsfr_lngth; +reg concurrent; + +reg [id_bus_width-1:0] wr_id; +reg [axi_size_width-1:0] siz; +reg [axi_brst_type_width-1:0] burst; +reg [axi_lock_width-1:0] lck; +reg [axi_cache_width-1:0] cache; +reg [axi_prot_width-1:0] prot; +begin +if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_from_file' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; +end else begin + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + + addr = start_addr; + bytes = wr_size; + wresp = 0; + concurrent = $random; + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_bytes = (axi_burst_len * data_bus_width/8); + else + trnsfr_bytes = bytes; + + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_lngth = axi_burst_len-1; + else if(bytes%(data_bus_width/8) == 0) + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = bytes/(data_bus_width/8); + + wr_id = get_id(1); + wr_fd = $fopen(file_name,"r"); + + while (bytes > 0) begin + repeat(axi_burst_len) begin /// get the data for 1 AXI burst transaction + wr_data = wr_data >> data_bus_width; + succ = $fscanf(wr_fd,"%h",wr_data[(axi_burst_len*data_bus_width)-1 :(axi_burst_len*data_bus_width)-data_bus_width ]); /// write as 4 bytes (data_bus_width) .. + end + if(concurrent) + master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp); + else + master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp); + bytes = bytes - trnsfr_bytes; + addr = addr + trnsfr_bytes; + if(bytes >= (axi_burst_len * data_bus_width/8) ) + trnsfr_bytes = (axi_burst_len * data_bus_width/8); // + else + trnsfr_bytes = bytes; + + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_lngth = axi_burst_len-1; + else if(bytes%(data_bus_width/8) == 0) + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = bytes/(data_bus_width/8); + + wresp = wresp | rwrsp; + end /// while + response = wresp; +end +end +endtask + +/* Read data to file */ +task automatic read_to_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] rd_size; +output [axi_rsp_width-1:0] response; +reg [axi_rsp_width-1:0] rresp, rrrsp; +reg [addr_width-1:0] addr; +integer bytes; +integer trnsfr_lngth; +reg [(axi_burst_len*data_bus_width)-1 :0] rd_data; +integer rd_fd; +reg [id_bus_width-1:0] rd_id; + +reg [axi_size_width-1:0] siz; +reg [axi_brst_type_width-1:0] burst; +reg [axi_lock_width-1:0] lck; +reg [axi_cache_width-1:0] cache; +reg [axi_prot_width-1:0] prot; +begin +if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'read_to_file' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; +end else begin + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + + addr = start_addr; + rresp = 0; + bytes = rd_size; + + rd_id = get_id(1'b1); + + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_lngth = axi_burst_len-1; + else if(bytes%(data_bus_width/8) == 0) + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = bytes/(data_bus_width/8); + + rd_fd = $fopen(file_name,"w"); + + while (bytes > 0) begin + master.READ_BURST(rd_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, rd_data, rrrsp); + repeat(trnsfr_lngth+1) begin + $fdisplayh(rd_fd,rd_data[data_bus_width-1:0]); + rd_data = rd_data >> data_bus_width; + end + + addr = addr + (trnsfr_lngth+1)*4; + + if(bytes >= (axi_burst_len * data_bus_width/8) ) + bytes = bytes - (axi_burst_len * data_bus_width/8); // + else + bytes = 0; + + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_lngth = axi_burst_len-1; + else if(bytes%(data_bus_width/8) == 0) + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = bytes/(data_bus_width/8); + + rresp = rresp | rrrsp; + end /// while + response = rresp; +end +end +endtask + +/* Write data (used for transfer size <= 128 Bytes */ +task automatic write_data; +input [addr_width-1:0] start_addr; +input [max_transfer_bytes_width:0] wr_size; +input [(max_transfer_bytes*8)-1:0] w_data; +output [axi_rsp_width-1:0] response; +reg [axi_rsp_width-1:0] wresp,rwrsp; +reg [addr_width-1:0] addr; +reg [7:0] bytes,tmp_bytes; +integer trnsfr_bytes; +reg [(max_transfer_bytes*8)-1:0] wr_data; +integer trnsfr_lngth; +reg concurrent; + +reg [id_bus_width-1:0] wr_id; +reg [axi_size_width-1:0] siz; +reg [axi_brst_type_width-1:0] burst; +reg [axi_lock_width-1:0] lck; +reg [axi_cache_width-1:0] cache; +reg [axi_prot_width-1:0] prot; + +integer pad_bytes; +begin +if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_data' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; +end else begin + addr = start_addr; + bytes = wr_size; + wresp = 0; + wr_data = w_data; + concurrent = $random; + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0]; + wr_id = get_id(1); + if(bytes+pad_bytes > (data_bus_width/8*axi_burst_len)) begin /// for unaligned address + trnsfr_bytes = (data_bus_width*axi_burst_len)/8 - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = axi_burst_len-1; + end else begin + trnsfr_bytes = bytes; + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + end + + while (bytes > 0) begin + if(concurrent) + master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp); + else + master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp); + wr_data = wr_data >> (trnsfr_bytes*8); + bytes = bytes - trnsfr_bytes; + addr = addr + trnsfr_bytes; + if(bytes > (axi_burst_len * data_bus_width/8)) begin + trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = axi_burst_len-1; + end else begin + trnsfr_bytes = bytes; + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + end + wresp = wresp | rwrsp; + end /// while + response = wresp; +end +end +endtask + +/* Read data (used for transfer size <= 128 Bytes */ +task automatic read_data; +input [addr_width-1:0] start_addr; +input [max_transfer_bytes_width:0] rd_size; +output [(max_transfer_bytes*8)-1:0] r_data; +output [axi_rsp_width-1:0] response; +reg [axi_rsp_width-1:0] rresp,rdrsp; +reg [addr_width-1:0] addr; +reg [max_transfer_bytes_width:0] bytes,tmp_bytes; +integer trnsfr_bytes; +reg [(max_transfer_bytes*8)-1 : 0] rd_data; +reg [(axi_burst_len*data_bus_width)-1:0] rcv_rd_data; +integer total_rcvd_bytes; +integer trnsfr_lngth; +integer i; +reg [id_bus_width-1:0] rd_id; + +reg [axi_size_width-1:0] siz; +reg [axi_brst_type_width-1:0] burst; +reg [axi_lock_width-1:0] lck; +reg [axi_cache_width-1:0] cache; +reg [axi_prot_width-1:0] prot; + +integer pad_bytes; + +begin +if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'read_data' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; +end else begin + addr = start_addr; + bytes = rd_size; + rresp = 0; + total_rcvd_bytes = 0; + rd_data = 0; + rd_id = get_id(1'b1); + + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0]; + + if(bytes+ pad_bytes > (axi_burst_len * data_bus_width/8)) begin /// for unaligned address + trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = axi_burst_len-1; + end else begin + trnsfr_bytes = bytes; + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + end + while (bytes > 0) begin + master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_rd_data, rdrsp); + for(i = 0; i < trnsfr_bytes; i = i+1) begin + rd_data = rd_data >> 8; + rd_data[(max_transfer_bytes*8)-1 : (max_transfer_bytes*8)-8] = rcv_rd_data[7:0]; + rcv_rd_data = rcv_rd_data >> 8; + total_rcvd_bytes = total_rcvd_bytes+1; + end + bytes = bytes - trnsfr_bytes; + addr = addr + trnsfr_bytes; + if(bytes > (axi_burst_len * data_bus_width/8)) begin + trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = 15; + end else begin + trnsfr_bytes = bytes; + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + end + rresp = rresp | rdrsp; + end /// while + rd_data = rd_data >> (max_transfer_bytes - total_rcvd_bytes)*8; + r_data = rd_data; + response = rresp; +end +end +endtask + + +/* Wait Register Update in PL */ +/* Issue a series of 1 burst length reads until the expected data pattern is received */ + +task automatic wait_reg_update; +input [addr_width-1:0] addri; +input [data_width-1:0] datai; +input [data_width-1:0] maski; +input [int_width-1:0] time_interval; +input [int_width-1:0] time_out; +output [data_width-1:0] data_o; +output upd_done; + +reg [addr_width-1:0] addr; +reg [data_width-1:0] data_i; +reg [data_width-1:0] mask_i; +integer time_int; +integer timeout; + +reg [axi_rsp_width-1:0] rdrsp; +reg [id_bus_width-1:0] rd_id; +reg [axi_size_width-1:0] siz; +reg [axi_brst_type_width-1:0] burst; +reg [axi_lock_width-1:0] lck; +reg [axi_cache_width-1:0] cache; +reg [axi_prot_width-1:0] prot; +reg [data_width-1:0] rcv_data; +integer trnsfr_lngth; +reg rd_loop; +reg timed_out; +integer i; +integer cycle_cnt; + +begin +addr = addri; +data_i = datai; +mask_i = maski; +time_int = time_interval; +timeout = time_out; +timed_out = 0; +cycle_cnt = 0; + +if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'wait_reg_update' will not be executed...",$time, DISP_ERR, master_name); + upd_done = 0; + if(STOP_ON_ERROR) $stop; +end else begin + rd_id = get_id(1'b1); + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + trnsfr_lngth = 0; + rd_loop = 1; + fork + begin + while(!timed_out & rd_loop) begin + cycle_cnt = cycle_cnt + 1; + if(cycle_cnt >= timeout) timed_out = 1; + @(posedge M_ACLK); + end + end + begin + while (rd_loop) begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reading Register mapped at Address(0x%0h) ",$time, master_name, DISP_INFO, addr); + master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_data, rdrsp); + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reading Register returned (0x%0h) ",$time, master_name, DISP_INFO, rcv_data); + if(((rcv_data & ~mask_i) === (data_i & ~mask_i)) | timed_out) + rd_loop = 0; + else + repeat(time_int) @(posedge M_ACLK); + end /// while + end + join + data_o = rcv_data & ~mask_i; + if(timed_out) begin + $display("[%0d] : %0s : %0s : 'wait_reg_update' timed out ... Register is not updated ",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end else + upd_done = 1; +end +end +endtask + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_slave.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_slave.v new file mode 100644 index 0000000..17f1744 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_slave.v @@ -0,0 +1,935 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_axi_slave.v + * + * Date : 2012-11 + * + * Description : Model that acts as PS AXI Slave port interface. + * It uses AXI3 Slave BFM + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_axi_slave ( + S_RESETN, + + S_ARREADY, + S_AWREADY, + S_BVALID, + S_RLAST, + S_RVALID, + S_WREADY, + S_BRESP, + S_RRESP, + S_RDATA, + S_BID, + S_RID, + S_ACLK, + S_ARVALID, + S_AWVALID, + S_BREADY, + S_RREADY, + S_WLAST, + S_WVALID, + S_ARBURST, + S_ARLOCK, + S_ARSIZE, + S_AWBURST, + S_AWLOCK, + S_AWSIZE, + S_ARPROT, + S_AWPROT, + S_ARADDR, + S_AWADDR, + S_WDATA, + S_ARCACHE, + S_ARLEN, + S_AWCACHE, + S_AWLEN, + S_WSTRB, + S_ARID, + S_AWID, + S_WID, + + S_AWQOS, + S_ARQOS, + + SW_CLK, + WR_DATA_ACK_OCM, + WR_DATA_ACK_DDR, + WR_ADDR, + WR_DATA, + WR_BYTES, + WR_DATA_VALID_OCM, + WR_DATA_VALID_DDR, + WR_QOS, + + RD_QOS, + RD_REQ_DDR, + RD_REQ_OCM, + RD_REQ_REG, + RD_ADDR, + RD_DATA_OCM, + RD_DATA_DDR, + RD_DATA_REG, + RD_BYTES, + RD_DATA_VALID_OCM, + RD_DATA_VALID_DDR, + RD_DATA_VALID_REG + +); + parameter enable_this_port = 0; + parameter slave_name = "Slave"; + parameter data_bus_width = 32; + parameter address_bus_width = 32; + parameter id_bus_width = 6; + parameter slave_base_address = 0; + parameter slave_high_address = 4; + parameter max_outstanding_transactions = 8; + parameter exclusive_access_supported = 0; + parameter max_wr_outstanding_transactions = 8; + parameter max_rd_outstanding_transactions = 8; + + `include "processing_system7_bfm_v2_0_local_params.v" + + /* Local parameters only for this module */ + /* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles. + This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported. + 1-bit extra width than the no.of.bits needed to represent the outstanding transactions + Extra bit helps in generating the empty and full flags + */ + parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions+1); + parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions+1); + + /* RESP data */ + parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; + parameter rsp_lsb = 0; + parameter rsp_msb = axi_rsp_width-1; + parameter rsp_id_lsb = rsp_msb + 1; + parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1; + + input S_RESETN; + + output S_ARREADY; + output S_AWREADY; + output S_BVALID; + output S_RLAST; + output S_RVALID; + output S_WREADY; + output [axi_rsp_width-1:0] S_BRESP; + output [axi_rsp_width-1:0] S_RRESP; + output [data_bus_width-1:0] S_RDATA; + output [id_bus_width-1:0] S_BID; + output [id_bus_width-1:0] S_RID; + input S_ACLK; + input S_ARVALID; + input S_AWVALID; + input S_BREADY; + input S_RREADY; + input S_WLAST; + input S_WVALID; + input [axi_brst_type_width-1:0] S_ARBURST; + input [axi_lock_width-1:0] S_ARLOCK; + input [axi_size_width-1:0] S_ARSIZE; + input [axi_brst_type_width-1:0] S_AWBURST; + input [axi_lock_width-1:0] S_AWLOCK; + input [axi_size_width-1:0] S_AWSIZE; + input [axi_prot_width-1:0] S_ARPROT; + input [axi_prot_width-1:0] S_AWPROT; + input [address_bus_width-1:0] S_ARADDR; + input [address_bus_width-1:0] S_AWADDR; + input [data_bus_width-1:0] S_WDATA; + input [axi_cache_width-1:0] S_ARCACHE; + input [axi_cache_width-1:0] S_ARLEN; + + input [axi_qos_width-1:0] S_ARQOS; + + input [axi_cache_width-1:0] S_AWCACHE; + input [axi_len_width-1:0] S_AWLEN; + + input [axi_qos_width-1:0] S_AWQOS; + input [(data_bus_width/8)-1:0] S_WSTRB; + input [id_bus_width-1:0] S_ARID; + input [id_bus_width-1:0] S_AWID; + input [id_bus_width-1:0] S_WID; + + input SW_CLK; + input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; + output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; + output reg [max_burst_bits-1:0] WR_DATA; + output reg [addr_width-1:0] WR_ADDR; + output reg [max_burst_bytes_width:0] WR_BYTES; + output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG; + output reg [addr_width-1:0] RD_ADDR; + input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG; + output reg[max_burst_bytes_width:0] RD_BYTES; + input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG; + output reg [axi_qos_width-1:0] WR_QOS, RD_QOS; + wire net_ARVALID; + wire net_AWVALID; + wire net_WVALID; + + real s_aclk_period; + + cdn_axi3_slave_bfm #(slave_name, + data_bus_width, + address_bus_width, + id_bus_width, + slave_base_address, + (slave_high_address- slave_base_address), + max_outstanding_transactions, + 0, ///MEMORY_MODEL_MODE, + exclusive_access_supported) + slave (.ACLK (S_ACLK), + .ARESETn (S_RESETN), /// confirm this + // Write Address Channel + .AWID (S_AWID), + .AWADDR (S_AWADDR), + .AWLEN (S_AWLEN), + .AWSIZE (S_AWSIZE), + .AWBURST (S_AWBURST), + .AWLOCK (S_AWLOCK), + .AWCACHE (S_AWCACHE), + .AWPROT (S_AWPROT), + .AWVALID (net_AWVALID), + .AWREADY (S_AWREADY), + // Write Data Channel Signals. + .WID (S_WID), + .WDATA (S_WDATA), + .WSTRB (S_WSTRB), + .WLAST (S_WLAST), + .WVALID (net_WVALID), + .WREADY (S_WREADY), + // Write Response Channel Signals. + .BID (S_BID), + .BRESP (S_BRESP), + .BVALID (S_BVALID), + .BREADY (S_BREADY), + // Read Address Channel Signals. + .ARID (S_ARID), + .ARADDR (S_ARADDR), + .ARLEN (S_ARLEN), + .ARSIZE (S_ARSIZE), + .ARBURST (S_ARBURST), + .ARLOCK (S_ARLOCK), + .ARCACHE (S_ARCACHE), + .ARPROT (S_ARPROT), + .ARVALID (net_ARVALID), + .ARREADY (S_ARREADY), + // Read Data Channel Signals. + .RID (S_RID), + .RDATA (S_RDATA), + .RRESP (S_RRESP), + .RLAST (S_RLAST), + .RVALID (S_RVALID), + .RREADY (S_RREADY)); + + /* Latency type and Debug/Error Control */ + reg[1:0] latency_type = RANDOM_CASE; + reg DEBUG_INFO = 1; + reg STOP_ON_ERROR = 1'b1; + + /* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */ + reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1]; + reg [int_wr_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0; + wire wr_fifo_empty; + + /* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/ + reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0; + real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received + reg awvalid_flag[0:max_wr_outstanding_transactions]; // indicates awvalid is received + + /* Address Write Channel handshake*/ + reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid + + /* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] awsize [0:max_wr_outstanding_transactions-1]; + reg [axi_prot_width-1:0] awprot [0:max_wr_outstanding_transactions-1]; + reg [axi_lock_width-1:0] awlock [0:max_wr_outstanding_transactions-1]; + reg [axi_cache_width-1:0] awcache [0:max_wr_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] awbrst [0:max_wr_outstanding_transactions-1]; + reg [axi_len_width-1:0] awlen [0:max_wr_outstanding_transactions-1]; + reg aw_flag [0:max_wr_outstanding_transactions-1]; + reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1]; + reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1]; + reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1]; + wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached) + + /* internal fifos to store burst write data, ID & strobes*/ + reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1]; + reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer + reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag to indicate WLAST received + wire wd_fifo_full; + + /* Write Data Channel and Write Response handshake signals*/ + reg [int_wr_cntr_width-1:0] wd_cnt = 0; + reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data; + reg [addr_width-1:0] aligned_wr_addr; + reg [max_burst_bytes_width:0] valid_data_bytes; + reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0; + reg [axi_rsp_width-1:0] bresp; + reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response + reg enable_write_bresp; + reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0; + integer wr_latency_count; + reg wr_delayed; + wire bresp_fifo_empty; + + /* states for managing read/write to WR_FIFO */ + parameter SEND_DATA = 0, WAIT_ACK = 1; + reg state; + + /* Qos*/ + reg [axi_qos_width-1:0] ar_qos, aw_qos; + + initial begin + if(DEBUG_INFO) begin + if(enable_this_port) + $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name); + else + $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name); + end + end + + initial slave.set_disable_reset_value_checks(1); + initial begin + repeat(2) @(posedge S_ACLK); + if(!enable_this_port) begin + slave.set_channel_level_info(0); + slave.set_function_level_info(0); + end + slave.RESPONSE_TIMEOUT = 0; + end + /*--------------------------------------------------------------------------------*/ + + /* Set Latency type to be used */ + task set_latency_type; + input[1:0] lat; + begin + if(enable_this_port) + latency_type = lat; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set ARQoS to be used */ + task set_arqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) + ar_qos = qos; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name); + end + + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set AWQoS to be used */ + task set_awqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) + aw_qos = qos; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + /* get the wr latency number */ + function [31:0] get_wr_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min; + AVG_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg; + WORST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min); + 2'b01 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg); + default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* get the rd latency number */ + function [31:0] get_rd_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min; + AVG_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg; + WORST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min); + 2'b01 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg); + default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* Store the Clock cycle time period */ + always@(S_RESETN) + begin + if(S_RESETN) begin + @(posedge S_ACLK); + s_aclk_period = $time; + @(posedge S_ACLK); + s_aclk_period = $time - s_aclk_period; + end + end + /*--------------------------------------------------------------------------------*/ + + /* Check for any WRITE/READs when this port is disabled */ + always@(S_AWVALID or S_WVALID or S_ARVALID) + begin + if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name); + $stop; + end + end + + /*--------------------------------------------------------------------------------*/ + + + assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0; + assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0; + assign net_WVALID = enable_this_port ? S_WVALID : 1'b0; + + assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0; + assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this + assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this + assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0; + + + /* Store the awvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID ) + begin + if(!S_RESETN) + aw_time_cnt = 0; + else begin + if(S_AWVALID) begin + awvalid_receive_time[aw_time_cnt] = $time; + awvalid_flag[aw_time_cnt] = 1'b1; + aw_time_cnt = aw_time_cnt + 1; + if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt = 0; + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_AWVALID && S_AWREADY) begin + if(S_AWQOS === 0) awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos; + else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS; + end + end + /*--------------------------------------------------------------------------------*/ + + always@(aw_fifo_full) + begin + if(aw_fifo_full && DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions); + end + /*--------------------------------------------------------------------------------*/ + + /* Address Write Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + aw_cnt = 0; + end else begin + if(!aw_fifo_full) begin + slave.RECEIVE_WRITE_ADDRESS(0, + id_invalid, + awaddr[aw_cnt[int_wr_cntr_width-2:0]], + awlen[aw_cnt[int_wr_cntr_width-2:0]], + awsize[aw_cnt[int_wr_cntr_width-2:0]], + awbrst[aw_cnt[int_wr_cntr_width-2:0]], + awlock[aw_cnt[int_wr_cntr_width-2:0]], + awcache[aw_cnt[int_wr_cntr_width-2:0]], + awprot[aw_cnt[int_wr_cntr_width-2:0]], + awid[aw_cnt[int_wr_cntr_width-2:0]]); /// sampled valid ID. + aw_flag[aw_cnt[int_wr_cntr_width-2:0]] = 1; + aw_cnt = aw_cnt + 1; + if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + aw_cnt[int_wr_cntr_width-1] = ~aw_cnt[int_wr_cntr_width-1]; + aw_cnt[int_wr_cntr_width-2:0] = 0; + end + end // if (!aw_fifo_full) + end /// if else + end /// always + /*--------------------------------------------------------------------------------*/ + + /* Write Data Channel Handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wd_cnt = 0; + end else begin + if(!wd_fifo_full && S_WVALID) begin + slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, + burst_data[wd_cnt[int_wr_cntr_width-2:0]], + burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]]); + wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1'b1; + wd_cnt = wd_cnt + 1; + if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1]; + wd_cnt[int_wr_cntr_width-2:0] = 0; + end + end /// if + end /// else + end /// always + /*--------------------------------------------------------------------------------*/ + + /* Align the wrap data for write transaction */ + task automatic get_wrap_aligned_wr_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + output [addr_width-1:0] start_addr; /// aligned start address + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8)); + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data << 8; + temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8]; + wrp_data = wrp_data << 8; + wrp_bytes = wrp_bytes - 1; + end + wrp_bytes = addr - start_addr; + wrp_data = b_data << (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Calculate the Response for each read/write transaction */ + function [axi_rsp_width-1:0] calculate_resp; + input rd_wr; // indicates Read(1) or Write(0) transaction + input [addr_width-1:0] awaddr; + input [axi_prot_width-1:0] awprot; + reg [axi_rsp_width-1:0] rsp; + begin + rsp = AXI_OK; + /* Address Decode */ + if(decode_address(awaddr) === INVALID_MEM_TYPE) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr); + end + if(!rd_wr && decode_address(awaddr) === REG_MEM) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr); + end + if(secure_access_enabled && awprot[1]) + rsp = AXI_DEC_ERR; // decode error + calculate_resp = rsp; + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* Store the Write response for each write transaction */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wr_bresp_cnt = 0; + wr_fifo_wr_ptr = 0; + end else begin + enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + /* calculate bresp only when AWVALID && WLAST is received */ + if(enable_write_bresp) begin + aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0; + wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0; + + bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]); + fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp}; + /* Fill WR data FIFO */ + if(bresp === AXI_OK) begin + if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data + get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address + end else begin + aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ; + end + valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + end else + valid_data_bytes = 0; + + wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1; + wr_bresp_cnt = wr_bresp_cnt+1; + if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + wr_bresp_cnt[int_wr_cntr_width-1] = ~ wr_bresp_cnt[int_wr_cntr_width-1]; + wr_bresp_cnt[int_wr_cntr_width-2:0] = 0; + end + end + end // else + end // always + /*--------------------------------------------------------------------------------*/ + + /* Send Write Response Channel handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + rd_bresp_cnt = 0; + wr_latency_count = get_wr_lat_number(1); + wr_delayed = 0; + bresp_time_cnt = 0; + end else begin + wr_delayed = 1'b0; + if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count)) + wr_delayed = 1; + if(!bresp_fifo_empty && wr_delayed) begin + slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID + fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response + ); + wr_delayed = 0; + awvalid_flag[bresp_time_cnt] = 1'b0; + bresp_time_cnt = bresp_time_cnt+1; + rd_bresp_cnt = rd_bresp_cnt + 1; + if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + rd_bresp_cnt[int_wr_cntr_width-1] = ~ rd_bresp_cnt[int_wr_cntr_width-1]; + rd_bresp_cnt[int_wr_cntr_width-2:0] = 0; + end + if(bresp_time_cnt === max_wr_outstanding_transactions) begin + bresp_time_cnt = 0; + end + wr_latency_count = get_wr_lat_number(1); + end + end // else + end//always + /*--------------------------------------------------------------------------------*/ + + /* Reading from the wr_fifo */ + always@(negedge S_RESETN or posedge SW_CLK) begin + if(!S_RESETN) begin + WR_DATA_VALID_DDR = 1'b0; + WR_DATA_VALID_OCM = 1'b0; + wr_fifo_rd_ptr = 0; + state = SEND_DATA; + WR_QOS = 0; + end else begin + case(state) + SEND_DATA :begin + state = SEND_DATA; + WR_DATA_VALID_OCM = 0; + WR_DATA_VALID_DDR = 0; + if(!wr_fifo_empty) begin + WR_DATA = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb]; + WR_ADDR = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]; + WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb]; + WR_QOS = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb]; + state = WAIT_ACK; + case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb])) + OCM_MEM : WR_DATA_VALID_OCM = 1; + DDR_MEM : WR_DATA_VALID_DDR = 1; + default : state = SEND_DATA; + endcase + wr_fifo_rd_ptr = wr_fifo_rd_ptr+1; + end + end + WAIT_ACK :begin + state = WAIT_ACK; + if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin + WR_DATA_VALID_OCM = 1'b0; + WR_DATA_VALID_DDR = 1'b0; + state = SEND_DATA; + end + end + endcase + end + end + /*--------------------------------------------------------------------------------*/ +/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/ + +/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/ + + /* READ CHANNELS */ + /* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */ + reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0; + real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received + reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received + reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info + + /* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] arsize [0:max_rd_outstanding_transactions-1]; + reg [axi_prot_width-1:0] arprot [0:max_rd_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] arbrst [0:max_rd_outstanding_transactions-1]; + reg [axi_len_width-1:0] arlen [0:max_rd_outstanding_transactions-1]; + reg [axi_cache_width-1:0] arcache [0:max_rd_outstanding_transactions-1]; + reg [axi_lock_width-1:0] arlock [0:max_rd_outstanding_transactions-1]; + reg ar_flag [0:max_rd_outstanding_transactions-1]; + reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1]; + reg [id_bus_width-1:0] arid [0:max_rd_outstanding_transactions-1]; + reg [axi_qos_width-1:0] arqos [0:max_rd_outstanding_transactions-1]; + wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached) + + reg [int_rd_cntr_width-1:0] rd_cnt = 0; + reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0; + reg [axi_rsp_width-1:0] rresp; + reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response + + /* Send Read Response & Data Channel handshake */ + integer rd_latency_count; + reg rd_delayed; + + reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data .. + reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0; + wire read_fifo_full; + + assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1'b1: 1'b0; + assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0; + assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1'b1 :1'b0; + + /* Store the arvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID ) + begin + if(!S_RESETN) + ar_time_cnt = 0; + else begin + if(S_ARVALID) begin + arvalid_receive_time[ar_time_cnt] = $time; + arvalid_flag[ar_time_cnt] = 1'b1; + ar_time_cnt = ar_time_cnt + 1; + if(ar_time_cnt === max_rd_outstanding_transactions) + ar_time_cnt = 0; + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_ARVALID && S_ARREADY) begin + if(S_ARQOS === 0) arqos[aw_cnt[int_rd_cntr_width-2:0]] = ar_qos; + else arqos[aw_cnt[int_rd_cntr_width-2:0]] = S_ARQOS; + end + end + /*--------------------------------------------------------------------------------*/ + + always@(ar_fifo_full) + begin + if(ar_fifo_full && DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions); + end + /*--------------------------------------------------------------------------------*/ + + /* Address Read Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + ar_cnt = 0; + end else begin + if(!ar_fifo_full) begin + slave.RECEIVE_READ_ADDRESS(0, + id_invalid, + araddr[ar_cnt[int_rd_cntr_width-2:0]], + arlen[ar_cnt[int_rd_cntr_width-2:0]], + arsize[ar_cnt[int_rd_cntr_width-2:0]], + arbrst[ar_cnt[int_rd_cntr_width-2:0]], + arlock[ar_cnt[int_rd_cntr_width-2:0]], + arcache[ar_cnt[int_rd_cntr_width-2:0]], + arprot[ar_cnt[int_rd_cntr_width-2:0]], + arid[ar_cnt[int_rd_cntr_width-2:0]]); /// sampled valid ID. + ar_flag[ar_cnt[int_rd_cntr_width-2:0]] = 1'b1; + ar_cnt = ar_cnt+1; + if(ar_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin + ar_cnt[int_rd_cntr_width-1] = ~ ar_cnt[int_rd_cntr_width-1]; + ar_cnt[int_rd_cntr_width-2:0] = 0; + end + end /// if(!ar_fifo_full) + end /// if else + end /// always*/ + /*--------------------------------------------------------------------------------*/ + + /* Align Wrap data for read transaction*/ + task automatic get_wrap_aligned_rd_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [addr_width-1:0] start_addr; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data >> 8; + temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0]; + wrp_data = wrp_data >> 8; + wrp_bytes = wrp_bytes - 1; + end + temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8)); + wrp_bytes = addr - start_addr; + wrp_data = b_data >> (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1; + reg [addr_width-1:0] temp_read_address; + reg [max_burst_bytes_width:0] temp_rd_valid_bytes; + reg rd_fifo_state; + reg invalid_rd_req; + /* get the data from memory && also calculate the rresp*/ + always@(negedge S_RESETN or posedge SW_CLK) + begin + if(!S_RESETN)begin + rd_fifo_wr_ptr = 0; + wr_rresp_cnt =0; + rd_fifo_state = RD_DATA_REQ; + temp_rd_valid_bytes = 0; + temp_read_address = 0; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + invalid_rd_req = 0; + end else begin + case(rd_fifo_state) + RD_DATA_REQ : begin + rd_fifo_state = RD_DATA_REQ; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin + ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] = 0; + rresp = calculate_resp(1'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]); + fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] = {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp}; + temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8; + + if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin + temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes; + else + temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + if(rresp === AXI_OK) begin + case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]); + OCM_MEM : RD_REQ_OCM = 1; + DDR_MEM : RD_REQ_DDR = 1; + REG_MEM : RD_REQ_REG = 1; + default : invalid_rd_req = 1; + endcase + end else + invalid_rd_req = 1; + + RD_QOS = arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + RD_BYTES = temp_rd_valid_bytes; + rd_fifo_state = WAIT_RD_VALID; + wr_rresp_cnt = wr_rresp_cnt + 1; + if(wr_rresp_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin + wr_rresp_cnt[int_rd_cntr_width-1] = ~ wr_rresp_cnt[int_rd_cntr_width-1]; + wr_rresp_cnt[int_rd_cntr_width-2:0] = 0; + end + end + end + WAIT_RD_VALID : begin + rd_fifo_state = WAIT_RD_VALID; + if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2'b11) begin + if(RD_DATA_VALID_DDR) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_DDR; + else if(RD_DATA_VALID_OCM) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_OCM; + else if(RD_DATA_VALID_REG) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_REG; + else + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = 0; + rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + invalid_rd_req = 0; + rd_fifo_state = RD_DATA_REQ; + end + end + endcase + end /// else + end /// always + + /*--------------------------------------------------------------------------------*/ + reg[max_burst_bytes_width:0] rd_v_b; + reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data; + reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data; + reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp; + + /* Read Data Channel handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN)begin + rd_fifo_rd_ptr = 0; + rd_cnt = 0; + rd_latency_count = get_rd_lat_number(1); + rd_delayed = 0; + rresp_time_cnt = 0; + rd_v_b = 0; + end else begin + if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) + rd_delayed = 1; + if(!read_fifo_empty && rd_delayed)begin + rd_delayed = 0; + arvalid_flag[rresp_time_cnt] = 1'b0; + rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]])); + temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]]; + rd_fifo_rd_ptr = rd_fifo_rd_ptr+1; + + if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin + get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b); + temp_read_data = temp_wrap_data; + end + temp_read_rsp = 0; + repeat(axi_burst_len) begin + temp_read_rsp = temp_read_rsp >> axi_rsp_width; + temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb]; + end + slave.SEND_READ_BURST_RESP_CTRL(arid[rd_cnt[int_rd_cntr_width-2:0]], + araddr[rd_cnt[int_rd_cntr_width-2:0]], + arlen[rd_cnt[int_rd_cntr_width-2:0]], + arsize[rd_cnt[int_rd_cntr_width-2:0]], + arbrst[rd_cnt[int_rd_cntr_width-2:0]], + temp_read_data, + temp_read_rsp); + rd_cnt = rd_cnt + 1; + rresp_time_cnt = rresp_time_cnt+1; + if(rresp_time_cnt === max_rd_outstanding_transactions) rresp_time_cnt = 0; + if(rd_cnt[int_rd_cntr_width-2:0] === (max_rd_outstanding_transactions-1)) begin + rd_cnt[int_rd_cntr_width-1] = ~ rd_cnt[int_rd_cntr_width-1]; + rd_cnt[int_rd_cntr_width-2:0] = 0; + end + rd_latency_count = get_rd_lat_number(1); + end + end /// else + end /// always +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ddrc.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ddrc.v new file mode 100644 index 0000000..e244c9d --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ddrc.v @@ -0,0 +1,268 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_ddrc.v + * + * Date : 2012-11 + * + * Description : Module that acts as controller for sparse memory (DDR). + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_ddrc( + rstn, + sw_clk, + +/* Goes to port 0 of DDR */ + ddr_wr_ack_port0, + ddr_wr_dv_port0, + ddr_rd_req_port0, + ddr_rd_dv_port0, + ddr_wr_addr_port0, + ddr_wr_data_port0, + ddr_wr_bytes_port0, + ddr_rd_addr_port0, + ddr_rd_data_port0, + ddr_rd_bytes_port0, + ddr_wr_qos_port0, + ddr_rd_qos_port0, + + +/* Goes to port 1 of DDR */ + ddr_wr_ack_port1, + ddr_wr_dv_port1, + ddr_rd_req_port1, + ddr_rd_dv_port1, + ddr_wr_addr_port1, + ddr_wr_data_port1, + ddr_wr_bytes_port1, + ddr_rd_addr_port1, + ddr_rd_data_port1, + ddr_rd_bytes_port1, + ddr_wr_qos_port1, + ddr_rd_qos_port1, + +/* Goes to port2 of DDR */ + ddr_wr_ack_port2, + ddr_wr_dv_port2, + ddr_rd_req_port2, + ddr_rd_dv_port2, + ddr_wr_addr_port2, + ddr_wr_data_port2, + ddr_wr_bytes_port2, + ddr_rd_addr_port2, + ddr_rd_data_port2, + ddr_rd_bytes_port2, + ddr_wr_qos_port2, + ddr_rd_qos_port2, + +/* Goes to port3 of DDR */ + ddr_wr_ack_port3, + ddr_wr_dv_port3, + ddr_rd_req_port3, + ddr_rd_dv_port3, + ddr_wr_addr_port3, + ddr_wr_data_port3, + ddr_wr_bytes_port3, + ddr_rd_addr_port3, + ddr_rd_data_port3, + ddr_rd_bytes_port3, + ddr_wr_qos_port3, + ddr_rd_qos_port3 + +); + +`include "processing_system7_bfm_v2_0_local_params.v" + +input rstn; +input sw_clk; + +output ddr_wr_ack_port0; +input ddr_wr_dv_port0; +input ddr_rd_req_port0; +output ddr_rd_dv_port0; +input[addr_width-1:0] ddr_wr_addr_port0; +input[max_burst_bits-1:0] ddr_wr_data_port0; +input[max_burst_bytes_width:0] ddr_wr_bytes_port0; +input[addr_width-1:0] ddr_rd_addr_port0; +output[max_burst_bits-1:0] ddr_rd_data_port0; +input[max_burst_bytes_width:0] ddr_rd_bytes_port0; +input [axi_qos_width-1:0] ddr_wr_qos_port0; +input [axi_qos_width-1:0] ddr_rd_qos_port0; + +output ddr_wr_ack_port1; +input ddr_wr_dv_port1; +input ddr_rd_req_port1; +output ddr_rd_dv_port1; +input[addr_width-1:0] ddr_wr_addr_port1; +input[max_burst_bits-1:0] ddr_wr_data_port1; +input[max_burst_bytes_width:0] ddr_wr_bytes_port1; +input[addr_width-1:0] ddr_rd_addr_port1; +output[max_burst_bits-1:0] ddr_rd_data_port1; +input[max_burst_bytes_width:0] ddr_rd_bytes_port1; +input[axi_qos_width-1:0] ddr_wr_qos_port1; +input[axi_qos_width-1:0] ddr_rd_qos_port1; + +output ddr_wr_ack_port2; +input ddr_wr_dv_port2; +input ddr_rd_req_port2; +output ddr_rd_dv_port2; +input[addr_width-1:0] ddr_wr_addr_port2; +input[max_burst_bits-1:0] ddr_wr_data_port2; +input[max_burst_bytes_width:0] ddr_wr_bytes_port2; +input[addr_width-1:0] ddr_rd_addr_port2; +output[max_burst_bits-1:0] ddr_rd_data_port2; +input[max_burst_bytes_width:0] ddr_rd_bytes_port2; +input[axi_qos_width-1:0] ddr_wr_qos_port2; +input[axi_qos_width-1:0] ddr_rd_qos_port2; + +output ddr_wr_ack_port3; +input ddr_wr_dv_port3; +input ddr_rd_req_port3; +output ddr_rd_dv_port3; +input[addr_width-1:0] ddr_wr_addr_port3; +input[max_burst_bits-1:0] ddr_wr_data_port3; +input[max_burst_bytes_width:0] ddr_wr_bytes_port3; +input[addr_width-1:0] ddr_rd_addr_port3; +output[max_burst_bits-1:0] ddr_rd_data_port3; +input[max_burst_bytes_width:0] ddr_rd_bytes_port3; +input[axi_qos_width-1:0] ddr_wr_qos_port3; +input[axi_qos_width-1:0] ddr_rd_qos_port3; + +wire [axi_qos_width-1:0] wr_qos; +wire wr_req; +wire [max_burst_bits-1:0] wr_data; +wire [addr_width-1:0] wr_addr; +wire [max_burst_bytes_width:0] wr_bytes; +reg wr_ack; + +wire [axi_qos_width-1:0] rd_qos; +reg [max_burst_bits-1:0] rd_data; +wire [addr_width-1:0] rd_addr; +wire [max_burst_bytes_width:0] rd_bytes; +reg rd_dv; +wire rd_req; + +processing_system7_bfm_v2_0_arb_wr_4 ddr_write_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ddr_wr_qos_port0), + .qos2(ddr_wr_qos_port1), + .qos3(ddr_wr_qos_port2), + .qos4(ddr_wr_qos_port3), + + .prt_dv1(ddr_wr_dv_port0), + .prt_dv2(ddr_wr_dv_port1), + .prt_dv3(ddr_wr_dv_port2), + .prt_dv4(ddr_wr_dv_port3), + + .prt_data1(ddr_wr_data_port0), + .prt_data2(ddr_wr_data_port1), + .prt_data3(ddr_wr_data_port2), + .prt_data4(ddr_wr_data_port3), + + .prt_addr1(ddr_wr_addr_port0), + .prt_addr2(ddr_wr_addr_port1), + .prt_addr3(ddr_wr_addr_port2), + .prt_addr4(ddr_wr_addr_port3), + + .prt_bytes1(ddr_wr_bytes_port0), + .prt_bytes2(ddr_wr_bytes_port1), + .prt_bytes3(ddr_wr_bytes_port2), + .prt_bytes4(ddr_wr_bytes_port3), + + .prt_ack1(ddr_wr_ack_port0), + .prt_ack2(ddr_wr_ack_port1), + .prt_ack3(ddr_wr_ack_port2), + .prt_ack4(ddr_wr_ack_port3), + + .prt_qos(wr_qos), + .prt_req(wr_req), + .prt_data(wr_data), + .prt_addr(wr_addr), + .prt_bytes(wr_bytes), + .prt_ack(wr_ack) + +); + +processing_system7_bfm_v2_0_arb_rd_4 ddr_read_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ddr_rd_qos_port0), + .qos2(ddr_rd_qos_port1), + .qos3(ddr_rd_qos_port2), + .qos4(ddr_rd_qos_port3), + + .prt_req1(ddr_rd_req_port0), + .prt_req2(ddr_rd_req_port1), + .prt_req3(ddr_rd_req_port2), + .prt_req4(ddr_rd_req_port3), + + .prt_data1(ddr_rd_data_port0), + .prt_data2(ddr_rd_data_port1), + .prt_data3(ddr_rd_data_port2), + .prt_data4(ddr_rd_data_port3), + + .prt_addr1(ddr_rd_addr_port0), + .prt_addr2(ddr_rd_addr_port1), + .prt_addr3(ddr_rd_addr_port2), + .prt_addr4(ddr_rd_addr_port3), + + .prt_bytes1(ddr_rd_bytes_port0), + .prt_bytes2(ddr_rd_bytes_port1), + .prt_bytes3(ddr_rd_bytes_port2), + .prt_bytes4(ddr_rd_bytes_port3), + + .prt_dv1(ddr_rd_dv_port0), + .prt_dv2(ddr_rd_dv_port1), + .prt_dv3(ddr_rd_dv_port2), + .prt_dv4(ddr_rd_dv_port3), + + .prt_qos(rd_qos), + .prt_req(rd_req), + .prt_data(rd_data), + .prt_addr(rd_addr), + .prt_bytes(rd_bytes), + .prt_dv(rd_dv) + +); + +processing_system7_bfm_v2_0_sparse_mem ddr(); + +reg [1:0] state; +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + wr_ack <= 0; + rd_dv <= 0; + state <= 2'd0; +end else begin + case(state) + 0:begin + state <= 0; + wr_ack <= 0; + rd_dv <= 0; + if(wr_req) begin + ddr.write_mem(wr_data , wr_addr, wr_bytes); + wr_ack <= 1; + state <= 1; + end + if(rd_req) begin + ddr.read_mem(rd_data,rd_addr, rd_bytes); + rd_dv <= 1; + state <= 1; + end + + end + 1:begin + wr_ack <= 0; + rd_dv <= 0; + state <= 0; + end + + endcase +end /// if +end// always + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_fmsw_gp.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_fmsw_gp.v new file mode 100644 index 0000000..00de7ba --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_fmsw_gp.v @@ -0,0 +1,300 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_fmsw_gp.v + * + * Date : 2012-11 + * + * Description : Mimics FMSW switch. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_fmsw_gp( + sw_clk, + rstn, + + w_qos_gp0, + r_qos_gp0, + wr_ack_ocm_gp0, + wr_ack_ddr_gp0, + wr_data_gp0, + wr_addr_gp0, + wr_bytes_gp0, + wr_dv_ocm_gp0, + wr_dv_ddr_gp0, + rd_req_ocm_gp0, + rd_req_ddr_gp0, + rd_req_reg_gp0, + rd_addr_gp0, + rd_bytes_gp0, + rd_data_ocm_gp0, + rd_data_ddr_gp0, + rd_data_reg_gp0, + rd_dv_ocm_gp0, + rd_dv_ddr_gp0, + rd_dv_reg_gp0, + + w_qos_gp1, + r_qos_gp1, + wr_ack_ocm_gp1, + wr_ack_ddr_gp1, + wr_data_gp1, + wr_addr_gp1, + wr_bytes_gp1, + wr_dv_ocm_gp1, + wr_dv_ddr_gp1, + rd_req_ocm_gp1, + rd_req_ddr_gp1, + rd_req_reg_gp1, + rd_addr_gp1, + rd_bytes_gp1, + rd_data_ocm_gp1, + rd_data_ddr_gp1, + rd_data_reg_gp1, + rd_dv_ocm_gp1, + rd_dv_ddr_gp1, + rd_dv_reg_gp1, + + ocm_wr_ack, + ocm_wr_dv, + ocm_rd_req, + ocm_rd_dv, + ddr_wr_ack, + ddr_wr_dv, + ddr_rd_req, + ddr_rd_dv, + + reg_rd_req, + reg_rd_dv, + + ocm_wr_qos, + ddr_wr_qos, + ocm_rd_qos, + ddr_rd_qos, + reg_rd_qos, + + ocm_wr_addr, + ocm_wr_data, + ocm_wr_bytes, + ocm_rd_addr, + ocm_rd_data, + ocm_rd_bytes, + + ddr_wr_addr, + ddr_wr_data, + ddr_wr_bytes, + ddr_rd_addr, + ddr_rd_data, + ddr_rd_bytes, + + reg_rd_addr, + reg_rd_data, + reg_rd_bytes + +); + +`include "processing_system7_bfm_v2_0_local_params.v" + +input sw_clk; +input rstn; + +input [axi_qos_width-1:0]w_qos_gp0; +input [axi_qos_width-1:0]r_qos_gp0; +input [axi_qos_width-1:0]w_qos_gp1; +input [axi_qos_width-1:0]r_qos_gp1; + +output [axi_qos_width-1:0]ocm_wr_qos; +output [axi_qos_width-1:0]ocm_rd_qos; +output [axi_qos_width-1:0]ddr_wr_qos; +output [axi_qos_width-1:0]ddr_rd_qos; +output [axi_qos_width-1:0]reg_rd_qos; + +output wr_ack_ocm_gp0; +output wr_ack_ddr_gp0; +input [max_burst_bits-1:0] wr_data_gp0; +input [addr_width-1:0] wr_addr_gp0; +input [max_burst_bytes_width:0] wr_bytes_gp0; +output wr_dv_ocm_gp0; +output wr_dv_ddr_gp0; + +input rd_req_ocm_gp0; +input rd_req_ddr_gp0; +input rd_req_reg_gp0; +input [addr_width-1:0] rd_addr_gp0; +input [max_burst_bytes_width:0] rd_bytes_gp0; +output [max_burst_bits-1:0] rd_data_ocm_gp0; +output [max_burst_bits-1:0] rd_data_ddr_gp0; +output [max_burst_bits-1:0] rd_data_reg_gp0; +output rd_dv_ocm_gp0; +output rd_dv_ddr_gp0; +output rd_dv_reg_gp0; + +output wr_ack_ocm_gp1; +output wr_ack_ddr_gp1; +input [max_burst_bits-1:0] wr_data_gp1; +input [addr_width-1:0] wr_addr_gp1; +input [max_burst_bytes_width:0] wr_bytes_gp1; +output wr_dv_ocm_gp1; +output wr_dv_ddr_gp1; + +input rd_req_ocm_gp1; +input rd_req_ddr_gp1; +input rd_req_reg_gp1; +input [addr_width-1:0] rd_addr_gp1; +input [max_burst_bytes_width:0] rd_bytes_gp1; +output [max_burst_bits-1:0] rd_data_ocm_gp1; +output [max_burst_bits-1:0] rd_data_ddr_gp1; +output [max_burst_bits-1:0] rd_data_reg_gp1; +output rd_dv_ocm_gp1; +output rd_dv_ddr_gp1; +output rd_dv_reg_gp1; + + +input ocm_wr_ack; +output ocm_wr_dv; +output [addr_width-1:0]ocm_wr_addr; +output [max_burst_bits-1:0]ocm_wr_data; +output [max_burst_bytes_width:0]ocm_wr_bytes; + +input ocm_rd_dv; +input [max_burst_bits-1:0] ocm_rd_data; +output ocm_rd_req; +output [addr_width-1:0] ocm_rd_addr; +output [max_burst_bytes_width:0] ocm_rd_bytes; + +input ddr_wr_ack; +output ddr_wr_dv; +output [addr_width-1:0]ddr_wr_addr; +output [max_burst_bits-1:0]ddr_wr_data; +output [max_burst_bytes_width:0]ddr_wr_bytes; + +input ddr_rd_dv; +input [max_burst_bits-1:0] ddr_rd_data; +output ddr_rd_req; +output [addr_width-1:0] ddr_rd_addr; +output [max_burst_bytes_width:0] ddr_rd_bytes; + +input reg_rd_dv; +input [max_burst_bits-1:0] reg_rd_data; +output reg_rd_req; +output [addr_width-1:0] reg_rd_addr; +output [max_burst_bytes_width:0] reg_rd_bytes; + + + +processing_system7_bfm_v2_0_arb_wr ocm_gp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_gp0), + .qos2(w_qos_gp1), + .prt_dv1(wr_dv_ocm_gp0), + .prt_dv2(wr_dv_ocm_gp1), + .prt_data1(wr_data_gp0), + .prt_data2(wr_data_gp1), + .prt_addr1(wr_addr_gp0), + .prt_addr2(wr_addr_gp1), + .prt_bytes1(wr_bytes_gp0), + .prt_bytes2(wr_bytes_gp1), + .prt_ack1(wr_ack_ocm_gp0), + .prt_ack2(wr_ack_ocm_gp1), + .prt_req(ocm_wr_dv), + .prt_qos(ocm_wr_qos), + .prt_data(ocm_wr_data), + .prt_addr(ocm_wr_addr), + .prt_bytes(ocm_wr_bytes), + .prt_ack(ocm_wr_ack) +); + +processing_system7_bfm_v2_0_arb_wr ddr_gp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_gp0), + .qos2(w_qos_gp1), + .prt_dv1(wr_dv_ddr_gp0), + .prt_dv2(wr_dv_ddr_gp1), + .prt_data1(wr_data_gp0), + .prt_data2(wr_data_gp1), + .prt_addr1(wr_addr_gp0), + .prt_addr2(wr_addr_gp1), + .prt_bytes1(wr_bytes_gp0), + .prt_bytes2(wr_bytes_gp1), + .prt_ack1(wr_ack_ddr_gp0), + .prt_ack2(wr_ack_ddr_gp1), + .prt_req(ddr_wr_dv), + .prt_qos(ddr_wr_qos), + .prt_data(ddr_wr_data), + .prt_addr(ddr_wr_addr), + .prt_bytes(ddr_wr_bytes), + .prt_ack(ddr_wr_ack) +); + +processing_system7_bfm_v2_0_arb_rd ocm_gp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_gp0), + .qos2(r_qos_gp1), + .prt_req1(rd_req_ocm_gp0), + .prt_req2(rd_req_ocm_gp1), + .prt_data1(rd_data_ocm_gp0), + .prt_data2(rd_data_ocm_gp1), + .prt_addr1(rd_addr_gp0), + .prt_addr2(rd_addr_gp1), + .prt_bytes1(rd_bytes_gp0), + .prt_bytes2(rd_bytes_gp1), + .prt_dv1(rd_dv_ocm_gp0), + .prt_dv2(rd_dv_ocm_gp1), + .prt_req(ocm_rd_req), + .prt_qos(ocm_rd_qos), + .prt_data(ocm_rd_data), + .prt_addr(ocm_rd_addr), + .prt_bytes(ocm_rd_bytes), + .prt_dv(ocm_rd_dv) +); + +processing_system7_bfm_v2_0_arb_rd ddr_gp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_gp0), + .qos2(r_qos_gp1), + .prt_req1(rd_req_ddr_gp0), + .prt_req2(rd_req_ddr_gp1), + .prt_data1(rd_data_ddr_gp0), + .prt_data2(rd_data_ddr_gp1), + .prt_addr1(rd_addr_gp0), + .prt_addr2(rd_addr_gp1), + .prt_bytes1(rd_bytes_gp0), + .prt_bytes2(rd_bytes_gp1), + .prt_dv1(rd_dv_ddr_gp0), + .prt_dv2(rd_dv_ddr_gp1), + .prt_req(ddr_rd_req), + .prt_qos(ddr_rd_qos), + .prt_data(ddr_rd_data), + .prt_addr(ddr_rd_addr), + .prt_bytes(ddr_rd_bytes), + .prt_dv(ddr_rd_dv) +); + +processing_system7_bfm_v2_0_arb_rd reg_gp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_gp0), + .qos2(r_qos_gp1), + .prt_req1(rd_req_reg_gp0), + .prt_req2(rd_req_reg_gp1), + .prt_data1(rd_data_reg_gp0), + .prt_data2(rd_data_reg_gp1), + .prt_addr1(rd_addr_gp0), + .prt_addr2(rd_addr_gp1), + .prt_bytes1(rd_bytes_gp0), + .prt_bytes2(rd_bytes_gp1), + .prt_dv1(rd_dv_reg_gp0), + .prt_dv2(rd_dv_reg_gp1), + .prt_req(reg_rd_req), + .prt_qos(reg_rd_qos), + .prt_data(reg_rd_data), + .prt_addr(reg_rd_addr), + .prt_bytes(reg_rd_bytes), + .prt_dv(reg_rd_dv) +); + + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_gen_clock.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_gen_clock.v new file mode 100644 index 0000000..4c94a39 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_gen_clock.v @@ -0,0 +1,58 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_gen_clock.v + * + * Date : 2012-11 + * + * Description : Module that generates FCLK clocks and internal clock for Zynq BFM. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_gen_clock( + ps_clk, + sw_clk, + + fclk_clk3, + fclk_clk2, + fclk_clk1, + fclk_clk0 +); + +input ps_clk; +output sw_clk; + +output fclk_clk3; +output fclk_clk2; +output fclk_clk1; +output fclk_clk0; + +parameter freq_clk3 = 50; +parameter freq_clk2 = 50; +parameter freq_clk1 = 50; +parameter freq_clk0 = 50; + +reg clk0 = 1'b0; +reg clk1 = 1'b0; +reg clk2 = 1'b0; +reg clk3 = 1'b0; +reg sw_clk = 1'b0; + +assign fclk_clk0 = clk0; +assign fclk_clk1 = clk1; +assign fclk_clk2 = clk2; +assign fclk_clk3 = clk3; + +real clk3_p = (1000.00/freq_clk3)/2; +real clk2_p = (1000.00/freq_clk2)/2; +real clk1_p = (1000.00/freq_clk1)/2; +real clk0_p = (1000.00/freq_clk0)/2; + +always #(clk3_p) clk3 = !clk3; +always #(clk2_p) clk2 = !clk2; +always #(clk1_p) clk1 = !clk1; +always #(clk0_p) clk0 = !clk0; + +always #(0.5) sw_clk = !sw_clk; + + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_gen_reset.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_gen_reset.v new file mode 100644 index 0000000..ea880db --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_gen_reset.v @@ -0,0 +1,225 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_gen_reset.v + * + * Date : 2012-11 + * + * Description : Module that generates FPGA_RESETs and synchronizes RESETs to the + * respective clocks. + *****************************************************************************/ + `timescale 1ns/1ps +module processing_system7_bfm_v2_0_gen_reset( + por_rst_n, + sys_rst_n, + rst_out_n, + + m_axi_gp0_clk, + m_axi_gp1_clk, + s_axi_gp0_clk, + s_axi_gp1_clk, + s_axi_hp0_clk, + s_axi_hp1_clk, + s_axi_hp2_clk, + s_axi_hp3_clk, + s_axi_acp_clk, + + m_axi_gp0_rstn, + m_axi_gp1_rstn, + s_axi_gp0_rstn, + s_axi_gp1_rstn, + s_axi_hp0_rstn, + s_axi_hp1_rstn, + s_axi_hp2_rstn, + s_axi_hp3_rstn, + s_axi_acp_rstn, + + fclk_reset3_n, + fclk_reset2_n, + fclk_reset1_n, + fclk_reset0_n, + + fpga_acp_reset_n, + fpga_gp_m0_reset_n, + fpga_gp_m1_reset_n, + fpga_gp_s0_reset_n, + fpga_gp_s1_reset_n, + fpga_hp_s0_reset_n, + fpga_hp_s1_reset_n, + fpga_hp_s2_reset_n, + fpga_hp_s3_reset_n + +); + +input por_rst_n; +input sys_rst_n; +input m_axi_gp0_clk; +input m_axi_gp1_clk; +input s_axi_gp0_clk; +input s_axi_gp1_clk; +input s_axi_hp0_clk; +input s_axi_hp1_clk; +input s_axi_hp2_clk; +input s_axi_hp3_clk; +input s_axi_acp_clk; + +output reg m_axi_gp0_rstn; +output reg m_axi_gp1_rstn; +output reg s_axi_gp0_rstn; +output reg s_axi_gp1_rstn; +output reg s_axi_hp0_rstn; +output reg s_axi_hp1_rstn; +output reg s_axi_hp2_rstn; +output reg s_axi_hp3_rstn; +output reg s_axi_acp_rstn; + +output rst_out_n; +output fclk_reset3_n; +output fclk_reset2_n; +output fclk_reset1_n; +output fclk_reset0_n; + +output fpga_acp_reset_n; +output fpga_gp_m0_reset_n; +output fpga_gp_m1_reset_n; +output fpga_gp_s0_reset_n; +output fpga_gp_s1_reset_n; +output fpga_hp_s0_reset_n; +output fpga_hp_s1_reset_n; +output fpga_hp_s2_reset_n; +output fpga_hp_s3_reset_n; + +reg [31:0] fabric_rst_n; + +reg r_m_axi_gp0_rstn; +reg r_m_axi_gp1_rstn; +reg r_s_axi_gp0_rstn; +reg r_s_axi_gp1_rstn; +reg r_s_axi_hp0_rstn; +reg r_s_axi_hp1_rstn; +reg r_s_axi_hp2_rstn; +reg r_s_axi_hp3_rstn; +reg r_s_axi_acp_rstn; + +assign rst_out_n = por_rst_n & sys_rst_n; + +assign fclk_reset0_n = !fabric_rst_n[0]; +assign fclk_reset1_n = !fabric_rst_n[1]; +assign fclk_reset2_n = !fabric_rst_n[2]; +assign fclk_reset3_n = !fabric_rst_n[3]; + +assign fpga_acp_reset_n = !fabric_rst_n[24]; + +assign fpga_hp_s3_reset_n = !fabric_rst_n[23]; +assign fpga_hp_s2_reset_n = !fabric_rst_n[22]; +assign fpga_hp_s1_reset_n = !fabric_rst_n[21]; +assign fpga_hp_s0_reset_n = !fabric_rst_n[20]; + +assign fpga_gp_s1_reset_n = !fabric_rst_n[17]; +assign fpga_gp_s0_reset_n = !fabric_rst_n[16]; +assign fpga_gp_m1_reset_n = !fabric_rst_n[13]; +assign fpga_gp_m0_reset_n = !fabric_rst_n[12]; + +task fpga_soft_reset; +input[31:0] reset_ctrl; + begin + fabric_rst_n[0] = reset_ctrl[0]; + fabric_rst_n[1] = reset_ctrl[1]; + fabric_rst_n[2] = reset_ctrl[2]; + fabric_rst_n[3] = reset_ctrl[3]; + + fabric_rst_n[12] = reset_ctrl[12]; + fabric_rst_n[13] = reset_ctrl[13]; + fabric_rst_n[16] = reset_ctrl[16]; + fabric_rst_n[17] = reset_ctrl[17]; + + fabric_rst_n[20] = reset_ctrl[20]; + fabric_rst_n[21] = reset_ctrl[21]; + fabric_rst_n[22] = reset_ctrl[22]; + fabric_rst_n[23] = reset_ctrl[23]; + + fabric_rst_n[24] = reset_ctrl[24]; + end +endtask + +always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f; + +always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + m_axi_gp0_rstn = 1'b0; + else + m_axi_gp0_rstn = 1'b1; + end + +always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + m_axi_gp1_rstn = 1'b0; + else + m_axi_gp1_rstn = 1'b1; + end + +always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_gp0_rstn = 1'b0; + else + s_axi_gp0_rstn = 1'b1; + end + +always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_gp1_rstn = 1'b0; + else + s_axi_gp1_rstn = 1'b1; + end + +always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp0_rstn = 1'b0; + else + s_axi_hp0_rstn = 1'b1; + end + +always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp1_rstn = 1'b0; + else + s_axi_hp1_rstn = 1'b1; + end + +always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp2_rstn = 1'b0; + else + s_axi_hp2_rstn = 1'b1; + end + +always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp3_rstn = 1'b0; + else + s_axi_hp3_rstn = 1'b1; + end + +always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_acp_rstn = 1'b0; + else + s_axi_acp_rstn = 1'b1; + end + + +always@(*) begin + if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin + $display(" Error:processing_system7_bfm_v2_0_gen_reset. PS_PORB and PS_SRSTB must be driven to known state"); + $finish(); + end +end + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_interconnect_model.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_interconnect_model.v new file mode 100644 index 0000000..fc04be8 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_interconnect_model.v @@ -0,0 +1,662 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_interconnect_model.v + * + * Date : 2012-11 + * + * Description : Mimics Top_interconnect Switch. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_interconnect_model ( + rstn, + sw_clk, + + w_qos_gp0, + w_qos_gp1, + w_qos_hp0, + w_qos_hp1, + w_qos_hp2, + w_qos_hp3, + + r_qos_gp0, + r_qos_gp1, + r_qos_hp0, + r_qos_hp1, + r_qos_hp2, + r_qos_hp3, + + wr_ack_ddr_gp0, + wr_ack_ocm_gp0, + wr_data_gp0, + wr_addr_gp0, + wr_bytes_gp0, + wr_dv_ddr_gp0, + wr_dv_ocm_gp0, + + rd_req_ddr_gp0, + rd_req_ocm_gp0, + rd_req_reg_gp0, + rd_addr_gp0, + rd_bytes_gp0, + rd_data_ddr_gp0, + rd_data_ocm_gp0, + rd_data_reg_gp0, + rd_dv_ddr_gp0, + rd_dv_ocm_gp0, + rd_dv_reg_gp0, + + wr_ack_ddr_gp1, + wr_ack_ocm_gp1, + wr_data_gp1, + wr_addr_gp1, + wr_bytes_gp1, + wr_dv_ddr_gp1, + wr_dv_ocm_gp1, + rd_req_ddr_gp1, + rd_req_ocm_gp1, + rd_req_reg_gp1, + rd_addr_gp1, + rd_bytes_gp1, + rd_data_ddr_gp1, + rd_data_ocm_gp1, + rd_data_reg_gp1, + rd_dv_ddr_gp1, + rd_dv_ocm_gp1, + rd_dv_reg_gp1, + + wr_ack_ddr_hp0, + wr_ack_ocm_hp0, + wr_data_hp0, + wr_addr_hp0, + wr_bytes_hp0, + wr_dv_ddr_hp0, + wr_dv_ocm_hp0, + rd_req_ddr_hp0, + rd_req_ocm_hp0, + rd_addr_hp0, + rd_bytes_hp0, + rd_data_ddr_hp0, + rd_data_ocm_hp0, + rd_dv_ddr_hp0, + rd_dv_ocm_hp0, + + wr_ack_ddr_hp1, + wr_ack_ocm_hp1, + wr_data_hp1, + wr_addr_hp1, + wr_bytes_hp1, + wr_dv_ddr_hp1, + wr_dv_ocm_hp1, + rd_req_ddr_hp1, + rd_req_ocm_hp1, + rd_addr_hp1, + rd_bytes_hp1, + rd_data_ddr_hp1, + rd_data_ocm_hp1, + rd_dv_ddr_hp1, + rd_dv_ocm_hp1, + + wr_ack_ddr_hp2, + wr_ack_ocm_hp2, + wr_data_hp2, + wr_addr_hp2, + wr_bytes_hp2, + wr_dv_ddr_hp2, + wr_dv_ocm_hp2, + rd_req_ddr_hp2, + rd_req_ocm_hp2, + rd_addr_hp2, + rd_bytes_hp2, + rd_data_ddr_hp2, + rd_data_ocm_hp2, + rd_dv_ddr_hp2, + rd_dv_ocm_hp2, + + wr_ack_ddr_hp3, + wr_ack_ocm_hp3, + wr_data_hp3, + wr_addr_hp3, + wr_bytes_hp3, + wr_dv_ddr_hp3, + wr_dv_ocm_hp3, + rd_req_ddr_hp3, + rd_req_ocm_hp3, + rd_addr_hp3, + rd_bytes_hp3, + rd_data_ddr_hp3, + rd_data_ocm_hp3, + rd_dv_ddr_hp3, + rd_dv_ocm_hp3, + +/* Goes to port 1 of DDR */ + ddr_wr_ack_port1, + ddr_wr_dv_port1, + ddr_rd_req_port1, + ddr_rd_dv_port1, + ddr_wr_addr_port1, + ddr_wr_data_port1, + ddr_wr_bytes_port1, + ddr_rd_addr_port1, + ddr_rd_data_port1, + ddr_rd_bytes_port1, + ddr_wr_qos_port1, + ddr_rd_qos_port1, + +/* Goes to port2 of DDR */ + ddr_wr_ack_port2, + ddr_wr_dv_port2, + ddr_rd_req_port2, + ddr_rd_dv_port2, + ddr_wr_addr_port2, + ddr_wr_data_port2, + ddr_wr_bytes_port2, + ddr_rd_addr_port2, + ddr_rd_data_port2, + ddr_rd_bytes_port2, + ddr_wr_qos_port2, + ddr_rd_qos_port2, + +/* Goes to port3 of DDR */ + ddr_wr_ack_port3, + ddr_wr_dv_port3, + ddr_rd_req_port3, + ddr_rd_dv_port3, + ddr_wr_addr_port3, + ddr_wr_data_port3, + ddr_wr_bytes_port3, + ddr_rd_addr_port3, + ddr_rd_data_port3, + ddr_rd_bytes_port3, + ddr_wr_qos_port3, + ddr_rd_qos_port3, + +/* Goes to port1 of OCM */ + ocm_wr_qos_port1, + ocm_rd_qos_port1, + ocm_wr_dv_port1, + ocm_wr_data_port1, + ocm_wr_addr_port1, + ocm_wr_bytes_port1, + ocm_wr_ack_port1, + ocm_rd_req_port1, + ocm_rd_data_port1, + ocm_rd_addr_port1, + ocm_rd_bytes_port1, + ocm_rd_dv_port1, + +/* Goes to port1 for RegMap */ + reg_rd_qos_port1, + reg_rd_req_port1, + reg_rd_data_port1, + reg_rd_addr_port1, + reg_rd_bytes_port1, + reg_rd_dv_port1 + +); +`include "processing_system7_bfm_v2_0_local_params.v" + +input rstn; +input sw_clk; + +input [axi_qos_width-1:0] w_qos_gp0; +input [axi_qos_width-1:0] w_qos_gp1; +input [axi_qos_width-1:0] w_qos_hp0; +input [axi_qos_width-1:0] w_qos_hp1; +input [axi_qos_width-1:0] w_qos_hp2; +input [axi_qos_width-1:0] w_qos_hp3; + +input [axi_qos_width-1:0] r_qos_gp0; +input [axi_qos_width-1:0] r_qos_gp1; +input [axi_qos_width-1:0] r_qos_hp0; +input [axi_qos_width-1:0] r_qos_hp1; +input [axi_qos_width-1:0] r_qos_hp2; +input [axi_qos_width-1:0] r_qos_hp3; + +output [axi_qos_width-1:0] ocm_wr_qos_port1; +output [axi_qos_width-1:0] ocm_rd_qos_port1; + +output wr_ack_ddr_gp0; +output wr_ack_ocm_gp0; +input[max_burst_bits-1:0] wr_data_gp0; +input[addr_width-1:0] wr_addr_gp0; +input[max_burst_bytes_width:0] wr_bytes_gp0; +input wr_dv_ddr_gp0; +input wr_dv_ocm_gp0; +input rd_req_ddr_gp0; +input rd_req_ocm_gp0; +input rd_req_reg_gp0; +input[addr_width-1:0] rd_addr_gp0; +input[max_burst_bytes_width:0] rd_bytes_gp0; +output[max_burst_bits-1:0] rd_data_ddr_gp0; +output[max_burst_bits-1:0] rd_data_ocm_gp0; +output[max_burst_bits-1:0] rd_data_reg_gp0; +output rd_dv_ddr_gp0; +output rd_dv_ocm_gp0; +output rd_dv_reg_gp0; + +output wr_ack_ddr_gp1; +output wr_ack_ocm_gp1; +input[max_burst_bits-1:0] wr_data_gp1; +input[addr_width-1:0] wr_addr_gp1; +input[max_burst_bytes_width:0] wr_bytes_gp1; +input wr_dv_ddr_gp1; +input wr_dv_ocm_gp1; +input rd_req_ddr_gp1; +input rd_req_ocm_gp1; +input rd_req_reg_gp1; +input[addr_width-1:0] rd_addr_gp1; +input[max_burst_bytes_width:0] rd_bytes_gp1; +output[max_burst_bits-1:0] rd_data_ddr_gp1; +output[max_burst_bits-1:0] rd_data_ocm_gp1; +output[max_burst_bits-1:0] rd_data_reg_gp1; +output rd_dv_ddr_gp1; +output rd_dv_ocm_gp1; +output rd_dv_reg_gp1; + +output wr_ack_ddr_hp0; +output wr_ack_ocm_hp0; +input[max_burst_bits-1:0] wr_data_hp0; +input[addr_width-1:0] wr_addr_hp0; +input[max_burst_bytes_width:0] wr_bytes_hp0; +input wr_dv_ddr_hp0; +input wr_dv_ocm_hp0; +input rd_req_ddr_hp0; +input rd_req_ocm_hp0; +input[addr_width-1:0] rd_addr_hp0; +input[max_burst_bytes_width:0] rd_bytes_hp0; +output[max_burst_bits-1:0] rd_data_ddr_hp0; +output[max_burst_bits-1:0] rd_data_ocm_hp0; +output rd_dv_ddr_hp0; +output rd_dv_ocm_hp0; + +output wr_ack_ddr_hp1; +output wr_ack_ocm_hp1; +input[max_burst_bits-1:0] wr_data_hp1; +input[addr_width-1:0] wr_addr_hp1; +input[max_burst_bytes_width:0] wr_bytes_hp1; +input wr_dv_ddr_hp1; +input wr_dv_ocm_hp1; +input rd_req_ddr_hp1; +input rd_req_ocm_hp1; +input[addr_width-1:0] rd_addr_hp1; +input[max_burst_bytes_width:0] rd_bytes_hp1; +output[max_burst_bits-1:0] rd_data_ddr_hp1; +output[max_burst_bits-1:0] rd_data_ocm_hp1; +output rd_dv_ddr_hp1; +output rd_dv_ocm_hp1; + +output wr_ack_ddr_hp2; +output wr_ack_ocm_hp2; +input[max_burst_bits-1:0] wr_data_hp2; +input[addr_width-1:0] wr_addr_hp2; +input[max_burst_bytes_width:0] wr_bytes_hp2; +input wr_dv_ddr_hp2; +input wr_dv_ocm_hp2; +input rd_req_ddr_hp2; +input rd_req_ocm_hp2; +input[addr_width-1:0] rd_addr_hp2; +input[max_burst_bytes_width:0] rd_bytes_hp2; +output[max_burst_bits-1:0] rd_data_ddr_hp2; +output[max_burst_bits-1:0] rd_data_ocm_hp2; +output rd_dv_ddr_hp2; +output rd_dv_ocm_hp2; + +output wr_ack_ddr_hp3; +output wr_ack_ocm_hp3; +input[max_burst_bits-1:0] wr_data_hp3; +input[addr_width-1:0] wr_addr_hp3; +input[max_burst_bytes_width:0] wr_bytes_hp3; +input wr_dv_ddr_hp3; +input wr_dv_ocm_hp3; +input rd_req_ddr_hp3; +input rd_req_ocm_hp3; +input[addr_width-1:0] rd_addr_hp3; +input[max_burst_bytes_width:0] rd_bytes_hp3; +output[max_burst_bits-1:0] rd_data_ddr_hp3; +output[max_burst_bits-1:0] rd_data_ocm_hp3; +output rd_dv_ddr_hp3; +output rd_dv_ocm_hp3; + +/* Goes to port 1 of DDR */ +input ddr_wr_ack_port1; +output ddr_wr_dv_port1; +output ddr_rd_req_port1; +input ddr_rd_dv_port1; +output[addr_width-1:0] ddr_wr_addr_port1; +output[max_burst_bits-1:0] ddr_wr_data_port1; +output[max_burst_bytes_width:0] ddr_wr_bytes_port1; +output[addr_width-1:0] ddr_rd_addr_port1; +input[max_burst_bits-1:0] ddr_rd_data_port1; +output[max_burst_bytes_width:0] ddr_rd_bytes_port1; +output [axi_qos_width-1:0] ddr_wr_qos_port1; +output [axi_qos_width-1:0] ddr_rd_qos_port1; + +/* Goes to port2 of DDR */ +input ddr_wr_ack_port2; +output ddr_wr_dv_port2; +output ddr_rd_req_port2; +input ddr_rd_dv_port2; +output[addr_width-1:0] ddr_wr_addr_port2; +output[max_burst_bits-1:0] ddr_wr_data_port2; +output[max_burst_bytes_width:0] ddr_wr_bytes_port2; +output[addr_width-1:0] ddr_rd_addr_port2; +input[max_burst_bits-1:0] ddr_rd_data_port2; +output[max_burst_bytes_width:0] ddr_rd_bytes_port2; +output [axi_qos_width-1:0] ddr_wr_qos_port2; +output [axi_qos_width-1:0] ddr_rd_qos_port2; + +/* Goes to port3 of DDR */ +input ddr_wr_ack_port3; +output ddr_wr_dv_port3; +output ddr_rd_req_port3; +input ddr_rd_dv_port3; +output[addr_width-1:0] ddr_wr_addr_port3; +output[max_burst_bits-1:0] ddr_wr_data_port3; +output[max_burst_bytes_width:0] ddr_wr_bytes_port3; +output[addr_width-1:0] ddr_rd_addr_port3; +input[max_burst_bits-1:0] ddr_rd_data_port3; +output[max_burst_bytes_width:0] ddr_rd_bytes_port3; +output [axi_qos_width-1:0] ddr_wr_qos_port3; +output [axi_qos_width-1:0] ddr_rd_qos_port3; + +/* Goes to port1 of OCM */ +input ocm_wr_ack_port1; +output ocm_wr_dv_port1; +output ocm_rd_req_port1; +input ocm_rd_dv_port1; +output[max_burst_bits-1:0] ocm_wr_data_port1; +output[addr_width-1:0] ocm_wr_addr_port1; +output[max_burst_bytes_width:0] ocm_wr_bytes_port1; +input[max_burst_bits-1:0] ocm_rd_data_port1; +output[addr_width-1:0] ocm_rd_addr_port1; +output[max_burst_bytes_width:0] ocm_rd_bytes_port1; + +/* Goes to port1 of REG */ +output [axi_qos_width-1:0] reg_rd_qos_port1; +output reg_rd_req_port1; +input reg_rd_dv_port1; +input[max_burst_bits-1:0] reg_rd_data_port1; +output[addr_width-1:0] reg_rd_addr_port1; +output[max_burst_bytes_width:0] reg_rd_bytes_port1; + +wire ocm_wr_dv_osw0; +wire ocm_wr_dv_osw1; +wire[max_burst_bits-1:0] ocm_wr_data_osw0; +wire[max_burst_bits-1:0] ocm_wr_data_osw1; +wire[addr_width-1:0] ocm_wr_addr_osw0; +wire[addr_width-1:0] ocm_wr_addr_osw1; +wire[max_burst_bytes_width:0] ocm_wr_bytes_osw0; +wire[max_burst_bytes_width:0] ocm_wr_bytes_osw1; +wire ocm_wr_ack_osw0; +wire ocm_wr_ack_osw1; +wire ocm_rd_req_osw0; +wire ocm_rd_req_osw1; +wire[max_burst_bits-1:0] ocm_rd_data_osw0; +wire[max_burst_bits-1:0] ocm_rd_data_osw1; +wire[addr_width-1:0] ocm_rd_addr_osw0; +wire[addr_width-1:0] ocm_rd_addr_osw1; +wire[max_burst_bytes_width:0] ocm_rd_bytes_osw0; +wire[max_burst_bytes_width:0] ocm_rd_bytes_osw1; +wire ocm_rd_dv_osw0; +wire ocm_rd_dv_osw1; + +wire [axi_qos_width-1:0] ocm_wr_qos_osw0; +wire [axi_qos_width-1:0] ocm_wr_qos_osw1; +wire [axi_qos_width-1:0] ocm_rd_qos_osw0; +wire [axi_qos_width-1:0] ocm_rd_qos_osw1; + + +processing_system7_bfm_v2_0_fmsw_gp fmsw ( + .sw_clk(sw_clk), + .rstn(rstn), + + .w_qos_gp0(w_qos_gp0), + .r_qos_gp0(r_qos_gp0), + .wr_ack_ocm_gp0(wr_ack_ocm_gp0), + .wr_ack_ddr_gp0(wr_ack_ddr_gp0), + .wr_data_gp0(wr_data_gp0), + .wr_addr_gp0(wr_addr_gp0), + .wr_bytes_gp0(wr_bytes_gp0), + .wr_dv_ocm_gp0(wr_dv_ocm_gp0), + .wr_dv_ddr_gp0(wr_dv_ddr_gp0), + .rd_req_ocm_gp0(rd_req_ocm_gp0), + .rd_req_ddr_gp0(rd_req_ddr_gp0), + .rd_req_reg_gp0(rd_req_reg_gp0), + .rd_addr_gp0(rd_addr_gp0), + .rd_bytes_gp0(rd_bytes_gp0), + .rd_data_ddr_gp0(rd_data_ddr_gp0), + .rd_data_ocm_gp0(rd_data_ocm_gp0), + .rd_data_reg_gp0(rd_data_reg_gp0), + .rd_dv_ocm_gp0(rd_dv_ocm_gp0), + .rd_dv_ddr_gp0(rd_dv_ddr_gp0), + .rd_dv_reg_gp0(rd_dv_reg_gp0), + + .w_qos_gp1(w_qos_gp1), + .r_qos_gp1(r_qos_gp1), + .wr_ack_ocm_gp1(wr_ack_ocm_gp1), + .wr_ack_ddr_gp1(wr_ack_ddr_gp1), + .wr_data_gp1(wr_data_gp1), + .wr_addr_gp1(wr_addr_gp1), + .wr_bytes_gp1(wr_bytes_gp1), + .wr_dv_ocm_gp1(wr_dv_ocm_gp1), + .wr_dv_ddr_gp1(wr_dv_ddr_gp1), + .rd_req_ocm_gp1(rd_req_ocm_gp1), + .rd_req_ddr_gp1(rd_req_ddr_gp1), + .rd_req_reg_gp1(rd_req_reg_gp1), + .rd_addr_gp1(rd_addr_gp1), + .rd_bytes_gp1(rd_bytes_gp1), + .rd_data_ddr_gp1(rd_data_ddr_gp1), + .rd_data_ocm_gp1(rd_data_ocm_gp1), + .rd_data_reg_gp1(rd_data_reg_gp1), + .rd_dv_ocm_gp1(rd_dv_ocm_gp1), + .rd_dv_ddr_gp1(rd_dv_ddr_gp1), + .rd_dv_reg_gp1(rd_dv_reg_gp1), + + .ocm_wr_ack (ocm_wr_ack_osw0), + .ocm_wr_dv (ocm_wr_dv_osw0), + .ocm_rd_req (ocm_rd_req_osw0), + .ocm_rd_dv (ocm_rd_dv_osw0), + .ocm_wr_addr(ocm_wr_addr_osw0), + .ocm_wr_data(ocm_wr_data_osw0), + .ocm_wr_bytes(ocm_wr_bytes_osw0), + .ocm_rd_addr(ocm_rd_addr_osw0), + .ocm_rd_data(ocm_rd_data_osw0), + .ocm_rd_bytes(ocm_rd_bytes_osw0), + + .ocm_wr_qos(ocm_wr_qos_osw0), + .ocm_rd_qos(ocm_rd_qos_osw0), + + .ddr_wr_qos(ddr_wr_qos_port1), + .ddr_rd_qos(ddr_rd_qos_port1), + + .reg_rd_qos(reg_rd_qos_port1), + + .ddr_wr_ack(ddr_wr_ack_port1), + .ddr_wr_dv(ddr_wr_dv_port1), + .ddr_rd_req(ddr_rd_req_port1), + .ddr_rd_dv(ddr_rd_dv_port1), + .ddr_wr_addr(ddr_wr_addr_port1), + .ddr_wr_data(ddr_wr_data_port1), + .ddr_wr_bytes(ddr_wr_bytes_port1), + .ddr_rd_addr(ddr_rd_addr_port1), + .ddr_rd_data(ddr_rd_data_port1), + .ddr_rd_bytes(ddr_rd_bytes_port1), + + .reg_rd_req(reg_rd_req_port1), + .reg_rd_dv(reg_rd_dv_port1), + .reg_rd_addr(reg_rd_addr_port1), + .reg_rd_data(reg_rd_data_port1), + .reg_rd_bytes(reg_rd_bytes_port1) +); + + +processing_system7_bfm_v2_0_ssw_hp ssw( + .sw_clk(sw_clk), + .rstn(rstn), + .w_qos_hp0(w_qos_hp0), + .r_qos_hp0(r_qos_hp0), + .w_qos_hp1(w_qos_hp1), + .r_qos_hp1(r_qos_hp1), + .w_qos_hp2(w_qos_hp2), + .r_qos_hp2(r_qos_hp2), + .w_qos_hp3(w_qos_hp3), + .r_qos_hp3(r_qos_hp3), + + .wr_ack_ddr_hp0(wr_ack_ddr_hp0), + .wr_data_hp0(wr_data_hp0), + .wr_addr_hp0(wr_addr_hp0), + .wr_bytes_hp0(wr_bytes_hp0), + .wr_dv_ddr_hp0(wr_dv_ddr_hp0), + .rd_req_ddr_hp0(rd_req_ddr_hp0), + .rd_addr_hp0(rd_addr_hp0), + .rd_bytes_hp0(rd_bytes_hp0), + .rd_data_ddr_hp0(rd_data_ddr_hp0), + .rd_data_ocm_hp0(rd_data_ocm_hp0), + .rd_dv_ddr_hp0(rd_dv_ddr_hp0), + + .wr_ack_ocm_hp0(wr_ack_ocm_hp0), + .wr_dv_ocm_hp0(wr_dv_ocm_hp0), + .rd_req_ocm_hp0(rd_req_ocm_hp0), + .rd_dv_ocm_hp0(rd_dv_ocm_hp0), + + .wr_ack_ddr_hp1(wr_ack_ddr_hp1), + .wr_data_hp1(wr_data_hp1), + .wr_addr_hp1(wr_addr_hp1), + .wr_bytes_hp1(wr_bytes_hp1), + .wr_dv_ddr_hp1(wr_dv_ddr_hp1), + .rd_req_ddr_hp1(rd_req_ddr_hp1), + .rd_addr_hp1(rd_addr_hp1), + .rd_bytes_hp1(rd_bytes_hp1), + .rd_data_ddr_hp1(rd_data_ddr_hp1), + .rd_data_ocm_hp1(rd_data_ocm_hp1), + .rd_dv_ddr_hp1(rd_dv_ddr_hp1), + + .wr_ack_ocm_hp1(wr_ack_ocm_hp1), + .wr_dv_ocm_hp1(wr_dv_ocm_hp1), + .rd_req_ocm_hp1(rd_req_ocm_hp1), + .rd_dv_ocm_hp1(rd_dv_ocm_hp1), + + .wr_ack_ddr_hp2(wr_ack_ddr_hp2), + .wr_data_hp2(wr_data_hp2), + .wr_addr_hp2(wr_addr_hp2), + .wr_bytes_hp2(wr_bytes_hp2), + .wr_dv_ddr_hp2(wr_dv_ddr_hp2), + .rd_req_ddr_hp2(rd_req_ddr_hp2), + .rd_addr_hp2(rd_addr_hp2), + .rd_bytes_hp2(rd_bytes_hp2), + .rd_data_ddr_hp2(rd_data_ddr_hp2), + .rd_data_ocm_hp2(rd_data_ocm_hp2), + .rd_dv_ddr_hp2(rd_dv_ddr_hp2), + + .wr_ack_ocm_hp2(wr_ack_ocm_hp2), + .wr_dv_ocm_hp2(wr_dv_ocm_hp2), + .rd_req_ocm_hp2(rd_req_ocm_hp2), + .rd_dv_ocm_hp2(rd_dv_ocm_hp2), + + .wr_ack_ddr_hp3(wr_ack_ddr_hp3), + .wr_data_hp3(wr_data_hp3), + .wr_addr_hp3(wr_addr_hp3), + .wr_bytes_hp3(wr_bytes_hp3), + .wr_dv_ddr_hp3(wr_dv_ddr_hp3), + .rd_req_ddr_hp3(rd_req_ddr_hp3), + .rd_addr_hp3(rd_addr_hp3), + .rd_bytes_hp3(rd_bytes_hp3), + .rd_data_ddr_hp3(rd_data_ddr_hp3), + .rd_data_ocm_hp3(rd_data_ocm_hp3), + .rd_dv_ddr_hp3(rd_dv_ddr_hp3), + + .wr_ack_ocm_hp3(wr_ack_ocm_hp3), + .wr_dv_ocm_hp3(wr_dv_ocm_hp3), + .rd_req_ocm_hp3(rd_req_ocm_hp3), + .rd_dv_ocm_hp3(rd_dv_ocm_hp3), + + .ddr_wr_ack0(ddr_wr_ack_port2), + .ddr_wr_dv0(ddr_wr_dv_port2), + .ddr_rd_req0(ddr_rd_req_port2), + .ddr_rd_dv0(ddr_rd_dv_port2), + .ddr_wr_addr0(ddr_wr_addr_port2), + .ddr_wr_data0(ddr_wr_data_port2), + .ddr_wr_bytes0(ddr_wr_bytes_port2), + .ddr_rd_addr0(ddr_rd_addr_port2), + .ddr_rd_data0(ddr_rd_data_port2), + .ddr_rd_bytes0(ddr_rd_bytes_port2), + .ddr_wr_qos0(ddr_wr_qos_port2), + .ddr_rd_qos0(ddr_rd_qos_port2), + + .ddr_wr_ack1(ddr_wr_ack_port3), + .ddr_wr_dv1(ddr_wr_dv_port3), + .ddr_rd_req1(ddr_rd_req_port3), + .ddr_rd_dv1(ddr_rd_dv_port3), + .ddr_wr_addr1(ddr_wr_addr_port3), + .ddr_wr_data1(ddr_wr_data_port3), + .ddr_wr_bytes1(ddr_wr_bytes_port3), + .ddr_rd_addr1(ddr_rd_addr_port3), + .ddr_rd_data1(ddr_rd_data_port3), + .ddr_rd_bytes1(ddr_rd_bytes_port3), + .ddr_wr_qos1(ddr_wr_qos_port3), + .ddr_rd_qos1(ddr_rd_qos_port3), + + .ocm_wr_qos(ocm_wr_qos_osw1), + .ocm_rd_qos(ocm_rd_qos_osw1), + + .ocm_wr_ack (ocm_wr_ack_osw1), + .ocm_wr_dv (ocm_wr_dv_osw1), + .ocm_rd_req (ocm_rd_req_osw1), + .ocm_rd_dv (ocm_rd_dv_osw1), + .ocm_wr_addr(ocm_wr_addr_osw1), + .ocm_wr_data(ocm_wr_data_osw1), + .ocm_wr_bytes(ocm_wr_bytes_osw1), + .ocm_rd_addr(ocm_rd_addr_osw1), + .ocm_rd_data(ocm_rd_data_osw1), + .ocm_rd_bytes(ocm_rd_bytes_osw1) + +); + +processing_system7_bfm_v2_0_arb_wr osw_wr ( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(ocm_wr_qos_osw0), /// chk + .qos2(ocm_wr_qos_osw1), /// chk + .prt_dv1(ocm_wr_dv_osw0), + .prt_dv2(ocm_wr_dv_osw1), + .prt_data1(ocm_wr_data_osw0), + .prt_data2(ocm_wr_data_osw1), + .prt_addr1(ocm_wr_addr_osw0), + .prt_addr2(ocm_wr_addr_osw1), + .prt_bytes1(ocm_wr_bytes_osw0), + .prt_bytes2(ocm_wr_bytes_osw1), + .prt_ack1(ocm_wr_ack_osw0), + .prt_ack2(ocm_wr_ack_osw1), + .prt_req(ocm_wr_dv_port1), + .prt_qos(ocm_wr_qos_port1), + .prt_data(ocm_wr_data_port1), + .prt_addr(ocm_wr_addr_port1), + .prt_bytes(ocm_wr_bytes_port1), + .prt_ack(ocm_wr_ack_port1) +); + +processing_system7_bfm_v2_0_arb_rd osw_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(ocm_rd_qos_osw0), // chk + .qos2(ocm_rd_qos_osw1), // chk + .prt_req1(ocm_rd_req_osw0), + .prt_req2(ocm_rd_req_osw1), + .prt_data1(ocm_rd_data_osw0), + .prt_data2(ocm_rd_data_osw1), + .prt_addr1(ocm_rd_addr_osw0), + .prt_addr2(ocm_rd_addr_osw1), + .prt_bytes1(ocm_rd_bytes_osw0), + .prt_bytes2(ocm_rd_bytes_osw1), + .prt_dv1(ocm_rd_dv_osw0), + .prt_dv2(ocm_rd_dv_osw1), + .prt_req(ocm_rd_req_port1), + .prt_qos(ocm_rd_qos_port1), + .prt_data(ocm_rd_data_port1), + .prt_addr(ocm_rd_addr_port1), + .prt_bytes(ocm_rd_bytes_port1), + .prt_dv(ocm_rd_dv_port1) +); + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v new file mode 100644 index 0000000..b6631de --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v @@ -0,0 +1,99 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_intr_rd_mem.v + * + * Date : 2012-11 + * + * Description : Mimics interconnect for Reads between AFI and DDRC/OCM + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_intr_rd_mem( +sw_clk, +rstn, + +full, +empty, + +req, +invalid_rd_req, +rd_info, + +RD_DATA_OCM, +RD_DATA_DDR, +RD_DATA_VALID_OCM, +RD_DATA_VALID_DDR + +); +`include "processing_system7_bfm_v2_0_local_params.v" + +input sw_clk, rstn; +output full, empty; + +input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM; +input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM; +input req, invalid_rd_req; +input [rd_info_bits-1:0] rd_info; + +reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; +reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes +wire full, empty; + + +assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0; +assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0; + +/* read from the fifo */ +task read_mem; +output [rd_afi_fifo_bits-1:0] data; +begin + data = rd_fifo[rd_ptr[intr_cnt_width-1:0]]; + if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) + rd_ptr[intr_cnt_width-2:0] = 0; + else + rd_ptr = rd_ptr + 1; +end +endtask + +reg state; +reg invalid_rd; +/* write in the fifo */ +always@(negedge rstn or posedge sw_clk) +begin +if(!rstn) begin + wr_ptr = 0; + rd_ptr = 0; + state = 0; + invalid_rd = 0; +end else begin + case (state) + 0 : begin + state = 0; + invalid_rd = 0; + if(req)begin + state = 1; + invalid_rd = invalid_rd_req; + end + end + 1 : begin + state = 1; + if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin + if(RD_DATA_VALID_DDR) + rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_DDR,rd_info}; + else if(RD_DATA_VALID_OCM) + rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_OCM,rd_info}; + else + rd_fifo[wr_ptr[intr_cnt_width-2:0]] = rd_info; + if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) + wr_ptr[intr_cnt_width-2:0] = 0; + else + wr_ptr = wr_ptr + 1; + state = 0; + invalid_rd = 0; + end + end + endcase +end +end + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v new file mode 100644 index 0000000..1961a29 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v @@ -0,0 +1,105 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_intr_wr_mem.v + * + * Date : 2012-11 + * + * Description : Mimics interconnect for Writes between AFI and DDRC/OCM + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_intr_wr_mem( +sw_clk, +rstn, + +full, + +WR_DATA_ACK_OCM, +WR_DATA_ACK_DDR, +WR_ADDR, +WR_DATA, +WR_BYTES, +WR_QOS, +WR_DATA_VALID_OCM, +WR_DATA_VALID_DDR +); + +`include "processing_system7_bfm_v2_0_local_params.v" +/* local parameters for interconnect wr fifo model */ + +input sw_clk, rstn; +output full; + +input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; +output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; +output reg [max_burst_bits-1:0] WR_DATA; +output reg [addr_width-1:0] WR_ADDR; +output reg [max_burst_bytes_width:0] WR_BYTES; +output reg [axi_qos_width-1:0] WR_QOS; +reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; +reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1]; +wire empty; + +assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0; +assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0; + +parameter SEND_DATA = 0, WAIT_ACK = 1; +reg state; + +task automatic write_mem; +input [wr_fifo_data_bits-1:0] data; +begin + wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data; + if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) + wr_ptr[intr_cnt_width-2:0] = 0; + else + wr_ptr = wr_ptr + 1; +end +endtask + +always@(negedge rstn or posedge sw_clk) +begin +if(!rstn) begin + wr_ptr = 0; + rd_ptr = 0; + WR_DATA_VALID_DDR = 1'b0; + WR_DATA_VALID_OCM = 1'b0; + WR_QOS = 0; + state = SEND_DATA; +end else begin + case(state) + SEND_DATA :begin + state = SEND_DATA; + WR_DATA_VALID_OCM = 1'b0; + WR_DATA_VALID_DDR = 1'b0; + if(!empty) begin + WR_DATA = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb]; + WR_ADDR = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]; + WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb]; + WR_QOS = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb]; + state = WAIT_ACK; + case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb])) + OCM_MEM : WR_DATA_VALID_OCM = 1; + DDR_MEM : WR_DATA_VALID_DDR = 1; + default : state = SEND_DATA; + endcase + if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) begin + rd_ptr[intr_cnt_width-2:0] = 0; + end else begin + rd_ptr = rd_ptr+1; + end + end + end + WAIT_ACK :begin + state = WAIT_ACK; + if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin + WR_DATA_VALID_OCM = 1'b0; + WR_DATA_VALID_DDR = 1'b0; + state = SEND_DATA; + end + end + endcase +end +end + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_local_params.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_local_params.v new file mode 100644 index 0000000..9336633 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_local_params.v @@ -0,0 +1,239 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_local_params.v + * + * Date : 2012-11 + * + * Description : Parameters used in Zynq BFM + * + *****************************************************************************/ + +/* local */ +parameter m_axi_gp0_baseaddr = 32'h4000_0000; +parameter m_axi_gp1_baseaddr = 32'h8000_0000; +parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF; +parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF; + +parameter addr_width = 32; // maximum address width +parameter data_width = 32; // maximum data width. +parameter max_chars = 128; // max characters for file name +parameter mem_width = data_width/8; /// memory width in bytes +parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted +parameter int_width = 32; //integre width + +/* for internal read/write APIs used for data transfers */ +parameter max_burst_len = 16; /// maximum brst length on axi +parameter max_data_width = 64; // maximum data width for internal AXI bursts +parameter max_burst_bits = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts +parameter max_burst_bytes = (max_burst_bits)/8; // maximum data bytes in each transfer +parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts + +parameter max_registers = 32; +parameter max_regs_width = clogb2(max_registers); + +parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11; + +/* Interrupt bits supported */ +parameter irq_width = 16; + +/* GP Master0 & Master1 address decode */ +parameter GP_M0 = 2'b01; +parameter GP_M1 = 2'b10; + +parameter ALL_RANDOM= 2'b00; +parameter ALL_ZEROS = 2'b01; +parameter ALL_ONES = 2'b10; + +parameter ddr_start_addr = 32'h0008_0000; +parameter ddr_end_addr = 32'h3FFF_FFFF; + +parameter ocm_start_addr = 32'h0000_0000; +parameter ocm_end_addr = 32'h0003_FFFF; +parameter high_ocm_start_addr = 32'hFFFC_0000; +parameter high_ocm_end_addr = 32'hFFFF_FFFF; +parameter ocm_low_addr = 32'hFFFF_0000; + +parameter reg_start_addr = 32'hE000_0000; +parameter reg_end_addr = 32'hF8F0_2F80; + + +/* for Master port APIs and AXI protocol related signal widths*/ +parameter axi_burst_len = 16; +parameter axi_len_width = clogb2(axi_burst_len); +parameter axi_size_width = 3; +parameter axi_brst_type_width = 2; +parameter axi_lock_width = 2; +parameter axi_cache_width = 4; +parameter axi_prot_width = 3; +parameter axi_rsp_width = 2; +parameter axi_mgp_data_width = 32; +parameter axi_mgp_id_width = 12; +parameter axi_mgp_outstanding = 8; +parameter axi_mgp_wr_id = 12'hC00; +parameter axi_mgp_rd_id = 12'hC0C; +parameter axi_mgp0_name = "M_AXI_GP0"; +parameter axi_mgp1_name = "M_AXI_GP1"; +parameter axi_qos_width = 4; +parameter max_transfer_bytes = 128; // For Master APIs. +parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs. + + +/* for GP slave ports*/ +parameter axi_sgp_data_width = 32; +parameter axi_sgp_id_width = 6; +parameter axi_sgp_rd_outstanding = 8; +parameter axi_sgp_wr_outstanding = 8; +parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding; +parameter axi_sgp0_name = "S_AXI_GP0"; +parameter axi_sgp1_name = "S_AXI_GP1"; + +/* for ACP slave ports*/ +parameter axi_acp_data_width = 64; +parameter axi_acp_id_width = 3; +parameter axi_acp_rd_outstanding = 7; +parameter axi_acp_wr_outstanding = 3; +parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding; +parameter axi_acp_name = "S_AXI_ACP"; + +/* for HP slave ports*/ +parameter axi_hp_id_width = 6; +parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT .. +parameter axi_hp0_name = "S_AXI_HP0"; +parameter axi_hp1_name = "S_AXI_HP1"; +parameter axi_hp2_name = "S_AXI_HP2"; +parameter axi_hp3_name = "S_AXI_HP3"; + + +parameter axi_slv_excl_support = 0; // For Slave ports EXCL access is not supported +parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported + +/* AXI transfer types */ +parameter AXI_FIXED = 2'b00; +parameter AXI_INCR = 2'b01; +parameter AXI_WRAP = 2'b10; + +/* Exclusive Access */ +parameter AXI_NRML = 2'b00; +parameter AXI_EXCL = 2'b01; +parameter AXI_LOCK = 2'b10; + +/* AXI Response types */ +parameter AXI_OK = 2'b00; +parameter AXI_EXCL_OK = 2'b01; +parameter AXI_SLV_ERR = 2'b10; +parameter AXI_DEC_ERR = 2'b11; + +function automatic integer clogb2; + input [31:0] value; + begin + value = value - 1; + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin + value = value >> 1; + end + end +endfunction + +/* needed only for AFI modules and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */ + /* WR FIFO data */ + parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1); + parameter wr_bytes_lsb = 0; + parameter wr_bytes_msb = max_burst_bytes_width; + parameter wr_addr_lsb = wr_bytes_msb + 1; + parameter wr_addr_msb = wr_addr_lsb + addr_width-1; + parameter wr_data_lsb = wr_addr_msb + 1; + parameter wr_data_msb = wr_data_lsb + max_burst_bits-1; + parameter wr_qos_lsb = wr_data_msb + 1; + parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1; + + /* WR AFI FIFO data */ + /* ID - 1071:1066 + Resp - 1065:1064 + data - 1063:40 + address - 39:8 + valid_bytes - 7:0 + */ + parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1); + parameter wr_afi_bytes_lsb = 0; + parameter wr_afi_bytes_msb = max_burst_bytes_width; + parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1; + parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1; + parameter wr_afi_data_lsb = wr_afi_addr_msb + 1; + parameter wr_afi_data_msb = wr_afi_data_lsb + max_burst_bits-1; + parameter wr_afi_rsp_lsb = wr_afi_data_msb + 1; + parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1; + parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1; + parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1; + parameter wr_afi_ln_lsb = wr_afi_id_msb + 1; + parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1; + parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1; + parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1; + + + parameter afi_fifo_size = 1024; /// AFI FIFO is stored as 1024-bytes + parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes) + parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location + +/* for interconnect fifo models */ + parameter intr_max_outstanding = 8; + parameter intr_cnt_width = clogb2(intr_max_outstanding)+1; + parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width + axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1); + parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ; + + //Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes + parameter rd_afi_bytes_lsb = 0; + parameter rd_afi_bytes_msb = max_burst_bytes_width; + parameter rd_afi_rsp_lsb = rd_afi_bytes_msb + 1; + parameter rd_afi_rsp_msb = rd_afi_rsp_lsb + axi_rsp_width-1; + parameter rd_afi_id_lsb = rd_afi_rsp_msb + 1; + parameter rd_afi_id_msb = rd_afi_id_lsb + axi_hp_id_width-1; + parameter rd_afi_ln_lsb = rd_afi_id_msb + 1; + parameter rd_afi_ln_msb = rd_afi_ln_lsb + axi_len_width-1; + parameter rd_afi_brst_lsb = rd_afi_ln_msb + 1; + parameter rd_afi_brst_msb = rd_afi_brst_lsb + axi_brst_type_width-1; + parameter rd_afi_siz_lsb = rd_afi_brst_msb + 1; + parameter rd_afi_siz_msb = rd_afi_siz_lsb + axi_size_width-1; + parameter rd_afi_addr_lsb = rd_afi_siz_msb + 1; + parameter rd_afi_addr_msb = rd_afi_addr_lsb + addr_width-1; + parameter rd_afi_data_lsb = rd_afi_addr_msb + 1; + parameter rd_afi_data_msb = rd_afi_data_lsb + max_burst_bits-1; + + +/* Latency types */ + parameter BEST_CASE = 0; + parameter AVG_CASE = 1; + parameter WORST_CASE = 2; + parameter RANDOM_CASE = 3; + +/* Latency Parameters ACP */ + parameter acp_wr_min = 21; + parameter acp_wr_avg = 16; + parameter acp_wr_max = 27; + parameter acp_rd_min = 34; + parameter acp_rd_avg = 125; + parameter acp_rd_max = 130; + +/* Latency Parameters GP */ + parameter gp_wr_min = 21; + parameter gp_wr_avg = 16; + parameter gp_wr_max = 46; + parameter gp_rd_min = 38; + parameter gp_rd_avg = 125; + parameter gp_rd_max = 130; + +/* Latency Parameters HP */ + parameter afi_wr_min = 37; + parameter afi_wr_avg = 41; + parameter afi_wr_max = 42; + parameter afi_rd_min = 41; + parameter afi_rd_avg = 221; + parameter afi_rd_max = 229; + +/* ID VALID and INVALID */ + parameter secure_access_enabled = 0; + parameter id_invalid = 0; + parameter id_valid = 1; + +/* Display */ + parameter DISP_INFO = "*ZYNQ_BFM_INFO"; + parameter DISP_WARN = "*ZYNQ_BFM_WARNING"; + parameter DISP_ERR = "*ZYNQ_BFM_ERROR"; + parameter DISP_INT_INFO = "ZYNQ_BFM_INT_INFO"; diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ocm_mem.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ocm_mem.v new file mode 100644 index 0000000..88de3c4 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ocm_mem.v @@ -0,0 +1,223 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_ocm_mem.v + * + * Date : 2012-11 + * + * Description : Mimics OCM model + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_ocm_mem(); +`include "processing_system7_bfm_v2_0_local_params.v" + +parameter mem_size = 32'h4_0000; /// 256 KB +parameter mem_addr_width = clogb2(mem_size/mem_width); + +reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory + +/* preload memory from file */ +task automatic pre_load_mem_from_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; + $readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits); +endtask + +/* preload memory with some random data */ +task automatic pre_load_mem; +input [1:0] data_type; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; +integer i; +reg [mem_addr_width-1:0] addr; +begin +addr = start_addr >> shft_addr_bits; + +for (i = 0; i < no_of_bytes; i = i + mem_width) begin + case(data_type) + ALL_RANDOM : ocm_memory[addr] = $random; + ALL_ZEROS : ocm_memory[addr] = 32'h0000_0000; + ALL_ONES : ocm_memory[addr] = 32'hFFFF_FFFF; + default : ocm_memory[addr] = $random; + endcase + addr = addr+1; +end +end +endtask + +/* Write memory */ +task write_mem; +input [max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +reg [mem_addr_width-1:0] addr; +reg [max_burst_bits-1 :0] wr_temp_data; +reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data; +integer bytes_left; +integer pre_pad_bytes; +integer post_pad_bytes; +begin +addr = start_addr >> shft_addr_bits; +wr_temp_data = data; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); +`endif + +temp_data = wr_temp_data[data_width-1:0]; +bytes_left = no_of_bytes; +/* when the no. of bytes to be updated is less than mem_width */ +if(bytes_left < mem_width) begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + temp_data = ocm_memory[addr]; + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) temp_data = temp_data << 8; + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + wr_temp_data = wr_temp_data >> 8; + end + bytes_left = bytes_left + pre_pad_bytes; + end + /* This is needed for post padding the data ...*/ + post_pad_bytes = mem_width - bytes_left; + post_pad_data = ocm_memory[addr]; + repeat(post_pad_bytes) temp_data = temp_data << 8; + repeat(bytes_left) post_pad_data = post_pad_data >> 8; + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + post_pad_data = post_pad_data >> 8; + end + ocm_memory[addr] = temp_data; +end else begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + temp_data = ocm_memory[addr]; + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) temp_data = temp_data << 8; + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + wr_temp_data = wr_temp_data >> 8; + bytes_left = bytes_left -1; + end + end else begin + wr_temp_data = wr_temp_data >> data_width; + bytes_left = bytes_left - mem_width; + end + /* first data word end */ + ocm_memory[addr] = temp_data; + addr = addr + 1; + while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes. + ocm_memory[addr] = wr_temp_data[data_width-1:0]; + addr = addr+1; + wr_temp_data = wr_temp_data >> data_width; + bytes_left = bytes_left - mem_width; + end + + post_pad_data = ocm_memory[addr]; + post_pad_bytes = mem_width - bytes_left; + /* This is needed for last transfer in unaliged burst */ + if(bytes_left > 0) begin + temp_data = wr_temp_data[data_width-1:0]; + repeat(post_pad_bytes) temp_data = temp_data << 8; + repeat(bytes_left) post_pad_data = post_pad_data >> 8; + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + post_pad_data = post_pad_data >> 8; + end + ocm_memory[addr] = temp_data; + end +end +`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); +`endif +end +endtask + +/* read_memory */ +task read_mem; +output[max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +integer i; +reg [mem_addr_width-1:0] addr; +reg [data_width-1:0] temp_rd_data; +reg [max_burst_bits-1:0] temp_data; +integer pre_bytes; +integer bytes_left; +begin +addr = start_addr >> shft_addr_bits; +pre_bytes = start_addr[shft_addr_bits-1:0]; +bytes_left = no_of_bytes; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); +`endif + +/* Get first data ... if unaligned address */ +temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; + +if(no_of_bytes < mem_width ) begin + temp_data = temp_data >> (pre_bytes * 8); + repeat(max_burst_bytes - mem_width) + temp_data = temp_data >> 8; + +end else begin + bytes_left = bytes_left - (mem_width - pre_bytes); + addr = addr+1; + /* Got first data */ + while (bytes_left > (mem_width-1) ) begin + temp_data = temp_data >> data_width; + temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; + addr = addr+1; + bytes_left = bytes_left - mem_width; + end + + /* Get last valid data in the burst*/ + temp_rd_data = ocm_memory[addr]; + while(bytes_left > 0) begin + temp_data = temp_data >> 8; + temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; + temp_rd_data = temp_rd_data >> 8; + bytes_left = bytes_left - 1; + end + /* align to the brst_byte length */ + repeat(max_burst_bytes - no_of_bytes) + temp_data = temp_data >> 8; +end +data = temp_data; +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); +`endif +end +endtask + +/* backdoor read to memory */ +task peek_mem_to_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; + +integer rd_fd; +integer bytes; +reg [addr_width-1:0] addr; +reg [data_width-1:0] rd_data; +begin +rd_fd = $fopen(file_name,"w"); +bytes = no_of_bytes; + +addr = start_addr >> shft_addr_bits; +while (bytes > 0) begin + rd_data = ocm_memory[addr]; + $fdisplayh(rd_fd,rd_data); + bytes = bytes - 4; + addr = addr + 1; +end +end +endtask + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ocmc.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ocmc.v new file mode 100644 index 0000000..1104861 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ocmc.v @@ -0,0 +1,189 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_ocmc.v + * + * Date : 2012-11 + * + * Description : Controller for OCM model + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_ocmc( + rstn, + sw_clk, + +/* Goes to port 0 of OCM */ + ocm_wr_ack_port0, + ocm_wr_dv_port0, + ocm_rd_req_port0, + ocm_rd_dv_port0, + ocm_wr_addr_port0, + ocm_wr_data_port0, + ocm_wr_bytes_port0, + ocm_rd_addr_port0, + ocm_rd_data_port0, + ocm_rd_bytes_port0, + ocm_wr_qos_port0, + ocm_rd_qos_port0, + + +/* Goes to port 1 of OCM */ + ocm_wr_ack_port1, + ocm_wr_dv_port1, + ocm_rd_req_port1, + ocm_rd_dv_port1, + ocm_wr_addr_port1, + ocm_wr_data_port1, + ocm_wr_bytes_port1, + ocm_rd_addr_port1, + ocm_rd_data_port1, + ocm_rd_bytes_port1, + ocm_wr_qos_port1, + ocm_rd_qos_port1 + +); + +`include "processing_system7_bfm_v2_0_local_params.v" +input rstn; +input sw_clk; + +output ocm_wr_ack_port0; +input ocm_wr_dv_port0; +input ocm_rd_req_port0; +output ocm_rd_dv_port0; +input[addr_width-1:0] ocm_wr_addr_port0; +input[max_burst_bits-1:0] ocm_wr_data_port0; +input[max_burst_bytes_width:0] ocm_wr_bytes_port0; +input[addr_width-1:0] ocm_rd_addr_port0; +output[max_burst_bits-1:0] ocm_rd_data_port0; +input[max_burst_bytes_width:0] ocm_rd_bytes_port0; +input [axi_qos_width-1:0] ocm_wr_qos_port0; +input [axi_qos_width-1:0] ocm_rd_qos_port0; + +output ocm_wr_ack_port1; +input ocm_wr_dv_port1; +input ocm_rd_req_port1; +output ocm_rd_dv_port1; +input[addr_width-1:0] ocm_wr_addr_port1; +input[max_burst_bits-1:0] ocm_wr_data_port1; +input[max_burst_bytes_width:0] ocm_wr_bytes_port1; +input[addr_width-1:0] ocm_rd_addr_port1; +output[max_burst_bits-1:0] ocm_rd_data_port1; +input[max_burst_bytes_width:0] ocm_rd_bytes_port1; +input[axi_qos_width-1:0] ocm_wr_qos_port1; +input[axi_qos_width-1:0] ocm_rd_qos_port1; + +wire [axi_qos_width-1:0] wr_qos; +wire wr_req; +wire [max_burst_bits-1:0] wr_data; +wire [addr_width-1:0] wr_addr; +wire [max_burst_bytes_width:0] wr_bytes; +reg wr_ack; + +wire [axi_qos_width-1:0] rd_qos; +reg [max_burst_bits-1:0] rd_data; +wire [addr_width-1:0] rd_addr; +wire [max_burst_bytes_width:0] rd_bytes; +reg rd_dv; +wire rd_req; + +processing_system7_bfm_v2_0_arb_wr ocm_write_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ocm_wr_qos_port0), + .qos2(ocm_wr_qos_port1), + + .prt_dv1(ocm_wr_dv_port0), + .prt_dv2(ocm_wr_dv_port1), + + .prt_data1(ocm_wr_data_port0), + .prt_data2(ocm_wr_data_port1), + + .prt_addr1(ocm_wr_addr_port0), + .prt_addr2(ocm_wr_addr_port1), + + .prt_bytes1(ocm_wr_bytes_port0), + .prt_bytes2(ocm_wr_bytes_port1), + + .prt_ack1(ocm_wr_ack_port0), + .prt_ack2(ocm_wr_ack_port1), + + .prt_qos(wr_qos), + .prt_req(wr_req), + .prt_data(wr_data), + .prt_addr(wr_addr), + .prt_bytes(wr_bytes), + .prt_ack(wr_ack) + +); + +processing_system7_bfm_v2_0_arb_rd ocm_read_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ocm_rd_qos_port0), + .qos2(ocm_rd_qos_port1), + + .prt_req1(ocm_rd_req_port0), + .prt_req2(ocm_rd_req_port1), + + .prt_data1(ocm_rd_data_port0), + .prt_data2(ocm_rd_data_port1), + + .prt_addr1(ocm_rd_addr_port0), + .prt_addr2(ocm_rd_addr_port1), + + .prt_bytes1(ocm_rd_bytes_port0), + .prt_bytes2(ocm_rd_bytes_port1), + + .prt_dv1(ocm_rd_dv_port0), + .prt_dv2(ocm_rd_dv_port1), + + .prt_qos(rd_qos), + .prt_req(rd_req), + .prt_data(rd_data), + .prt_addr(rd_addr), + .prt_bytes(rd_bytes), + .prt_dv(rd_dv) + +); + +processing_system7_bfm_v2_0_ocm_mem ocm(); + +reg [1:0] state; +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + wr_ack <= 0; + rd_dv <= 0; + state <= 2'd0; +end else begin + case(state) + 0:begin + state <= 0; + wr_ack <= 0; + rd_dv <= 0; + if(wr_req) begin + ocm.write_mem(wr_data , wr_addr, wr_bytes); + wr_ack <= 1; + state <= 1; + end + if(rd_req) begin + ocm.read_mem(rd_data,rd_addr, rd_bytes); + rd_dv <= 1; + state <= 1; + end + + end + 1:begin + wr_ack <= 0; + rd_dv <= 0; + state <= 0; + end + + endcase +end /// if +end// always + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v new file mode 100644 index 0000000..f447d3f --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v @@ -0,0 +1,2010 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_processing_system7_bfm.v + * + * Date : 2012-11 + * + * Description : Processing_system7_bfm Top (zynq_bfm top) + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_processing_system7_bfm + ( + CAN0_PHY_TX, + CAN0_PHY_RX, + CAN1_PHY_TX, + CAN1_PHY_RX, + ENET0_GMII_TX_EN, + ENET0_GMII_TX_ER, + ENET0_MDIO_MDC, + ENET0_MDIO_O, + ENET0_MDIO_T, + ENET0_PTP_DELAY_REQ_RX, + ENET0_PTP_DELAY_REQ_TX, + ENET0_PTP_PDELAY_REQ_RX, + ENET0_PTP_PDELAY_REQ_TX, + ENET0_PTP_PDELAY_RESP_RX, + ENET0_PTP_PDELAY_RESP_TX, + ENET0_PTP_SYNC_FRAME_RX, + ENET0_PTP_SYNC_FRAME_TX, + ENET0_SOF_RX, + ENET0_SOF_TX, + ENET0_GMII_TXD, + ENET0_GMII_COL, + ENET0_GMII_CRS, + ENET0_EXT_INTIN, + ENET0_GMII_RX_CLK, + ENET0_GMII_RX_DV, + ENET0_GMII_RX_ER, + ENET0_GMII_TX_CLK, + ENET0_MDIO_I, + ENET0_GMII_RXD, + ENET1_GMII_TX_EN, + ENET1_GMII_TX_ER, + ENET1_MDIO_MDC, + ENET1_MDIO_O, + ENET1_MDIO_T, + ENET1_PTP_DELAY_REQ_RX, + ENET1_PTP_DELAY_REQ_TX, + ENET1_PTP_PDELAY_REQ_RX, + ENET1_PTP_PDELAY_REQ_TX, + ENET1_PTP_PDELAY_RESP_RX, + ENET1_PTP_PDELAY_RESP_TX, + ENET1_PTP_SYNC_FRAME_RX, + ENET1_PTP_SYNC_FRAME_TX, + ENET1_SOF_RX, + ENET1_SOF_TX, + ENET1_GMII_TXD, + ENET1_GMII_COL, + ENET1_GMII_CRS, + ENET1_EXT_INTIN, + ENET1_GMII_RX_CLK, + ENET1_GMII_RX_DV, + ENET1_GMII_RX_ER, + ENET1_GMII_TX_CLK, + ENET1_MDIO_I, + ENET1_GMII_RXD, + GPIO_I, + GPIO_O, + GPIO_T, + I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + I2C1_SDA_I, + I2C1_SDA_O, + I2C1_SDA_T, + I2C1_SCL_I, + I2C1_SCL_O, + I2C1_SCL_T, + PJTAG_TCK, + PJTAG_TMS, + PJTAG_TD_I, + PJTAG_TD_T, + PJTAG_TD_O, + SDIO0_CLK, + SDIO0_CLK_FB, + SDIO0_CMD_O, + SDIO0_CMD_I, + SDIO0_CMD_T, + SDIO0_DATA_I, + SDIO0_DATA_O, + SDIO0_DATA_T, + SDIO0_LED, + SDIO0_CDN, + SDIO0_WP, + SDIO0_BUSPOW, + SDIO0_BUSVOLT, + SDIO1_CLK, + SDIO1_CLK_FB, + SDIO1_CMD_O, + SDIO1_CMD_I, + SDIO1_CMD_T, + SDIO1_DATA_I, + SDIO1_DATA_O, + SDIO1_DATA_T, + SDIO1_LED, + SDIO1_CDN, + SDIO1_WP, + SDIO1_BUSPOW, + SDIO1_BUSVOLT, + SPI0_SCLK_I, + SPI0_SCLK_O, + SPI0_SCLK_T, + SPI0_MOSI_I, + SPI0_MOSI_O, + SPI0_MOSI_T, + SPI0_MISO_I, + SPI0_MISO_O, + SPI0_MISO_T, + SPI0_SS_I, + SPI0_SS_O, + SPI0_SS1_O, + SPI0_SS2_O, + SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, + UART0_DTRN, + UART0_RTSN, + UART0_TX, + UART0_CTSN, + UART0_DCDN, + UART0_DSRN, + UART0_RIN, + UART0_RX, + UART1_DTRN, + UART1_RTSN, + UART1_TX, + UART1_CTSN, + UART1_DCDN, + UART1_DSRN, + UART1_RIN, + UART1_RX, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + TTC0_CLK0_IN, + TTC0_CLK1_IN, + TTC0_CLK2_IN, + TTC1_WAVE0_OUT, + TTC1_WAVE1_OUT, + TTC1_WAVE2_OUT, + TTC1_CLK0_IN, + TTC1_CLK1_IN, + TTC1_CLK2_IN, + WDT_CLK_IN, + WDT_RST_OUT, + TRACE_CLK, + TRACE_CTL, + TRACE_DATA, + USB0_PORT_INDCTL, + USB1_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB1_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + USB1_VBUS_PWRFAULT, + SRAM_INTIN, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + M_AXI_GP1_ARVALID, + M_AXI_GP1_AWVALID, + M_AXI_GP1_BREADY, + M_AXI_GP1_RREADY, + M_AXI_GP1_WLAST, + M_AXI_GP1_WVALID, + M_AXI_GP1_ARID, + M_AXI_GP1_AWID, + M_AXI_GP1_WID, + M_AXI_GP1_ARBURST, + M_AXI_GP1_ARLOCK, + M_AXI_GP1_ARSIZE, + M_AXI_GP1_AWBURST, + M_AXI_GP1_AWLOCK, + M_AXI_GP1_AWSIZE, + M_AXI_GP1_ARPROT, + M_AXI_GP1_AWPROT, + M_AXI_GP1_ARADDR, + M_AXI_GP1_AWADDR, + M_AXI_GP1_WDATA, + M_AXI_GP1_ARCACHE, + M_AXI_GP1_ARLEN, + M_AXI_GP1_ARQOS, + M_AXI_GP1_AWCACHE, + M_AXI_GP1_AWLEN, + M_AXI_GP1_AWQOS, + M_AXI_GP1_WSTRB, + M_AXI_GP1_ACLK, + M_AXI_GP1_ARREADY, + M_AXI_GP1_AWREADY, + M_AXI_GP1_BVALID, + M_AXI_GP1_RLAST, + M_AXI_GP1_RVALID, + M_AXI_GP1_WREADY, + M_AXI_GP1_BID, + M_AXI_GP1_RID, + M_AXI_GP1_BRESP, + M_AXI_GP1_RRESP, + M_AXI_GP1_RDATA, + S_AXI_GP0_ARREADY, + S_AXI_GP0_AWREADY, + S_AXI_GP0_BVALID, + S_AXI_GP0_RLAST, + S_AXI_GP0_RVALID, + S_AXI_GP0_WREADY, + S_AXI_GP0_BRESP, + S_AXI_GP0_RRESP, + S_AXI_GP0_RDATA, + S_AXI_GP0_BID, + S_AXI_GP0_RID, + S_AXI_GP0_ACLK, + S_AXI_GP0_ARVALID, + S_AXI_GP0_AWVALID, + S_AXI_GP0_BREADY, + S_AXI_GP0_RREADY, + S_AXI_GP0_WLAST, + S_AXI_GP0_WVALID, + S_AXI_GP0_ARBURST, + S_AXI_GP0_ARLOCK, + S_AXI_GP0_ARSIZE, + S_AXI_GP0_AWBURST, + S_AXI_GP0_AWLOCK, + S_AXI_GP0_AWSIZE, + S_AXI_GP0_ARPROT, + S_AXI_GP0_AWPROT, + S_AXI_GP0_ARADDR, + S_AXI_GP0_AWADDR, + S_AXI_GP0_WDATA, + S_AXI_GP0_ARCACHE, + S_AXI_GP0_ARLEN, + S_AXI_GP0_ARQOS, + S_AXI_GP0_AWCACHE, + S_AXI_GP0_AWLEN, + S_AXI_GP0_AWQOS, + S_AXI_GP0_WSTRB, + S_AXI_GP0_ARID, + S_AXI_GP0_AWID, + S_AXI_GP0_WID, + S_AXI_GP1_ARREADY, + S_AXI_GP1_AWREADY, + S_AXI_GP1_BVALID, + S_AXI_GP1_RLAST, + S_AXI_GP1_RVALID, + S_AXI_GP1_WREADY, + S_AXI_GP1_BRESP, + S_AXI_GP1_RRESP, + S_AXI_GP1_RDATA, + S_AXI_GP1_BID, + S_AXI_GP1_RID, + S_AXI_GP1_ACLK, + S_AXI_GP1_ARVALID, + S_AXI_GP1_AWVALID, + S_AXI_GP1_BREADY, + S_AXI_GP1_RREADY, + S_AXI_GP1_WLAST, + S_AXI_GP1_WVALID, + S_AXI_GP1_ARBURST, + S_AXI_GP1_ARLOCK, + S_AXI_GP1_ARSIZE, + S_AXI_GP1_AWBURST, + S_AXI_GP1_AWLOCK, + S_AXI_GP1_AWSIZE, + S_AXI_GP1_ARPROT, + S_AXI_GP1_AWPROT, + S_AXI_GP1_ARADDR, + S_AXI_GP1_AWADDR, + S_AXI_GP1_WDATA, + S_AXI_GP1_ARCACHE, + S_AXI_GP1_ARLEN, + S_AXI_GP1_ARQOS, + S_AXI_GP1_AWCACHE, + S_AXI_GP1_AWLEN, + S_AXI_GP1_AWQOS, + S_AXI_GP1_WSTRB, + S_AXI_GP1_ARID, + S_AXI_GP1_AWID, + S_AXI_GP1_WID, + S_AXI_ACP_AWREADY, + S_AXI_ACP_ARREADY, + S_AXI_ACP_BVALID, + S_AXI_ACP_RLAST, + S_AXI_ACP_RVALID, + S_AXI_ACP_WREADY, + S_AXI_ACP_BRESP, + S_AXI_ACP_RRESP, + S_AXI_ACP_BID, + S_AXI_ACP_RID, + S_AXI_ACP_RDATA, + S_AXI_ACP_ACLK, + S_AXI_ACP_ARVALID, + S_AXI_ACP_AWVALID, + S_AXI_ACP_BREADY, + S_AXI_ACP_RREADY, + S_AXI_ACP_WLAST, + S_AXI_ACP_WVALID, + S_AXI_ACP_ARID, + S_AXI_ACP_ARPROT, + S_AXI_ACP_AWID, + S_AXI_ACP_AWPROT, + S_AXI_ACP_WID, + S_AXI_ACP_ARADDR, + S_AXI_ACP_AWADDR, + S_AXI_ACP_ARCACHE, + S_AXI_ACP_ARLEN, + S_AXI_ACP_ARQOS, + S_AXI_ACP_AWCACHE, + S_AXI_ACP_AWLEN, + S_AXI_ACP_AWQOS, + S_AXI_ACP_ARBURST, + S_AXI_ACP_ARLOCK, + S_AXI_ACP_ARSIZE, + S_AXI_ACP_AWBURST, + S_AXI_ACP_AWLOCK, + S_AXI_ACP_AWSIZE, + S_AXI_ACP_ARUSER, + S_AXI_ACP_AWUSER, + S_AXI_ACP_WDATA, + S_AXI_ACP_WSTRB, + S_AXI_HP0_ARREADY, + S_AXI_HP0_AWREADY, + S_AXI_HP0_BVALID, + S_AXI_HP0_RLAST, + S_AXI_HP0_RVALID, + S_AXI_HP0_WREADY, + S_AXI_HP0_BRESP, + S_AXI_HP0_RRESP, + S_AXI_HP0_BID, + S_AXI_HP0_RID, + S_AXI_HP0_RDATA, + S_AXI_HP0_RCOUNT, + S_AXI_HP0_WCOUNT, + S_AXI_HP0_RACOUNT, + S_AXI_HP0_WACOUNT, + S_AXI_HP0_ACLK, + S_AXI_HP0_ARVALID, + S_AXI_HP0_AWVALID, + S_AXI_HP0_BREADY, + S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RREADY, + S_AXI_HP0_WLAST, + S_AXI_HP0_WRISSUECAP1_EN, + S_AXI_HP0_WVALID, + S_AXI_HP0_ARBURST, + S_AXI_HP0_ARLOCK, + S_AXI_HP0_ARSIZE, + S_AXI_HP0_AWBURST, + S_AXI_HP0_AWLOCK, + S_AXI_HP0_AWSIZE, + S_AXI_HP0_ARPROT, + S_AXI_HP0_AWPROT, + S_AXI_HP0_ARADDR, + S_AXI_HP0_AWADDR, + S_AXI_HP0_ARCACHE, + S_AXI_HP0_ARLEN, + S_AXI_HP0_ARQOS, + S_AXI_HP0_AWCACHE, + S_AXI_HP0_AWLEN, + S_AXI_HP0_AWQOS, + S_AXI_HP0_ARID, + S_AXI_HP0_AWID, + S_AXI_HP0_WID, + S_AXI_HP0_WDATA, + S_AXI_HP0_WSTRB, + S_AXI_HP1_ARREADY, + S_AXI_HP1_AWREADY, + S_AXI_HP1_BVALID, + S_AXI_HP1_RLAST, + S_AXI_HP1_RVALID, + S_AXI_HP1_WREADY, + S_AXI_HP1_BRESP, + S_AXI_HP1_RRESP, + S_AXI_HP1_BID, + S_AXI_HP1_RID, + S_AXI_HP1_RDATA, + S_AXI_HP1_RCOUNT, + S_AXI_HP1_WCOUNT, + S_AXI_HP1_RACOUNT, + S_AXI_HP1_WACOUNT, + S_AXI_HP1_ACLK, + S_AXI_HP1_ARVALID, + S_AXI_HP1_AWVALID, + S_AXI_HP1_BREADY, + S_AXI_HP1_RDISSUECAP1_EN, + S_AXI_HP1_RREADY, + S_AXI_HP1_WLAST, + S_AXI_HP1_WRISSUECAP1_EN, + S_AXI_HP1_WVALID, + S_AXI_HP1_ARBURST, + S_AXI_HP1_ARLOCK, + S_AXI_HP1_ARSIZE, + S_AXI_HP1_AWBURST, + S_AXI_HP1_AWLOCK, + S_AXI_HP1_AWSIZE, + S_AXI_HP1_ARPROT, + S_AXI_HP1_AWPROT, + S_AXI_HP1_ARADDR, + S_AXI_HP1_AWADDR, + S_AXI_HP1_ARCACHE, + S_AXI_HP1_ARLEN, + S_AXI_HP1_ARQOS, + S_AXI_HP1_AWCACHE, + S_AXI_HP1_AWLEN, + S_AXI_HP1_AWQOS, + S_AXI_HP1_ARID, + S_AXI_HP1_AWID, + S_AXI_HP1_WID, + S_AXI_HP1_WDATA, + S_AXI_HP1_WSTRB, + S_AXI_HP2_ARREADY, + S_AXI_HP2_AWREADY, + S_AXI_HP2_BVALID, + S_AXI_HP2_RLAST, + S_AXI_HP2_RVALID, + S_AXI_HP2_WREADY, + S_AXI_HP2_BRESP, + S_AXI_HP2_RRESP, + S_AXI_HP2_BID, + S_AXI_HP2_RID, + S_AXI_HP2_RDATA, + S_AXI_HP2_RCOUNT, + S_AXI_HP2_WCOUNT, + S_AXI_HP2_RACOUNT, + S_AXI_HP2_WACOUNT, + S_AXI_HP2_ACLK, + S_AXI_HP2_ARVALID, + S_AXI_HP2_AWVALID, + S_AXI_HP2_BREADY, + S_AXI_HP2_RDISSUECAP1_EN, + S_AXI_HP2_RREADY, + S_AXI_HP2_WLAST, + S_AXI_HP2_WRISSUECAP1_EN, + S_AXI_HP2_WVALID, + S_AXI_HP2_ARBURST, + S_AXI_HP2_ARLOCK, + S_AXI_HP2_ARSIZE, + S_AXI_HP2_AWBURST, + S_AXI_HP2_AWLOCK, + S_AXI_HP2_AWSIZE, + S_AXI_HP2_ARPROT, + S_AXI_HP2_AWPROT, + S_AXI_HP2_ARADDR, + S_AXI_HP2_AWADDR, + S_AXI_HP2_ARCACHE, + S_AXI_HP2_ARLEN, + S_AXI_HP2_ARQOS, + S_AXI_HP2_AWCACHE, + S_AXI_HP2_AWLEN, + S_AXI_HP2_AWQOS, + S_AXI_HP2_ARID, + S_AXI_HP2_AWID, + S_AXI_HP2_WID, + S_AXI_HP2_WDATA, + S_AXI_HP2_WSTRB, + S_AXI_HP3_ARREADY, + S_AXI_HP3_AWREADY, + S_AXI_HP3_BVALID, + S_AXI_HP3_RLAST, + S_AXI_HP3_RVALID, + S_AXI_HP3_WREADY, + S_AXI_HP3_BRESP, + S_AXI_HP3_RRESP, + S_AXI_HP3_BID, + S_AXI_HP3_RID, + S_AXI_HP3_RDATA, + S_AXI_HP3_RCOUNT, + S_AXI_HP3_WCOUNT, + S_AXI_HP3_RACOUNT, + S_AXI_HP3_WACOUNT, + S_AXI_HP3_ACLK, + S_AXI_HP3_ARVALID, + S_AXI_HP3_AWVALID, + S_AXI_HP3_BREADY, + S_AXI_HP3_RDISSUECAP1_EN, + S_AXI_HP3_RREADY, + S_AXI_HP3_WLAST, + S_AXI_HP3_WRISSUECAP1_EN, + S_AXI_HP3_WVALID, + S_AXI_HP3_ARBURST, + S_AXI_HP3_ARLOCK, + S_AXI_HP3_ARSIZE, + S_AXI_HP3_AWBURST, + S_AXI_HP3_AWLOCK, + S_AXI_HP3_AWSIZE, + S_AXI_HP3_ARPROT, + S_AXI_HP3_AWPROT, + S_AXI_HP3_ARADDR, + S_AXI_HP3_AWADDR, + S_AXI_HP3_ARCACHE, + S_AXI_HP3_ARLEN, + S_AXI_HP3_ARQOS, + S_AXI_HP3_AWCACHE, + S_AXI_HP3_AWLEN, + S_AXI_HP3_AWQOS, + S_AXI_HP3_ARID, + S_AXI_HP3_AWID, + S_AXI_HP3_WID, + S_AXI_HP3_WDATA, + S_AXI_HP3_WSTRB, + DMA0_DATYPE, + DMA0_DAVALID, + DMA0_DRREADY, + DMA0_ACLK, + DMA0_DAREADY, + DMA0_DRLAST, + DMA0_DRVALID, + DMA0_DRTYPE, + DMA1_DATYPE, + DMA1_DAVALID, + DMA1_DRREADY, + DMA1_ACLK, + DMA1_DAREADY, + DMA1_DRLAST, + DMA1_DRVALID, + DMA1_DRTYPE, + DMA2_DATYPE, + DMA2_DAVALID, + DMA2_DRREADY, + DMA2_ACLK, + DMA2_DAREADY, + DMA2_DRLAST, + DMA2_DRVALID, + DMA3_DRVALID, + DMA3_DATYPE, + DMA3_DAVALID, + DMA3_DRREADY, + DMA3_ACLK, + DMA3_DAREADY, + DMA3_DRLAST, + DMA2_DRTYPE, + DMA3_DRTYPE, + FTMD_TRACEIN_DATA, + FTMD_TRACEIN_VALID, + FTMD_TRACEIN_CLK, + FTMD_TRACEIN_ATID, + FTMT_F2P_TRIG, + FTMT_F2P_TRIGACK, + FTMT_F2P_DEBUG, + FTMT_P2F_TRIGACK, + FTMT_P2F_TRIG, + FTMT_P2F_DEBUG, + FCLK_CLK3, + FCLK_CLK2, + FCLK_CLK1, + FCLK_CLK0, + FCLK_CLKTRIG3_N, + FCLK_CLKTRIG2_N, + FCLK_CLKTRIG1_N, + FCLK_CLKTRIG0_N, + FCLK_RESET3_N, + FCLK_RESET2_N, + FCLK_RESET1_N, + FCLK_RESET0_N, + FPGA_IDLE_N, + DDR_ARB, + IRQ_F2P, + Core0_nFIQ, + Core0_nIRQ, + Core1_nFIQ, + Core1_nIRQ, + EVENT_EVENTO, + EVENT_STANDBYWFE, + EVENT_STANDBYWFI, + EVENT_EVENTI, + MIO, + DDR_Clk, + DDR_Clk_n, + DDR_CKE, + DDR_CS_n, + DDR_RAS_n, + DDR_CAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_ODT, + DDR_DRSTB, + DDR_DQ, + DDR_DM, + DDR_DQS, + DDR_DQS_n, + DDR_VRN, + DDR_VRP, + PS_SRSTB, + PS_CLK, + PS_PORB, + IRQ_P2F_DMAC_ABORT, + IRQ_P2F_DMAC0, + IRQ_P2F_DMAC1, + IRQ_P2F_DMAC2, + IRQ_P2F_DMAC3, + IRQ_P2F_DMAC4, + IRQ_P2F_DMAC5, + IRQ_P2F_DMAC6, + IRQ_P2F_DMAC7, + IRQ_P2F_SMC, + IRQ_P2F_QSPI, + IRQ_P2F_CTI, + IRQ_P2F_GPIO, + IRQ_P2F_USB0, + IRQ_P2F_ENET0, + IRQ_P2F_ENET_WAKE0, + IRQ_P2F_SDIO0, + IRQ_P2F_I2C0, + IRQ_P2F_SPI0, + IRQ_P2F_UART0, + IRQ_P2F_CAN0, + IRQ_P2F_USB1, + IRQ_P2F_ENET1, + IRQ_P2F_ENET_WAKE1, + IRQ_P2F_SDIO1, + IRQ_P2F_I2C1, + IRQ_P2F_SPI1, + IRQ_P2F_UART1, + IRQ_P2F_CAN1 + ); + + + /* parameters for gen_clk */ + parameter C_FCLK_CLK0_FREQ = 50; + parameter C_FCLK_CLK1_FREQ = 50; + parameter C_FCLK_CLK3_FREQ = 50; + parameter C_FCLK_CLK2_FREQ = 50; + + parameter C_HIGH_OCM_EN = 0; + + + /* parameters for HP ports */ + parameter C_USE_S_AXI_HP0 = 0; + parameter C_USE_S_AXI_HP1 = 0; + parameter C_USE_S_AXI_HP2 = 0; + parameter C_USE_S_AXI_HP3 = 0; + + parameter C_S_AXI_HP0_DATA_WIDTH = 32; + parameter C_S_AXI_HP1_DATA_WIDTH = 32; + parameter C_S_AXI_HP2_DATA_WIDTH = 32; + parameter C_S_AXI_HP3_DATA_WIDTH = 32; + + parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12; + parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; + parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0; + parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; + +/* Do we need these + parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */ + + parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000; + + parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF; + + /* parameters for GP and ACP ports */ + parameter C_USE_M_AXI_GP0 = 0; + parameter C_USE_M_AXI_GP1 = 0; + parameter C_USE_S_AXI_GP0 = 1; + parameter C_USE_S_AXI_GP1 = 1; + + /* Do we need this? + parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0; + parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0; + + parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/ + + parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000; + + parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF; + + parameter C_USE_S_AXI_ACP = 1; + parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF; + + `include "processing_system7_bfm_v2_0_local_params.v" + + output CAN0_PHY_TX; + input CAN0_PHY_RX; + output CAN1_PHY_TX; + input CAN1_PHY_RX; + output ENET0_GMII_TX_EN; + output ENET0_GMII_TX_ER; + output ENET0_MDIO_MDC; + output ENET0_MDIO_O; + output ENET0_MDIO_T; + output ENET0_PTP_DELAY_REQ_RX; + output ENET0_PTP_DELAY_REQ_TX; + output ENET0_PTP_PDELAY_REQ_RX; + output ENET0_PTP_PDELAY_REQ_TX; + output ENET0_PTP_PDELAY_RESP_RX; + output ENET0_PTP_PDELAY_RESP_TX; + output ENET0_PTP_SYNC_FRAME_RX; + output ENET0_PTP_SYNC_FRAME_TX; + output ENET0_SOF_RX; + output ENET0_SOF_TX; + output [7:0] ENET0_GMII_TXD; + input ENET0_GMII_COL; + input ENET0_GMII_CRS; + input ENET0_EXT_INTIN; + input ENET0_GMII_RX_CLK; + input ENET0_GMII_RX_DV; + input ENET0_GMII_RX_ER; + input ENET0_GMII_TX_CLK; + input ENET0_MDIO_I; + input [7:0] ENET0_GMII_RXD; + output ENET1_GMII_TX_EN; + output ENET1_GMII_TX_ER; + output ENET1_MDIO_MDC; + output ENET1_MDIO_O; + output ENET1_MDIO_T; + output ENET1_PTP_DELAY_REQ_RX; + output ENET1_PTP_DELAY_REQ_TX; + output ENET1_PTP_PDELAY_REQ_RX; + output ENET1_PTP_PDELAY_REQ_TX; + output ENET1_PTP_PDELAY_RESP_RX; + output ENET1_PTP_PDELAY_RESP_TX; + output ENET1_PTP_SYNC_FRAME_RX; + output ENET1_PTP_SYNC_FRAME_TX; + output ENET1_SOF_RX; + output ENET1_SOF_TX; + output [7:0] ENET1_GMII_TXD; + input ENET1_GMII_COL; + input ENET1_GMII_CRS; + input ENET1_EXT_INTIN; + input ENET1_GMII_RX_CLK; + input ENET1_GMII_RX_DV; + input ENET1_GMII_RX_ER; + input ENET1_GMII_TX_CLK; + input ENET1_MDIO_I; + input [7:0] ENET1_GMII_RXD; + input [63:0] GPIO_I; + output [63:0] GPIO_O; + output [63:0] GPIO_T; + input I2C0_SDA_I; + output I2C0_SDA_O; + output I2C0_SDA_T; + input I2C0_SCL_I; + output I2C0_SCL_O; + output I2C0_SCL_T; + input I2C1_SDA_I; + output I2C1_SDA_O; + output I2C1_SDA_T; + input I2C1_SCL_I; + output I2C1_SCL_O; + output I2C1_SCL_T; + input PJTAG_TCK; + input PJTAG_TMS; + input PJTAG_TD_I; + output PJTAG_TD_T; + output PJTAG_TD_O; + output SDIO0_CLK; + input SDIO0_CLK_FB; + output SDIO0_CMD_O; + input SDIO0_CMD_I; + output SDIO0_CMD_T; + input [3:0] SDIO0_DATA_I; + output [3:0] SDIO0_DATA_O; + output [3:0] SDIO0_DATA_T; + output SDIO0_LED; + input SDIO0_CDN; + input SDIO0_WP; + output SDIO0_BUSPOW; + output [2:0] SDIO0_BUSVOLT; + output SDIO1_CLK; + input SDIO1_CLK_FB; + output SDIO1_CMD_O; + input SDIO1_CMD_I; + output SDIO1_CMD_T; + input [3:0] SDIO1_DATA_I; + output [3:0] SDIO1_DATA_O; + output [3:0] SDIO1_DATA_T; + output SDIO1_LED; + input SDIO1_CDN; + input SDIO1_WP; + output SDIO1_BUSPOW; + output [2:0] SDIO1_BUSVOLT; + input SPI0_SCLK_I; + output SPI0_SCLK_O; + output SPI0_SCLK_T; + input SPI0_MOSI_I; + output SPI0_MOSI_O; + output SPI0_MOSI_T; + input SPI0_MISO_I; + output SPI0_MISO_O; + output SPI0_MISO_T; + input SPI0_SS_I; + output SPI0_SS_O; + output SPI0_SS1_O; + output SPI0_SS2_O; + output SPI0_SS_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; + output UART0_DTRN; + output UART0_RTSN; + output UART0_TX; + input UART0_CTSN; + input UART0_DCDN; + input UART0_DSRN; + input UART0_RIN; + input UART0_RX; + output UART1_DTRN; + output UART1_RTSN; + output UART1_TX; + input UART1_CTSN; + input UART1_DCDN; + input UART1_DSRN; + input UART1_RIN; + input UART1_RX; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + input TTC0_CLK0_IN; + input TTC0_CLK1_IN; + input TTC0_CLK2_IN; + output TTC1_WAVE0_OUT; + output TTC1_WAVE1_OUT; + output TTC1_WAVE2_OUT; + input TTC1_CLK0_IN; + input TTC1_CLK1_IN; + input TTC1_CLK2_IN; + input WDT_CLK_IN; + output WDT_RST_OUT; + input TRACE_CLK; + output TRACE_CTL; + output [31:0] TRACE_DATA; + output [1:0] USB0_PORT_INDCTL; + output [1:0] USB1_PORT_INDCTL; + output USB0_VBUS_PWRSELECT; + output USB1_VBUS_PWRSELECT; + input USB0_VBUS_PWRFAULT; + input USB1_VBUS_PWRFAULT; + input SRAM_INTIN; + output M_AXI_GP0_ARVALID; + output M_AXI_GP0_AWVALID; + output M_AXI_GP0_BREADY; + output M_AXI_GP0_RREADY; + output M_AXI_GP0_WLAST; + output M_AXI_GP0_WVALID; + output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID; + output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID; + output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID; + output [1:0] M_AXI_GP0_ARBURST; + output [1:0] M_AXI_GP0_ARLOCK; + output [2:0] M_AXI_GP0_ARSIZE; + output [1:0] M_AXI_GP0_AWBURST; + output [1:0] M_AXI_GP0_AWLOCK; + output [2:0] M_AXI_GP0_AWSIZE; + output [2:0] M_AXI_GP0_ARPROT; + output [2:0] M_AXI_GP0_AWPROT; + output [31:0] M_AXI_GP0_ARADDR; + output [31:0] M_AXI_GP0_AWADDR; + output [31:0] M_AXI_GP0_WDATA; + output [3:0] M_AXI_GP0_ARCACHE; + output [3:0] M_AXI_GP0_ARLEN; + output [3:0] M_AXI_GP0_ARQOS; + output [3:0] M_AXI_GP0_AWCACHE; + output [3:0] M_AXI_GP0_AWLEN; + output [3:0] M_AXI_GP0_AWQOS; + output [3:0] M_AXI_GP0_WSTRB; + input M_AXI_GP0_ACLK; + input M_AXI_GP0_ARREADY; + input M_AXI_GP0_AWREADY; + input M_AXI_GP0_BVALID; + input M_AXI_GP0_RLAST; + input M_AXI_GP0_RVALID; + input M_AXI_GP0_WREADY; + input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID; + input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID; + input [1:0] M_AXI_GP0_BRESP; + input [1:0] M_AXI_GP0_RRESP; + input [31:0] M_AXI_GP0_RDATA; + output M_AXI_GP1_ARVALID; + output M_AXI_GP1_AWVALID; + output M_AXI_GP1_BREADY; + output M_AXI_GP1_RREADY; + output M_AXI_GP1_WLAST; + output M_AXI_GP1_WVALID; + output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID; + output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID; + output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID; + output [1:0] M_AXI_GP1_ARBURST; + output [1:0] M_AXI_GP1_ARLOCK; + output [2:0] M_AXI_GP1_ARSIZE; + output [1:0] M_AXI_GP1_AWBURST; + output [1:0] M_AXI_GP1_AWLOCK; + output [2:0] M_AXI_GP1_AWSIZE; + output [2:0] M_AXI_GP1_ARPROT; + output [2:0] M_AXI_GP1_AWPROT; + output [31:0] M_AXI_GP1_ARADDR; + output [31:0] M_AXI_GP1_AWADDR; + output [31:0] M_AXI_GP1_WDATA; + output [3:0] M_AXI_GP1_ARCACHE; + output [3:0] M_AXI_GP1_ARLEN; + output [3:0] M_AXI_GP1_ARQOS; + output [3:0] M_AXI_GP1_AWCACHE; + output [3:0] M_AXI_GP1_AWLEN; + output [3:0] M_AXI_GP1_AWQOS; + output [3:0] M_AXI_GP1_WSTRB; + input M_AXI_GP1_ACLK; + input M_AXI_GP1_ARREADY; + input M_AXI_GP1_AWREADY; + input M_AXI_GP1_BVALID; + input M_AXI_GP1_RLAST; + input M_AXI_GP1_RVALID; + input M_AXI_GP1_WREADY; + input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID; + input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID; + input [1:0] M_AXI_GP1_BRESP; + input [1:0] M_AXI_GP1_RRESP; + input [31:0] M_AXI_GP1_RDATA; + output S_AXI_GP0_ARREADY; + output S_AXI_GP0_AWREADY; + output S_AXI_GP0_BVALID; + output S_AXI_GP0_RLAST; + output S_AXI_GP0_RVALID; + output S_AXI_GP0_WREADY; + output [1:0] S_AXI_GP0_BRESP; + output [1:0] S_AXI_GP0_RRESP; + output [31:0] S_AXI_GP0_RDATA; + output [5:0] S_AXI_GP0_BID; + output [5:0] S_AXI_GP0_RID; + input S_AXI_GP0_ACLK; + input S_AXI_GP0_ARVALID; + input S_AXI_GP0_AWVALID; + input S_AXI_GP0_BREADY; + input S_AXI_GP0_RREADY; + input S_AXI_GP0_WLAST; + input S_AXI_GP0_WVALID; + input [1:0] S_AXI_GP0_ARBURST; + input [1:0] S_AXI_GP0_ARLOCK; + input [2:0] S_AXI_GP0_ARSIZE; + input [1:0] S_AXI_GP0_AWBURST; + input [1:0] S_AXI_GP0_AWLOCK; + input [2:0] S_AXI_GP0_AWSIZE; + input [2:0] S_AXI_GP0_ARPROT; + input [2:0] S_AXI_GP0_AWPROT; + input [31:0] S_AXI_GP0_ARADDR; + input [31:0] S_AXI_GP0_AWADDR; + input [31:0] S_AXI_GP0_WDATA; + input [3:0] S_AXI_GP0_ARCACHE; + input [3:0] S_AXI_GP0_ARLEN; + input [3:0] S_AXI_GP0_ARQOS; + input [3:0] S_AXI_GP0_AWCACHE; + input [3:0] S_AXI_GP0_AWLEN; + input [3:0] S_AXI_GP0_AWQOS; + input [3:0] S_AXI_GP0_WSTRB; + input [5:0] S_AXI_GP0_ARID; + input [5:0] S_AXI_GP0_AWID; + input [5:0] S_AXI_GP0_WID; + output S_AXI_GP1_ARREADY; + output S_AXI_GP1_AWREADY; + output S_AXI_GP1_BVALID; + output S_AXI_GP1_RLAST; + output S_AXI_GP1_RVALID; + output S_AXI_GP1_WREADY; + output [1:0] S_AXI_GP1_BRESP; + output [1:0] S_AXI_GP1_RRESP; + output [31:0] S_AXI_GP1_RDATA; + output [5:0] S_AXI_GP1_BID; + output [5:0] S_AXI_GP1_RID; + input S_AXI_GP1_ACLK; + input S_AXI_GP1_ARVALID; + input S_AXI_GP1_AWVALID; + input S_AXI_GP1_BREADY; + input S_AXI_GP1_RREADY; + input S_AXI_GP1_WLAST; + input S_AXI_GP1_WVALID; + input [1:0] S_AXI_GP1_ARBURST; + input [1:0] S_AXI_GP1_ARLOCK; + input [2:0] S_AXI_GP1_ARSIZE; + input [1:0] S_AXI_GP1_AWBURST; + input [1:0] S_AXI_GP1_AWLOCK; + input [2:0] S_AXI_GP1_AWSIZE; + input [2:0] S_AXI_GP1_ARPROT; + input [2:0] S_AXI_GP1_AWPROT; + input [31:0] S_AXI_GP1_ARADDR; + input [31:0] S_AXI_GP1_AWADDR; + input [31:0] S_AXI_GP1_WDATA; + input [3:0] S_AXI_GP1_ARCACHE; + input [3:0] S_AXI_GP1_ARLEN; + input [3:0] S_AXI_GP1_ARQOS; + input [3:0] S_AXI_GP1_AWCACHE; + input [3:0] S_AXI_GP1_AWLEN; + input [3:0] S_AXI_GP1_AWQOS; + input [3:0] S_AXI_GP1_WSTRB; + input [5:0] S_AXI_GP1_ARID; + input [5:0] S_AXI_GP1_AWID; + input [5:0] S_AXI_GP1_WID; + output S_AXI_ACP_AWREADY; + output S_AXI_ACP_ARREADY; + output S_AXI_ACP_BVALID; + output S_AXI_ACP_RLAST; + output S_AXI_ACP_RVALID; + output S_AXI_ACP_WREADY; + output [1:0] S_AXI_ACP_BRESP; + output [1:0] S_AXI_ACP_RRESP; + output [2:0] S_AXI_ACP_BID; + output [2:0] S_AXI_ACP_RID; + output [63:0] S_AXI_ACP_RDATA; + input S_AXI_ACP_ACLK; + input S_AXI_ACP_ARVALID; + input S_AXI_ACP_AWVALID; + input S_AXI_ACP_BREADY; + input S_AXI_ACP_RREADY; + input S_AXI_ACP_WLAST; + input S_AXI_ACP_WVALID; + input [2:0] S_AXI_ACP_ARID; + input [2:0] S_AXI_ACP_ARPROT; + input [2:0] S_AXI_ACP_AWID; + input [2:0] S_AXI_ACP_AWPROT; + input [2:0] S_AXI_ACP_WID; + input [31:0] S_AXI_ACP_ARADDR; + input [31:0] S_AXI_ACP_AWADDR; + input [3:0] S_AXI_ACP_ARCACHE; + input [3:0] S_AXI_ACP_ARLEN; + input [3:0] S_AXI_ACP_ARQOS; + input [3:0] S_AXI_ACP_AWCACHE; + input [3:0] S_AXI_ACP_AWLEN; + input [3:0] S_AXI_ACP_AWQOS; + input [1:0] S_AXI_ACP_ARBURST; + input [1:0] S_AXI_ACP_ARLOCK; + input [2:0] S_AXI_ACP_ARSIZE; + input [1:0] S_AXI_ACP_AWBURST; + input [1:0] S_AXI_ACP_AWLOCK; + input [2:0] S_AXI_ACP_AWSIZE; + input [4:0] S_AXI_ACP_ARUSER; + input [4:0] S_AXI_ACP_AWUSER; + input [63:0] S_AXI_ACP_WDATA; + input [7:0] S_AXI_ACP_WSTRB; + output S_AXI_HP0_ARREADY; + output S_AXI_HP0_AWREADY; + output S_AXI_HP0_BVALID; + output S_AXI_HP0_RLAST; + output S_AXI_HP0_RVALID; + output S_AXI_HP0_WREADY; + output [1:0] S_AXI_HP0_BRESP; + output [1:0] S_AXI_HP0_RRESP; + output [5:0] S_AXI_HP0_BID; + output [5:0] S_AXI_HP0_RID; + output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA; + output [7:0] S_AXI_HP0_RCOUNT; + output [7:0] S_AXI_HP0_WCOUNT; + output [2:0] S_AXI_HP0_RACOUNT; + output [5:0] S_AXI_HP0_WACOUNT; + input S_AXI_HP0_ACLK; + input S_AXI_HP0_ARVALID; + input S_AXI_HP0_AWVALID; + input S_AXI_HP0_BREADY; + input S_AXI_HP0_RDISSUECAP1_EN; + input S_AXI_HP0_RREADY; + input S_AXI_HP0_WLAST; + input S_AXI_HP0_WRISSUECAP1_EN; + input S_AXI_HP0_WVALID; + input [1:0] S_AXI_HP0_ARBURST; + input [1:0] S_AXI_HP0_ARLOCK; + input [2:0] S_AXI_HP0_ARSIZE; + input [1:0] S_AXI_HP0_AWBURST; + input [1:0] S_AXI_HP0_AWLOCK; + input [2:0] S_AXI_HP0_AWSIZE; + input [2:0] S_AXI_HP0_ARPROT; + input [2:0] S_AXI_HP0_AWPROT; + input [31:0] S_AXI_HP0_ARADDR; + input [31:0] S_AXI_HP0_AWADDR; + input [3:0] S_AXI_HP0_ARCACHE; + input [3:0] S_AXI_HP0_ARLEN; + input [3:0] S_AXI_HP0_ARQOS; + input [3:0] S_AXI_HP0_AWCACHE; + input [3:0] S_AXI_HP0_AWLEN; + input [3:0] S_AXI_HP0_AWQOS; + input [5:0] S_AXI_HP0_ARID; + input [5:0] S_AXI_HP0_AWID; + input [5:0] S_AXI_HP0_WID; + input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA; + input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB; + output S_AXI_HP1_ARREADY; + output S_AXI_HP1_AWREADY; + output S_AXI_HP1_BVALID; + output S_AXI_HP1_RLAST; + output S_AXI_HP1_RVALID; + output S_AXI_HP1_WREADY; + output [1:0] S_AXI_HP1_BRESP; + output [1:0] S_AXI_HP1_RRESP; + output [5:0] S_AXI_HP1_BID; + output [5:0] S_AXI_HP1_RID; + output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA; + output [7:0] S_AXI_HP1_RCOUNT; + output [7:0] S_AXI_HP1_WCOUNT; + output [2:0] S_AXI_HP1_RACOUNT; + output [5:0] S_AXI_HP1_WACOUNT; + input S_AXI_HP1_ACLK; + input S_AXI_HP1_ARVALID; + input S_AXI_HP1_AWVALID; + input S_AXI_HP1_BREADY; + input S_AXI_HP1_RDISSUECAP1_EN; + input S_AXI_HP1_RREADY; + input S_AXI_HP1_WLAST; + input S_AXI_HP1_WRISSUECAP1_EN; + input S_AXI_HP1_WVALID; + input [1:0] S_AXI_HP1_ARBURST; + input [1:0] S_AXI_HP1_ARLOCK; + input [2:0] S_AXI_HP1_ARSIZE; + input [1:0] S_AXI_HP1_AWBURST; + input [1:0] S_AXI_HP1_AWLOCK; + input [2:0] S_AXI_HP1_AWSIZE; + input [2:0] S_AXI_HP1_ARPROT; + input [2:0] S_AXI_HP1_AWPROT; + input [31:0] S_AXI_HP1_ARADDR; + input [31:0] S_AXI_HP1_AWADDR; + input [3:0] S_AXI_HP1_ARCACHE; + input [3:0] S_AXI_HP1_ARLEN; + input [3:0] S_AXI_HP1_ARQOS; + input [3:0] S_AXI_HP1_AWCACHE; + input [3:0] S_AXI_HP1_AWLEN; + input [3:0] S_AXI_HP1_AWQOS; + input [5:0] S_AXI_HP1_ARID; + input [5:0] S_AXI_HP1_AWID; + input [5:0] S_AXI_HP1_WID; + input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA; + input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB; + output S_AXI_HP2_ARREADY; + output S_AXI_HP2_AWREADY; + output S_AXI_HP2_BVALID; + output S_AXI_HP2_RLAST; + output S_AXI_HP2_RVALID; + output S_AXI_HP2_WREADY; + output [1:0] S_AXI_HP2_BRESP; + output [1:0] S_AXI_HP2_RRESP; + output [5:0] S_AXI_HP2_BID; + output [5:0] S_AXI_HP2_RID; + output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA; + output [7:0] S_AXI_HP2_RCOUNT; + output [7:0] S_AXI_HP2_WCOUNT; + output [2:0] S_AXI_HP2_RACOUNT; + output [5:0] S_AXI_HP2_WACOUNT; + input S_AXI_HP2_ACLK; + input S_AXI_HP2_ARVALID; + input S_AXI_HP2_AWVALID; + input S_AXI_HP2_BREADY; + input S_AXI_HP2_RDISSUECAP1_EN; + input S_AXI_HP2_RREADY; + input S_AXI_HP2_WLAST; + input S_AXI_HP2_WRISSUECAP1_EN; + input S_AXI_HP2_WVALID; + input [1:0] S_AXI_HP2_ARBURST; + input [1:0] S_AXI_HP2_ARLOCK; + input [2:0] S_AXI_HP2_ARSIZE; + input [1:0] S_AXI_HP2_AWBURST; + input [1:0] S_AXI_HP2_AWLOCK; + input [2:0] S_AXI_HP2_AWSIZE; + input [2:0] S_AXI_HP2_ARPROT; + input [2:0] S_AXI_HP2_AWPROT; + input [31:0] S_AXI_HP2_ARADDR; + input [31:0] S_AXI_HP2_AWADDR; + input [3:0] S_AXI_HP2_ARCACHE; + input [3:0] S_AXI_HP2_ARLEN; + input [3:0] S_AXI_HP2_ARQOS; + input [3:0] S_AXI_HP2_AWCACHE; + input [3:0] S_AXI_HP2_AWLEN; + input [3:0] S_AXI_HP2_AWQOS; + input [5:0] S_AXI_HP2_ARID; + input [5:0] S_AXI_HP2_AWID; + input [5:0] S_AXI_HP2_WID; + input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA; + input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB; + output S_AXI_HP3_ARREADY; + output S_AXI_HP3_AWREADY; + output S_AXI_HP3_BVALID; + output S_AXI_HP3_RLAST; + output S_AXI_HP3_RVALID; + output S_AXI_HP3_WREADY; + output [1:0] S_AXI_HP3_BRESP; + output [1:0] S_AXI_HP3_RRESP; + output [5:0] S_AXI_HP3_BID; + output [5:0] S_AXI_HP3_RID; + output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA; + output [7:0] S_AXI_HP3_RCOUNT; + output [7:0] S_AXI_HP3_WCOUNT; + output [2:0] S_AXI_HP3_RACOUNT; + output [5:0] S_AXI_HP3_WACOUNT; + input S_AXI_HP3_ACLK; + input S_AXI_HP3_ARVALID; + input S_AXI_HP3_AWVALID; + input S_AXI_HP3_BREADY; + input S_AXI_HP3_RDISSUECAP1_EN; + input S_AXI_HP3_RREADY; + input S_AXI_HP3_WLAST; + input S_AXI_HP3_WRISSUECAP1_EN; + input S_AXI_HP3_WVALID; + input [1:0] S_AXI_HP3_ARBURST; + input [1:0] S_AXI_HP3_ARLOCK; + input [2:0] S_AXI_HP3_ARSIZE; + input [1:0] S_AXI_HP3_AWBURST; + input [1:0] S_AXI_HP3_AWLOCK; + input [2:0] S_AXI_HP3_AWSIZE; + input [2:0] S_AXI_HP3_ARPROT; + input [2:0] S_AXI_HP3_AWPROT; + input [31:0] S_AXI_HP3_ARADDR; + input [31:0] S_AXI_HP3_AWADDR; + input [3:0] S_AXI_HP3_ARCACHE; + input [3:0] S_AXI_HP3_ARLEN; + input [3:0] S_AXI_HP3_ARQOS; + input [3:0] S_AXI_HP3_AWCACHE; + input [3:0] S_AXI_HP3_AWLEN; + input [3:0] S_AXI_HP3_AWQOS; + input [5:0] S_AXI_HP3_ARID; + input [5:0] S_AXI_HP3_AWID; + input [5:0] S_AXI_HP3_WID; + input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA; + input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB; + output [1:0] DMA0_DATYPE; + output DMA0_DAVALID; + output DMA0_DRREADY; + input DMA0_ACLK; + input DMA0_DAREADY; + input DMA0_DRLAST; + input DMA0_DRVALID; + input [1:0] DMA0_DRTYPE; + output [1:0] DMA1_DATYPE; + output DMA1_DAVALID; + output DMA1_DRREADY; + input DMA1_ACLK; + input DMA1_DAREADY; + input DMA1_DRLAST; + input DMA1_DRVALID; + input [1:0] DMA1_DRTYPE; + output [1:0] DMA2_DATYPE; + output DMA2_DAVALID; + output DMA2_DRREADY; + input DMA2_ACLK; + input DMA2_DAREADY; + input DMA2_DRLAST; + input DMA2_DRVALID; + input DMA3_DRVALID; + output [1:0] DMA3_DATYPE; + output DMA3_DAVALID; + output DMA3_DRREADY; + input DMA3_ACLK; + input DMA3_DAREADY; + input DMA3_DRLAST; + input [1:0] DMA2_DRTYPE; + input [1:0] DMA3_DRTYPE; + input [31:0] FTMD_TRACEIN_DATA; + input FTMD_TRACEIN_VALID; + input FTMD_TRACEIN_CLK; + input [3:0] FTMD_TRACEIN_ATID; + input [3:0] FTMT_F2P_TRIG; + output [3:0] FTMT_F2P_TRIGACK; + input [31:0] FTMT_F2P_DEBUG; + input [3:0] FTMT_P2F_TRIGACK; + output [3:0] FTMT_P2F_TRIG; + output [31:0] FTMT_P2F_DEBUG; + output FCLK_CLK3; + output FCLK_CLK2; + output FCLK_CLK1; + output FCLK_CLK0; + input FCLK_CLKTRIG3_N; + input FCLK_CLKTRIG2_N; + input FCLK_CLKTRIG1_N; + input FCLK_CLKTRIG0_N; + output FCLK_RESET3_N; + output FCLK_RESET2_N; + output FCLK_RESET1_N; + output FCLK_RESET0_N; + input FPGA_IDLE_N; + input [3:0] DDR_ARB; + input [irq_width-1:0] IRQ_F2P; + input Core0_nFIQ; + input Core0_nIRQ; + input Core1_nFIQ; + input Core1_nIRQ; + output EVENT_EVENTO; + output [1:0] EVENT_STANDBYWFE; + output [1:0] EVENT_STANDBYWFI; + input EVENT_EVENTI; + inout [53:0] MIO; + inout DDR_Clk; + inout DDR_Clk_n; + inout DDR_CKE; + inout DDR_CS_n; + inout DDR_RAS_n; + inout DDR_CAS_n; + output DDR_WEB; + inout [2:0] DDR_BankAddr; + inout [14:0] DDR_Addr; + inout DDR_ODT; + inout DDR_DRSTB; + inout [31:0] DDR_DQ; + inout [3:0] DDR_DM; + inout [3:0] DDR_DQS; + inout [3:0] DDR_DQS_n; + inout DDR_VRN; + inout DDR_VRP; +/* Reset Input & Clock Input */ + input PS_SRSTB; + input PS_CLK; + input PS_PORB; + output IRQ_P2F_DMAC_ABORT; + output IRQ_P2F_DMAC0; + output IRQ_P2F_DMAC1; + output IRQ_P2F_DMAC2; + output IRQ_P2F_DMAC3; + output IRQ_P2F_DMAC4; + output IRQ_P2F_DMAC5; + output IRQ_P2F_DMAC6; + output IRQ_P2F_DMAC7; + output IRQ_P2F_SMC; + output IRQ_P2F_QSPI; + output IRQ_P2F_CTI; + output IRQ_P2F_GPIO; + output IRQ_P2F_USB0; + output IRQ_P2F_ENET0; + output IRQ_P2F_ENET_WAKE0; + output IRQ_P2F_SDIO0; + output IRQ_P2F_I2C0; + output IRQ_P2F_SPI0; + output IRQ_P2F_UART0; + output IRQ_P2F_CAN0; + output IRQ_P2F_USB1; + output IRQ_P2F_ENET1; + output IRQ_P2F_ENET_WAKE1; + output IRQ_P2F_SDIO1; + output IRQ_P2F_I2C1; + output IRQ_P2F_SPI1; + output IRQ_P2F_UART1; + output IRQ_P2F_CAN1; + + + /* Internal wires/nets used for connectivity */ + wire net_rstn; + wire net_sw_clk; + wire net_ocm_clk; + wire net_arbiter_clk; + + wire net_axi_mgp0_rstn; + wire net_axi_mgp1_rstn; + wire net_axi_gp0_rstn; + wire net_axi_gp1_rstn; + wire net_axi_hp0_rstn; + wire net_axi_hp1_rstn; + wire net_axi_hp2_rstn; + wire net_axi_hp3_rstn; + wire net_axi_acp_rstn; + wire [4:0] net_axi_acp_awuser; + wire [4:0] net_axi_acp_aruser; + + + /* Dummy */ + assign net_axi_acp_awuser = S_AXI_ACP_AWUSER; + assign net_axi_acp_aruser = S_AXI_ACP_ARUSER; + + /* Global variables */ + reg DEBUG_INFO = 1; + reg STOP_ON_ERROR = 1; + + /* local variable acting as semaphore for wait_mem_update and wait_reg_update task */ + reg mem_update_key = 1; + reg reg_update_key_0 = 1; + reg reg_update_key_1 = 1; + + /* assignments and semantic checks for unused ports */ + `include "processing_system7_bfm_v2_0_unused_ports.v" + + /* include api definition */ + `include "processing_system7_bfm_v2_0_apis.v" + + /* Reset Generator */ + processing_system7_bfm_v2_0_gen_reset gen_rst(.por_rst_n(PS_PORB), + .sys_rst_n(PS_SRSTB), + .rst_out_n(net_rstn), + + .m_axi_gp0_clk(M_AXI_GP0_ACLK), + .m_axi_gp1_clk(M_AXI_GP1_ACLK), + .s_axi_gp0_clk(S_AXI_GP0_ACLK), + .s_axi_gp1_clk(S_AXI_GP1_ACLK), + .s_axi_hp0_clk(S_AXI_HP0_ACLK), + .s_axi_hp1_clk(S_AXI_HP1_ACLK), + .s_axi_hp2_clk(S_AXI_HP2_ACLK), + .s_axi_hp3_clk(S_AXI_HP3_ACLK), + .s_axi_acp_clk(S_AXI_ACP_ACLK), + + .m_axi_gp0_rstn(net_axi_mgp0_rstn), + .m_axi_gp1_rstn(net_axi_mgp1_rstn), + .s_axi_gp0_rstn(net_axi_gp0_rstn), + .s_axi_gp1_rstn(net_axi_gp1_rstn), + .s_axi_hp0_rstn(net_axi_hp0_rstn), + .s_axi_hp1_rstn(net_axi_hp1_rstn), + .s_axi_hp2_rstn(net_axi_hp2_rstn), + .s_axi_hp3_rstn(net_axi_hp3_rstn), + .s_axi_acp_rstn(net_axi_acp_rstn), + + .fclk_reset3_n(FCLK_RESET3_N), + .fclk_reset2_n(FCLK_RESET2_N), + .fclk_reset1_n(FCLK_RESET1_N), + .fclk_reset0_n(FCLK_RESET0_N), + + .fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP) + .fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN), + .fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN), + .fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN), + .fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN), + .fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN), + .fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN), + .fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN), + .fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN) + ); + + /* Clock Generator */ + processing_system7_bfm_v2_0_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ) + gen_clk(.ps_clk(PS_CLK), + .sw_clk(net_sw_clk), + + .fclk_clk3(FCLK_CLK3), + .fclk_clk2(FCLK_CLK2), + .fclk_clk1(FCLK_CLK1), + .fclk_clk0(FCLK_CLK0) + ); + + wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1; + wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1; + wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1; + wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1; + wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1; + wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1; + + wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1; + wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1; + wire net_rd_req_reg_gp0, net_rd_req_reg_gp1; + wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1; + wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1; + wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1; + wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1; + wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1; + wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1; + wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1; + wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1; + wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1; + + wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3; + wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3; + wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3; + wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3; + wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3; + wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3; + wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3; + wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3; + + wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3; + wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3; + wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3; + wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3; + wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3; + wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3; + wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3; + wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3; + wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3; + + wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp; + wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp; + wire [max_burst_bits-1:0] net_wr_data_acp; + wire [addr_width-1:0] net_wr_addr_acp; + wire [max_burst_bytes_width:0] net_wr_bytes_acp; + wire [axi_qos_width-1:0] net_wr_qos_acp; + + wire net_rd_req_ddr_acp, net_rd_req_ocm_acp; + wire [addr_width-1:0] net_rd_addr_acp; + wire [max_burst_bytes_width:0] net_rd_bytes_acp; + wire [max_burst_bits-1:0] net_rd_data_ddr_acp; + wire [max_burst_bits-1:0] net_rd_data_ocm_acp; + wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp; + wire [axi_qos_width-1:0] net_rd_qos_acp; + + wire ocm_wr_ack_port0; + wire ocm_wr_dv_port0; + wire ocm_rd_req_port0; + wire ocm_rd_dv_port0; + wire [addr_width-1:0] ocm_wr_addr_port0; + wire [max_burst_bits-1:0] ocm_wr_data_port0; + wire [max_burst_bytes_width:0] ocm_wr_bytes_port0; + wire [addr_width-1:0] ocm_rd_addr_port0; + wire [max_burst_bits-1:0] ocm_rd_data_port0; + wire [max_burst_bytes_width:0] ocm_rd_bytes_port0; + wire [axi_qos_width-1:0] ocm_wr_qos_port0; + wire [axi_qos_width-1:0] ocm_rd_qos_port0; + + wire ocm_wr_ack_port1; + wire ocm_wr_dv_port1; + wire ocm_rd_req_port1; + wire ocm_rd_dv_port1; + wire [addr_width-1:0] ocm_wr_addr_port1; + wire [max_burst_bits-1:0] ocm_wr_data_port1; + wire [max_burst_bytes_width:0] ocm_wr_bytes_port1; + wire [addr_width-1:0] ocm_rd_addr_port1; + wire [max_burst_bits-1:0] ocm_rd_data_port1; + wire [max_burst_bytes_width:0] ocm_rd_bytes_port1; + wire [axi_qos_width-1:0] ocm_wr_qos_port1; + wire [axi_qos_width-1:0] ocm_rd_qos_port1; + + wire ddr_wr_ack_port0; + wire ddr_wr_dv_port0; + wire ddr_rd_req_port0; + wire ddr_rd_dv_port0; + wire[addr_width-1:0] ddr_wr_addr_port0; + wire[max_burst_bits-1:0] ddr_wr_data_port0; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port0; + wire[addr_width-1:0] ddr_rd_addr_port0; + wire[max_burst_bits-1:0] ddr_rd_data_port0; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port0; + wire [axi_qos_width-1:0] ddr_wr_qos_port0; + wire [axi_qos_width-1:0] ddr_rd_qos_port0; + + wire ddr_wr_ack_port1; + wire ddr_wr_dv_port1; + wire ddr_rd_req_port1; + wire ddr_rd_dv_port1; + wire[addr_width-1:0] ddr_wr_addr_port1; + wire[max_burst_bits-1:0] ddr_wr_data_port1; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port1; + wire[addr_width-1:0] ddr_rd_addr_port1; + wire[max_burst_bits-1:0] ddr_rd_data_port1; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port1; + wire[axi_qos_width-1:0] ddr_wr_qos_port1; + wire[axi_qos_width-1:0] ddr_rd_qos_port1; + + wire ddr_wr_ack_port2; + wire ddr_wr_dv_port2; + wire ddr_rd_req_port2; + wire ddr_rd_dv_port2; + wire[addr_width-1:0] ddr_wr_addr_port2; + wire[max_burst_bits-1:0] ddr_wr_data_port2; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port2; + wire[addr_width-1:0] ddr_rd_addr_port2; + wire[max_burst_bits-1:0] ddr_rd_data_port2; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port2; + wire[axi_qos_width-1:0] ddr_wr_qos_port2; + wire[axi_qos_width-1:0] ddr_rd_qos_port2; + + wire ddr_wr_ack_port3; + wire ddr_wr_dv_port3; + wire ddr_rd_req_port3; + wire ddr_rd_dv_port3; + wire[addr_width-1:0] ddr_wr_addr_port3; + wire[max_burst_bits-1:0] ddr_wr_data_port3; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port3; + wire[addr_width-1:0] ddr_rd_addr_port3; + wire[max_burst_bits-1:0] ddr_rd_data_port3; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port3; + wire[axi_qos_width-1:0] ddr_wr_qos_port3; + wire[axi_qos_width-1:0] ddr_rd_qos_port3; + + wire reg_rd_req_port0; + wire reg_rd_dv_port0; + wire[addr_width-1:0] reg_rd_addr_port0; + wire[max_burst_bits-1:0] reg_rd_data_port0; + wire[max_burst_bytes_width:0] reg_rd_bytes_port0; + wire [axi_qos_width-1:0] reg_rd_qos_port0; + + wire reg_rd_req_port1; + wire reg_rd_dv_port1; + wire[addr_width-1:0] reg_rd_addr_port1; + wire[max_burst_bits-1:0] reg_rd_data_port1; + wire[max_burst_bytes_width:0] reg_rd_bytes_port1; + wire [axi_qos_width-1:0] reg_rd_qos_port1; + + wire [11:0] M_AXI_GP0_AWID_FULL; + wire [11:0] M_AXI_GP0_WID_FULL; + wire [11:0] M_AXI_GP0_ARID_FULL; + + wire [11:0] M_AXI_GP0_BID_FULL; + wire [11:0] M_AXI_GP0_RID_FULL; + + wire [11:0] M_AXI_GP1_AWID_FULL; + wire [11:0] M_AXI_GP1_WID_FULL; + wire [11:0] M_AXI_GP1_ARID_FULL; + + wire [11:0] M_AXI_GP1_BID_FULL; + wire [11:0] M_AXI_GP1_RID_FULL; + + + function [5:0] compress_id; + input [11:0] id; + begin + compress_id = id[5:0]; + end + endfunction + + function [11:0] uncompress_id; + input [5:0] id; + begin + uncompress_id = {6'b110000, id[5:0]}; + end + endfunction + + assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; + assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; + assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; + assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; + assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; + + + assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; + assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; + assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; + assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; + assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; + + + + + processing_system7_bfm_v2_0_interconnect_model icm ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + .w_qos_gp0(net_wr_qos_gp0), + .w_qos_gp1(net_wr_qos_gp1), + .w_qos_hp0(net_wr_qos_hp0), + .w_qos_hp1(net_wr_qos_hp1), + .w_qos_hp2(net_wr_qos_hp2), + .w_qos_hp3(net_wr_qos_hp3), + + .r_qos_gp0(net_rd_qos_gp0), + .r_qos_gp1(net_rd_qos_gp1), + .r_qos_hp0(net_rd_qos_hp0), + .r_qos_hp1(net_rd_qos_hp1), + .r_qos_hp2(net_rd_qos_hp2), + .r_qos_hp3(net_rd_qos_hp3), + + /* GP Slave ports access */ + .wr_ack_ddr_gp0(net_wr_ack_ddr_gp0), + .wr_ack_ocm_gp0(net_wr_ack_ocm_gp0), + .wr_data_gp0(net_wr_data_gp0), + .wr_addr_gp0(net_wr_addr_gp0), + .wr_bytes_gp0(net_wr_bytes_gp0), + .wr_dv_ddr_gp0(net_wr_dv_ddr_gp0), + .wr_dv_ocm_gp0(net_wr_dv_ocm_gp0), + .rd_req_ddr_gp0(net_rd_req_ddr_gp0), + .rd_req_ocm_gp0(net_rd_req_ocm_gp0), + .rd_req_reg_gp0(net_rd_req_reg_gp0), + .rd_addr_gp0(net_rd_addr_gp0), + .rd_bytes_gp0(net_rd_bytes_gp0), + .rd_data_ddr_gp0(net_rd_data_ddr_gp0), + .rd_data_ocm_gp0(net_rd_data_ocm_gp0), + .rd_data_reg_gp0(net_rd_data_reg_gp0), + .rd_dv_ddr_gp0(net_rd_dv_ddr_gp0), + .rd_dv_ocm_gp0(net_rd_dv_ocm_gp0), + .rd_dv_reg_gp0(net_rd_dv_reg_gp0), + + .wr_ack_ddr_gp1(net_wr_ack_ddr_gp1), + .wr_ack_ocm_gp1(net_wr_ack_ocm_gp1), + .wr_data_gp1(net_wr_data_gp1), + .wr_addr_gp1(net_wr_addr_gp1), + .wr_bytes_gp1(net_wr_bytes_gp1), + .wr_dv_ddr_gp1(net_wr_dv_ddr_gp1), + .wr_dv_ocm_gp1(net_wr_dv_ocm_gp1), + .rd_req_ddr_gp1(net_rd_req_ddr_gp1), + .rd_req_ocm_gp1(net_rd_req_ocm_gp1), + .rd_req_reg_gp1(net_rd_req_reg_gp1), + .rd_addr_gp1(net_rd_addr_gp1), + .rd_bytes_gp1(net_rd_bytes_gp1), + .rd_data_ddr_gp1(net_rd_data_ddr_gp1), + .rd_data_ocm_gp1(net_rd_data_ocm_gp1), + .rd_data_reg_gp1(net_rd_data_reg_gp1), + .rd_dv_ddr_gp1(net_rd_dv_ddr_gp1), + .rd_dv_ocm_gp1(net_rd_dv_ocm_gp1), + .rd_dv_reg_gp1(net_rd_dv_reg_gp1), + + /* HP Slave ports access */ + .wr_ack_ddr_hp0(net_wr_ack_ddr_hp0), + .wr_ack_ocm_hp0(net_wr_ack_ocm_hp0), + .wr_data_hp0(net_wr_data_hp0), + .wr_addr_hp0(net_wr_addr_hp0), + .wr_bytes_hp0(net_wr_bytes_hp0), + .wr_dv_ddr_hp0(net_wr_dv_ddr_hp0), + .wr_dv_ocm_hp0(net_wr_dv_ocm_hp0), + .rd_req_ddr_hp0(net_rd_req_ddr_hp0), + .rd_req_ocm_hp0(net_rd_req_ocm_hp0), + .rd_addr_hp0(net_rd_addr_hp0), + .rd_bytes_hp0(net_rd_bytes_hp0), + .rd_data_ddr_hp0(net_rd_data_ddr_hp0), + .rd_data_ocm_hp0(net_rd_data_ocm_hp0), + .rd_dv_ddr_hp0(net_rd_dv_ddr_hp0), + .rd_dv_ocm_hp0(net_rd_dv_ocm_hp0), + + .wr_ack_ddr_hp1(net_wr_ack_ddr_hp1), + .wr_ack_ocm_hp1(net_wr_ack_ocm_hp1), + .wr_data_hp1(net_wr_data_hp1), + .wr_addr_hp1(net_wr_addr_hp1), + .wr_bytes_hp1(net_wr_bytes_hp1), + .wr_dv_ddr_hp1(net_wr_dv_ddr_hp1), + .wr_dv_ocm_hp1(net_wr_dv_ocm_hp1), + .rd_req_ddr_hp1(net_rd_req_ddr_hp1), + .rd_req_ocm_hp1(net_rd_req_ocm_hp1), + .rd_addr_hp1(net_rd_addr_hp1), + .rd_bytes_hp1(net_rd_bytes_hp1), + .rd_data_ddr_hp1(net_rd_data_ddr_hp1), + .rd_data_ocm_hp1(net_rd_data_ocm_hp1), + .rd_dv_ocm_hp1(net_rd_dv_ocm_hp1), + .rd_dv_ddr_hp1(net_rd_dv_ddr_hp1), + + .wr_ack_ddr_hp2(net_wr_ack_ddr_hp2), + .wr_ack_ocm_hp2(net_wr_ack_ocm_hp2), + .wr_data_hp2(net_wr_data_hp2), + .wr_addr_hp2(net_wr_addr_hp2), + .wr_bytes_hp2(net_wr_bytes_hp2), + .wr_dv_ocm_hp2(net_wr_dv_ocm_hp2), + .wr_dv_ddr_hp2(net_wr_dv_ddr_hp2), + .rd_req_ddr_hp2(net_rd_req_ddr_hp2), + .rd_req_ocm_hp2(net_rd_req_ocm_hp2), + .rd_addr_hp2(net_rd_addr_hp2), + .rd_bytes_hp2(net_rd_bytes_hp2), + .rd_data_ddr_hp2(net_rd_data_ddr_hp2), + .rd_data_ocm_hp2(net_rd_data_ocm_hp2), + .rd_dv_ddr_hp2(net_rd_dv_ddr_hp2), + .rd_dv_ocm_hp2(net_rd_dv_ocm_hp2), + + .wr_ack_ocm_hp3(net_wr_ack_ocm_hp3), + .wr_ack_ddr_hp3(net_wr_ack_ddr_hp3), + .wr_data_hp3(net_wr_data_hp3), + .wr_addr_hp3(net_wr_addr_hp3), + .wr_bytes_hp3(net_wr_bytes_hp3), + .wr_dv_ddr_hp3(net_wr_dv_ddr_hp3), + .wr_dv_ocm_hp3(net_wr_dv_ocm_hp3), + .rd_req_ddr_hp3(net_rd_req_ddr_hp3), + .rd_req_ocm_hp3(net_rd_req_ocm_hp3), + .rd_addr_hp3(net_rd_addr_hp3), + .rd_bytes_hp3(net_rd_bytes_hp3), + .rd_data_ddr_hp3(net_rd_data_ddr_hp3), + .rd_data_ocm_hp3(net_rd_data_ocm_hp3), + .rd_dv_ddr_hp3(net_rd_dv_ddr_hp3), + .rd_dv_ocm_hp3(net_rd_dv_ocm_hp3), + + /* Goes to port 1 of DDR */ + .ddr_wr_ack_port1(ddr_wr_ack_port1), + .ddr_wr_dv_port1(ddr_wr_dv_port1), + .ddr_rd_req_port1(ddr_rd_req_port1), + .ddr_rd_dv_port1 (ddr_rd_dv_port1), + .ddr_wr_addr_port1(ddr_wr_addr_port1), + .ddr_wr_data_port1(ddr_wr_data_port1), + .ddr_wr_bytes_port1(ddr_wr_bytes_port1), + .ddr_rd_addr_port1(ddr_rd_addr_port1), + .ddr_rd_data_port1(ddr_rd_data_port1), + .ddr_rd_bytes_port1(ddr_rd_bytes_port1), + .ddr_wr_qos_port1(ddr_wr_qos_port1), + .ddr_rd_qos_port1(ddr_rd_qos_port1), + + /* Goes to port2 of DDR */ + .ddr_wr_ack_port2 (ddr_wr_ack_port2), + .ddr_wr_dv_port2 (ddr_wr_dv_port2), + .ddr_rd_req_port2 (ddr_rd_req_port2), + .ddr_rd_dv_port2 (ddr_rd_dv_port2), + .ddr_wr_addr_port2(ddr_wr_addr_port2), + .ddr_wr_data_port2(ddr_wr_data_port2), + .ddr_wr_bytes_port2(ddr_wr_bytes_port2), + .ddr_rd_addr_port2(ddr_rd_addr_port2), + .ddr_rd_data_port2(ddr_rd_data_port2), + .ddr_rd_bytes_port2(ddr_rd_bytes_port2), + .ddr_wr_qos_port2 (ddr_wr_qos_port2), + .ddr_rd_qos_port2 (ddr_rd_qos_port2), + + /* Goes to port3 of DDR */ + .ddr_wr_ack_port3 (ddr_wr_ack_port3), + .ddr_wr_dv_port3 (ddr_wr_dv_port3), + .ddr_rd_req_port3 (ddr_rd_req_port3), + .ddr_rd_dv_port3 (ddr_rd_dv_port3), + .ddr_wr_addr_port3(ddr_wr_addr_port3), + .ddr_wr_data_port3(ddr_wr_data_port3), + .ddr_wr_bytes_port3(ddr_wr_bytes_port3), + .ddr_rd_addr_port3(ddr_rd_addr_port3), + .ddr_rd_data_port3(ddr_rd_data_port3), + .ddr_rd_bytes_port3(ddr_rd_bytes_port3), + .ddr_wr_qos_port3 (ddr_wr_qos_port3), + .ddr_rd_qos_port3 (ddr_rd_qos_port3), + + /* Goes to port 0 of OCM */ + .ocm_wr_ack_port1 (ocm_wr_ack_port1), + .ocm_wr_dv_port1 (ocm_wr_dv_port1), + .ocm_rd_req_port1 (ocm_rd_req_port1), + .ocm_rd_dv_port1 (ocm_rd_dv_port1), + .ocm_wr_addr_port1(ocm_wr_addr_port1), + .ocm_wr_data_port1(ocm_wr_data_port1), + .ocm_wr_bytes_port1(ocm_wr_bytes_port1), + .ocm_rd_addr_port1(ocm_rd_addr_port1), + .ocm_rd_data_port1(ocm_rd_data_port1), + .ocm_rd_bytes_port1(ocm_rd_bytes_port1), + .ocm_wr_qos_port1(ocm_wr_qos_port1), + .ocm_rd_qos_port1(ocm_rd_qos_port1), + + /* Goes to port 0 of REG */ + .reg_rd_qos_port1 (reg_rd_qos_port1) , + .reg_rd_req_port1 (reg_rd_req_port1), + .reg_rd_dv_port1 (reg_rd_dv_port1), + .reg_rd_addr_port1(reg_rd_addr_port1), + .reg_rd_data_port1(reg_rd_data_port1), + .reg_rd_bytes_port1(reg_rd_bytes_port1) + ); + + processing_system7_bfm_v2_0_ddrc ddrc ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + /* Goes to port 0 of DDR */ + .ddr_wr_ack_port0 (ddr_wr_ack_port0), + .ddr_wr_dv_port0 (ddr_wr_dv_port0), + .ddr_rd_req_port0 (ddr_rd_req_port0), + .ddr_rd_dv_port0 (ddr_rd_dv_port0), + + .ddr_wr_addr_port0(net_wr_addr_acp), + .ddr_wr_data_port0(net_wr_data_acp), + .ddr_wr_bytes_port0(net_wr_bytes_acp), + + .ddr_rd_addr_port0(net_rd_addr_acp), + .ddr_rd_bytes_port0(net_rd_bytes_acp), + + .ddr_rd_data_port0(ddr_rd_data_port0), + + .ddr_wr_qos_port0 (net_wr_qos_acp), + .ddr_rd_qos_port0 (net_rd_qos_acp), + + + /* Goes to port 1 of DDR */ + .ddr_wr_ack_port1 (ddr_wr_ack_port1), + .ddr_wr_dv_port1 (ddr_wr_dv_port1), + .ddr_rd_req_port1 (ddr_rd_req_port1), + .ddr_rd_dv_port1 (ddr_rd_dv_port1), + .ddr_wr_addr_port1(ddr_wr_addr_port1), + .ddr_wr_data_port1(ddr_wr_data_port1), + .ddr_wr_bytes_port1(ddr_wr_bytes_port1), + .ddr_rd_addr_port1(ddr_rd_addr_port1), + .ddr_rd_data_port1(ddr_rd_data_port1), + .ddr_rd_bytes_port1(ddr_rd_bytes_port1), + .ddr_wr_qos_port1 (ddr_wr_qos_port1), + .ddr_rd_qos_port1 (ddr_rd_qos_port1), + + /* Goes to port2 of DDR */ + .ddr_wr_ack_port2 (ddr_wr_ack_port2), + .ddr_wr_dv_port2 (ddr_wr_dv_port2), + .ddr_rd_req_port2 (ddr_rd_req_port2), + .ddr_rd_dv_port2 (ddr_rd_dv_port2), + .ddr_wr_addr_port2(ddr_wr_addr_port2), + .ddr_wr_data_port2(ddr_wr_data_port2), + .ddr_wr_bytes_port2(ddr_wr_bytes_port2), + .ddr_rd_addr_port2(ddr_rd_addr_port2), + .ddr_rd_data_port2(ddr_rd_data_port2), + .ddr_rd_bytes_port2(ddr_rd_bytes_port2), + .ddr_wr_qos_port2 (ddr_wr_qos_port2), + .ddr_rd_qos_port2 (ddr_rd_qos_port2), + + /* Goes to port3 of DDR */ + .ddr_wr_ack_port3 (ddr_wr_ack_port3), + .ddr_wr_dv_port3 (ddr_wr_dv_port3), + .ddr_rd_req_port3 (ddr_rd_req_port3), + .ddr_rd_dv_port3 (ddr_rd_dv_port3), + .ddr_wr_addr_port3(ddr_wr_addr_port3), + .ddr_wr_data_port3(ddr_wr_data_port3), + .ddr_wr_bytes_port3(ddr_wr_bytes_port3), + .ddr_rd_addr_port3(ddr_rd_addr_port3), + .ddr_rd_data_port3(ddr_rd_data_port3), + .ddr_rd_bytes_port3(ddr_rd_bytes_port3), + .ddr_wr_qos_port3 (ddr_wr_qos_port3), + .ddr_rd_qos_port3 (ddr_rd_qos_port3) + + ); + + processing_system7_bfm_v2_0_ocmc ocmc ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + /* Goes to port 0 of OCM */ + .ocm_wr_ack_port0 (ocm_wr_ack_port0), + .ocm_wr_dv_port0 (ocm_wr_dv_port0), + .ocm_rd_req_port0 (ocm_rd_req_port0), + .ocm_rd_dv_port0 (ocm_rd_dv_port0), + + .ocm_wr_addr_port0(net_wr_addr_acp), + .ocm_wr_data_port0(net_wr_data_acp), + .ocm_wr_bytes_port0(net_wr_bytes_acp), + + .ocm_rd_addr_port0(net_rd_addr_acp), + .ocm_rd_bytes_port0(net_rd_bytes_acp), + + .ocm_rd_data_port0(ocm_rd_data_port0), + + .ocm_wr_qos_port0 (net_wr_qos_acp), + .ocm_rd_qos_port0 (net_rd_qos_acp), + + /* Goes to port 1 of OCM */ + .ocm_wr_ack_port1 (ocm_wr_ack_port1), + .ocm_wr_dv_port1 (ocm_wr_dv_port1), + .ocm_rd_req_port1 (ocm_rd_req_port1), + .ocm_rd_dv_port1 (ocm_rd_dv_port1), + .ocm_wr_addr_port1(ocm_wr_addr_port1), + .ocm_wr_data_port1(ocm_wr_data_port1), + .ocm_wr_bytes_port1(ocm_wr_bytes_port1), + .ocm_rd_addr_port1(ocm_rd_addr_port1), + .ocm_rd_data_port1(ocm_rd_data_port1), + .ocm_rd_bytes_port1(ocm_rd_bytes_port1), + .ocm_wr_qos_port1(ocm_wr_qos_port1), + .ocm_rd_qos_port1(ocm_rd_qos_port1) + + ); + + processing_system7_bfm_v2_0_regc regc ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + /* Goes to port 0 of REG */ + .reg_rd_req_port0 (reg_rd_req_port0), + .reg_rd_dv_port0 (reg_rd_dv_port0), + .reg_rd_addr_port0(net_rd_addr_acp), + .reg_rd_bytes_port0(net_rd_bytes_acp), + .reg_rd_data_port0(reg_rd_data_port0), + .reg_rd_qos_port0 (net_rd_qos_acp), + + /* Goes to port 1 of REG */ + .reg_rd_req_port1 (reg_rd_req_port1), + .reg_rd_dv_port1 (reg_rd_dv_port1), + .reg_rd_addr_port1(reg_rd_addr_port1), + .reg_rd_data_port1(reg_rd_data_port1), + .reg_rd_bytes_port1(reg_rd_bytes_port1), + .reg_rd_qos_port1(reg_rd_qos_port1) + + ); + + /* include axi_gp port instantiations */ + `include "processing_system7_bfm_v2_0_axi_gp.v" + + /* include axi_hp port instantiations */ + `include "processing_system7_bfm_v2_0_axi_hp.v" + + /* include axi_acp port instantiations */ + `include "processing_system7_bfm_v2_0_axi_acp.v" + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_init.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_init.v new file mode 100644 index 0000000..24aa8a7 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_init.v @@ -0,0 +1,2924 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_reg_init.v + * + * Date : 2012-11 + * + * Description : Initialize register default values. + * + *****************************************************************************/ + +// Register default value info for chip pele_ps +// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012 +// 54 modules, 2532 registers. + + +// ************************************************************ +// Module afi0 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi0__AFI_RDCHAN_CTRL, val_afi0__AFI_RDCHAN_CTRL); +set_reset_data( afi0__AFI_RDCHAN_ISSUINGCAP, val_afi0__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi0__AFI_RDQOS, val_afi0__AFI_RDQOS); +set_reset_data( afi0__AFI_RDDATAFIFO_LEVEL, val_afi0__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi0__AFI_RDDEBUG, val_afi0__AFI_RDDEBUG); +set_reset_data( afi0__AFI_WRCHAN_CTRL, val_afi0__AFI_WRCHAN_CTRL); +set_reset_data( afi0__AFI_WRCHAN_ISSUINGCAP, val_afi0__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi0__AFI_WRQOS, val_afi0__AFI_WRQOS); +set_reset_data( afi0__AFI_WRDATAFIFO_LEVEL, val_afi0__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi0__AFI_WRDEBUG, val_afi0__AFI_WRDEBUG); + +// ************************************************************ +// Module afi1 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi1__AFI_RDCHAN_CTRL, val_afi1__AFI_RDCHAN_CTRL); +set_reset_data( afi1__AFI_RDCHAN_ISSUINGCAP, val_afi1__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi1__AFI_RDQOS, val_afi1__AFI_RDQOS); +set_reset_data( afi1__AFI_RDDATAFIFO_LEVEL, val_afi1__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi1__AFI_RDDEBUG, val_afi1__AFI_RDDEBUG); +set_reset_data( afi1__AFI_WRCHAN_CTRL, val_afi1__AFI_WRCHAN_CTRL); +set_reset_data( afi1__AFI_WRCHAN_ISSUINGCAP, val_afi1__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi1__AFI_WRQOS, val_afi1__AFI_WRQOS); +set_reset_data( afi1__AFI_WRDATAFIFO_LEVEL, val_afi1__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi1__AFI_WRDEBUG, val_afi1__AFI_WRDEBUG); + +// ************************************************************ +// Module afi2 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi2__AFI_RDCHAN_CTRL, val_afi2__AFI_RDCHAN_CTRL); +set_reset_data( afi2__AFI_RDCHAN_ISSUINGCAP, val_afi2__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi2__AFI_RDQOS, val_afi2__AFI_RDQOS); +set_reset_data( afi2__AFI_RDDATAFIFO_LEVEL, val_afi2__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi2__AFI_RDDEBUG, val_afi2__AFI_RDDEBUG); +set_reset_data( afi2__AFI_WRCHAN_CTRL, val_afi2__AFI_WRCHAN_CTRL); +set_reset_data( afi2__AFI_WRCHAN_ISSUINGCAP, val_afi2__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi2__AFI_WRQOS, val_afi2__AFI_WRQOS); +set_reset_data( afi2__AFI_WRDATAFIFO_LEVEL, val_afi2__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi2__AFI_WRDEBUG, val_afi2__AFI_WRDEBUG); + +// ************************************************************ +// Module afi3 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi3__AFI_RDCHAN_CTRL, val_afi3__AFI_RDCHAN_CTRL); +set_reset_data( afi3__AFI_RDCHAN_ISSUINGCAP, val_afi3__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi3__AFI_RDQOS, val_afi3__AFI_RDQOS); +set_reset_data( afi3__AFI_RDDATAFIFO_LEVEL, val_afi3__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi3__AFI_RDDEBUG, val_afi3__AFI_RDDEBUG); +set_reset_data( afi3__AFI_WRCHAN_CTRL, val_afi3__AFI_WRCHAN_CTRL); +set_reset_data( afi3__AFI_WRCHAN_ISSUINGCAP, val_afi3__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi3__AFI_WRQOS, val_afi3__AFI_WRQOS); +set_reset_data( afi3__AFI_WRDATAFIFO_LEVEL, val_afi3__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi3__AFI_WRDEBUG, val_afi3__AFI_WRDEBUG); + +// ************************************************************ +// Module can0 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( can0__SRR, val_can0__SRR); +set_reset_data( can0__MSR, val_can0__MSR); +set_reset_data( can0__BRPR, val_can0__BRPR); +set_reset_data( can0__BTR, val_can0__BTR); +set_reset_data( can0__ECR, val_can0__ECR); +set_reset_data( can0__ESR, val_can0__ESR); +set_reset_data( can0__SR, val_can0__SR); +set_reset_data( can0__ISR, val_can0__ISR); +set_reset_data( can0__IER, val_can0__IER); +set_reset_data( can0__ICR, val_can0__ICR); +set_reset_data( can0__TCR, val_can0__TCR); +set_reset_data( can0__WIR, val_can0__WIR); +set_reset_data( can0__TXFIFO_ID, val_can0__TXFIFO_ID); +set_reset_data( can0__TXFIFO_DLC, val_can0__TXFIFO_DLC); +set_reset_data( can0__TXFIFO_DATA1, val_can0__TXFIFO_DATA1); +set_reset_data( can0__TXFIFO_DATA2, val_can0__TXFIFO_DATA2); +set_reset_data( can0__TXHPB_ID, val_can0__TXHPB_ID); +set_reset_data( can0__TXHPB_DLC, val_can0__TXHPB_DLC); +set_reset_data( can0__TXHPB_DATA1, val_can0__TXHPB_DATA1); +set_reset_data( can0__TXHPB_DATA2, val_can0__TXHPB_DATA2); +set_reset_data( can0__RXFIFO_ID, val_can0__RXFIFO_ID); +set_reset_data( can0__RXFIFO_DLC, val_can0__RXFIFO_DLC); +set_reset_data( can0__RXFIFO_DATA1, val_can0__RXFIFO_DATA1); +set_reset_data( can0__RXFIFO_DATA2, val_can0__RXFIFO_DATA2); +set_reset_data( can0__AFR, val_can0__AFR); +set_reset_data( can0__AFMR1, val_can0__AFMR1); +set_reset_data( can0__AFIR1, val_can0__AFIR1); +set_reset_data( can0__AFMR2, val_can0__AFMR2); +set_reset_data( can0__AFIR2, val_can0__AFIR2); +set_reset_data( can0__AFMR3, val_can0__AFMR3); +set_reset_data( can0__AFIR3, val_can0__AFIR3); +set_reset_data( can0__AFMR4, val_can0__AFMR4); +set_reset_data( can0__AFIR4, val_can0__AFIR4); + +// ************************************************************ +// Module can1 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( can1__SRR, val_can1__SRR); +set_reset_data( can1__MSR, val_can1__MSR); +set_reset_data( can1__BRPR, val_can1__BRPR); +set_reset_data( can1__BTR, val_can1__BTR); +set_reset_data( can1__ECR, val_can1__ECR); +set_reset_data( can1__ESR, val_can1__ESR); +set_reset_data( can1__SR, val_can1__SR); +set_reset_data( can1__ISR, val_can1__ISR); +set_reset_data( can1__IER, val_can1__IER); +set_reset_data( can1__ICR, val_can1__ICR); +set_reset_data( can1__TCR, val_can1__TCR); +set_reset_data( can1__WIR, val_can1__WIR); +set_reset_data( can1__TXFIFO_ID, val_can1__TXFIFO_ID); +set_reset_data( can1__TXFIFO_DLC, val_can1__TXFIFO_DLC); +set_reset_data( can1__TXFIFO_DATA1, val_can1__TXFIFO_DATA1); +set_reset_data( can1__TXFIFO_DATA2, val_can1__TXFIFO_DATA2); +set_reset_data( can1__TXHPB_ID, val_can1__TXHPB_ID); +set_reset_data( can1__TXHPB_DLC, val_can1__TXHPB_DLC); +set_reset_data( can1__TXHPB_DATA1, val_can1__TXHPB_DATA1); +set_reset_data( can1__TXHPB_DATA2, val_can1__TXHPB_DATA2); +set_reset_data( can1__RXFIFO_ID, val_can1__RXFIFO_ID); +set_reset_data( can1__RXFIFO_DLC, val_can1__RXFIFO_DLC); +set_reset_data( can1__RXFIFO_DATA1, val_can1__RXFIFO_DATA1); +set_reset_data( can1__RXFIFO_DATA2, val_can1__RXFIFO_DATA2); +set_reset_data( can1__AFR, val_can1__AFR); +set_reset_data( can1__AFMR1, val_can1__AFMR1); +set_reset_data( can1__AFIR1, val_can1__AFIR1); +set_reset_data( can1__AFMR2, val_can1__AFMR2); +set_reset_data( can1__AFIR2, val_can1__AFIR2); +set_reset_data( can1__AFMR3, val_can1__AFMR3); +set_reset_data( can1__AFIR3, val_can1__AFIR3); +set_reset_data( can1__AFMR4, val_can1__AFMR4); +set_reset_data( can1__AFIR4, val_can1__AFIR4); + +// ************************************************************ +// Module ddrc ddrc +// doc version: 1.25 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ddrc__ddrc_ctrl, val_ddrc__ddrc_ctrl); +set_reset_data( ddrc__Two_rank_cfg, val_ddrc__Two_rank_cfg); +set_reset_data( ddrc__HPR_reg, val_ddrc__HPR_reg); +set_reset_data( ddrc__LPR_reg, val_ddrc__LPR_reg); +set_reset_data( ddrc__WR_reg, val_ddrc__WR_reg); +set_reset_data( ddrc__DRAM_param_reg0, val_ddrc__DRAM_param_reg0); +set_reset_data( ddrc__DRAM_param_reg1, val_ddrc__DRAM_param_reg1); +set_reset_data( ddrc__DRAM_param_reg2, val_ddrc__DRAM_param_reg2); +set_reset_data( ddrc__DRAM_param_reg3, val_ddrc__DRAM_param_reg3); +set_reset_data( ddrc__DRAM_param_reg4, val_ddrc__DRAM_param_reg4); +set_reset_data( ddrc__DRAM_init_param, val_ddrc__DRAM_init_param); +set_reset_data( ddrc__DRAM_EMR_reg, val_ddrc__DRAM_EMR_reg); +set_reset_data( ddrc__DRAM_EMR_MR_reg, val_ddrc__DRAM_EMR_MR_reg); +set_reset_data( ddrc__DRAM_burst8_rdwr, val_ddrc__DRAM_burst8_rdwr); +set_reset_data( ddrc__DRAM_disable_DQ, val_ddrc__DRAM_disable_DQ); +set_reset_data( ddrc__DRAM_addr_map_bank, val_ddrc__DRAM_addr_map_bank); +set_reset_data( ddrc__DRAM_addr_map_col, val_ddrc__DRAM_addr_map_col); +set_reset_data( ddrc__DRAM_addr_map_row, val_ddrc__DRAM_addr_map_row); +set_reset_data( ddrc__DRAM_ODT_reg, val_ddrc__DRAM_ODT_reg); +set_reset_data( ddrc__phy_dbg_reg, val_ddrc__phy_dbg_reg); +set_reset_data( ddrc__phy_cmd_timeout_rddata_cpt, val_ddrc__phy_cmd_timeout_rddata_cpt); +set_reset_data( ddrc__mode_sts_reg, val_ddrc__mode_sts_reg); +set_reset_data( ddrc__DLL_calib, val_ddrc__DLL_calib); +set_reset_data( ddrc__ODT_delay_hold, val_ddrc__ODT_delay_hold); +set_reset_data( ddrc__ctrl_reg1, val_ddrc__ctrl_reg1); +set_reset_data( ddrc__ctrl_reg2, val_ddrc__ctrl_reg2); +set_reset_data( ddrc__ctrl_reg3, val_ddrc__ctrl_reg3); +set_reset_data( ddrc__ctrl_reg4, val_ddrc__ctrl_reg4); +set_reset_data( ddrc__ctrl_reg5, val_ddrc__ctrl_reg5); +set_reset_data( ddrc__ctrl_reg6, val_ddrc__ctrl_reg6); +set_reset_data( ddrc__CHE_REFRESH_TIMER01, val_ddrc__CHE_REFRESH_TIMER01); +set_reset_data( ddrc__CHE_T_ZQ, val_ddrc__CHE_T_ZQ); +set_reset_data( ddrc__CHE_T_ZQ_Short_Interval_Reg, val_ddrc__CHE_T_ZQ_Short_Interval_Reg); +set_reset_data( ddrc__deep_pwrdwn_reg, val_ddrc__deep_pwrdwn_reg); +set_reset_data( ddrc__reg_2c, val_ddrc__reg_2c); +set_reset_data( ddrc__reg_2d, val_ddrc__reg_2d); +set_reset_data( ddrc__dfi_timing, val_ddrc__dfi_timing); +set_reset_data( ddrc__refresh_timer_2, val_ddrc__refresh_timer_2); +set_reset_data( ddrc__nc_timing, val_ddrc__nc_timing); +set_reset_data( ddrc__CHE_ECC_CONTROL_REG_OFFSET, val_ddrc__CHE_ECC_CONTROL_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET); +set_reset_data( ddrc__CHE_ECC_STATS_REG_OFFSET, val_ddrc__CHE_ECC_STATS_REG_OFFSET); +set_reset_data( ddrc__ECC_scrub, val_ddrc__ECC_scrub); +set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET); +set_reset_data( ddrc__phy_rcvr_enable, val_ddrc__phy_rcvr_enable); +set_reset_data( ddrc__PHY_Config0, val_ddrc__PHY_Config0); +set_reset_data( ddrc__PHY_Config1, val_ddrc__PHY_Config1); +set_reset_data( ddrc__PHY_Config2, val_ddrc__PHY_Config2); +set_reset_data( ddrc__PHY_Config3, val_ddrc__PHY_Config3); +set_reset_data( ddrc__phy_init_ratio0, val_ddrc__phy_init_ratio0); +set_reset_data( ddrc__phy_init_ratio1, val_ddrc__phy_init_ratio1); +set_reset_data( ddrc__phy_init_ratio2, val_ddrc__phy_init_ratio2); +set_reset_data( ddrc__phy_init_ratio3, val_ddrc__phy_init_ratio3); +set_reset_data( ddrc__phy_rd_dqs_cfg0, val_ddrc__phy_rd_dqs_cfg0); +set_reset_data( ddrc__phy_rd_dqs_cfg1, val_ddrc__phy_rd_dqs_cfg1); +set_reset_data( ddrc__phy_rd_dqs_cfg2, val_ddrc__phy_rd_dqs_cfg2); +set_reset_data( ddrc__phy_rd_dqs_cfg3, val_ddrc__phy_rd_dqs_cfg3); +set_reset_data( ddrc__phy_wr_dqs_cfg0, val_ddrc__phy_wr_dqs_cfg0); +set_reset_data( ddrc__phy_wr_dqs_cfg1, val_ddrc__phy_wr_dqs_cfg1); +set_reset_data( ddrc__phy_wr_dqs_cfg2, val_ddrc__phy_wr_dqs_cfg2); +set_reset_data( ddrc__phy_wr_dqs_cfg3, val_ddrc__phy_wr_dqs_cfg3); +set_reset_data( ddrc__phy_we_cfg0, val_ddrc__phy_we_cfg0); +set_reset_data( ddrc__phy_we_cfg1, val_ddrc__phy_we_cfg1); +set_reset_data( ddrc__phy_we_cfg2, val_ddrc__phy_we_cfg2); +set_reset_data( ddrc__phy_we_cfg3, val_ddrc__phy_we_cfg3); +set_reset_data( ddrc__wr_data_slv0, val_ddrc__wr_data_slv0); +set_reset_data( ddrc__wr_data_slv1, val_ddrc__wr_data_slv1); +set_reset_data( ddrc__wr_data_slv2, val_ddrc__wr_data_slv2); +set_reset_data( ddrc__wr_data_slv3, val_ddrc__wr_data_slv3); +set_reset_data( ddrc__reg_64, val_ddrc__reg_64); +set_reset_data( ddrc__reg_65, val_ddrc__reg_65); +set_reset_data( ddrc__reg69_6a0, val_ddrc__reg69_6a0); +set_reset_data( ddrc__reg69_6a1, val_ddrc__reg69_6a1); +set_reset_data( ddrc__reg6c_6d2, val_ddrc__reg6c_6d2); +set_reset_data( ddrc__reg6c_6d3, val_ddrc__reg6c_6d3); +set_reset_data( ddrc__reg6e_710, val_ddrc__reg6e_710); +set_reset_data( ddrc__reg6e_711, val_ddrc__reg6e_711); +set_reset_data( ddrc__reg6e_712, val_ddrc__reg6e_712); +set_reset_data( ddrc__reg6e_713, val_ddrc__reg6e_713); +set_reset_data( ddrc__phy_dll_sts0, val_ddrc__phy_dll_sts0); +set_reset_data( ddrc__phy_dll_sts1, val_ddrc__phy_dll_sts1); +set_reset_data( ddrc__phy_dll_sts2, val_ddrc__phy_dll_sts2); +set_reset_data( ddrc__phy_dll_sts3, val_ddrc__phy_dll_sts3); +set_reset_data( ddrc__dll_lock_sts, val_ddrc__dll_lock_sts); +set_reset_data( ddrc__phy_ctrl_sts, val_ddrc__phy_ctrl_sts); +set_reset_data( ddrc__phy_ctrl_sts_reg2, val_ddrc__phy_ctrl_sts_reg2); +set_reset_data( ddrc__axi_id, val_ddrc__axi_id); +set_reset_data( ddrc__page_mask, val_ddrc__page_mask); +set_reset_data( ddrc__axi_priority_wr_port0, val_ddrc__axi_priority_wr_port0); +set_reset_data( ddrc__axi_priority_wr_port1, val_ddrc__axi_priority_wr_port1); +set_reset_data( ddrc__axi_priority_wr_port2, val_ddrc__axi_priority_wr_port2); +set_reset_data( ddrc__axi_priority_wr_port3, val_ddrc__axi_priority_wr_port3); +set_reset_data( ddrc__axi_priority_rd_port0, val_ddrc__axi_priority_rd_port0); +set_reset_data( ddrc__axi_priority_rd_port1, val_ddrc__axi_priority_rd_port1); +set_reset_data( ddrc__axi_priority_rd_port2, val_ddrc__axi_priority_rd_port2); +set_reset_data( ddrc__axi_priority_rd_port3, val_ddrc__axi_priority_rd_port3); +set_reset_data( ddrc__AHB_priority_cfg0, val_ddrc__AHB_priority_cfg0); +set_reset_data( ddrc__AHB_priority_cfg1, val_ddrc__AHB_priority_cfg1); +set_reset_data( ddrc__AHB_priority_cfg2, val_ddrc__AHB_priority_cfg2); +set_reset_data( ddrc__AHB_priority_cfg3, val_ddrc__AHB_priority_cfg3); +set_reset_data( ddrc__perf_mon0, val_ddrc__perf_mon0); +set_reset_data( ddrc__perf_mon1, val_ddrc__perf_mon1); +set_reset_data( ddrc__perf_mon2, val_ddrc__perf_mon2); +set_reset_data( ddrc__perf_mon3, val_ddrc__perf_mon3); +set_reset_data( ddrc__perf_mon20, val_ddrc__perf_mon20); +set_reset_data( ddrc__perf_mon21, val_ddrc__perf_mon21); +set_reset_data( ddrc__perf_mon22, val_ddrc__perf_mon22); +set_reset_data( ddrc__perf_mon23, val_ddrc__perf_mon23); +set_reset_data( ddrc__perf_mon30, val_ddrc__perf_mon30); +set_reset_data( ddrc__perf_mon31, val_ddrc__perf_mon31); +set_reset_data( ddrc__perf_mon32, val_ddrc__perf_mon32); +set_reset_data( ddrc__perf_mon33, val_ddrc__perf_mon33); +set_reset_data( ddrc__trusted_mem_cfg, val_ddrc__trusted_mem_cfg); +set_reset_data( ddrc__excl_access_cfg0, val_ddrc__excl_access_cfg0); +set_reset_data( ddrc__excl_access_cfg1, val_ddrc__excl_access_cfg1); +set_reset_data( ddrc__excl_access_cfg2, val_ddrc__excl_access_cfg2); +set_reset_data( ddrc__excl_access_cfg3, val_ddrc__excl_access_cfg3); +set_reset_data( ddrc__mode_reg_read, val_ddrc__mode_reg_read); +set_reset_data( ddrc__lpddr_ctrl0, val_ddrc__lpddr_ctrl0); +set_reset_data( ddrc__lpddr_ctrl1, val_ddrc__lpddr_ctrl1); +set_reset_data( ddrc__lpddr_ctrl2, val_ddrc__lpddr_ctrl2); +set_reset_data( ddrc__lpddr_ctrl3, val_ddrc__lpddr_ctrl3); +set_reset_data( ddrc__phy_wr_lvl_fsm, val_ddrc__phy_wr_lvl_fsm); +set_reset_data( ddrc__phy_rd_lvl_fsm, val_ddrc__phy_rd_lvl_fsm); +set_reset_data( ddrc__phy_gate_lvl_fsm, val_ddrc__phy_gate_lvl_fsm); + +// ************************************************************ +// Module debug_axim axim +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_axim__GLOBAL_CTRL, val_debug_axim__GLOBAL_CTRL); +set_reset_data( debug_axim__GLOBAL_STATUS, val_debug_axim__GLOBAL_STATUS); +set_reset_data( debug_axim__FILTER_CTRL, val_debug_axim__FILTER_CTRL); +set_reset_data( debug_axim__TRIGGER_CTRL, val_debug_axim__TRIGGER_CTRL); +set_reset_data( debug_axim__TRIGGER_STATUS, val_debug_axim__TRIGGER_STATUS); +set_reset_data( debug_axim__PACKET_CTRL, val_debug_axim__PACKET_CTRL); +set_reset_data( debug_axim__TOUT_CTRL, val_debug_axim__TOUT_CTRL); +set_reset_data( debug_axim__TOUT_THRESH, val_debug_axim__TOUT_THRESH); +set_reset_data( debug_axim__FIFO_CURRENT, val_debug_axim__FIFO_CURRENT); +set_reset_data( debug_axim__FIFO_HYSTER, val_debug_axim__FIFO_HYSTER); +set_reset_data( debug_axim__SYNC_CURRENT, val_debug_axim__SYNC_CURRENT); +set_reset_data( debug_axim__SYNC_RELOAD, val_debug_axim__SYNC_RELOAD); +set_reset_data( debug_axim__TSTMP_CURRENT, val_debug_axim__TSTMP_CURRENT); +set_reset_data( debug_axim__ADDR0_MASK, val_debug_axim__ADDR0_MASK); +set_reset_data( debug_axim__ADDR0_LOWER, val_debug_axim__ADDR0_LOWER); +set_reset_data( debug_axim__ADDR0_UPPER, val_debug_axim__ADDR0_UPPER); +set_reset_data( debug_axim__ADDR0_MISC, val_debug_axim__ADDR0_MISC); +set_reset_data( debug_axim__ADDR1_MASK, val_debug_axim__ADDR1_MASK); +set_reset_data( debug_axim__ADDR1_LOWER, val_debug_axim__ADDR1_LOWER); +set_reset_data( debug_axim__ADDR1_UPPER, val_debug_axim__ADDR1_UPPER); +set_reset_data( debug_axim__ADDR1_MISC, val_debug_axim__ADDR1_MISC); +set_reset_data( debug_axim__ADDR2_MASK, val_debug_axim__ADDR2_MASK); +set_reset_data( debug_axim__ADDR2_LOWER, val_debug_axim__ADDR2_LOWER); +set_reset_data( debug_axim__ADDR2_UPPER, val_debug_axim__ADDR2_UPPER); +set_reset_data( debug_axim__ADDR2_MISC, val_debug_axim__ADDR2_MISC); +set_reset_data( debug_axim__ADDR3_MASK, val_debug_axim__ADDR3_MASK); +set_reset_data( debug_axim__ADDR3_LOWER, val_debug_axim__ADDR3_LOWER); +set_reset_data( debug_axim__ADDR3_UPPER, val_debug_axim__ADDR3_UPPER); +set_reset_data( debug_axim__ADDR3_MISC, val_debug_axim__ADDR3_MISC); +set_reset_data( debug_axim__ID0_MASK, val_debug_axim__ID0_MASK); +set_reset_data( debug_axim__ID0_LOWER, val_debug_axim__ID0_LOWER); +set_reset_data( debug_axim__ID0_UPPER, val_debug_axim__ID0_UPPER); +set_reset_data( debug_axim__ID0_MISC, val_debug_axim__ID0_MISC); +set_reset_data( debug_axim__ID1_MASK, val_debug_axim__ID1_MASK); +set_reset_data( debug_axim__ID1_LOWER, val_debug_axim__ID1_LOWER); +set_reset_data( debug_axim__ID1_UPPER, val_debug_axim__ID1_UPPER); +set_reset_data( debug_axim__ID1_MISC, val_debug_axim__ID1_MISC); +set_reset_data( debug_axim__ID2_MASK, val_debug_axim__ID2_MASK); +set_reset_data( debug_axim__ID2_LOWER, val_debug_axim__ID2_LOWER); +set_reset_data( debug_axim__ID2_UPPER, val_debug_axim__ID2_UPPER); +set_reset_data( debug_axim__ID2_MISC, val_debug_axim__ID2_MISC); +set_reset_data( debug_axim__ID3_MASK, val_debug_axim__ID3_MASK); +set_reset_data( debug_axim__ID3_LOWER, val_debug_axim__ID3_LOWER); +set_reset_data( debug_axim__ID3_UPPER, val_debug_axim__ID3_UPPER); +set_reset_data( debug_axim__ID3_MISC, val_debug_axim__ID3_MISC); +set_reset_data( debug_axim__AXI_SEL, val_debug_axim__AXI_SEL); +set_reset_data( debug_axim__IT_TRIGOUT, val_debug_axim__IT_TRIGOUT); +set_reset_data( debug_axim__IT_TRIGOUTACK, val_debug_axim__IT_TRIGOUTACK); +set_reset_data( debug_axim__IT_TRIGIN, val_debug_axim__IT_TRIGIN); +set_reset_data( debug_axim__IT_TRIGINACK, val_debug_axim__IT_TRIGINACK); +set_reset_data( debug_axim__IT_ATBDATA, val_debug_axim__IT_ATBDATA); +set_reset_data( debug_axim__IT_ATBSTATUS, val_debug_axim__IT_ATBSTATUS); +set_reset_data( debug_axim__IT_ATBCTRL1, val_debug_axim__IT_ATBCTRL1); +set_reset_data( debug_axim__IT_ATBCTRL0, val_debug_axim__IT_ATBCTRL0); +set_reset_data( debug_axim__IT_CTRL, val_debug_axim__IT_CTRL); +set_reset_data( debug_axim__CLAIM_SET, val_debug_axim__CLAIM_SET); +set_reset_data( debug_axim__CLAIM_CLEAR, val_debug_axim__CLAIM_CLEAR); +set_reset_data( debug_axim__LOCK_ACCESS, val_debug_axim__LOCK_ACCESS); +set_reset_data( debug_axim__LOCK_STATUS, val_debug_axim__LOCK_STATUS); +set_reset_data( debug_axim__AUTH_STATUS, val_debug_axim__AUTH_STATUS); +set_reset_data( debug_axim__DEV_ID, val_debug_axim__DEV_ID); +set_reset_data( debug_axim__DEV_TYPE, val_debug_axim__DEV_TYPE); +set_reset_data( debug_axim__PERIPHID4, val_debug_axim__PERIPHID4); +set_reset_data( debug_axim__PERIPHID5, val_debug_axim__PERIPHID5); +set_reset_data( debug_axim__PERIPHID6, val_debug_axim__PERIPHID6); +set_reset_data( debug_axim__PERIPHID7, val_debug_axim__PERIPHID7); +set_reset_data( debug_axim__PERIPHID0, val_debug_axim__PERIPHID0); +set_reset_data( debug_axim__PERIPHID1, val_debug_axim__PERIPHID1); +set_reset_data( debug_axim__PERIPHID2, val_debug_axim__PERIPHID2); +set_reset_data( debug_axim__PERIPHID3, val_debug_axim__PERIPHID3); +set_reset_data( debug_axim__COMPID0, val_debug_axim__COMPID0); +set_reset_data( debug_axim__COMPID1, val_debug_axim__COMPID1); +set_reset_data( debug_axim__COMPID2, val_debug_axim__COMPID2); +set_reset_data( debug_axim__COMPID3, val_debug_axim__COMPID3); + +// ************************************************************ +// Module debug_cpu_cti0 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_cti0__CTICONTROL, val_debug_cpu_cti0__CTICONTROL); +set_reset_data( debug_cpu_cti0__CTIINTACK, val_debug_cpu_cti0__CTIINTACK); +set_reset_data( debug_cpu_cti0__CTIAPPSET, val_debug_cpu_cti0__CTIAPPSET); +set_reset_data( debug_cpu_cti0__CTIAPPCLEAR, val_debug_cpu_cti0__CTIAPPCLEAR); +set_reset_data( debug_cpu_cti0__CTIAPPPULSE, val_debug_cpu_cti0__CTIAPPPULSE); +set_reset_data( debug_cpu_cti0__CTIINEN0, val_debug_cpu_cti0__CTIINEN0); +set_reset_data( debug_cpu_cti0__CTIINEN1, val_debug_cpu_cti0__CTIINEN1); +set_reset_data( debug_cpu_cti0__CTIINEN2, val_debug_cpu_cti0__CTIINEN2); +set_reset_data( debug_cpu_cti0__CTIINEN3, val_debug_cpu_cti0__CTIINEN3); +set_reset_data( debug_cpu_cti0__CTIINEN4, val_debug_cpu_cti0__CTIINEN4); +set_reset_data( debug_cpu_cti0__CTIINEN5, val_debug_cpu_cti0__CTIINEN5); +set_reset_data( debug_cpu_cti0__CTIINEN6, val_debug_cpu_cti0__CTIINEN6); +set_reset_data( debug_cpu_cti0__CTIINEN7, val_debug_cpu_cti0__CTIINEN7); +set_reset_data( debug_cpu_cti0__CTIOUTEN0, val_debug_cpu_cti0__CTIOUTEN0); +set_reset_data( debug_cpu_cti0__CTIOUTEN1, val_debug_cpu_cti0__CTIOUTEN1); +set_reset_data( debug_cpu_cti0__CTIOUTEN2, val_debug_cpu_cti0__CTIOUTEN2); +set_reset_data( debug_cpu_cti0__CTIOUTEN3, val_debug_cpu_cti0__CTIOUTEN3); +set_reset_data( debug_cpu_cti0__CTIOUTEN4, val_debug_cpu_cti0__CTIOUTEN4); +set_reset_data( debug_cpu_cti0__CTIOUTEN5, val_debug_cpu_cti0__CTIOUTEN5); +set_reset_data( debug_cpu_cti0__CTIOUTEN6, val_debug_cpu_cti0__CTIOUTEN6); +set_reset_data( debug_cpu_cti0__CTIOUTEN7, val_debug_cpu_cti0__CTIOUTEN7); +set_reset_data( debug_cpu_cti0__CTITRIGINSTATUS, val_debug_cpu_cti0__CTITRIGINSTATUS); +set_reset_data( debug_cpu_cti0__CTITRIGOUTSTATUS, val_debug_cpu_cti0__CTITRIGOUTSTATUS); +set_reset_data( debug_cpu_cti0__CTICHINSTATUS, val_debug_cpu_cti0__CTICHINSTATUS); +set_reset_data( debug_cpu_cti0__CTICHOUTSTATUS, val_debug_cpu_cti0__CTICHOUTSTATUS); +set_reset_data( debug_cpu_cti0__CTIGATE, val_debug_cpu_cti0__CTIGATE); +set_reset_data( debug_cpu_cti0__ASICCTL, val_debug_cpu_cti0__ASICCTL); +set_reset_data( debug_cpu_cti0__ITCHINACK, val_debug_cpu_cti0__ITCHINACK); +set_reset_data( debug_cpu_cti0__ITTRIGINACK, val_debug_cpu_cti0__ITTRIGINACK); +set_reset_data( debug_cpu_cti0__ITCHOUT, val_debug_cpu_cti0__ITCHOUT); +set_reset_data( debug_cpu_cti0__ITTRIGOUT, val_debug_cpu_cti0__ITTRIGOUT); +set_reset_data( debug_cpu_cti0__ITCHOUTACK, val_debug_cpu_cti0__ITCHOUTACK); +set_reset_data( debug_cpu_cti0__ITTRIGOUTACK, val_debug_cpu_cti0__ITTRIGOUTACK); +set_reset_data( debug_cpu_cti0__ITCHIN, val_debug_cpu_cti0__ITCHIN); +set_reset_data( debug_cpu_cti0__ITTRIGIN, val_debug_cpu_cti0__ITTRIGIN); +set_reset_data( debug_cpu_cti0__ITCTRL, val_debug_cpu_cti0__ITCTRL); +set_reset_data( debug_cpu_cti0__CTSR, val_debug_cpu_cti0__CTSR); +set_reset_data( debug_cpu_cti0__CTCR, val_debug_cpu_cti0__CTCR); +set_reset_data( debug_cpu_cti0__LAR, val_debug_cpu_cti0__LAR); +set_reset_data( debug_cpu_cti0__LSR, val_debug_cpu_cti0__LSR); +set_reset_data( debug_cpu_cti0__ASR, val_debug_cpu_cti0__ASR); +set_reset_data( debug_cpu_cti0__DEVID, val_debug_cpu_cti0__DEVID); +set_reset_data( debug_cpu_cti0__DTIR, val_debug_cpu_cti0__DTIR); +set_reset_data( debug_cpu_cti0__PERIPHID4, val_debug_cpu_cti0__PERIPHID4); +set_reset_data( debug_cpu_cti0__PERIPHID5, val_debug_cpu_cti0__PERIPHID5); +set_reset_data( debug_cpu_cti0__PERIPHID6, val_debug_cpu_cti0__PERIPHID6); +set_reset_data( debug_cpu_cti0__PERIPHID7, val_debug_cpu_cti0__PERIPHID7); +set_reset_data( debug_cpu_cti0__PERIPHID0, val_debug_cpu_cti0__PERIPHID0); +set_reset_data( debug_cpu_cti0__PERIPHID1, val_debug_cpu_cti0__PERIPHID1); +set_reset_data( debug_cpu_cti0__PERIPHID2, val_debug_cpu_cti0__PERIPHID2); +set_reset_data( debug_cpu_cti0__PERIPHID3, val_debug_cpu_cti0__PERIPHID3); +set_reset_data( debug_cpu_cti0__COMPID0, val_debug_cpu_cti0__COMPID0); +set_reset_data( debug_cpu_cti0__COMPID1, val_debug_cpu_cti0__COMPID1); +set_reset_data( debug_cpu_cti0__COMPID2, val_debug_cpu_cti0__COMPID2); +set_reset_data( debug_cpu_cti0__COMPID3, val_debug_cpu_cti0__COMPID3); + +// ************************************************************ +// Module debug_cpu_cti1 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_cti1__CTICONTROL, val_debug_cpu_cti1__CTICONTROL); +set_reset_data( debug_cpu_cti1__CTIINTACK, val_debug_cpu_cti1__CTIINTACK); +set_reset_data( debug_cpu_cti1__CTIAPPSET, val_debug_cpu_cti1__CTIAPPSET); +set_reset_data( debug_cpu_cti1__CTIAPPCLEAR, val_debug_cpu_cti1__CTIAPPCLEAR); +set_reset_data( debug_cpu_cti1__CTIAPPPULSE, val_debug_cpu_cti1__CTIAPPPULSE); +set_reset_data( debug_cpu_cti1__CTIINEN0, val_debug_cpu_cti1__CTIINEN0); +set_reset_data( debug_cpu_cti1__CTIINEN1, val_debug_cpu_cti1__CTIINEN1); +set_reset_data( debug_cpu_cti1__CTIINEN2, val_debug_cpu_cti1__CTIINEN2); +set_reset_data( debug_cpu_cti1__CTIINEN3, val_debug_cpu_cti1__CTIINEN3); +set_reset_data( debug_cpu_cti1__CTIINEN4, val_debug_cpu_cti1__CTIINEN4); +set_reset_data( debug_cpu_cti1__CTIINEN5, val_debug_cpu_cti1__CTIINEN5); +set_reset_data( debug_cpu_cti1__CTIINEN6, val_debug_cpu_cti1__CTIINEN6); +set_reset_data( debug_cpu_cti1__CTIINEN7, val_debug_cpu_cti1__CTIINEN7); +set_reset_data( debug_cpu_cti1__CTIOUTEN0, val_debug_cpu_cti1__CTIOUTEN0); +set_reset_data( debug_cpu_cti1__CTIOUTEN1, val_debug_cpu_cti1__CTIOUTEN1); +set_reset_data( debug_cpu_cti1__CTIOUTEN2, val_debug_cpu_cti1__CTIOUTEN2); +set_reset_data( debug_cpu_cti1__CTIOUTEN3, val_debug_cpu_cti1__CTIOUTEN3); +set_reset_data( debug_cpu_cti1__CTIOUTEN4, val_debug_cpu_cti1__CTIOUTEN4); +set_reset_data( debug_cpu_cti1__CTIOUTEN5, val_debug_cpu_cti1__CTIOUTEN5); +set_reset_data( debug_cpu_cti1__CTIOUTEN6, val_debug_cpu_cti1__CTIOUTEN6); +set_reset_data( debug_cpu_cti1__CTIOUTEN7, val_debug_cpu_cti1__CTIOUTEN7); +set_reset_data( debug_cpu_cti1__CTITRIGINSTATUS, val_debug_cpu_cti1__CTITRIGINSTATUS); +set_reset_data( debug_cpu_cti1__CTITRIGOUTSTATUS, val_debug_cpu_cti1__CTITRIGOUTSTATUS); +set_reset_data( debug_cpu_cti1__CTICHINSTATUS, val_debug_cpu_cti1__CTICHINSTATUS); +set_reset_data( debug_cpu_cti1__CTICHOUTSTATUS, val_debug_cpu_cti1__CTICHOUTSTATUS); +set_reset_data( debug_cpu_cti1__CTIGATE, val_debug_cpu_cti1__CTIGATE); +set_reset_data( debug_cpu_cti1__ASICCTL, val_debug_cpu_cti1__ASICCTL); +set_reset_data( debug_cpu_cti1__ITCHINACK, val_debug_cpu_cti1__ITCHINACK); +set_reset_data( debug_cpu_cti1__ITTRIGINACK, val_debug_cpu_cti1__ITTRIGINACK); +set_reset_data( debug_cpu_cti1__ITCHOUT, val_debug_cpu_cti1__ITCHOUT); +set_reset_data( debug_cpu_cti1__ITTRIGOUT, val_debug_cpu_cti1__ITTRIGOUT); +set_reset_data( debug_cpu_cti1__ITCHOUTACK, val_debug_cpu_cti1__ITCHOUTACK); +set_reset_data( debug_cpu_cti1__ITTRIGOUTACK, val_debug_cpu_cti1__ITTRIGOUTACK); +set_reset_data( debug_cpu_cti1__ITCHIN, val_debug_cpu_cti1__ITCHIN); +set_reset_data( debug_cpu_cti1__ITTRIGIN, val_debug_cpu_cti1__ITTRIGIN); +set_reset_data( debug_cpu_cti1__ITCTRL, val_debug_cpu_cti1__ITCTRL); +set_reset_data( debug_cpu_cti1__CTSR, val_debug_cpu_cti1__CTSR); +set_reset_data( debug_cpu_cti1__CTCR, val_debug_cpu_cti1__CTCR); +set_reset_data( debug_cpu_cti1__LAR, val_debug_cpu_cti1__LAR); +set_reset_data( debug_cpu_cti1__LSR, val_debug_cpu_cti1__LSR); +set_reset_data( debug_cpu_cti1__ASR, val_debug_cpu_cti1__ASR); +set_reset_data( debug_cpu_cti1__DEVID, val_debug_cpu_cti1__DEVID); +set_reset_data( debug_cpu_cti1__DTIR, val_debug_cpu_cti1__DTIR); +set_reset_data( debug_cpu_cti1__PERIPHID4, val_debug_cpu_cti1__PERIPHID4); +set_reset_data( debug_cpu_cti1__PERIPHID5, val_debug_cpu_cti1__PERIPHID5); +set_reset_data( debug_cpu_cti1__PERIPHID6, val_debug_cpu_cti1__PERIPHID6); +set_reset_data( debug_cpu_cti1__PERIPHID7, val_debug_cpu_cti1__PERIPHID7); +set_reset_data( debug_cpu_cti1__PERIPHID0, val_debug_cpu_cti1__PERIPHID0); +set_reset_data( debug_cpu_cti1__PERIPHID1, val_debug_cpu_cti1__PERIPHID1); +set_reset_data( debug_cpu_cti1__PERIPHID2, val_debug_cpu_cti1__PERIPHID2); +set_reset_data( debug_cpu_cti1__PERIPHID3, val_debug_cpu_cti1__PERIPHID3); +set_reset_data( debug_cpu_cti1__COMPID0, val_debug_cpu_cti1__COMPID0); +set_reset_data( debug_cpu_cti1__COMPID1, val_debug_cpu_cti1__COMPID1); +set_reset_data( debug_cpu_cti1__COMPID2, val_debug_cpu_cti1__COMPID2); +set_reset_data( debug_cpu_cti1__COMPID3, val_debug_cpu_cti1__COMPID3); + +// ************************************************************ +// Module debug_cpu_pmu0 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_pmu0__PMXEVCNTR0, val_debug_cpu_pmu0__PMXEVCNTR0); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR1, val_debug_cpu_pmu0__PMXEVCNTR1); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR2, val_debug_cpu_pmu0__PMXEVCNTR2); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR3, val_debug_cpu_pmu0__PMXEVCNTR3); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR4, val_debug_cpu_pmu0__PMXEVCNTR4); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR5, val_debug_cpu_pmu0__PMXEVCNTR5); +set_reset_data( debug_cpu_pmu0__PMCCNTR, val_debug_cpu_pmu0__PMCCNTR); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER0, val_debug_cpu_pmu0__PMXEVTYPER0); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER1, val_debug_cpu_pmu0__PMXEVTYPER1); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER2, val_debug_cpu_pmu0__PMXEVTYPER2); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER3, val_debug_cpu_pmu0__PMXEVTYPER3); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER4, val_debug_cpu_pmu0__PMXEVTYPER4); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER5, val_debug_cpu_pmu0__PMXEVTYPER5); +set_reset_data( debug_cpu_pmu0__PMCNTENSET, val_debug_cpu_pmu0__PMCNTENSET); +set_reset_data( debug_cpu_pmu0__PMCNTENCLR, val_debug_cpu_pmu0__PMCNTENCLR); +set_reset_data( debug_cpu_pmu0__PMINTENSET, val_debug_cpu_pmu0__PMINTENSET); +set_reset_data( debug_cpu_pmu0__PMINTENCLR, val_debug_cpu_pmu0__PMINTENCLR); +set_reset_data( debug_cpu_pmu0__PMOVSR, val_debug_cpu_pmu0__PMOVSR); +set_reset_data( debug_cpu_pmu0__PMSWINC, val_debug_cpu_pmu0__PMSWINC); +set_reset_data( debug_cpu_pmu0__PMCR, val_debug_cpu_pmu0__PMCR); +set_reset_data( debug_cpu_pmu0__PMUSERENR, val_debug_cpu_pmu0__PMUSERENR); + +// ************************************************************ +// Module debug_cpu_pmu1 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_pmu1__PMXEVCNTR0, val_debug_cpu_pmu1__PMXEVCNTR0); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR1, val_debug_cpu_pmu1__PMXEVCNTR1); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR2, val_debug_cpu_pmu1__PMXEVCNTR2); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR3, val_debug_cpu_pmu1__PMXEVCNTR3); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR4, val_debug_cpu_pmu1__PMXEVCNTR4); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR5, val_debug_cpu_pmu1__PMXEVCNTR5); +set_reset_data( debug_cpu_pmu1__PMCCNTR, val_debug_cpu_pmu1__PMCCNTR); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER0, val_debug_cpu_pmu1__PMXEVTYPER0); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER1, val_debug_cpu_pmu1__PMXEVTYPER1); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER2, val_debug_cpu_pmu1__PMXEVTYPER2); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER3, val_debug_cpu_pmu1__PMXEVTYPER3); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER4, val_debug_cpu_pmu1__PMXEVTYPER4); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER5, val_debug_cpu_pmu1__PMXEVTYPER5); +set_reset_data( debug_cpu_pmu1__PMCNTENSET, val_debug_cpu_pmu1__PMCNTENSET); +set_reset_data( debug_cpu_pmu1__PMCNTENCLR, val_debug_cpu_pmu1__PMCNTENCLR); +set_reset_data( debug_cpu_pmu1__PMINTENSET, val_debug_cpu_pmu1__PMINTENSET); +set_reset_data( debug_cpu_pmu1__PMINTENCLR, val_debug_cpu_pmu1__PMINTENCLR); +set_reset_data( debug_cpu_pmu1__PMOVSR, val_debug_cpu_pmu1__PMOVSR); +set_reset_data( debug_cpu_pmu1__PMSWINC, val_debug_cpu_pmu1__PMSWINC); +set_reset_data( debug_cpu_pmu1__PMCR, val_debug_cpu_pmu1__PMCR); +set_reset_data( debug_cpu_pmu1__PMUSERENR, val_debug_cpu_pmu1__PMUSERENR); + +// ************************************************************ +// Module debug_cpu_ptm0 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_ptm0__ETMCR, val_debug_cpu_ptm0__ETMCR); +set_reset_data( debug_cpu_ptm0__ETMCCR, val_debug_cpu_ptm0__ETMCCR); +set_reset_data( debug_cpu_ptm0__ETMTRIGGER, val_debug_cpu_ptm0__ETMTRIGGER); +set_reset_data( debug_cpu_ptm0__ETMSR, val_debug_cpu_ptm0__ETMSR); +set_reset_data( debug_cpu_ptm0__ETMSCR, val_debug_cpu_ptm0__ETMSCR); +set_reset_data( debug_cpu_ptm0__ETMTSSCR, val_debug_cpu_ptm0__ETMTSSCR); +set_reset_data( debug_cpu_ptm0__ETMTECR1, val_debug_cpu_ptm0__ETMTECR1); +set_reset_data( debug_cpu_ptm0__ETMACVR1, val_debug_cpu_ptm0__ETMACVR1); +set_reset_data( debug_cpu_ptm0__ETMACVR2, val_debug_cpu_ptm0__ETMACVR2); +set_reset_data( debug_cpu_ptm0__ETMACVR3, val_debug_cpu_ptm0__ETMACVR3); +set_reset_data( debug_cpu_ptm0__ETMACVR4, val_debug_cpu_ptm0__ETMACVR4); +set_reset_data( debug_cpu_ptm0__ETMACVR5, val_debug_cpu_ptm0__ETMACVR5); +set_reset_data( debug_cpu_ptm0__ETMACVR6, val_debug_cpu_ptm0__ETMACVR6); +set_reset_data( debug_cpu_ptm0__ETMACVR7, val_debug_cpu_ptm0__ETMACVR7); +set_reset_data( debug_cpu_ptm0__ETMACVR8, val_debug_cpu_ptm0__ETMACVR8); +set_reset_data( debug_cpu_ptm0__ETMACTR1, val_debug_cpu_ptm0__ETMACTR1); +set_reset_data( debug_cpu_ptm0__ETMACTR2, val_debug_cpu_ptm0__ETMACTR2); +set_reset_data( debug_cpu_ptm0__ETMACTR3, val_debug_cpu_ptm0__ETMACTR3); +set_reset_data( debug_cpu_ptm0__ETMACTR4, val_debug_cpu_ptm0__ETMACTR4); +set_reset_data( debug_cpu_ptm0__ETMACTR5, val_debug_cpu_ptm0__ETMACTR5); +set_reset_data( debug_cpu_ptm0__ETMACTR6, val_debug_cpu_ptm0__ETMACTR6); +set_reset_data( debug_cpu_ptm0__ETMACTR7, val_debug_cpu_ptm0__ETMACTR7); +set_reset_data( debug_cpu_ptm0__ETMACTR8, val_debug_cpu_ptm0__ETMACTR8); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR1, val_debug_cpu_ptm0__ETMCNTRLDVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR2, val_debug_cpu_ptm0__ETMCNTRLDVR2); +set_reset_data( debug_cpu_ptm0__ETMCNTENR1, val_debug_cpu_ptm0__ETMCNTENR1); +set_reset_data( debug_cpu_ptm0__ETMCNTENR2, val_debug_cpu_ptm0__ETMCNTENR2); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR1, val_debug_cpu_ptm0__ETMCNTRLDEVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR2, val_debug_cpu_ptm0__ETMCNTRLDEVR2); +set_reset_data( debug_cpu_ptm0__ETMCNTVR1, val_debug_cpu_ptm0__ETMCNTVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTVR2, val_debug_cpu_ptm0__ETMCNTVR2); +set_reset_data( debug_cpu_ptm0__ETMSQ12EVR, val_debug_cpu_ptm0__ETMSQ12EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ21EVR, val_debug_cpu_ptm0__ETMSQ21EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ23EVR, val_debug_cpu_ptm0__ETMSQ23EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ31EVR, val_debug_cpu_ptm0__ETMSQ31EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ32EVR, val_debug_cpu_ptm0__ETMSQ32EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ13EVR, val_debug_cpu_ptm0__ETMSQ13EVR); +set_reset_data( debug_cpu_ptm0__ETMSQR, val_debug_cpu_ptm0__ETMSQR); +set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR1, val_debug_cpu_ptm0__ETMEXTOUTEVR1); +set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR2, val_debug_cpu_ptm0__ETMEXTOUTEVR2); +set_reset_data( debug_cpu_ptm0__ETMCIDCVR1, val_debug_cpu_ptm0__ETMCIDCVR1); +set_reset_data( debug_cpu_ptm0__ETMCIDCMR, val_debug_cpu_ptm0__ETMCIDCMR); +set_reset_data( debug_cpu_ptm0__ETMSYNCFR, val_debug_cpu_ptm0__ETMSYNCFR); +set_reset_data( debug_cpu_ptm0__ETMIDR, val_debug_cpu_ptm0__ETMIDR); +set_reset_data( debug_cpu_ptm0__ETMCCER, val_debug_cpu_ptm0__ETMCCER); +set_reset_data( debug_cpu_ptm0__ETMEXTINSELR, val_debug_cpu_ptm0__ETMEXTINSELR); +set_reset_data( debug_cpu_ptm0__ETMAUXCR, val_debug_cpu_ptm0__ETMAUXCR); +set_reset_data( debug_cpu_ptm0__ETMTRACEIDR, val_debug_cpu_ptm0__ETMTRACEIDR); +set_reset_data( debug_cpu_ptm0__OSLSR, val_debug_cpu_ptm0__OSLSR); +set_reset_data( debug_cpu_ptm0__ETMPDSR, val_debug_cpu_ptm0__ETMPDSR); +set_reset_data( debug_cpu_ptm0__ITMISCOUT, val_debug_cpu_ptm0__ITMISCOUT); +set_reset_data( debug_cpu_ptm0__ITMISCIN, val_debug_cpu_ptm0__ITMISCIN); +set_reset_data( debug_cpu_ptm0__ITTRIGGER, val_debug_cpu_ptm0__ITTRIGGER); +set_reset_data( debug_cpu_ptm0__ITATBDATA0, val_debug_cpu_ptm0__ITATBDATA0); +set_reset_data( debug_cpu_ptm0__ITATBCTR2, val_debug_cpu_ptm0__ITATBCTR2); +set_reset_data( debug_cpu_ptm0__ITATBID, val_debug_cpu_ptm0__ITATBID); +set_reset_data( debug_cpu_ptm0__ITATBCTR0, val_debug_cpu_ptm0__ITATBCTR0); +set_reset_data( debug_cpu_ptm0__ETMITCTRL, val_debug_cpu_ptm0__ETMITCTRL); +set_reset_data( debug_cpu_ptm0__CTSR, val_debug_cpu_ptm0__CTSR); +set_reset_data( debug_cpu_ptm0__CTCR, val_debug_cpu_ptm0__CTCR); +set_reset_data( debug_cpu_ptm0__LAR, val_debug_cpu_ptm0__LAR); +set_reset_data( debug_cpu_ptm0__LSR, val_debug_cpu_ptm0__LSR); +set_reset_data( debug_cpu_ptm0__ASR, val_debug_cpu_ptm0__ASR); +set_reset_data( debug_cpu_ptm0__DEVID, val_debug_cpu_ptm0__DEVID); +set_reset_data( debug_cpu_ptm0__DTIR, val_debug_cpu_ptm0__DTIR); +set_reset_data( debug_cpu_ptm0__PERIPHID4, val_debug_cpu_ptm0__PERIPHID4); +set_reset_data( debug_cpu_ptm0__PERIPHID5, val_debug_cpu_ptm0__PERIPHID5); +set_reset_data( debug_cpu_ptm0__PERIPHID6, val_debug_cpu_ptm0__PERIPHID6); +set_reset_data( debug_cpu_ptm0__PERIPHID7, val_debug_cpu_ptm0__PERIPHID7); +set_reset_data( debug_cpu_ptm0__PERIPHID0, val_debug_cpu_ptm0__PERIPHID0); +set_reset_data( debug_cpu_ptm0__PERIPHID1, val_debug_cpu_ptm0__PERIPHID1); +set_reset_data( debug_cpu_ptm0__PERIPHID2, val_debug_cpu_ptm0__PERIPHID2); +set_reset_data( debug_cpu_ptm0__PERIPHID3, val_debug_cpu_ptm0__PERIPHID3); +set_reset_data( debug_cpu_ptm0__COMPID0, val_debug_cpu_ptm0__COMPID0); +set_reset_data( debug_cpu_ptm0__COMPID1, val_debug_cpu_ptm0__COMPID1); +set_reset_data( debug_cpu_ptm0__COMPID2, val_debug_cpu_ptm0__COMPID2); +set_reset_data( debug_cpu_ptm0__COMPID3, val_debug_cpu_ptm0__COMPID3); + +// ************************************************************ +// Module debug_cpu_ptm1 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_ptm1__ETMCR, val_debug_cpu_ptm1__ETMCR); +set_reset_data( debug_cpu_ptm1__ETMCCR, val_debug_cpu_ptm1__ETMCCR); +set_reset_data( debug_cpu_ptm1__ETMTRIGGER, val_debug_cpu_ptm1__ETMTRIGGER); +set_reset_data( debug_cpu_ptm1__ETMSR, val_debug_cpu_ptm1__ETMSR); +set_reset_data( debug_cpu_ptm1__ETMSCR, val_debug_cpu_ptm1__ETMSCR); +set_reset_data( debug_cpu_ptm1__ETMTSSCR, val_debug_cpu_ptm1__ETMTSSCR); +set_reset_data( debug_cpu_ptm1__ETMTECR1, val_debug_cpu_ptm1__ETMTECR1); +set_reset_data( debug_cpu_ptm1__ETMACVR1, val_debug_cpu_ptm1__ETMACVR1); +set_reset_data( debug_cpu_ptm1__ETMACVR2, val_debug_cpu_ptm1__ETMACVR2); +set_reset_data( debug_cpu_ptm1__ETMACVR3, val_debug_cpu_ptm1__ETMACVR3); +set_reset_data( debug_cpu_ptm1__ETMACVR4, val_debug_cpu_ptm1__ETMACVR4); +set_reset_data( debug_cpu_ptm1__ETMACVR5, val_debug_cpu_ptm1__ETMACVR5); +set_reset_data( debug_cpu_ptm1__ETMACVR6, val_debug_cpu_ptm1__ETMACVR6); +set_reset_data( debug_cpu_ptm1__ETMACVR7, val_debug_cpu_ptm1__ETMACVR7); +set_reset_data( debug_cpu_ptm1__ETMACVR8, val_debug_cpu_ptm1__ETMACVR8); +set_reset_data( debug_cpu_ptm1__ETMACTR1, val_debug_cpu_ptm1__ETMACTR1); +set_reset_data( debug_cpu_ptm1__ETMACTR2, val_debug_cpu_ptm1__ETMACTR2); +set_reset_data( debug_cpu_ptm1__ETMACTR3, val_debug_cpu_ptm1__ETMACTR3); +set_reset_data( debug_cpu_ptm1__ETMACTR4, val_debug_cpu_ptm1__ETMACTR4); +set_reset_data( debug_cpu_ptm1__ETMACTR5, val_debug_cpu_ptm1__ETMACTR5); +set_reset_data( debug_cpu_ptm1__ETMACTR6, val_debug_cpu_ptm1__ETMACTR6); +set_reset_data( debug_cpu_ptm1__ETMACTR7, val_debug_cpu_ptm1__ETMACTR7); +set_reset_data( debug_cpu_ptm1__ETMACTR8, val_debug_cpu_ptm1__ETMACTR8); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR1, val_debug_cpu_ptm1__ETMCNTRLDVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR2, val_debug_cpu_ptm1__ETMCNTRLDVR2); +set_reset_data( debug_cpu_ptm1__ETMCNTENR1, val_debug_cpu_ptm1__ETMCNTENR1); +set_reset_data( debug_cpu_ptm1__ETMCNTENR2, val_debug_cpu_ptm1__ETMCNTENR2); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR1, val_debug_cpu_ptm1__ETMCNTRLDEVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR2, val_debug_cpu_ptm1__ETMCNTRLDEVR2); +set_reset_data( debug_cpu_ptm1__ETMCNTVR1, val_debug_cpu_ptm1__ETMCNTVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTVR2, val_debug_cpu_ptm1__ETMCNTVR2); +set_reset_data( debug_cpu_ptm1__ETMSQ12EVR, val_debug_cpu_ptm1__ETMSQ12EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ21EVR, val_debug_cpu_ptm1__ETMSQ21EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ23EVR, val_debug_cpu_ptm1__ETMSQ23EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ31EVR, val_debug_cpu_ptm1__ETMSQ31EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ32EVR, val_debug_cpu_ptm1__ETMSQ32EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ13EVR, val_debug_cpu_ptm1__ETMSQ13EVR); +set_reset_data( debug_cpu_ptm1__ETMSQR, val_debug_cpu_ptm1__ETMSQR); +set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR1, val_debug_cpu_ptm1__ETMEXTOUTEVR1); +set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR2, val_debug_cpu_ptm1__ETMEXTOUTEVR2); +set_reset_data( debug_cpu_ptm1__ETMCIDCVR1, val_debug_cpu_ptm1__ETMCIDCVR1); +set_reset_data( debug_cpu_ptm1__ETMCIDCMR, val_debug_cpu_ptm1__ETMCIDCMR); +set_reset_data( debug_cpu_ptm1__ETMSYNCFR, val_debug_cpu_ptm1__ETMSYNCFR); +set_reset_data( debug_cpu_ptm1__ETMIDR, val_debug_cpu_ptm1__ETMIDR); +set_reset_data( debug_cpu_ptm1__ETMCCER, val_debug_cpu_ptm1__ETMCCER); +set_reset_data( debug_cpu_ptm1__ETMEXTINSELR, val_debug_cpu_ptm1__ETMEXTINSELR); +set_reset_data( debug_cpu_ptm1__ETMAUXCR, val_debug_cpu_ptm1__ETMAUXCR); +set_reset_data( debug_cpu_ptm1__ETMTRACEIDR, val_debug_cpu_ptm1__ETMTRACEIDR); +set_reset_data( debug_cpu_ptm1__OSLSR, val_debug_cpu_ptm1__OSLSR); +set_reset_data( debug_cpu_ptm1__ETMPDSR, val_debug_cpu_ptm1__ETMPDSR); +set_reset_data( debug_cpu_ptm1__ITMISCOUT, val_debug_cpu_ptm1__ITMISCOUT); +set_reset_data( debug_cpu_ptm1__ITMISCIN, val_debug_cpu_ptm1__ITMISCIN); +set_reset_data( debug_cpu_ptm1__ITTRIGGER, val_debug_cpu_ptm1__ITTRIGGER); +set_reset_data( debug_cpu_ptm1__ITATBDATA0, val_debug_cpu_ptm1__ITATBDATA0); +set_reset_data( debug_cpu_ptm1__ITATBCTR2, val_debug_cpu_ptm1__ITATBCTR2); +set_reset_data( debug_cpu_ptm1__ITATBID, val_debug_cpu_ptm1__ITATBID); +set_reset_data( debug_cpu_ptm1__ITATBCTR0, val_debug_cpu_ptm1__ITATBCTR0); +set_reset_data( debug_cpu_ptm1__ETMITCTRL, val_debug_cpu_ptm1__ETMITCTRL); +set_reset_data( debug_cpu_ptm1__CTSR, val_debug_cpu_ptm1__CTSR); +set_reset_data( debug_cpu_ptm1__CTCR, val_debug_cpu_ptm1__CTCR); +set_reset_data( debug_cpu_ptm1__LAR, val_debug_cpu_ptm1__LAR); +set_reset_data( debug_cpu_ptm1__LSR, val_debug_cpu_ptm1__LSR); +set_reset_data( debug_cpu_ptm1__ASR, val_debug_cpu_ptm1__ASR); +set_reset_data( debug_cpu_ptm1__DEVID, val_debug_cpu_ptm1__DEVID); +set_reset_data( debug_cpu_ptm1__DTIR, val_debug_cpu_ptm1__DTIR); +set_reset_data( debug_cpu_ptm1__PERIPHID4, val_debug_cpu_ptm1__PERIPHID4); +set_reset_data( debug_cpu_ptm1__PERIPHID5, val_debug_cpu_ptm1__PERIPHID5); +set_reset_data( debug_cpu_ptm1__PERIPHID6, val_debug_cpu_ptm1__PERIPHID6); +set_reset_data( debug_cpu_ptm1__PERIPHID7, val_debug_cpu_ptm1__PERIPHID7); +set_reset_data( debug_cpu_ptm1__PERIPHID0, val_debug_cpu_ptm1__PERIPHID0); +set_reset_data( debug_cpu_ptm1__PERIPHID1, val_debug_cpu_ptm1__PERIPHID1); +set_reset_data( debug_cpu_ptm1__PERIPHID2, val_debug_cpu_ptm1__PERIPHID2); +set_reset_data( debug_cpu_ptm1__PERIPHID3, val_debug_cpu_ptm1__PERIPHID3); +set_reset_data( debug_cpu_ptm1__COMPID0, val_debug_cpu_ptm1__COMPID0); +set_reset_data( debug_cpu_ptm1__COMPID1, val_debug_cpu_ptm1__COMPID1); +set_reset_data( debug_cpu_ptm1__COMPID2, val_debug_cpu_ptm1__COMPID2); +set_reset_data( debug_cpu_ptm1__COMPID3, val_debug_cpu_ptm1__COMPID3); + +// ************************************************************ +// Module debug_cti_axim cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_axim__CTICONTROL, val_debug_cti_axim__CTICONTROL); +set_reset_data( debug_cti_axim__CTIINTACK, val_debug_cti_axim__CTIINTACK); +set_reset_data( debug_cti_axim__CTIAPPSET, val_debug_cti_axim__CTIAPPSET); +set_reset_data( debug_cti_axim__CTIAPPCLEAR, val_debug_cti_axim__CTIAPPCLEAR); +set_reset_data( debug_cti_axim__CTIAPPPULSE, val_debug_cti_axim__CTIAPPPULSE); +set_reset_data( debug_cti_axim__CTIINEN0, val_debug_cti_axim__CTIINEN0); +set_reset_data( debug_cti_axim__CTIINEN1, val_debug_cti_axim__CTIINEN1); +set_reset_data( debug_cti_axim__CTIINEN2, val_debug_cti_axim__CTIINEN2); +set_reset_data( debug_cti_axim__CTIINEN3, val_debug_cti_axim__CTIINEN3); +set_reset_data( debug_cti_axim__CTIINEN4, val_debug_cti_axim__CTIINEN4); +set_reset_data( debug_cti_axim__CTIINEN5, val_debug_cti_axim__CTIINEN5); +set_reset_data( debug_cti_axim__CTIINEN6, val_debug_cti_axim__CTIINEN6); +set_reset_data( debug_cti_axim__CTIINEN7, val_debug_cti_axim__CTIINEN7); +set_reset_data( debug_cti_axim__CTIOUTEN0, val_debug_cti_axim__CTIOUTEN0); +set_reset_data( debug_cti_axim__CTIOUTEN1, val_debug_cti_axim__CTIOUTEN1); +set_reset_data( debug_cti_axim__CTIOUTEN2, val_debug_cti_axim__CTIOUTEN2); +set_reset_data( debug_cti_axim__CTIOUTEN3, val_debug_cti_axim__CTIOUTEN3); +set_reset_data( debug_cti_axim__CTIOUTEN4, val_debug_cti_axim__CTIOUTEN4); +set_reset_data( debug_cti_axim__CTIOUTEN5, val_debug_cti_axim__CTIOUTEN5); +set_reset_data( debug_cti_axim__CTIOUTEN6, val_debug_cti_axim__CTIOUTEN6); +set_reset_data( debug_cti_axim__CTIOUTEN7, val_debug_cti_axim__CTIOUTEN7); +set_reset_data( debug_cti_axim__CTITRIGINSTATUS, val_debug_cti_axim__CTITRIGINSTATUS); +set_reset_data( debug_cti_axim__CTITRIGOUTSTATUS, val_debug_cti_axim__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_axim__CTICHINSTATUS, val_debug_cti_axim__CTICHINSTATUS); +set_reset_data( debug_cti_axim__CTICHOUTSTATUS, val_debug_cti_axim__CTICHOUTSTATUS); +set_reset_data( debug_cti_axim__CTIGATE, val_debug_cti_axim__CTIGATE); +set_reset_data( debug_cti_axim__ASICCTL, val_debug_cti_axim__ASICCTL); +set_reset_data( debug_cti_axim__ITCHINACK, val_debug_cti_axim__ITCHINACK); +set_reset_data( debug_cti_axim__ITTRIGINACK, val_debug_cti_axim__ITTRIGINACK); +set_reset_data( debug_cti_axim__ITCHOUT, val_debug_cti_axim__ITCHOUT); +set_reset_data( debug_cti_axim__ITTRIGOUT, val_debug_cti_axim__ITTRIGOUT); +set_reset_data( debug_cti_axim__ITCHOUTACK, val_debug_cti_axim__ITCHOUTACK); +set_reset_data( debug_cti_axim__ITTRIGOUTACK, val_debug_cti_axim__ITTRIGOUTACK); +set_reset_data( debug_cti_axim__ITCHIN, val_debug_cti_axim__ITCHIN); +set_reset_data( debug_cti_axim__ITTRIGIN, val_debug_cti_axim__ITTRIGIN); +set_reset_data( debug_cti_axim__ITCTRL, val_debug_cti_axim__ITCTRL); +set_reset_data( debug_cti_axim__CTSR, val_debug_cti_axim__CTSR); +set_reset_data( debug_cti_axim__CTCR, val_debug_cti_axim__CTCR); +set_reset_data( debug_cti_axim__LAR, val_debug_cti_axim__LAR); +set_reset_data( debug_cti_axim__LSR, val_debug_cti_axim__LSR); +set_reset_data( debug_cti_axim__ASR, val_debug_cti_axim__ASR); +set_reset_data( debug_cti_axim__DEVID, val_debug_cti_axim__DEVID); +set_reset_data( debug_cti_axim__DTIR, val_debug_cti_axim__DTIR); +set_reset_data( debug_cti_axim__PERIPHID4, val_debug_cti_axim__PERIPHID4); +set_reset_data( debug_cti_axim__PERIPHID5, val_debug_cti_axim__PERIPHID5); +set_reset_data( debug_cti_axim__PERIPHID6, val_debug_cti_axim__PERIPHID6); +set_reset_data( debug_cti_axim__PERIPHID7, val_debug_cti_axim__PERIPHID7); +set_reset_data( debug_cti_axim__PERIPHID0, val_debug_cti_axim__PERIPHID0); +set_reset_data( debug_cti_axim__PERIPHID1, val_debug_cti_axim__PERIPHID1); +set_reset_data( debug_cti_axim__PERIPHID2, val_debug_cti_axim__PERIPHID2); +set_reset_data( debug_cti_axim__PERIPHID3, val_debug_cti_axim__PERIPHID3); +set_reset_data( debug_cti_axim__COMPID0, val_debug_cti_axim__COMPID0); +set_reset_data( debug_cti_axim__COMPID1, val_debug_cti_axim__COMPID1); +set_reset_data( debug_cti_axim__COMPID2, val_debug_cti_axim__COMPID2); +set_reset_data( debug_cti_axim__COMPID3, val_debug_cti_axim__COMPID3); + +// ************************************************************ +// Module debug_cti_etb_tpiu cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_etb_tpiu__CTICONTROL, val_debug_cti_etb_tpiu__CTICONTROL); +set_reset_data( debug_cti_etb_tpiu__CTIINTACK, val_debug_cti_etb_tpiu__CTIINTACK); +set_reset_data( debug_cti_etb_tpiu__CTIAPPSET, val_debug_cti_etb_tpiu__CTIAPPSET); +set_reset_data( debug_cti_etb_tpiu__CTIAPPCLEAR, val_debug_cti_etb_tpiu__CTIAPPCLEAR); +set_reset_data( debug_cti_etb_tpiu__CTIAPPPULSE, val_debug_cti_etb_tpiu__CTIAPPPULSE); +set_reset_data( debug_cti_etb_tpiu__CTIINEN0, val_debug_cti_etb_tpiu__CTIINEN0); +set_reset_data( debug_cti_etb_tpiu__CTIINEN1, val_debug_cti_etb_tpiu__CTIINEN1); +set_reset_data( debug_cti_etb_tpiu__CTIINEN2, val_debug_cti_etb_tpiu__CTIINEN2); +set_reset_data( debug_cti_etb_tpiu__CTIINEN3, val_debug_cti_etb_tpiu__CTIINEN3); +set_reset_data( debug_cti_etb_tpiu__CTIINEN4, val_debug_cti_etb_tpiu__CTIINEN4); +set_reset_data( debug_cti_etb_tpiu__CTIINEN5, val_debug_cti_etb_tpiu__CTIINEN5); +set_reset_data( debug_cti_etb_tpiu__CTIINEN6, val_debug_cti_etb_tpiu__CTIINEN6); +set_reset_data( debug_cti_etb_tpiu__CTIINEN7, val_debug_cti_etb_tpiu__CTIINEN7); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN0, val_debug_cti_etb_tpiu__CTIOUTEN0); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN1, val_debug_cti_etb_tpiu__CTIOUTEN1); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN2, val_debug_cti_etb_tpiu__CTIOUTEN2); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN3, val_debug_cti_etb_tpiu__CTIOUTEN3); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN4, val_debug_cti_etb_tpiu__CTIOUTEN4); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN5, val_debug_cti_etb_tpiu__CTIOUTEN5); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN6, val_debug_cti_etb_tpiu__CTIOUTEN6); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN7, val_debug_cti_etb_tpiu__CTIOUTEN7); +set_reset_data( debug_cti_etb_tpiu__CTITRIGINSTATUS, val_debug_cti_etb_tpiu__CTITRIGINSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTITRIGOUTSTATUS, val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTICHINSTATUS, val_debug_cti_etb_tpiu__CTICHINSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTICHOUTSTATUS, val_debug_cti_etb_tpiu__CTICHOUTSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTIGATE, val_debug_cti_etb_tpiu__CTIGATE); +set_reset_data( debug_cti_etb_tpiu__ASICCTL, val_debug_cti_etb_tpiu__ASICCTL); +set_reset_data( debug_cti_etb_tpiu__ITCHINACK, val_debug_cti_etb_tpiu__ITCHINACK); +set_reset_data( debug_cti_etb_tpiu__ITTRIGINACK, val_debug_cti_etb_tpiu__ITTRIGINACK); +set_reset_data( debug_cti_etb_tpiu__ITCHOUT, val_debug_cti_etb_tpiu__ITCHOUT); +set_reset_data( debug_cti_etb_tpiu__ITTRIGOUT, val_debug_cti_etb_tpiu__ITTRIGOUT); +set_reset_data( debug_cti_etb_tpiu__ITCHOUTACK, val_debug_cti_etb_tpiu__ITCHOUTACK); +set_reset_data( debug_cti_etb_tpiu__ITTRIGOUTACK, val_debug_cti_etb_tpiu__ITTRIGOUTACK); +set_reset_data( debug_cti_etb_tpiu__ITCHIN, val_debug_cti_etb_tpiu__ITCHIN); +set_reset_data( debug_cti_etb_tpiu__ITTRIGIN, val_debug_cti_etb_tpiu__ITTRIGIN); +set_reset_data( debug_cti_etb_tpiu__ITCTRL, val_debug_cti_etb_tpiu__ITCTRL); +set_reset_data( debug_cti_etb_tpiu__CTSR, val_debug_cti_etb_tpiu__CTSR); +set_reset_data( debug_cti_etb_tpiu__CTCR, val_debug_cti_etb_tpiu__CTCR); +set_reset_data( debug_cti_etb_tpiu__LAR, val_debug_cti_etb_tpiu__LAR); +set_reset_data( debug_cti_etb_tpiu__LSR, val_debug_cti_etb_tpiu__LSR); +set_reset_data( debug_cti_etb_tpiu__ASR, val_debug_cti_etb_tpiu__ASR); +set_reset_data( debug_cti_etb_tpiu__DEVID, val_debug_cti_etb_tpiu__DEVID); +set_reset_data( debug_cti_etb_tpiu__DTIR, val_debug_cti_etb_tpiu__DTIR); +set_reset_data( debug_cti_etb_tpiu__PERIPHID4, val_debug_cti_etb_tpiu__PERIPHID4); +set_reset_data( debug_cti_etb_tpiu__PERIPHID5, val_debug_cti_etb_tpiu__PERIPHID5); +set_reset_data( debug_cti_etb_tpiu__PERIPHID6, val_debug_cti_etb_tpiu__PERIPHID6); +set_reset_data( debug_cti_etb_tpiu__PERIPHID7, val_debug_cti_etb_tpiu__PERIPHID7); +set_reset_data( debug_cti_etb_tpiu__PERIPHID0, val_debug_cti_etb_tpiu__PERIPHID0); +set_reset_data( debug_cti_etb_tpiu__PERIPHID1, val_debug_cti_etb_tpiu__PERIPHID1); +set_reset_data( debug_cti_etb_tpiu__PERIPHID2, val_debug_cti_etb_tpiu__PERIPHID2); +set_reset_data( debug_cti_etb_tpiu__PERIPHID3, val_debug_cti_etb_tpiu__PERIPHID3); +set_reset_data( debug_cti_etb_tpiu__COMPID0, val_debug_cti_etb_tpiu__COMPID0); +set_reset_data( debug_cti_etb_tpiu__COMPID1, val_debug_cti_etb_tpiu__COMPID1); +set_reset_data( debug_cti_etb_tpiu__COMPID2, val_debug_cti_etb_tpiu__COMPID2); +set_reset_data( debug_cti_etb_tpiu__COMPID3, val_debug_cti_etb_tpiu__COMPID3); + +// ************************************************************ +// Module debug_cti_ftm cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_ftm__CTICONTROL, val_debug_cti_ftm__CTICONTROL); +set_reset_data( debug_cti_ftm__CTIINTACK, val_debug_cti_ftm__CTIINTACK); +set_reset_data( debug_cti_ftm__CTIAPPSET, val_debug_cti_ftm__CTIAPPSET); +set_reset_data( debug_cti_ftm__CTIAPPCLEAR, val_debug_cti_ftm__CTIAPPCLEAR); +set_reset_data( debug_cti_ftm__CTIAPPPULSE, val_debug_cti_ftm__CTIAPPPULSE); +set_reset_data( debug_cti_ftm__CTIINEN0, val_debug_cti_ftm__CTIINEN0); +set_reset_data( debug_cti_ftm__CTIINEN1, val_debug_cti_ftm__CTIINEN1); +set_reset_data( debug_cti_ftm__CTIINEN2, val_debug_cti_ftm__CTIINEN2); +set_reset_data( debug_cti_ftm__CTIINEN3, val_debug_cti_ftm__CTIINEN3); +set_reset_data( debug_cti_ftm__CTIINEN4, val_debug_cti_ftm__CTIINEN4); +set_reset_data( debug_cti_ftm__CTIINEN5, val_debug_cti_ftm__CTIINEN5); +set_reset_data( debug_cti_ftm__CTIINEN6, val_debug_cti_ftm__CTIINEN6); +set_reset_data( debug_cti_ftm__CTIINEN7, val_debug_cti_ftm__CTIINEN7); +set_reset_data( debug_cti_ftm__CTIOUTEN0, val_debug_cti_ftm__CTIOUTEN0); +set_reset_data( debug_cti_ftm__CTIOUTEN1, val_debug_cti_ftm__CTIOUTEN1); +set_reset_data( debug_cti_ftm__CTIOUTEN2, val_debug_cti_ftm__CTIOUTEN2); +set_reset_data( debug_cti_ftm__CTIOUTEN3, val_debug_cti_ftm__CTIOUTEN3); +set_reset_data( debug_cti_ftm__CTIOUTEN4, val_debug_cti_ftm__CTIOUTEN4); +set_reset_data( debug_cti_ftm__CTIOUTEN5, val_debug_cti_ftm__CTIOUTEN5); +set_reset_data( debug_cti_ftm__CTIOUTEN6, val_debug_cti_ftm__CTIOUTEN6); +set_reset_data( debug_cti_ftm__CTIOUTEN7, val_debug_cti_ftm__CTIOUTEN7); +set_reset_data( debug_cti_ftm__CTITRIGINSTATUS, val_debug_cti_ftm__CTITRIGINSTATUS); +set_reset_data( debug_cti_ftm__CTITRIGOUTSTATUS, val_debug_cti_ftm__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_ftm__CTICHINSTATUS, val_debug_cti_ftm__CTICHINSTATUS); +set_reset_data( debug_cti_ftm__CTICHOUTSTATUS, val_debug_cti_ftm__CTICHOUTSTATUS); +set_reset_data( debug_cti_ftm__CTIGATE, val_debug_cti_ftm__CTIGATE); +set_reset_data( debug_cti_ftm__ASICCTL, val_debug_cti_ftm__ASICCTL); +set_reset_data( debug_cti_ftm__ITCHINACK, val_debug_cti_ftm__ITCHINACK); +set_reset_data( debug_cti_ftm__ITTRIGINACK, val_debug_cti_ftm__ITTRIGINACK); +set_reset_data( debug_cti_ftm__ITCHOUT, val_debug_cti_ftm__ITCHOUT); +set_reset_data( debug_cti_ftm__ITTRIGOUT, val_debug_cti_ftm__ITTRIGOUT); +set_reset_data( debug_cti_ftm__ITCHOUTACK, val_debug_cti_ftm__ITCHOUTACK); +set_reset_data( debug_cti_ftm__ITTRIGOUTACK, val_debug_cti_ftm__ITTRIGOUTACK); +set_reset_data( debug_cti_ftm__ITCHIN, val_debug_cti_ftm__ITCHIN); +set_reset_data( debug_cti_ftm__ITTRIGIN, val_debug_cti_ftm__ITTRIGIN); +set_reset_data( debug_cti_ftm__ITCTRL, val_debug_cti_ftm__ITCTRL); +set_reset_data( debug_cti_ftm__CTSR, val_debug_cti_ftm__CTSR); +set_reset_data( debug_cti_ftm__CTCR, val_debug_cti_ftm__CTCR); +set_reset_data( debug_cti_ftm__LAR, val_debug_cti_ftm__LAR); +set_reset_data( debug_cti_ftm__LSR, val_debug_cti_ftm__LSR); +set_reset_data( debug_cti_ftm__ASR, val_debug_cti_ftm__ASR); +set_reset_data( debug_cti_ftm__DEVID, val_debug_cti_ftm__DEVID); +set_reset_data( debug_cti_ftm__DTIR, val_debug_cti_ftm__DTIR); +set_reset_data( debug_cti_ftm__PERIPHID4, val_debug_cti_ftm__PERIPHID4); +set_reset_data( debug_cti_ftm__PERIPHID5, val_debug_cti_ftm__PERIPHID5); +set_reset_data( debug_cti_ftm__PERIPHID6, val_debug_cti_ftm__PERIPHID6); +set_reset_data( debug_cti_ftm__PERIPHID7, val_debug_cti_ftm__PERIPHID7); +set_reset_data( debug_cti_ftm__PERIPHID0, val_debug_cti_ftm__PERIPHID0); +set_reset_data( debug_cti_ftm__PERIPHID1, val_debug_cti_ftm__PERIPHID1); +set_reset_data( debug_cti_ftm__PERIPHID2, val_debug_cti_ftm__PERIPHID2); +set_reset_data( debug_cti_ftm__PERIPHID3, val_debug_cti_ftm__PERIPHID3); +set_reset_data( debug_cti_ftm__COMPID0, val_debug_cti_ftm__COMPID0); +set_reset_data( debug_cti_ftm__COMPID1, val_debug_cti_ftm__COMPID1); +set_reset_data( debug_cti_ftm__COMPID2, val_debug_cti_ftm__COMPID2); +set_reset_data( debug_cti_ftm__COMPID3, val_debug_cti_ftm__COMPID3); + +// ************************************************************ +// Module debug_dap_rom dap +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_dap_rom__ROMENTRY00, val_debug_dap_rom__ROMENTRY00); +set_reset_data( debug_dap_rom__ROMENTRY01, val_debug_dap_rom__ROMENTRY01); +set_reset_data( debug_dap_rom__ROMENTRY02, val_debug_dap_rom__ROMENTRY02); +set_reset_data( debug_dap_rom__ROMENTRY03, val_debug_dap_rom__ROMENTRY03); +set_reset_data( debug_dap_rom__ROMENTRY04, val_debug_dap_rom__ROMENTRY04); +set_reset_data( debug_dap_rom__ROMENTRY05, val_debug_dap_rom__ROMENTRY05); +set_reset_data( debug_dap_rom__ROMENTRY06, val_debug_dap_rom__ROMENTRY06); +set_reset_data( debug_dap_rom__ROMENTRY07, val_debug_dap_rom__ROMENTRY07); +set_reset_data( debug_dap_rom__ROMENTRY08, val_debug_dap_rom__ROMENTRY08); +set_reset_data( debug_dap_rom__ROMENTRY09, val_debug_dap_rom__ROMENTRY09); +set_reset_data( debug_dap_rom__ROMENTRY10, val_debug_dap_rom__ROMENTRY10); +set_reset_data( debug_dap_rom__ROMENTRY11, val_debug_dap_rom__ROMENTRY11); +set_reset_data( debug_dap_rom__ROMENTRY12, val_debug_dap_rom__ROMENTRY12); +set_reset_data( debug_dap_rom__ROMENTRY13, val_debug_dap_rom__ROMENTRY13); +set_reset_data( debug_dap_rom__ROMENTRY14, val_debug_dap_rom__ROMENTRY14); +set_reset_data( debug_dap_rom__ROMENTRY15, val_debug_dap_rom__ROMENTRY15); +set_reset_data( debug_dap_rom__PERIPHID4, val_debug_dap_rom__PERIPHID4); +set_reset_data( debug_dap_rom__PERIPHID5, val_debug_dap_rom__PERIPHID5); +set_reset_data( debug_dap_rom__PERIPHID6, val_debug_dap_rom__PERIPHID6); +set_reset_data( debug_dap_rom__PERIPHID7, val_debug_dap_rom__PERIPHID7); +set_reset_data( debug_dap_rom__PERIPHID0, val_debug_dap_rom__PERIPHID0); +set_reset_data( debug_dap_rom__PERIPHID1, val_debug_dap_rom__PERIPHID1); +set_reset_data( debug_dap_rom__PERIPHID2, val_debug_dap_rom__PERIPHID2); +set_reset_data( debug_dap_rom__PERIPHID3, val_debug_dap_rom__PERIPHID3); +set_reset_data( debug_dap_rom__COMPID0, val_debug_dap_rom__COMPID0); +set_reset_data( debug_dap_rom__COMPID1, val_debug_dap_rom__COMPID1); +set_reset_data( debug_dap_rom__COMPID2, val_debug_dap_rom__COMPID2); +set_reset_data( debug_dap_rom__COMPID3, val_debug_dap_rom__COMPID3); + +// ************************************************************ +// Module debug_etb etb +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_etb__RDP, val_debug_etb__RDP); +set_reset_data( debug_etb__STS, val_debug_etb__STS); +set_reset_data( debug_etb__RRD, val_debug_etb__RRD); +set_reset_data( debug_etb__RRP, val_debug_etb__RRP); +set_reset_data( debug_etb__RWP, val_debug_etb__RWP); +set_reset_data( debug_etb__TRG, val_debug_etb__TRG); +set_reset_data( debug_etb__CTL, val_debug_etb__CTL); +set_reset_data( debug_etb__RWD, val_debug_etb__RWD); +set_reset_data( debug_etb__FFSR, val_debug_etb__FFSR); +set_reset_data( debug_etb__FFCR, val_debug_etb__FFCR); +set_reset_data( debug_etb__ITMISCOP0, val_debug_etb__ITMISCOP0); +set_reset_data( debug_etb__ITTRFLINACK, val_debug_etb__ITTRFLINACK); +set_reset_data( debug_etb__ITTRFLIN, val_debug_etb__ITTRFLIN); +set_reset_data( debug_etb__ITATBDATA0, val_debug_etb__ITATBDATA0); +set_reset_data( debug_etb__ITATBCTR2, val_debug_etb__ITATBCTR2); +set_reset_data( debug_etb__ITATBCTR1, val_debug_etb__ITATBCTR1); +set_reset_data( debug_etb__ITATBCTR0, val_debug_etb__ITATBCTR0); +set_reset_data( debug_etb__IMCR, val_debug_etb__IMCR); +set_reset_data( debug_etb__CTSR, val_debug_etb__CTSR); +set_reset_data( debug_etb__CTCR, val_debug_etb__CTCR); +set_reset_data( debug_etb__LAR, val_debug_etb__LAR); +set_reset_data( debug_etb__LSR, val_debug_etb__LSR); +set_reset_data( debug_etb__ASR, val_debug_etb__ASR); +set_reset_data( debug_etb__DEVID, val_debug_etb__DEVID); +set_reset_data( debug_etb__DTIR, val_debug_etb__DTIR); +set_reset_data( debug_etb__PERIPHID4, val_debug_etb__PERIPHID4); +set_reset_data( debug_etb__PERIPHID5, val_debug_etb__PERIPHID5); +set_reset_data( debug_etb__PERIPHID6, val_debug_etb__PERIPHID6); +set_reset_data( debug_etb__PERIPHID7, val_debug_etb__PERIPHID7); +set_reset_data( debug_etb__PERIPHID0, val_debug_etb__PERIPHID0); +set_reset_data( debug_etb__PERIPHID1, val_debug_etb__PERIPHID1); +set_reset_data( debug_etb__PERIPHID2, val_debug_etb__PERIPHID2); +set_reset_data( debug_etb__PERIPHID3, val_debug_etb__PERIPHID3); +set_reset_data( debug_etb__COMPID0, val_debug_etb__COMPID0); +set_reset_data( debug_etb__COMPID1, val_debug_etb__COMPID1); +set_reset_data( debug_etb__COMPID2, val_debug_etb__COMPID2); +set_reset_data( debug_etb__COMPID3, val_debug_etb__COMPID3); + +// ************************************************************ +// Module debug_ftm ftm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_ftm__FTMGLBCTRL, val_debug_ftm__FTMGLBCTRL); +set_reset_data( debug_ftm__FTMSTATUS, val_debug_ftm__FTMSTATUS); +set_reset_data( debug_ftm__FTMCONTROL, val_debug_ftm__FTMCONTROL); +set_reset_data( debug_ftm__FTMP2FDBG0, val_debug_ftm__FTMP2FDBG0); +set_reset_data( debug_ftm__FTMP2FDBG1, val_debug_ftm__FTMP2FDBG1); +set_reset_data( debug_ftm__FTMP2FDBG2, val_debug_ftm__FTMP2FDBG2); +set_reset_data( debug_ftm__FTMP2FDBG3, val_debug_ftm__FTMP2FDBG3); +set_reset_data( debug_ftm__FTMF2PDBG0, val_debug_ftm__FTMF2PDBG0); +set_reset_data( debug_ftm__FTMF2PDBG1, val_debug_ftm__FTMF2PDBG1); +set_reset_data( debug_ftm__FTMF2PDBG2, val_debug_ftm__FTMF2PDBG2); +set_reset_data( debug_ftm__FTMF2PDBG3, val_debug_ftm__FTMF2PDBG3); +set_reset_data( debug_ftm__CYCOUNTPRE, val_debug_ftm__CYCOUNTPRE); +set_reset_data( debug_ftm__FTMSYNCRELOAD, val_debug_ftm__FTMSYNCRELOAD); +set_reset_data( debug_ftm__FTMSYNCCOUT, val_debug_ftm__FTMSYNCCOUT); +set_reset_data( debug_ftm__FTMATID, val_debug_ftm__FTMATID); +set_reset_data( debug_ftm__FTMITTRIGOUTACK, val_debug_ftm__FTMITTRIGOUTACK); +set_reset_data( debug_ftm__FTMITTRIGGER, val_debug_ftm__FTMITTRIGGER); +set_reset_data( debug_ftm__FTMITTRACEDIS, val_debug_ftm__FTMITTRACEDIS); +set_reset_data( debug_ftm__FTMITCYCCOUNT, val_debug_ftm__FTMITCYCCOUNT); +set_reset_data( debug_ftm__FTMITATBDATA0, val_debug_ftm__FTMITATBDATA0); +set_reset_data( debug_ftm__FTMITATBCTR2, val_debug_ftm__FTMITATBCTR2); +set_reset_data( debug_ftm__FTMITATBCTR1, val_debug_ftm__FTMITATBCTR1); +set_reset_data( debug_ftm__FTMITATBCTR0, val_debug_ftm__FTMITATBCTR0); +set_reset_data( debug_ftm__FTMITCR, val_debug_ftm__FTMITCR); +set_reset_data( debug_ftm__CLAIMTAGSET, val_debug_ftm__CLAIMTAGSET); +set_reset_data( debug_ftm__CLAIMTAGCLR, val_debug_ftm__CLAIMTAGCLR); +set_reset_data( debug_ftm__LOCK_ACCESS, val_debug_ftm__LOCK_ACCESS); +set_reset_data( debug_ftm__LOCK_STATUS, val_debug_ftm__LOCK_STATUS); +set_reset_data( debug_ftm__FTMAUTHSTATUS, val_debug_ftm__FTMAUTHSTATUS); +set_reset_data( debug_ftm__FTMDEVID, val_debug_ftm__FTMDEVID); +set_reset_data( debug_ftm__FTMDEV_TYPE, val_debug_ftm__FTMDEV_TYPE); +set_reset_data( debug_ftm__FTMPERIPHID4, val_debug_ftm__FTMPERIPHID4); +set_reset_data( debug_ftm__FTMPERIPHID5, val_debug_ftm__FTMPERIPHID5); +set_reset_data( debug_ftm__FTMPERIPHID6, val_debug_ftm__FTMPERIPHID6); +set_reset_data( debug_ftm__FTMPERIPHID7, val_debug_ftm__FTMPERIPHID7); +set_reset_data( debug_ftm__FTMPERIPHID0, val_debug_ftm__FTMPERIPHID0); +set_reset_data( debug_ftm__FTMPERIPHID1, val_debug_ftm__FTMPERIPHID1); +set_reset_data( debug_ftm__FTMPERIPHID2, val_debug_ftm__FTMPERIPHID2); +set_reset_data( debug_ftm__FTMPERIPHID3, val_debug_ftm__FTMPERIPHID3); +set_reset_data( debug_ftm__FTMCOMPONID0, val_debug_ftm__FTMCOMPONID0); +set_reset_data( debug_ftm__FTMCOMPONID1, val_debug_ftm__FTMCOMPONID1); +set_reset_data( debug_ftm__FTMCOMPONID2, val_debug_ftm__FTMCOMPONID2); +set_reset_data( debug_ftm__FTMCOMPONID3, val_debug_ftm__FTMCOMPONID3); + +// ************************************************************ +// Module debug_funnel funnel +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_funnel__Control, val_debug_funnel__Control); +set_reset_data( debug_funnel__PriControl, val_debug_funnel__PriControl); +set_reset_data( debug_funnel__ITATBDATA0, val_debug_funnel__ITATBDATA0); +set_reset_data( debug_funnel__ITATBCTR2, val_debug_funnel__ITATBCTR2); +set_reset_data( debug_funnel__ITATBCTR1, val_debug_funnel__ITATBCTR1); +set_reset_data( debug_funnel__ITATBCTR0, val_debug_funnel__ITATBCTR0); +set_reset_data( debug_funnel__IMCR, val_debug_funnel__IMCR); +set_reset_data( debug_funnel__CTSR, val_debug_funnel__CTSR); +set_reset_data( debug_funnel__CTCR, val_debug_funnel__CTCR); +set_reset_data( debug_funnel__LAR, val_debug_funnel__LAR); +set_reset_data( debug_funnel__LSR, val_debug_funnel__LSR); +set_reset_data( debug_funnel__ASR, val_debug_funnel__ASR); +set_reset_data( debug_funnel__DEVID, val_debug_funnel__DEVID); +set_reset_data( debug_funnel__DTIR, val_debug_funnel__DTIR); +set_reset_data( debug_funnel__PERIPHID4, val_debug_funnel__PERIPHID4); +set_reset_data( debug_funnel__PERIPHID5, val_debug_funnel__PERIPHID5); +set_reset_data( debug_funnel__PERIPHID6, val_debug_funnel__PERIPHID6); +set_reset_data( debug_funnel__PERIPHID7, val_debug_funnel__PERIPHID7); +set_reset_data( debug_funnel__PERIPHID0, val_debug_funnel__PERIPHID0); +set_reset_data( debug_funnel__PERIPHID1, val_debug_funnel__PERIPHID1); +set_reset_data( debug_funnel__PERIPHID2, val_debug_funnel__PERIPHID2); +set_reset_data( debug_funnel__PERIPHID3, val_debug_funnel__PERIPHID3); +set_reset_data( debug_funnel__COMPID0, val_debug_funnel__COMPID0); +set_reset_data( debug_funnel__COMPID1, val_debug_funnel__COMPID1); +set_reset_data( debug_funnel__COMPID2, val_debug_funnel__COMPID2); +set_reset_data( debug_funnel__COMPID3, val_debug_funnel__COMPID3); + +// ************************************************************ +// Module debug_itm itm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_itm__StimPort00, val_debug_itm__StimPort00); +set_reset_data( debug_itm__StimPort01, val_debug_itm__StimPort01); +set_reset_data( debug_itm__StimPort02, val_debug_itm__StimPort02); +set_reset_data( debug_itm__StimPort03, val_debug_itm__StimPort03); +set_reset_data( debug_itm__StimPort04, val_debug_itm__StimPort04); +set_reset_data( debug_itm__StimPort05, val_debug_itm__StimPort05); +set_reset_data( debug_itm__StimPort06, val_debug_itm__StimPort06); +set_reset_data( debug_itm__StimPort07, val_debug_itm__StimPort07); +set_reset_data( debug_itm__StimPort08, val_debug_itm__StimPort08); +set_reset_data( debug_itm__StimPort09, val_debug_itm__StimPort09); +set_reset_data( debug_itm__StimPort10, val_debug_itm__StimPort10); +set_reset_data( debug_itm__StimPort11, val_debug_itm__StimPort11); +set_reset_data( debug_itm__StimPort12, val_debug_itm__StimPort12); +set_reset_data( debug_itm__StimPort13, val_debug_itm__StimPort13); +set_reset_data( debug_itm__StimPort14, val_debug_itm__StimPort14); +set_reset_data( debug_itm__StimPort15, val_debug_itm__StimPort15); +set_reset_data( debug_itm__StimPort16, val_debug_itm__StimPort16); +set_reset_data( debug_itm__StimPort17, val_debug_itm__StimPort17); +set_reset_data( debug_itm__StimPort18, val_debug_itm__StimPort18); +set_reset_data( debug_itm__StimPort19, val_debug_itm__StimPort19); +set_reset_data( debug_itm__StimPort20, val_debug_itm__StimPort20); +set_reset_data( debug_itm__StimPort21, val_debug_itm__StimPort21); +set_reset_data( debug_itm__StimPort22, val_debug_itm__StimPort22); +set_reset_data( debug_itm__StimPort23, val_debug_itm__StimPort23); +set_reset_data( debug_itm__StimPort24, val_debug_itm__StimPort24); +set_reset_data( debug_itm__StimPort25, val_debug_itm__StimPort25); +set_reset_data( debug_itm__StimPort26, val_debug_itm__StimPort26); +set_reset_data( debug_itm__StimPort27, val_debug_itm__StimPort27); +set_reset_data( debug_itm__StimPort28, val_debug_itm__StimPort28); +set_reset_data( debug_itm__StimPort29, val_debug_itm__StimPort29); +set_reset_data( debug_itm__StimPort30, val_debug_itm__StimPort30); +set_reset_data( debug_itm__StimPort31, val_debug_itm__StimPort31); +set_reset_data( debug_itm__TER, val_debug_itm__TER); +set_reset_data( debug_itm__TTR, val_debug_itm__TTR); +set_reset_data( debug_itm__CR, val_debug_itm__CR); +set_reset_data( debug_itm__SCR, val_debug_itm__SCR); +set_reset_data( debug_itm__ITTRIGOUTACK, val_debug_itm__ITTRIGOUTACK); +set_reset_data( debug_itm__ITTRIGOUT, val_debug_itm__ITTRIGOUT); +set_reset_data( debug_itm__ITATBDATA0, val_debug_itm__ITATBDATA0); +set_reset_data( debug_itm__ITATBCTR2, val_debug_itm__ITATBCTR2); +set_reset_data( debug_itm__ITATABCTR1, val_debug_itm__ITATABCTR1); +set_reset_data( debug_itm__ITATBCTR0, val_debug_itm__ITATBCTR0); +set_reset_data( debug_itm__IMCR, val_debug_itm__IMCR); +set_reset_data( debug_itm__CTSR, val_debug_itm__CTSR); +set_reset_data( debug_itm__CTCR, val_debug_itm__CTCR); +set_reset_data( debug_itm__LAR, val_debug_itm__LAR); +set_reset_data( debug_itm__LSR, val_debug_itm__LSR); +set_reset_data( debug_itm__ASR, val_debug_itm__ASR); +set_reset_data( debug_itm__DEVID, val_debug_itm__DEVID); +set_reset_data( debug_itm__DTIR, val_debug_itm__DTIR); +set_reset_data( debug_itm__PERIPHID4, val_debug_itm__PERIPHID4); +set_reset_data( debug_itm__PERIPHID5, val_debug_itm__PERIPHID5); +set_reset_data( debug_itm__PERIPHID6, val_debug_itm__PERIPHID6); +set_reset_data( debug_itm__PERIPHID7, val_debug_itm__PERIPHID7); +set_reset_data( debug_itm__PERIPHID0, val_debug_itm__PERIPHID0); +set_reset_data( debug_itm__PERIPHID1, val_debug_itm__PERIPHID1); +set_reset_data( debug_itm__PERIPHID2, val_debug_itm__PERIPHID2); +set_reset_data( debug_itm__PERIPHID3, val_debug_itm__PERIPHID3); +set_reset_data( debug_itm__COMPID0, val_debug_itm__COMPID0); +set_reset_data( debug_itm__COMPID1, val_debug_itm__COMPID1); +set_reset_data( debug_itm__COMPID2, val_debug_itm__COMPID2); +set_reset_data( debug_itm__COMPID3, val_debug_itm__COMPID3); + +// ************************************************************ +// Module debug_tpiu tpiu +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_tpiu__SuppSize, val_debug_tpiu__SuppSize); +set_reset_data( debug_tpiu__CurrentSize, val_debug_tpiu__CurrentSize); +set_reset_data( debug_tpiu__SuppTrigMode, val_debug_tpiu__SuppTrigMode); +set_reset_data( debug_tpiu__TrigCount, val_debug_tpiu__TrigCount); +set_reset_data( debug_tpiu__TrigMult, val_debug_tpiu__TrigMult); +set_reset_data( debug_tpiu__SuppTest, val_debug_tpiu__SuppTest); +set_reset_data( debug_tpiu__CurrentTest, val_debug_tpiu__CurrentTest); +set_reset_data( debug_tpiu__TestRepeatCount, val_debug_tpiu__TestRepeatCount); +set_reset_data( debug_tpiu__FFSR, val_debug_tpiu__FFSR); +set_reset_data( debug_tpiu__FFCR, val_debug_tpiu__FFCR); +set_reset_data( debug_tpiu__FormatSyncCount, val_debug_tpiu__FormatSyncCount); +set_reset_data( debug_tpiu__EXTCTLIn, val_debug_tpiu__EXTCTLIn); +set_reset_data( debug_tpiu__EXTCTLOut, val_debug_tpiu__EXTCTLOut); +set_reset_data( debug_tpiu__ITTRFLINACK, val_debug_tpiu__ITTRFLINACK); +set_reset_data( debug_tpiu__ITTRFLIN, val_debug_tpiu__ITTRFLIN); +set_reset_data( debug_tpiu__ITATBDATA0, val_debug_tpiu__ITATBDATA0); +set_reset_data( debug_tpiu__ITATBCTR2, val_debug_tpiu__ITATBCTR2); +set_reset_data( debug_tpiu__ITATBCTR1, val_debug_tpiu__ITATBCTR1); +set_reset_data( debug_tpiu__ITATBCTR0, val_debug_tpiu__ITATBCTR0); +set_reset_data( debug_tpiu__IMCR, val_debug_tpiu__IMCR); +set_reset_data( debug_tpiu__CTSR, val_debug_tpiu__CTSR); +set_reset_data( debug_tpiu__CTCR, val_debug_tpiu__CTCR); +set_reset_data( debug_tpiu__LAR, val_debug_tpiu__LAR); +set_reset_data( debug_tpiu__LSR, val_debug_tpiu__LSR); +set_reset_data( debug_tpiu__ASR, val_debug_tpiu__ASR); +set_reset_data( debug_tpiu__DEVID, val_debug_tpiu__DEVID); +set_reset_data( debug_tpiu__DTIR, val_debug_tpiu__DTIR); +set_reset_data( debug_tpiu__PERIPHID4, val_debug_tpiu__PERIPHID4); +set_reset_data( debug_tpiu__PERIPHID5, val_debug_tpiu__PERIPHID5); +set_reset_data( debug_tpiu__PERIPHID6, val_debug_tpiu__PERIPHID6); +set_reset_data( debug_tpiu__PERIPHID7, val_debug_tpiu__PERIPHID7); +set_reset_data( debug_tpiu__PERIPHID0, val_debug_tpiu__PERIPHID0); +set_reset_data( debug_tpiu__PERIPHID1, val_debug_tpiu__PERIPHID1); +set_reset_data( debug_tpiu__PERIPHID2, val_debug_tpiu__PERIPHID2); +set_reset_data( debug_tpiu__PERIPHID3, val_debug_tpiu__PERIPHID3); +set_reset_data( debug_tpiu__COMPID0, val_debug_tpiu__COMPID0); +set_reset_data( debug_tpiu__COMPID1, val_debug_tpiu__COMPID1); +set_reset_data( debug_tpiu__COMPID2, val_debug_tpiu__COMPID2); +set_reset_data( debug_tpiu__COMPID3, val_debug_tpiu__COMPID3); + +// ************************************************************ +// Module devcfg devcfg +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( devcfg__CTRL, val_devcfg__CTRL); +set_reset_data( devcfg__LOCK, val_devcfg__LOCK); +set_reset_data( devcfg__CFG, val_devcfg__CFG); +set_reset_data( devcfg__INT_STS, val_devcfg__INT_STS); +set_reset_data( devcfg__INT_MASK, val_devcfg__INT_MASK); +set_reset_data( devcfg__STATUS, val_devcfg__STATUS); +set_reset_data( devcfg__DMA_SRC_ADDR, val_devcfg__DMA_SRC_ADDR); +set_reset_data( devcfg__DMA_DST_ADDR, val_devcfg__DMA_DST_ADDR); +set_reset_data( devcfg__DMA_SRC_LEN, val_devcfg__DMA_SRC_LEN); +set_reset_data( devcfg__DMA_DEST_LEN, val_devcfg__DMA_DEST_LEN); +set_reset_data( devcfg__ROM_SHADOW, val_devcfg__ROM_SHADOW); +set_reset_data( devcfg__MULTIBOOT_ADDR, val_devcfg__MULTIBOOT_ADDR); +set_reset_data( devcfg__SW_ID, val_devcfg__SW_ID); +set_reset_data( devcfg__UNLOCK, val_devcfg__UNLOCK); +set_reset_data( devcfg__MCTRL, val_devcfg__MCTRL); +set_reset_data( devcfg__XADCIF_CFG, val_devcfg__XADCIF_CFG); +set_reset_data( devcfg__XADCIF_INT_STS, val_devcfg__XADCIF_INT_STS); +set_reset_data( devcfg__XADCIF_INT_MASK, val_devcfg__XADCIF_INT_MASK); +set_reset_data( devcfg__XADCIF_MSTS, val_devcfg__XADCIF_MSTS); +set_reset_data( devcfg__XADCIF_CMDFIFO, val_devcfg__XADCIF_CMDFIFO); +set_reset_data( devcfg__XADCIF_RDFIFO, val_devcfg__XADCIF_RDFIFO); +set_reset_data( devcfg__XADCIF_MCTL, val_devcfg__XADCIF_MCTL); + +// ************************************************************ +// Module dmac0_ns dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( dmac0_ns__DSR, val_dmac0_ns__DSR); +set_reset_data( dmac0_ns__DPC, val_dmac0_ns__DPC); +set_reset_data( dmac0_ns__INTEN, val_dmac0_ns__INTEN); +set_reset_data( dmac0_ns__INT_EVENT_RIS, val_dmac0_ns__INT_EVENT_RIS); +set_reset_data( dmac0_ns__INTMIS, val_dmac0_ns__INTMIS); +set_reset_data( dmac0_ns__INTCLR, val_dmac0_ns__INTCLR); +set_reset_data( dmac0_ns__FSRD, val_dmac0_ns__FSRD); +set_reset_data( dmac0_ns__FSRC, val_dmac0_ns__FSRC); +set_reset_data( dmac0_ns__FTRD, val_dmac0_ns__FTRD); +set_reset_data( dmac0_ns__FTR0, val_dmac0_ns__FTR0); +set_reset_data( dmac0_ns__FTR1, val_dmac0_ns__FTR1); +set_reset_data( dmac0_ns__FTR2, val_dmac0_ns__FTR2); +set_reset_data( dmac0_ns__FTR3, val_dmac0_ns__FTR3); +set_reset_data( dmac0_ns__FTR4, val_dmac0_ns__FTR4); +set_reset_data( dmac0_ns__FTR5, val_dmac0_ns__FTR5); +set_reset_data( dmac0_ns__FTR6, val_dmac0_ns__FTR6); +set_reset_data( dmac0_ns__FTR7, val_dmac0_ns__FTR7); +set_reset_data( dmac0_ns__CSR0, val_dmac0_ns__CSR0); +set_reset_data( dmac0_ns__CPC0, val_dmac0_ns__CPC0); +set_reset_data( dmac0_ns__CSR1, val_dmac0_ns__CSR1); +set_reset_data( dmac0_ns__CPC1, val_dmac0_ns__CPC1); +set_reset_data( dmac0_ns__CSR2, val_dmac0_ns__CSR2); +set_reset_data( dmac0_ns__CPC2, val_dmac0_ns__CPC2); +set_reset_data( dmac0_ns__CSR3, val_dmac0_ns__CSR3); +set_reset_data( dmac0_ns__CPC3, val_dmac0_ns__CPC3); +set_reset_data( dmac0_ns__CSR4, val_dmac0_ns__CSR4); +set_reset_data( dmac0_ns__CPC4, val_dmac0_ns__CPC4); +set_reset_data( dmac0_ns__CSR5, val_dmac0_ns__CSR5); +set_reset_data( dmac0_ns__CPC5, val_dmac0_ns__CPC5); +set_reset_data( dmac0_ns__CSR6, val_dmac0_ns__CSR6); +set_reset_data( dmac0_ns__CPC6, val_dmac0_ns__CPC6); +set_reset_data( dmac0_ns__CSR7, val_dmac0_ns__CSR7); +set_reset_data( dmac0_ns__CPC7, val_dmac0_ns__CPC7); +set_reset_data( dmac0_ns__SAR0, val_dmac0_ns__SAR0); +set_reset_data( dmac0_ns__DAR0, val_dmac0_ns__DAR0); +set_reset_data( dmac0_ns__CCR0, val_dmac0_ns__CCR0); +set_reset_data( dmac0_ns__LC0_0, val_dmac0_ns__LC0_0); +set_reset_data( dmac0_ns__LC1_0, val_dmac0_ns__LC1_0); +set_reset_data( dmac0_ns__SAR1, val_dmac0_ns__SAR1); +set_reset_data( dmac0_ns__DAR1, val_dmac0_ns__DAR1); +set_reset_data( dmac0_ns__CCR1, val_dmac0_ns__CCR1); +set_reset_data( dmac0_ns__LC0_1, val_dmac0_ns__LC0_1); +set_reset_data( dmac0_ns__LC1_1, val_dmac0_ns__LC1_1); +set_reset_data( dmac0_ns__SAR2, val_dmac0_ns__SAR2); +set_reset_data( dmac0_ns__DAR2, val_dmac0_ns__DAR2); +set_reset_data( dmac0_ns__CCR2, val_dmac0_ns__CCR2); +set_reset_data( dmac0_ns__LC0_2, val_dmac0_ns__LC0_2); +set_reset_data( dmac0_ns__LC1_2, val_dmac0_ns__LC1_2); +set_reset_data( dmac0_ns__SAR3, val_dmac0_ns__SAR3); +set_reset_data( dmac0_ns__DAR3, val_dmac0_ns__DAR3); +set_reset_data( dmac0_ns__CCR3, val_dmac0_ns__CCR3); +set_reset_data( dmac0_ns__LC0_3, val_dmac0_ns__LC0_3); +set_reset_data( dmac0_ns__LC1_3, val_dmac0_ns__LC1_3); +set_reset_data( dmac0_ns__SAR4, val_dmac0_ns__SAR4); +set_reset_data( dmac0_ns__DAR4, val_dmac0_ns__DAR4); +set_reset_data( dmac0_ns__CCR4, val_dmac0_ns__CCR4); +set_reset_data( dmac0_ns__LC0_4, val_dmac0_ns__LC0_4); +set_reset_data( dmac0_ns__LC1_4, val_dmac0_ns__LC1_4); +set_reset_data( dmac0_ns__SAR5, val_dmac0_ns__SAR5); +set_reset_data( dmac0_ns__DAR5, val_dmac0_ns__DAR5); +set_reset_data( dmac0_ns__CCR5, val_dmac0_ns__CCR5); +set_reset_data( dmac0_ns__LC0_5, val_dmac0_ns__LC0_5); +set_reset_data( dmac0_ns__LC1_5, val_dmac0_ns__LC1_5); +set_reset_data( dmac0_ns__SAR6, val_dmac0_ns__SAR6); +set_reset_data( dmac0_ns__DAR6, val_dmac0_ns__DAR6); +set_reset_data( dmac0_ns__CCR6, val_dmac0_ns__CCR6); +set_reset_data( dmac0_ns__LC0_6, val_dmac0_ns__LC0_6); +set_reset_data( dmac0_ns__LC1_6, val_dmac0_ns__LC1_6); +set_reset_data( dmac0_ns__SAR7, val_dmac0_ns__SAR7); +set_reset_data( dmac0_ns__DAR7, val_dmac0_ns__DAR7); +set_reset_data( dmac0_ns__CCR7, val_dmac0_ns__CCR7); +set_reset_data( dmac0_ns__LC0_7, val_dmac0_ns__LC0_7); +set_reset_data( dmac0_ns__LC1_7, val_dmac0_ns__LC1_7); +set_reset_data( dmac0_ns__DBGSTATUS, val_dmac0_ns__DBGSTATUS); +set_reset_data( dmac0_ns__DBGCMD, val_dmac0_ns__DBGCMD); +set_reset_data( dmac0_ns__DBGINST0, val_dmac0_ns__DBGINST0); +set_reset_data( dmac0_ns__DBGINST1, val_dmac0_ns__DBGINST1); +set_reset_data( dmac0_ns__CR0, val_dmac0_ns__CR0); +set_reset_data( dmac0_ns__CR1, val_dmac0_ns__CR1); +set_reset_data( dmac0_ns__CR2, val_dmac0_ns__CR2); +set_reset_data( dmac0_ns__CR3, val_dmac0_ns__CR3); +set_reset_data( dmac0_ns__CR4, val_dmac0_ns__CR4); +set_reset_data( dmac0_ns__CRD, val_dmac0_ns__CRD); +set_reset_data( dmac0_ns__WD, val_dmac0_ns__WD); +set_reset_data( dmac0_ns__periph_id_0, val_dmac0_ns__periph_id_0); +set_reset_data( dmac0_ns__periph_id_1, val_dmac0_ns__periph_id_1); +set_reset_data( dmac0_ns__periph_id_2, val_dmac0_ns__periph_id_2); +set_reset_data( dmac0_ns__periph_id_3, val_dmac0_ns__periph_id_3); +set_reset_data( dmac0_ns__pcell_id_0, val_dmac0_ns__pcell_id_0); +set_reset_data( dmac0_ns__pcell_id_1, val_dmac0_ns__pcell_id_1); +set_reset_data( dmac0_ns__pcell_id_2, val_dmac0_ns__pcell_id_2); +set_reset_data( dmac0_ns__pcell_id_3, val_dmac0_ns__pcell_id_3); + +// ************************************************************ +// Module dmac0_s dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( dmac0_s__DSR, val_dmac0_s__DSR); +set_reset_data( dmac0_s__DPC, val_dmac0_s__DPC); +set_reset_data( dmac0_s__INTEN, val_dmac0_s__INTEN); +set_reset_data( dmac0_s__INT_EVENT_RIS, val_dmac0_s__INT_EVENT_RIS); +set_reset_data( dmac0_s__INTMIS, val_dmac0_s__INTMIS); +set_reset_data( dmac0_s__INTCLR, val_dmac0_s__INTCLR); +set_reset_data( dmac0_s__FSRD, val_dmac0_s__FSRD); +set_reset_data( dmac0_s__FSRC, val_dmac0_s__FSRC); +set_reset_data( dmac0_s__FTRD, val_dmac0_s__FTRD); +set_reset_data( dmac0_s__FTR0, val_dmac0_s__FTR0); +set_reset_data( dmac0_s__FTR1, val_dmac0_s__FTR1); +set_reset_data( dmac0_s__FTR2, val_dmac0_s__FTR2); +set_reset_data( dmac0_s__FTR3, val_dmac0_s__FTR3); +set_reset_data( dmac0_s__FTR4, val_dmac0_s__FTR4); +set_reset_data( dmac0_s__FTR5, val_dmac0_s__FTR5); +set_reset_data( dmac0_s__FTR6, val_dmac0_s__FTR6); +set_reset_data( dmac0_s__FTR7, val_dmac0_s__FTR7); +set_reset_data( dmac0_s__CSR0, val_dmac0_s__CSR0); +set_reset_data( dmac0_s__CPC0, val_dmac0_s__CPC0); +set_reset_data( dmac0_s__CSR1, val_dmac0_s__CSR1); +set_reset_data( dmac0_s__CPC1, val_dmac0_s__CPC1); +set_reset_data( dmac0_s__CSR2, val_dmac0_s__CSR2); +set_reset_data( dmac0_s__CPC2, val_dmac0_s__CPC2); +set_reset_data( dmac0_s__CSR3, val_dmac0_s__CSR3); +set_reset_data( dmac0_s__CPC3, val_dmac0_s__CPC3); +set_reset_data( dmac0_s__CSR4, val_dmac0_s__CSR4); +set_reset_data( dmac0_s__CPC4, val_dmac0_s__CPC4); +set_reset_data( dmac0_s__CSR5, val_dmac0_s__CSR5); +set_reset_data( dmac0_s__CPC5, val_dmac0_s__CPC5); +set_reset_data( dmac0_s__CSR6, val_dmac0_s__CSR6); +set_reset_data( dmac0_s__CPC6, val_dmac0_s__CPC6); +set_reset_data( dmac0_s__CSR7, val_dmac0_s__CSR7); +set_reset_data( dmac0_s__CPC7, val_dmac0_s__CPC7); +set_reset_data( dmac0_s__SAR0, val_dmac0_s__SAR0); +set_reset_data( dmac0_s__DAR0, val_dmac0_s__DAR0); +set_reset_data( dmac0_s__CCR0, val_dmac0_s__CCR0); +set_reset_data( dmac0_s__LC0_0, val_dmac0_s__LC0_0); +set_reset_data( dmac0_s__LC1_0, val_dmac0_s__LC1_0); +set_reset_data( dmac0_s__SAR1, val_dmac0_s__SAR1); +set_reset_data( dmac0_s__DAR1, val_dmac0_s__DAR1); +set_reset_data( dmac0_s__CCR1, val_dmac0_s__CCR1); +set_reset_data( dmac0_s__LC0_1, val_dmac0_s__LC0_1); +set_reset_data( dmac0_s__LC1_1, val_dmac0_s__LC1_1); +set_reset_data( dmac0_s__SAR2, val_dmac0_s__SAR2); +set_reset_data( dmac0_s__DAR2, val_dmac0_s__DAR2); +set_reset_data( dmac0_s__CCR2, val_dmac0_s__CCR2); +set_reset_data( dmac0_s__LC0_2, val_dmac0_s__LC0_2); +set_reset_data( dmac0_s__LC1_2, val_dmac0_s__LC1_2); +set_reset_data( dmac0_s__SAR3, val_dmac0_s__SAR3); +set_reset_data( dmac0_s__DAR3, val_dmac0_s__DAR3); +set_reset_data( dmac0_s__CCR3, val_dmac0_s__CCR3); +set_reset_data( dmac0_s__LC0_3, val_dmac0_s__LC0_3); +set_reset_data( dmac0_s__LC1_3, val_dmac0_s__LC1_3); +set_reset_data( dmac0_s__SAR4, val_dmac0_s__SAR4); +set_reset_data( dmac0_s__DAR4, val_dmac0_s__DAR4); +set_reset_data( dmac0_s__CCR4, val_dmac0_s__CCR4); +set_reset_data( dmac0_s__LC0_4, val_dmac0_s__LC0_4); +set_reset_data( dmac0_s__LC1_4, val_dmac0_s__LC1_4); +set_reset_data( dmac0_s__SAR5, val_dmac0_s__SAR5); +set_reset_data( dmac0_s__DAR5, val_dmac0_s__DAR5); +set_reset_data( dmac0_s__CCR5, val_dmac0_s__CCR5); +set_reset_data( dmac0_s__LC0_5, val_dmac0_s__LC0_5); +set_reset_data( dmac0_s__LC1_5, val_dmac0_s__LC1_5); +set_reset_data( dmac0_s__SAR6, val_dmac0_s__SAR6); +set_reset_data( dmac0_s__DAR6, val_dmac0_s__DAR6); +set_reset_data( dmac0_s__CCR6, val_dmac0_s__CCR6); +set_reset_data( dmac0_s__LC0_6, val_dmac0_s__LC0_6); +set_reset_data( dmac0_s__LC1_6, val_dmac0_s__LC1_6); +set_reset_data( dmac0_s__SAR7, val_dmac0_s__SAR7); +set_reset_data( dmac0_s__DAR7, val_dmac0_s__DAR7); +set_reset_data( dmac0_s__CCR7, val_dmac0_s__CCR7); +set_reset_data( dmac0_s__LC0_7, val_dmac0_s__LC0_7); +set_reset_data( dmac0_s__LC1_7, val_dmac0_s__LC1_7); +set_reset_data( dmac0_s__DBGSTATUS, val_dmac0_s__DBGSTATUS); +set_reset_data( dmac0_s__DBGCMD, val_dmac0_s__DBGCMD); +set_reset_data( dmac0_s__DBGINST0, val_dmac0_s__DBGINST0); +set_reset_data( dmac0_s__DBGINST1, val_dmac0_s__DBGINST1); +set_reset_data( dmac0_s__CR0, val_dmac0_s__CR0); +set_reset_data( dmac0_s__CR1, val_dmac0_s__CR1); +set_reset_data( dmac0_s__CR2, val_dmac0_s__CR2); +set_reset_data( dmac0_s__CR3, val_dmac0_s__CR3); +set_reset_data( dmac0_s__CR4, val_dmac0_s__CR4); +set_reset_data( dmac0_s__CRD, val_dmac0_s__CRD); +set_reset_data( dmac0_s__WD, val_dmac0_s__WD); +set_reset_data( dmac0_s__periph_id_0, val_dmac0_s__periph_id_0); +set_reset_data( dmac0_s__periph_id_1, val_dmac0_s__periph_id_1); +set_reset_data( dmac0_s__periph_id_2, val_dmac0_s__periph_id_2); +set_reset_data( dmac0_s__periph_id_3, val_dmac0_s__periph_id_3); +set_reset_data( dmac0_s__pcell_id_0, val_dmac0_s__pcell_id_0); +set_reset_data( dmac0_s__pcell_id_1, val_dmac0_s__pcell_id_1); +set_reset_data( dmac0_s__pcell_id_2, val_dmac0_s__pcell_id_2); +set_reset_data( dmac0_s__pcell_id_3, val_dmac0_s__pcell_id_3); + +// ************************************************************ +// Module efuse_ctrl efuse_ctrl +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( efuse_ctrl__WR_LOCK, val_efuse_ctrl__WR_LOCK); +set_reset_data( efuse_ctrl__WR_UNLOCK, val_efuse_ctrl__WR_UNLOCK); +set_reset_data( efuse_ctrl__WR_LOCKSTA, val_efuse_ctrl__WR_LOCKSTA); +set_reset_data( efuse_ctrl__CFG, val_efuse_ctrl__CFG); +set_reset_data( efuse_ctrl__STATUS, val_efuse_ctrl__STATUS); +set_reset_data( efuse_ctrl__CONTROL, val_efuse_ctrl__CONTROL); +set_reset_data( efuse_ctrl__PGM_STBW, val_efuse_ctrl__PGM_STBW); +set_reset_data( efuse_ctrl__RD_STBW, val_efuse_ctrl__RD_STBW); + +// ************************************************************ +// Module gem0 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gem0__net_ctrl, val_gem0__net_ctrl); +set_reset_data( gem0__net_cfg, val_gem0__net_cfg); +set_reset_data( gem0__net_status, val_gem0__net_status); +set_reset_data( gem0__user_io, val_gem0__user_io); +set_reset_data( gem0__dma_cfg, val_gem0__dma_cfg); +set_reset_data( gem0__tx_status, val_gem0__tx_status); +set_reset_data( gem0__rx_qbar, val_gem0__rx_qbar); +set_reset_data( gem0__tx_qbar, val_gem0__tx_qbar); +set_reset_data( gem0__rx_status, val_gem0__rx_status); +set_reset_data( gem0__intr_status, val_gem0__intr_status); +set_reset_data( gem0__intr_en, val_gem0__intr_en); +set_reset_data( gem0__intr_dis, val_gem0__intr_dis); +set_reset_data( gem0__intr_mask, val_gem0__intr_mask); +set_reset_data( gem0__phy_maint, val_gem0__phy_maint); +set_reset_data( gem0__rx_pauseq, val_gem0__rx_pauseq); +set_reset_data( gem0__tx_pauseq, val_gem0__tx_pauseq); +set_reset_data( gem0__tx_partial_st_fwd, val_gem0__tx_partial_st_fwd); +set_reset_data( gem0__rx_partial_st_fwd, val_gem0__rx_partial_st_fwd); +set_reset_data( gem0__hash_bot, val_gem0__hash_bot); +set_reset_data( gem0__hash_top, val_gem0__hash_top); +set_reset_data( gem0__spec_addr1_bot, val_gem0__spec_addr1_bot); +set_reset_data( gem0__spec_addr1_top, val_gem0__spec_addr1_top); +set_reset_data( gem0__spec_addr2_bot, val_gem0__spec_addr2_bot); +set_reset_data( gem0__spec_addr2_top, val_gem0__spec_addr2_top); +set_reset_data( gem0__spec_addr3_bot, val_gem0__spec_addr3_bot); +set_reset_data( gem0__spec_addr3_top, val_gem0__spec_addr3_top); +set_reset_data( gem0__spec_addr4_bot, val_gem0__spec_addr4_bot); +set_reset_data( gem0__spec_addr4_top, val_gem0__spec_addr4_top); +set_reset_data( gem0__type_id_match1, val_gem0__type_id_match1); +set_reset_data( gem0__type_id_match2, val_gem0__type_id_match2); +set_reset_data( gem0__type_id_match3, val_gem0__type_id_match3); +set_reset_data( gem0__type_id_match4, val_gem0__type_id_match4); +set_reset_data( gem0__wake_on_lan, val_gem0__wake_on_lan); +set_reset_data( gem0__ipg_stretch, val_gem0__ipg_stretch); +set_reset_data( gem0__stacked_vlan, val_gem0__stacked_vlan); +set_reset_data( gem0__tx_pfc_pause, val_gem0__tx_pfc_pause); +set_reset_data( gem0__spec_addr1_mask_bot, val_gem0__spec_addr1_mask_bot); +set_reset_data( gem0__spec_addr1_mask_top, val_gem0__spec_addr1_mask_top); +set_reset_data( gem0__module_id, val_gem0__module_id); +set_reset_data( gem0__octets_tx_bot, val_gem0__octets_tx_bot); +set_reset_data( gem0__octets_tx_top, val_gem0__octets_tx_top); +set_reset_data( gem0__frames_tx, val_gem0__frames_tx); +set_reset_data( gem0__broadcast_frames_tx, val_gem0__broadcast_frames_tx); +set_reset_data( gem0__multi_frames_tx, val_gem0__multi_frames_tx); +set_reset_data( gem0__pause_frames_tx, val_gem0__pause_frames_tx); +set_reset_data( gem0__frames_64b_tx, val_gem0__frames_64b_tx); +set_reset_data( gem0__frames_65to127b_tx, val_gem0__frames_65to127b_tx); +set_reset_data( gem0__frames_128to255b_tx, val_gem0__frames_128to255b_tx); +set_reset_data( gem0__frames_256to511b_tx, val_gem0__frames_256to511b_tx); +set_reset_data( gem0__frames_512to1023b_tx, val_gem0__frames_512to1023b_tx); +set_reset_data( gem0__frames_1024to1518b_tx, val_gem0__frames_1024to1518b_tx); +set_reset_data( gem0__frames_gt1518b_tx, val_gem0__frames_gt1518b_tx); +set_reset_data( gem0__tx_under_runs, val_gem0__tx_under_runs); +set_reset_data( gem0__single_collisn_frames, val_gem0__single_collisn_frames); +set_reset_data( gem0__multi_collisn_frames, val_gem0__multi_collisn_frames); +set_reset_data( gem0__excessive_collisns, val_gem0__excessive_collisns); +set_reset_data( gem0__late_collisns, val_gem0__late_collisns); +set_reset_data( gem0__deferred_tx_frames, val_gem0__deferred_tx_frames); +set_reset_data( gem0__carrier_sense_errs, val_gem0__carrier_sense_errs); +set_reset_data( gem0__octets_rx_bot, val_gem0__octets_rx_bot); +set_reset_data( gem0__octets_rx_top, val_gem0__octets_rx_top); +set_reset_data( gem0__frames_rx, val_gem0__frames_rx); +set_reset_data( gem0__bdcast_fames_rx, val_gem0__bdcast_fames_rx); +set_reset_data( gem0__multi_frames_rx, val_gem0__multi_frames_rx); +set_reset_data( gem0__pause_rx, val_gem0__pause_rx); +set_reset_data( gem0__frames_64b_rx, val_gem0__frames_64b_rx); +set_reset_data( gem0__frames_65to127b_rx, val_gem0__frames_65to127b_rx); +set_reset_data( gem0__frames_128to255b_rx, val_gem0__frames_128to255b_rx); +set_reset_data( gem0__frames_256to511b_rx, val_gem0__frames_256to511b_rx); +set_reset_data( gem0__frames_512to1023b_rx, val_gem0__frames_512to1023b_rx); +set_reset_data( gem0__frames_1024to1518b_rx, val_gem0__frames_1024to1518b_rx); +set_reset_data( gem0__frames_gt1518b_rx, val_gem0__frames_gt1518b_rx); +set_reset_data( gem0__undersz_rx, val_gem0__undersz_rx); +set_reset_data( gem0__oversz_rx, val_gem0__oversz_rx); +set_reset_data( gem0__jab_rx, val_gem0__jab_rx); +set_reset_data( gem0__fcs_errors, val_gem0__fcs_errors); +set_reset_data( gem0__length_field_errors, val_gem0__length_field_errors); +set_reset_data( gem0__rx_symbol_errors, val_gem0__rx_symbol_errors); +set_reset_data( gem0__align_errors, val_gem0__align_errors); +set_reset_data( gem0__rx_resource_errors, val_gem0__rx_resource_errors); +set_reset_data( gem0__rx_overrun_errors, val_gem0__rx_overrun_errors); +set_reset_data( gem0__ip_hdr_csum_errors, val_gem0__ip_hdr_csum_errors); +set_reset_data( gem0__tcp_csum_errors, val_gem0__tcp_csum_errors); +set_reset_data( gem0__udp_csum_errors, val_gem0__udp_csum_errors); +set_reset_data( gem0__timer_strobe_s, val_gem0__timer_strobe_s); +set_reset_data( gem0__timer_strobe_ns, val_gem0__timer_strobe_ns); +set_reset_data( gem0__timer_s, val_gem0__timer_s); +set_reset_data( gem0__timer_ns, val_gem0__timer_ns); +set_reset_data( gem0__timer_adjust, val_gem0__timer_adjust); +set_reset_data( gem0__timer_incr, val_gem0__timer_incr); +set_reset_data( gem0__ptp_tx_s, val_gem0__ptp_tx_s); +set_reset_data( gem0__ptp_tx_ns, val_gem0__ptp_tx_ns); +set_reset_data( gem0__ptp_rx_s, val_gem0__ptp_rx_s); +set_reset_data( gem0__ptp_rx_ns, val_gem0__ptp_rx_ns); +set_reset_data( gem0__ptp_peer_tx_s, val_gem0__ptp_peer_tx_s); +set_reset_data( gem0__ptp_peer_tx_ns, val_gem0__ptp_peer_tx_ns); +set_reset_data( gem0__ptp_peer_rx_s, val_gem0__ptp_peer_rx_s); +set_reset_data( gem0__ptp_peer_rx_ns, val_gem0__ptp_peer_rx_ns); +set_reset_data( gem0__pcs_ctrl, val_gem0__pcs_ctrl); +set_reset_data( gem0__pcs_status, val_gem0__pcs_status); +set_reset_data( gem0__pcs_upper_phy_id, val_gem0__pcs_upper_phy_id); +set_reset_data( gem0__pcs_lower_phy_id, val_gem0__pcs_lower_phy_id); +set_reset_data( gem0__pcs_autoneg_ad, val_gem0__pcs_autoneg_ad); +set_reset_data( gem0__pcs_autoneg_ability, val_gem0__pcs_autoneg_ability); +set_reset_data( gem0__pcs_autonec_exp, val_gem0__pcs_autonec_exp); +set_reset_data( gem0__pcs_autoneg_next_pg, val_gem0__pcs_autoneg_next_pg); +set_reset_data( gem0__pcs_autoneg_pnext_pg, val_gem0__pcs_autoneg_pnext_pg); +set_reset_data( gem0__pcs_extended_status, val_gem0__pcs_extended_status); +set_reset_data( gem0__design_cfg1, val_gem0__design_cfg1); +set_reset_data( gem0__design_cfg2, val_gem0__design_cfg2); +set_reset_data( gem0__design_cfg3, val_gem0__design_cfg3); +set_reset_data( gem0__design_cfg4, val_gem0__design_cfg4); +set_reset_data( gem0__design_cfg5, val_gem0__design_cfg5); +set_reset_data( gem0__design_cfg6, val_gem0__design_cfg6); +set_reset_data( gem0__design_cfg7, val_gem0__design_cfg7); +set_reset_data( gem0__isr_pq1, val_gem0__isr_pq1); +set_reset_data( gem0__isr_pq2, val_gem0__isr_pq2); +set_reset_data( gem0__isr_pq3, val_gem0__isr_pq3); +set_reset_data( gem0__isr_pq4, val_gem0__isr_pq4); +set_reset_data( gem0__isr_pq5, val_gem0__isr_pq5); +set_reset_data( gem0__isr_pq6, val_gem0__isr_pq6); +set_reset_data( gem0__isr_pq7, val_gem0__isr_pq7); +set_reset_data( gem0__tx_qbar_q1, val_gem0__tx_qbar_q1); +set_reset_data( gem0__tx_qbar_q2, val_gem0__tx_qbar_q2); +set_reset_data( gem0__tx_qbar_q3, val_gem0__tx_qbar_q3); +set_reset_data( gem0__tx_qbar_q4, val_gem0__tx_qbar_q4); +set_reset_data( gem0__tx_qbar_q5, val_gem0__tx_qbar_q5); +set_reset_data( gem0__tx_qbar_q6, val_gem0__tx_qbar_q6); +set_reset_data( gem0__tx_qbar_q7, val_gem0__tx_qbar_q7); +set_reset_data( gem0__rx_qbar_q1, val_gem0__rx_qbar_q1); +set_reset_data( gem0__rx_qbar_q2, val_gem0__rx_qbar_q2); +set_reset_data( gem0__rx_qbar_q3, val_gem0__rx_qbar_q3); +set_reset_data( gem0__rx_qbar_q4, val_gem0__rx_qbar_q4); +set_reset_data( gem0__rx_qbar_q5, val_gem0__rx_qbar_q5); +set_reset_data( gem0__rx_qbar_q6, val_gem0__rx_qbar_q6); +set_reset_data( gem0__rx_qbar_q7, val_gem0__rx_qbar_q7); +set_reset_data( gem0__rx_bufsz_q1, val_gem0__rx_bufsz_q1); +set_reset_data( gem0__rx_bufsz_q2, val_gem0__rx_bufsz_q2); +set_reset_data( gem0__rx_bufsz_q3, val_gem0__rx_bufsz_q3); +set_reset_data( gem0__rx_bufsz_q4, val_gem0__rx_bufsz_q4); +set_reset_data( gem0__rx_bufsz_q5, val_gem0__rx_bufsz_q5); +set_reset_data( gem0__rx_bufsz_q6, val_gem0__rx_bufsz_q6); +set_reset_data( gem0__rx_bufsz_q7, val_gem0__rx_bufsz_q7); +set_reset_data( gem0__screen_t1_r0, val_gem0__screen_t1_r0); +set_reset_data( gem0__screen_t1_r1, val_gem0__screen_t1_r1); +set_reset_data( gem0__screen_t1_r2, val_gem0__screen_t1_r2); +set_reset_data( gem0__screen_t1_r3, val_gem0__screen_t1_r3); +set_reset_data( gem0__screen_t1_r4, val_gem0__screen_t1_r4); +set_reset_data( gem0__screen_t1_r5, val_gem0__screen_t1_r5); +set_reset_data( gem0__screen_t1_r6, val_gem0__screen_t1_r6); +set_reset_data( gem0__screen_t1_r7, val_gem0__screen_t1_r7); +set_reset_data( gem0__screen_t1_r8, val_gem0__screen_t1_r8); +set_reset_data( gem0__screen_t1_r9, val_gem0__screen_t1_r9); +set_reset_data( gem0__screen_t1_r10, val_gem0__screen_t1_r10); +set_reset_data( gem0__screen_t1_r11, val_gem0__screen_t1_r11); +set_reset_data( gem0__screen_t1_r12, val_gem0__screen_t1_r12); +set_reset_data( gem0__screen_t1_r13, val_gem0__screen_t1_r13); +set_reset_data( gem0__screen_t1_r14, val_gem0__screen_t1_r14); +set_reset_data( gem0__screen_t1_r15, val_gem0__screen_t1_r15); +set_reset_data( gem0__screen_t2_r0, val_gem0__screen_t2_r0); +set_reset_data( gem0__screen_t2_r1, val_gem0__screen_t2_r1); +set_reset_data( gem0__screen_t2_r2, val_gem0__screen_t2_r2); +set_reset_data( gem0__screen_t2_r3, val_gem0__screen_t2_r3); +set_reset_data( gem0__screen_t2_r4, val_gem0__screen_t2_r4); +set_reset_data( gem0__screen_t2_r5, val_gem0__screen_t2_r5); +set_reset_data( gem0__screen_t2_r6, val_gem0__screen_t2_r6); +set_reset_data( gem0__screen_t2_r7, val_gem0__screen_t2_r7); +set_reset_data( gem0__screen_t2_r8, val_gem0__screen_t2_r8); +set_reset_data( gem0__screen_t2_r9, val_gem0__screen_t2_r9); +set_reset_data( gem0__screen_t2_r10, val_gem0__screen_t2_r10); +set_reset_data( gem0__screen_t2_r11, val_gem0__screen_t2_r11); +set_reset_data( gem0__screen_t2_r12, val_gem0__screen_t2_r12); +set_reset_data( gem0__screen_t2_r13, val_gem0__screen_t2_r13); +set_reset_data( gem0__screen_t2_r14, val_gem0__screen_t2_r14); +set_reset_data( gem0__screen_t2_r15, val_gem0__screen_t2_r15); +set_reset_data( gem0__intr_en_pq1, val_gem0__intr_en_pq1); +set_reset_data( gem0__intr_en_pq2, val_gem0__intr_en_pq2); +set_reset_data( gem0__intr_en_pq3, val_gem0__intr_en_pq3); +set_reset_data( gem0__intr_en_pq4, val_gem0__intr_en_pq4); +set_reset_data( gem0__intr_en_pq5, val_gem0__intr_en_pq5); +set_reset_data( gem0__intr_en_pq6, val_gem0__intr_en_pq6); +set_reset_data( gem0__intr_en_pq7, val_gem0__intr_en_pq7); +set_reset_data( gem0__intr_dis_pq1, val_gem0__intr_dis_pq1); +set_reset_data( gem0__intr_dis_pq2, val_gem0__intr_dis_pq2); +set_reset_data( gem0__intr_dis_pq3, val_gem0__intr_dis_pq3); +set_reset_data( gem0__intr_dis_pq4, val_gem0__intr_dis_pq4); +set_reset_data( gem0__intr_dis_pq5, val_gem0__intr_dis_pq5); +set_reset_data( gem0__intr_dis_pq6, val_gem0__intr_dis_pq6); +set_reset_data( gem0__intr_dis_pq7, val_gem0__intr_dis_pq7); +set_reset_data( gem0__intr_mask_pq1, val_gem0__intr_mask_pq1); +set_reset_data( gem0__intr_mask_pq2, val_gem0__intr_mask_pq2); +set_reset_data( gem0__intr_mask_pq3, val_gem0__intr_mask_pq3); +set_reset_data( gem0__intr_mask_pq4, val_gem0__intr_mask_pq4); +set_reset_data( gem0__intr_mask_pq5, val_gem0__intr_mask_pq5); +set_reset_data( gem0__intr_mask_pq6, val_gem0__intr_mask_pq6); +set_reset_data( gem0__intr_mask_pq7, val_gem0__intr_mask_pq7); + +// ************************************************************ +// Module gem1 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gem1__net_ctrl, val_gem1__net_ctrl); +set_reset_data( gem1__net_cfg, val_gem1__net_cfg); +set_reset_data( gem1__net_status, val_gem1__net_status); +set_reset_data( gem1__user_io, val_gem1__user_io); +set_reset_data( gem1__dma_cfg, val_gem1__dma_cfg); +set_reset_data( gem1__tx_status, val_gem1__tx_status); +set_reset_data( gem1__rx_qbar, val_gem1__rx_qbar); +set_reset_data( gem1__tx_qbar, val_gem1__tx_qbar); +set_reset_data( gem1__rx_status, val_gem1__rx_status); +set_reset_data( gem1__intr_status, val_gem1__intr_status); +set_reset_data( gem1__intr_en, val_gem1__intr_en); +set_reset_data( gem1__intr_dis, val_gem1__intr_dis); +set_reset_data( gem1__intr_mask, val_gem1__intr_mask); +set_reset_data( gem1__phy_maint, val_gem1__phy_maint); +set_reset_data( gem1__rx_pauseq, val_gem1__rx_pauseq); +set_reset_data( gem1__tx_pauseq, val_gem1__tx_pauseq); +set_reset_data( gem1__tx_partial_st_fwd, val_gem1__tx_partial_st_fwd); +set_reset_data( gem1__rx_partial_st_fwd, val_gem1__rx_partial_st_fwd); +set_reset_data( gem1__hash_bot, val_gem1__hash_bot); +set_reset_data( gem1__hash_top, val_gem1__hash_top); +set_reset_data( gem1__spec_addr1_bot, val_gem1__spec_addr1_bot); +set_reset_data( gem1__spec_addr1_top, val_gem1__spec_addr1_top); +set_reset_data( gem1__spec_addr2_bot, val_gem1__spec_addr2_bot); +set_reset_data( gem1__spec_addr2_top, val_gem1__spec_addr2_top); +set_reset_data( gem1__spec_addr3_bot, val_gem1__spec_addr3_bot); +set_reset_data( gem1__spec_addr3_top, val_gem1__spec_addr3_top); +set_reset_data( gem1__spec_addr4_bot, val_gem1__spec_addr4_bot); +set_reset_data( gem1__spec_addr4_top, val_gem1__spec_addr4_top); +set_reset_data( gem1__type_id_match1, val_gem1__type_id_match1); +set_reset_data( gem1__type_id_match2, val_gem1__type_id_match2); +set_reset_data( gem1__type_id_match3, val_gem1__type_id_match3); +set_reset_data( gem1__type_id_match4, val_gem1__type_id_match4); +set_reset_data( gem1__wake_on_lan, val_gem1__wake_on_lan); +set_reset_data( gem1__ipg_stretch, val_gem1__ipg_stretch); +set_reset_data( gem1__stacked_vlan, val_gem1__stacked_vlan); +set_reset_data( gem1__tx_pfc_pause, val_gem1__tx_pfc_pause); +set_reset_data( gem1__spec_addr1_mask_bot, val_gem1__spec_addr1_mask_bot); +set_reset_data( gem1__spec_addr1_mask_top, val_gem1__spec_addr1_mask_top); +set_reset_data( gem1__module_id, val_gem1__module_id); +set_reset_data( gem1__octets_tx_bot, val_gem1__octets_tx_bot); +set_reset_data( gem1__octets_tx_top, val_gem1__octets_tx_top); +set_reset_data( gem1__frames_tx, val_gem1__frames_tx); +set_reset_data( gem1__broadcast_frames_tx, val_gem1__broadcast_frames_tx); +set_reset_data( gem1__multi_frames_tx, val_gem1__multi_frames_tx); +set_reset_data( gem1__pause_frames_tx, val_gem1__pause_frames_tx); +set_reset_data( gem1__frames_64b_tx, val_gem1__frames_64b_tx); +set_reset_data( gem1__frames_65to127b_tx, val_gem1__frames_65to127b_tx); +set_reset_data( gem1__frames_128to255b_tx, val_gem1__frames_128to255b_tx); +set_reset_data( gem1__frames_256to511b_tx, val_gem1__frames_256to511b_tx); +set_reset_data( gem1__frames_512to1023b_tx, val_gem1__frames_512to1023b_tx); +set_reset_data( gem1__frames_1024to1518b_tx, val_gem1__frames_1024to1518b_tx); +set_reset_data( gem1__frames_gt1518b_tx, val_gem1__frames_gt1518b_tx); +set_reset_data( gem1__tx_under_runs, val_gem1__tx_under_runs); +set_reset_data( gem1__single_collisn_frames, val_gem1__single_collisn_frames); +set_reset_data( gem1__multi_collisn_frames, val_gem1__multi_collisn_frames); +set_reset_data( gem1__excessive_collisns, val_gem1__excessive_collisns); +set_reset_data( gem1__late_collisns, val_gem1__late_collisns); +set_reset_data( gem1__deferred_tx_frames, val_gem1__deferred_tx_frames); +set_reset_data( gem1__carrier_sense_errs, val_gem1__carrier_sense_errs); +set_reset_data( gem1__octets_rx_bot, val_gem1__octets_rx_bot); +set_reset_data( gem1__octets_rx_top, val_gem1__octets_rx_top); +set_reset_data( gem1__frames_rx, val_gem1__frames_rx); +set_reset_data( gem1__bdcast_fames_rx, val_gem1__bdcast_fames_rx); +set_reset_data( gem1__multi_frames_rx, val_gem1__multi_frames_rx); +set_reset_data( gem1__pause_rx, val_gem1__pause_rx); +set_reset_data( gem1__frames_64b_rx, val_gem1__frames_64b_rx); +set_reset_data( gem1__frames_65to127b_rx, val_gem1__frames_65to127b_rx); +set_reset_data( gem1__frames_128to255b_rx, val_gem1__frames_128to255b_rx); +set_reset_data( gem1__frames_256to511b_rx, val_gem1__frames_256to511b_rx); +set_reset_data( gem1__frames_512to1023b_rx, val_gem1__frames_512to1023b_rx); +set_reset_data( gem1__frames_1024to1518b_rx, val_gem1__frames_1024to1518b_rx); +set_reset_data( gem1__frames_gt1518b_rx, val_gem1__frames_gt1518b_rx); +set_reset_data( gem1__undersz_rx, val_gem1__undersz_rx); +set_reset_data( gem1__oversz_rx, val_gem1__oversz_rx); +set_reset_data( gem1__jab_rx, val_gem1__jab_rx); +set_reset_data( gem1__fcs_errors, val_gem1__fcs_errors); +set_reset_data( gem1__length_field_errors, val_gem1__length_field_errors); +set_reset_data( gem1__rx_symbol_errors, val_gem1__rx_symbol_errors); +set_reset_data( gem1__align_errors, val_gem1__align_errors); +set_reset_data( gem1__rx_resource_errors, val_gem1__rx_resource_errors); +set_reset_data( gem1__rx_overrun_errors, val_gem1__rx_overrun_errors); +set_reset_data( gem1__ip_hdr_csum_errors, val_gem1__ip_hdr_csum_errors); +set_reset_data( gem1__tcp_csum_errors, val_gem1__tcp_csum_errors); +set_reset_data( gem1__udp_csum_errors, val_gem1__udp_csum_errors); +set_reset_data( gem1__timer_strobe_s, val_gem1__timer_strobe_s); +set_reset_data( gem1__timer_strobe_ns, val_gem1__timer_strobe_ns); +set_reset_data( gem1__timer_s, val_gem1__timer_s); +set_reset_data( gem1__timer_ns, val_gem1__timer_ns); +set_reset_data( gem1__timer_adjust, val_gem1__timer_adjust); +set_reset_data( gem1__timer_incr, val_gem1__timer_incr); +set_reset_data( gem1__ptp_tx_s, val_gem1__ptp_tx_s); +set_reset_data( gem1__ptp_tx_ns, val_gem1__ptp_tx_ns); +set_reset_data( gem1__ptp_rx_s, val_gem1__ptp_rx_s); +set_reset_data( gem1__ptp_rx_ns, val_gem1__ptp_rx_ns); +set_reset_data( gem1__ptp_peer_tx_s, val_gem1__ptp_peer_tx_s); +set_reset_data( gem1__ptp_peer_tx_ns, val_gem1__ptp_peer_tx_ns); +set_reset_data( gem1__ptp_peer_rx_s, val_gem1__ptp_peer_rx_s); +set_reset_data( gem1__ptp_peer_rx_ns, val_gem1__ptp_peer_rx_ns); +set_reset_data( gem1__pcs_ctrl, val_gem1__pcs_ctrl); +set_reset_data( gem1__pcs_status, val_gem1__pcs_status); +set_reset_data( gem1__pcs_upper_phy_id, val_gem1__pcs_upper_phy_id); +set_reset_data( gem1__pcs_lower_phy_id, val_gem1__pcs_lower_phy_id); +set_reset_data( gem1__pcs_autoneg_ad, val_gem1__pcs_autoneg_ad); +set_reset_data( gem1__pcs_autoneg_ability, val_gem1__pcs_autoneg_ability); +set_reset_data( gem1__pcs_autonec_exp, val_gem1__pcs_autonec_exp); +set_reset_data( gem1__pcs_autoneg_next_pg, val_gem1__pcs_autoneg_next_pg); +set_reset_data( gem1__pcs_autoneg_pnext_pg, val_gem1__pcs_autoneg_pnext_pg); +set_reset_data( gem1__pcs_extended_status, val_gem1__pcs_extended_status); +set_reset_data( gem1__design_cfg1, val_gem1__design_cfg1); +set_reset_data( gem1__design_cfg2, val_gem1__design_cfg2); +set_reset_data( gem1__design_cfg3, val_gem1__design_cfg3); +set_reset_data( gem1__design_cfg4, val_gem1__design_cfg4); +set_reset_data( gem1__design_cfg5, val_gem1__design_cfg5); +set_reset_data( gem1__design_cfg6, val_gem1__design_cfg6); +set_reset_data( gem1__design_cfg7, val_gem1__design_cfg7); +set_reset_data( gem1__isr_pq1, val_gem1__isr_pq1); +set_reset_data( gem1__isr_pq2, val_gem1__isr_pq2); +set_reset_data( gem1__isr_pq3, val_gem1__isr_pq3); +set_reset_data( gem1__isr_pq4, val_gem1__isr_pq4); +set_reset_data( gem1__isr_pq5, val_gem1__isr_pq5); +set_reset_data( gem1__isr_pq6, val_gem1__isr_pq6); +set_reset_data( gem1__isr_pq7, val_gem1__isr_pq7); +set_reset_data( gem1__tx_qbar_q1, val_gem1__tx_qbar_q1); +set_reset_data( gem1__tx_qbar_q2, val_gem1__tx_qbar_q2); +set_reset_data( gem1__tx_qbar_q3, val_gem1__tx_qbar_q3); +set_reset_data( gem1__tx_qbar_q4, val_gem1__tx_qbar_q4); +set_reset_data( gem1__tx_qbar_q5, val_gem1__tx_qbar_q5); +set_reset_data( gem1__tx_qbar_q6, val_gem1__tx_qbar_q6); +set_reset_data( gem1__tx_qbar_q7, val_gem1__tx_qbar_q7); +set_reset_data( gem1__rx_qbar_q1, val_gem1__rx_qbar_q1); +set_reset_data( gem1__rx_qbar_q2, val_gem1__rx_qbar_q2); +set_reset_data( gem1__rx_qbar_q3, val_gem1__rx_qbar_q3); +set_reset_data( gem1__rx_qbar_q4, val_gem1__rx_qbar_q4); +set_reset_data( gem1__rx_qbar_q5, val_gem1__rx_qbar_q5); +set_reset_data( gem1__rx_qbar_q6, val_gem1__rx_qbar_q6); +set_reset_data( gem1__rx_qbar_q7, val_gem1__rx_qbar_q7); +set_reset_data( gem1__rx_bufsz_q1, val_gem1__rx_bufsz_q1); +set_reset_data( gem1__rx_bufsz_q2, val_gem1__rx_bufsz_q2); +set_reset_data( gem1__rx_bufsz_q3, val_gem1__rx_bufsz_q3); +set_reset_data( gem1__rx_bufsz_q4, val_gem1__rx_bufsz_q4); +set_reset_data( gem1__rx_bufsz_q5, val_gem1__rx_bufsz_q5); +set_reset_data( gem1__rx_bufsz_q6, val_gem1__rx_bufsz_q6); +set_reset_data( gem1__rx_bufsz_q7, val_gem1__rx_bufsz_q7); +set_reset_data( gem1__screen_t1_r0, val_gem1__screen_t1_r0); +set_reset_data( gem1__screen_t1_r1, val_gem1__screen_t1_r1); +set_reset_data( gem1__screen_t1_r2, val_gem1__screen_t1_r2); +set_reset_data( gem1__screen_t1_r3, val_gem1__screen_t1_r3); +set_reset_data( gem1__screen_t1_r4, val_gem1__screen_t1_r4); +set_reset_data( gem1__screen_t1_r5, val_gem1__screen_t1_r5); +set_reset_data( gem1__screen_t1_r6, val_gem1__screen_t1_r6); +set_reset_data( gem1__screen_t1_r7, val_gem1__screen_t1_r7); +set_reset_data( gem1__screen_t1_r8, val_gem1__screen_t1_r8); +set_reset_data( gem1__screen_t1_r9, val_gem1__screen_t1_r9); +set_reset_data( gem1__screen_t1_r10, val_gem1__screen_t1_r10); +set_reset_data( gem1__screen_t1_r11, val_gem1__screen_t1_r11); +set_reset_data( gem1__screen_t1_r12, val_gem1__screen_t1_r12); +set_reset_data( gem1__screen_t1_r13, val_gem1__screen_t1_r13); +set_reset_data( gem1__screen_t1_r14, val_gem1__screen_t1_r14); +set_reset_data( gem1__screen_t1_r15, val_gem1__screen_t1_r15); +set_reset_data( gem1__screen_t2_r0, val_gem1__screen_t2_r0); +set_reset_data( gem1__screen_t2_r1, val_gem1__screen_t2_r1); +set_reset_data( gem1__screen_t2_r2, val_gem1__screen_t2_r2); +set_reset_data( gem1__screen_t2_r3, val_gem1__screen_t2_r3); +set_reset_data( gem1__screen_t2_r4, val_gem1__screen_t2_r4); +set_reset_data( gem1__screen_t2_r5, val_gem1__screen_t2_r5); +set_reset_data( gem1__screen_t2_r6, val_gem1__screen_t2_r6); +set_reset_data( gem1__screen_t2_r7, val_gem1__screen_t2_r7); +set_reset_data( gem1__screen_t2_r8, val_gem1__screen_t2_r8); +set_reset_data( gem1__screen_t2_r9, val_gem1__screen_t2_r9); +set_reset_data( gem1__screen_t2_r10, val_gem1__screen_t2_r10); +set_reset_data( gem1__screen_t2_r11, val_gem1__screen_t2_r11); +set_reset_data( gem1__screen_t2_r12, val_gem1__screen_t2_r12); +set_reset_data( gem1__screen_t2_r13, val_gem1__screen_t2_r13); +set_reset_data( gem1__screen_t2_r14, val_gem1__screen_t2_r14); +set_reset_data( gem1__screen_t2_r15, val_gem1__screen_t2_r15); +set_reset_data( gem1__intr_en_pq1, val_gem1__intr_en_pq1); +set_reset_data( gem1__intr_en_pq2, val_gem1__intr_en_pq2); +set_reset_data( gem1__intr_en_pq3, val_gem1__intr_en_pq3); +set_reset_data( gem1__intr_en_pq4, val_gem1__intr_en_pq4); +set_reset_data( gem1__intr_en_pq5, val_gem1__intr_en_pq5); +set_reset_data( gem1__intr_en_pq6, val_gem1__intr_en_pq6); +set_reset_data( gem1__intr_en_pq7, val_gem1__intr_en_pq7); +set_reset_data( gem1__intr_dis_pq1, val_gem1__intr_dis_pq1); +set_reset_data( gem1__intr_dis_pq2, val_gem1__intr_dis_pq2); +set_reset_data( gem1__intr_dis_pq3, val_gem1__intr_dis_pq3); +set_reset_data( gem1__intr_dis_pq4, val_gem1__intr_dis_pq4); +set_reset_data( gem1__intr_dis_pq5, val_gem1__intr_dis_pq5); +set_reset_data( gem1__intr_dis_pq6, val_gem1__intr_dis_pq6); +set_reset_data( gem1__intr_dis_pq7, val_gem1__intr_dis_pq7); +set_reset_data( gem1__intr_mask_pq1, val_gem1__intr_mask_pq1); +set_reset_data( gem1__intr_mask_pq2, val_gem1__intr_mask_pq2); +set_reset_data( gem1__intr_mask_pq3, val_gem1__intr_mask_pq3); +set_reset_data( gem1__intr_mask_pq4, val_gem1__intr_mask_pq4); +set_reset_data( gem1__intr_mask_pq5, val_gem1__intr_mask_pq5); +set_reset_data( gem1__intr_mask_pq6, val_gem1__intr_mask_pq6); +set_reset_data( gem1__intr_mask_pq7, val_gem1__intr_mask_pq7); + +// ************************************************************ +// Module gpio gpio +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpio__MASK_DATA_0_LSW, val_gpio__MASK_DATA_0_LSW); +set_reset_data( gpio__MASK_DATA_0_MSW, val_gpio__MASK_DATA_0_MSW); +set_reset_data( gpio__MASK_DATA_1_LSW, val_gpio__MASK_DATA_1_LSW); +set_reset_data( gpio__MASK_DATA_1_MSW, val_gpio__MASK_DATA_1_MSW); +set_reset_data( gpio__MASK_DATA_2_LSW, val_gpio__MASK_DATA_2_LSW); +set_reset_data( gpio__MASK_DATA_2_MSW, val_gpio__MASK_DATA_2_MSW); +set_reset_data( gpio__MASK_DATA_3_LSW, val_gpio__MASK_DATA_3_LSW); +set_reset_data( gpio__MASK_DATA_3_MSW, val_gpio__MASK_DATA_3_MSW); +set_reset_data( gpio__DATA_0, val_gpio__DATA_0); +set_reset_data( gpio__DATA_1, val_gpio__DATA_1); +set_reset_data( gpio__DATA_2, val_gpio__DATA_2); +set_reset_data( gpio__DATA_3, val_gpio__DATA_3); +set_reset_data( gpio__DATA_0_RO, val_gpio__DATA_0_RO); +set_reset_data( gpio__DATA_1_RO, val_gpio__DATA_1_RO); +set_reset_data( gpio__DATA_2_RO, val_gpio__DATA_2_RO); +set_reset_data( gpio__DATA_3_RO, val_gpio__DATA_3_RO); +set_reset_data( gpio__BYPM_0, val_gpio__BYPM_0); +set_reset_data( gpio__DIRM_0, val_gpio__DIRM_0); +set_reset_data( gpio__OEN_0, val_gpio__OEN_0); +set_reset_data( gpio__INT_MASK_0, val_gpio__INT_MASK_0); +set_reset_data( gpio__INT_EN_0, val_gpio__INT_EN_0); +set_reset_data( gpio__INT_DIS_0, val_gpio__INT_DIS_0); +set_reset_data( gpio__INT_STAT_0, val_gpio__INT_STAT_0); +set_reset_data( gpio__INT_TYPE_0, val_gpio__INT_TYPE_0); +set_reset_data( gpio__INT_POLARITY_0, val_gpio__INT_POLARITY_0); +set_reset_data( gpio__INT_ANY_0, val_gpio__INT_ANY_0); +set_reset_data( gpio__BYPM_1, val_gpio__BYPM_1); +set_reset_data( gpio__DIRM_1, val_gpio__DIRM_1); +set_reset_data( gpio__OEN_1, val_gpio__OEN_1); +set_reset_data( gpio__INT_MASK_1, val_gpio__INT_MASK_1); +set_reset_data( gpio__INT_EN_1, val_gpio__INT_EN_1); +set_reset_data( gpio__INT_DIS_1, val_gpio__INT_DIS_1); +set_reset_data( gpio__INT_STAT_1, val_gpio__INT_STAT_1); +set_reset_data( gpio__INT_TYPE_1, val_gpio__INT_TYPE_1); +set_reset_data( gpio__INT_POLARITY_1, val_gpio__INT_POLARITY_1); +set_reset_data( gpio__INT_ANY_1, val_gpio__INT_ANY_1); +set_reset_data( gpio__BYPM_2, val_gpio__BYPM_2); +set_reset_data( gpio__DIRM_2, val_gpio__DIRM_2); +set_reset_data( gpio__OEN_2, val_gpio__OEN_2); +set_reset_data( gpio__INT_MASK_2, val_gpio__INT_MASK_2); +set_reset_data( gpio__INT_EN_2, val_gpio__INT_EN_2); +set_reset_data( gpio__INT_DIS_2, val_gpio__INT_DIS_2); +set_reset_data( gpio__INT_STAT_2, val_gpio__INT_STAT_2); +set_reset_data( gpio__INT_TYPE_2, val_gpio__INT_TYPE_2); +set_reset_data( gpio__INT_POLARITY_2, val_gpio__INT_POLARITY_2); +set_reset_data( gpio__INT_ANY_2, val_gpio__INT_ANY_2); +set_reset_data( gpio__BYPM_3, val_gpio__BYPM_3); +set_reset_data( gpio__DIRM_3, val_gpio__DIRM_3); +set_reset_data( gpio__OEN_3, val_gpio__OEN_3); +set_reset_data( gpio__INT_MASK_3, val_gpio__INT_MASK_3); +set_reset_data( gpio__INT_EN_3, val_gpio__INT_EN_3); +set_reset_data( gpio__INT_DIS_3, val_gpio__INT_DIS_3); +set_reset_data( gpio__INT_STAT_3, val_gpio__INT_STAT_3); +set_reset_data( gpio__INT_TYPE_3, val_gpio__INT_TYPE_3); +set_reset_data( gpio__INT_POLARITY_3, val_gpio__INT_POLARITY_3); +set_reset_data( gpio__INT_ANY_3, val_gpio__INT_ANY_3); + +// ************************************************************ +// Module gpv_iou_switch gpv_iou_switch +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_iou_switch__Remap, val_gpv_iou_switch__Remap); +set_reset_data( gpv_iou_switch__security2_sdio0, val_gpv_iou_switch__security2_sdio0); +set_reset_data( gpv_iou_switch__security3_sdio1, val_gpv_iou_switch__security3_sdio1); +set_reset_data( gpv_iou_switch__security4_qspi, val_gpv_iou_switch__security4_qspi); +set_reset_data( gpv_iou_switch__security5_miou, val_gpv_iou_switch__security5_miou); +set_reset_data( gpv_iou_switch__security6_apb_slaves, val_gpv_iou_switch__security6_apb_slaves); +set_reset_data( gpv_iou_switch__security7_smc, val_gpv_iou_switch__security7_smc); +set_reset_data( gpv_iou_switch__peripheral_id4, val_gpv_iou_switch__peripheral_id4); +set_reset_data( gpv_iou_switch__peripheral_id5, val_gpv_iou_switch__peripheral_id5); +set_reset_data( gpv_iou_switch__peripheral_id6, val_gpv_iou_switch__peripheral_id6); +set_reset_data( gpv_iou_switch__peripheral_id7, val_gpv_iou_switch__peripheral_id7); +set_reset_data( gpv_iou_switch__peripheral_id0, val_gpv_iou_switch__peripheral_id0); +set_reset_data( gpv_iou_switch__peripheral_id1, val_gpv_iou_switch__peripheral_id1); +set_reset_data( gpv_iou_switch__peripheral_id2, val_gpv_iou_switch__peripheral_id2); +set_reset_data( gpv_iou_switch__peripheral_id3, val_gpv_iou_switch__peripheral_id3); +set_reset_data( gpv_iou_switch__component_id0, val_gpv_iou_switch__component_id0); +set_reset_data( gpv_iou_switch__component_id1, val_gpv_iou_switch__component_id1); +set_reset_data( gpv_iou_switch__component_id2, val_gpv_iou_switch__component_id2); +set_reset_data( gpv_iou_switch__component_id3, val_gpv_iou_switch__component_id3); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio0, val_gpv_iou_switch__fn_mod_bm_iss_sdio0); +set_reset_data( gpv_iou_switch__ahb_cntl_sdio0, val_gpv_iou_switch__ahb_cntl_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio1, val_gpv_iou_switch__fn_mod_bm_iss_sdio1); +set_reset_data( gpv_iou_switch__ahb_cntl_sdio1, val_gpv_iou_switch__ahb_cntl_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_qspi, val_gpv_iou_switch__fn_mod_bm_iss_qspi); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_miou, val_gpv_iou_switch__fn_mod_bm_iss_miou); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_smc, val_gpv_iou_switch__fn_mod_bm_iss_smc); +set_reset_data( gpv_iou_switch__fn_mod_ahb_gem0, val_gpv_iou_switch__fn_mod_ahb_gem0); +set_reset_data( gpv_iou_switch__read_qos_gem0, val_gpv_iou_switch__read_qos_gem0); +set_reset_data( gpv_iou_switch__write_qos_gem0, val_gpv_iou_switch__write_qos_gem0); +set_reset_data( gpv_iou_switch__fn_mod_iss_gem0, val_gpv_iou_switch__fn_mod_iss_gem0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_gem1, val_gpv_iou_switch__fn_mod_ahb_gem1); +set_reset_data( gpv_iou_switch__read_qos_gem1, val_gpv_iou_switch__read_qos_gem1); +set_reset_data( gpv_iou_switch__write_qos_gem1, val_gpv_iou_switch__write_qos_gem1); +set_reset_data( gpv_iou_switch__fn_mod_iss_gem1, val_gpv_iou_switch__fn_mod_iss_gem1); +set_reset_data( gpv_iou_switch__fn_mod_ahb_usb0, val_gpv_iou_switch__fn_mod_ahb_usb0); +set_reset_data( gpv_iou_switch__read_qos_usb0, val_gpv_iou_switch__read_qos_usb0); +set_reset_data( gpv_iou_switch__write_qos_usb0, val_gpv_iou_switch__write_qos_usb0); +set_reset_data( gpv_iou_switch__fn_mod_iss_usb0, val_gpv_iou_switch__fn_mod_iss_usb0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_usb1, val_gpv_iou_switch__fn_mod_ahb_usb1); +set_reset_data( gpv_iou_switch__read_qos_usb1, val_gpv_iou_switch__read_qos_usb1); +set_reset_data( gpv_iou_switch__write_qos_usb1, val_gpv_iou_switch__write_qos_usb1); +set_reset_data( gpv_iou_switch__fn_mod_iss_usb1, val_gpv_iou_switch__fn_mod_iss_usb1); +set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio0, val_gpv_iou_switch__fn_mod_ahb_sdio0); +set_reset_data( gpv_iou_switch__read_qos_sdio0, val_gpv_iou_switch__read_qos_sdio0); +set_reset_data( gpv_iou_switch__write_qos_sdio0, val_gpv_iou_switch__write_qos_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_iss_sdio0, val_gpv_iou_switch__fn_mod_iss_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio1, val_gpv_iou_switch__fn_mod_ahb_sdio1); +set_reset_data( gpv_iou_switch__read_qos_sdio1, val_gpv_iou_switch__read_qos_sdio1); +set_reset_data( gpv_iou_switch__write_qos_sdio1, val_gpv_iou_switch__write_qos_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_iss_sdio1, val_gpv_iou_switch__fn_mod_iss_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_iss_siou, val_gpv_iou_switch__fn_mod_iss_siou); + +// ************************************************************ +// Module gpv_qos301_cpu qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_cpu__qos_cntl, val_gpv_qos301_cpu__qos_cntl); +set_reset_data( gpv_qos301_cpu__max_ot, val_gpv_qos301_cpu__max_ot); +set_reset_data( gpv_qos301_cpu__max_comb_ot, val_gpv_qos301_cpu__max_comb_ot); +set_reset_data( gpv_qos301_cpu__aw_p, val_gpv_qos301_cpu__aw_p); +set_reset_data( gpv_qos301_cpu__aw_b, val_gpv_qos301_cpu__aw_b); +set_reset_data( gpv_qos301_cpu__aw_r, val_gpv_qos301_cpu__aw_r); +set_reset_data( gpv_qos301_cpu__ar_p, val_gpv_qos301_cpu__ar_p); +set_reset_data( gpv_qos301_cpu__ar_b, val_gpv_qos301_cpu__ar_b); +set_reset_data( gpv_qos301_cpu__ar_r, val_gpv_qos301_cpu__ar_r); + +// ************************************************************ +// Module gpv_qos301_dmac qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_dmac__qos_cntl, val_gpv_qos301_dmac__qos_cntl); +set_reset_data( gpv_qos301_dmac__max_ot, val_gpv_qos301_dmac__max_ot); +set_reset_data( gpv_qos301_dmac__max_comb_ot, val_gpv_qos301_dmac__max_comb_ot); +set_reset_data( gpv_qos301_dmac__aw_p, val_gpv_qos301_dmac__aw_p); +set_reset_data( gpv_qos301_dmac__aw_b, val_gpv_qos301_dmac__aw_b); +set_reset_data( gpv_qos301_dmac__aw_r, val_gpv_qos301_dmac__aw_r); +set_reset_data( gpv_qos301_dmac__ar_p, val_gpv_qos301_dmac__ar_p); +set_reset_data( gpv_qos301_dmac__ar_b, val_gpv_qos301_dmac__ar_b); +set_reset_data( gpv_qos301_dmac__ar_r, val_gpv_qos301_dmac__ar_r); + +// ************************************************************ +// Module gpv_qos301_iou qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_iou__qos_cntl, val_gpv_qos301_iou__qos_cntl); +set_reset_data( gpv_qos301_iou__max_ot, val_gpv_qos301_iou__max_ot); +set_reset_data( gpv_qos301_iou__max_comb_ot, val_gpv_qos301_iou__max_comb_ot); +set_reset_data( gpv_qos301_iou__aw_p, val_gpv_qos301_iou__aw_p); +set_reset_data( gpv_qos301_iou__aw_b, val_gpv_qos301_iou__aw_b); +set_reset_data( gpv_qos301_iou__aw_r, val_gpv_qos301_iou__aw_r); +set_reset_data( gpv_qos301_iou__ar_p, val_gpv_qos301_iou__ar_p); +set_reset_data( gpv_qos301_iou__ar_b, val_gpv_qos301_iou__ar_b); +set_reset_data( gpv_qos301_iou__ar_r, val_gpv_qos301_iou__ar_r); + +// ************************************************************ +// Module gpv_trustzone nic301_addr_region_ctrl_registers +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_trustzone__Remap, val_gpv_trustzone__Remap); +set_reset_data( gpv_trustzone__security_fssw_s0, val_gpv_trustzone__security_fssw_s0); +set_reset_data( gpv_trustzone__security_fssw_s1, val_gpv_trustzone__security_fssw_s1); +set_reset_data( gpv_trustzone__security_apb, val_gpv_trustzone__security_apb); + +// ************************************************************ +// Module i2c0 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( i2c0__Control_reg0, val_i2c0__Control_reg0); +set_reset_data( i2c0__Status_reg0, val_i2c0__Status_reg0); +set_reset_data( i2c0__I2C_address_reg0, val_i2c0__I2C_address_reg0); +set_reset_data( i2c0__I2C_data_reg0, val_i2c0__I2C_data_reg0); +set_reset_data( i2c0__Interrupt_status_reg0, val_i2c0__Interrupt_status_reg0); +set_reset_data( i2c0__Transfer_size_reg0, val_i2c0__Transfer_size_reg0); +set_reset_data( i2c0__Slave_mon_pause_reg0, val_i2c0__Slave_mon_pause_reg0); +set_reset_data( i2c0__Time_out_reg0, val_i2c0__Time_out_reg0); +set_reset_data( i2c0__Intrpt_mask_reg0, val_i2c0__Intrpt_mask_reg0); +set_reset_data( i2c0__Intrpt_enable_reg0, val_i2c0__Intrpt_enable_reg0); +set_reset_data( i2c0__Intrpt_disable_reg0, val_i2c0__Intrpt_disable_reg0); + +// ************************************************************ +// Module i2c1 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( i2c1__Control_reg0, val_i2c1__Control_reg0); +set_reset_data( i2c1__Status_reg0, val_i2c1__Status_reg0); +set_reset_data( i2c1__I2C_address_reg0, val_i2c1__I2C_address_reg0); +set_reset_data( i2c1__I2C_data_reg0, val_i2c1__I2C_data_reg0); +set_reset_data( i2c1__Interrupt_status_reg0, val_i2c1__Interrupt_status_reg0); +set_reset_data( i2c1__Transfer_size_reg0, val_i2c1__Transfer_size_reg0); +set_reset_data( i2c1__Slave_mon_pause_reg0, val_i2c1__Slave_mon_pause_reg0); +set_reset_data( i2c1__Time_out_reg0, val_i2c1__Time_out_reg0); +set_reset_data( i2c1__Intrpt_mask_reg0, val_i2c1__Intrpt_mask_reg0); +set_reset_data( i2c1__Intrpt_enable_reg0, val_i2c1__Intrpt_enable_reg0); +set_reset_data( i2c1__Intrpt_disable_reg0, val_i2c1__Intrpt_disable_reg0); + +// ************************************************************ +// Module l2cache L2Cpl310 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( l2cache__reg0_cache_id, val_l2cache__reg0_cache_id); +set_reset_data( l2cache__reg0_cache_type, val_l2cache__reg0_cache_type); +set_reset_data( l2cache__reg1_control, val_l2cache__reg1_control); +set_reset_data( l2cache__reg1_aux_control, val_l2cache__reg1_aux_control); +set_reset_data( l2cache__reg1_tag_ram_control, val_l2cache__reg1_tag_ram_control); +set_reset_data( l2cache__reg1_data_ram_control, val_l2cache__reg1_data_ram_control); +set_reset_data( l2cache__reg2_ev_counter_ctrl, val_l2cache__reg2_ev_counter_ctrl); +set_reset_data( l2cache__reg2_ev_counter1_cfg, val_l2cache__reg2_ev_counter1_cfg); +set_reset_data( l2cache__reg2_ev_counter0_cfg, val_l2cache__reg2_ev_counter0_cfg); +set_reset_data( l2cache__reg2_ev_counter1, val_l2cache__reg2_ev_counter1); +set_reset_data( l2cache__reg2_ev_counter0, val_l2cache__reg2_ev_counter0); +set_reset_data( l2cache__reg2_int_mask, val_l2cache__reg2_int_mask); +set_reset_data( l2cache__reg2_int_mask_status, val_l2cache__reg2_int_mask_status); +set_reset_data( l2cache__reg2_int_raw_status, val_l2cache__reg2_int_raw_status); +set_reset_data( l2cache__reg2_int_clear, val_l2cache__reg2_int_clear); +set_reset_data( l2cache__reg7_cache_sync, val_l2cache__reg7_cache_sync); +set_reset_data( l2cache__reg7_inv_pa, val_l2cache__reg7_inv_pa); +set_reset_data( l2cache__reg7_inv_way, val_l2cache__reg7_inv_way); +set_reset_data( l2cache__reg7_clean_pa, val_l2cache__reg7_clean_pa); +set_reset_data( l2cache__reg7_clean_index, val_l2cache__reg7_clean_index); +set_reset_data( l2cache__reg7_clean_way, val_l2cache__reg7_clean_way); +set_reset_data( l2cache__reg7_clean_inv_pa, val_l2cache__reg7_clean_inv_pa); +set_reset_data( l2cache__reg7_clean_inv_index, val_l2cache__reg7_clean_inv_index); +set_reset_data( l2cache__reg7_clean_inv_way, val_l2cache__reg7_clean_inv_way); +set_reset_data( l2cache__reg9_d_lockdown0, val_l2cache__reg9_d_lockdown0); +set_reset_data( l2cache__reg9_i_lockdown0, val_l2cache__reg9_i_lockdown0); +set_reset_data( l2cache__reg9_d_lockdown1, val_l2cache__reg9_d_lockdown1); +set_reset_data( l2cache__reg9_i_lockdown1, val_l2cache__reg9_i_lockdown1); +set_reset_data( l2cache__reg9_d_lockdown2, val_l2cache__reg9_d_lockdown2); +set_reset_data( l2cache__reg9_i_lockdown2, val_l2cache__reg9_i_lockdown2); +set_reset_data( l2cache__reg9_d_lockdown3, val_l2cache__reg9_d_lockdown3); +set_reset_data( l2cache__reg9_i_lockdown3, val_l2cache__reg9_i_lockdown3); +set_reset_data( l2cache__reg9_d_lockdown4, val_l2cache__reg9_d_lockdown4); +set_reset_data( l2cache__reg9_i_lockdown4, val_l2cache__reg9_i_lockdown4); +set_reset_data( l2cache__reg9_d_lockdown5, val_l2cache__reg9_d_lockdown5); +set_reset_data( l2cache__reg9_i_lockdown5, val_l2cache__reg9_i_lockdown5); +set_reset_data( l2cache__reg9_d_lockdown6, val_l2cache__reg9_d_lockdown6); +set_reset_data( l2cache__reg9_i_lockdown6, val_l2cache__reg9_i_lockdown6); +set_reset_data( l2cache__reg9_d_lockdown7, val_l2cache__reg9_d_lockdown7); +set_reset_data( l2cache__reg9_i_lockdown7, val_l2cache__reg9_i_lockdown7); +set_reset_data( l2cache__reg9_lock_line_en, val_l2cache__reg9_lock_line_en); +set_reset_data( l2cache__reg9_unlock_way, val_l2cache__reg9_unlock_way); +set_reset_data( l2cache__reg12_addr_filtering_start, val_l2cache__reg12_addr_filtering_start); +set_reset_data( l2cache__reg12_addr_filtering_end, val_l2cache__reg12_addr_filtering_end); +set_reset_data( l2cache__reg15_debug_ctrl, val_l2cache__reg15_debug_ctrl); +set_reset_data( l2cache__reg15_prefetch_ctrl, val_l2cache__reg15_prefetch_ctrl); +set_reset_data( l2cache__reg15_power_ctrl, val_l2cache__reg15_power_ctrl); + +// ************************************************************ +// Module mpcore mpcore +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( mpcore__SCU_CONTROL_REGISTER, val_mpcore__SCU_CONTROL_REGISTER); +set_reset_data( mpcore__SCU_CONFIGURATION_REGISTER, val_mpcore__SCU_CONFIGURATION_REGISTER); +set_reset_data( mpcore__SCU_CPU_Power_Status_Register, val_mpcore__SCU_CPU_Power_Status_Register); +set_reset_data( mpcore__SCU_Invalidate_All_Registers_in_Secure_State, val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State); +set_reset_data( mpcore__Filtering_Start_Address_Register, val_mpcore__Filtering_Start_Address_Register); +set_reset_data( mpcore__Filtering_End_Address_Register, val_mpcore__Filtering_End_Address_Register); +set_reset_data( mpcore__SCU_Access_Control_Register_SAC, val_mpcore__SCU_Access_Control_Register_SAC); +set_reset_data( mpcore__SCU_Non_secure_Access_Control_Register, val_mpcore__SCU_Non_secure_Access_Control_Register); +set_reset_data( mpcore__ICCICR, val_mpcore__ICCICR); +set_reset_data( mpcore__ICCPMR, val_mpcore__ICCPMR); +set_reset_data( mpcore__ICCBPR, val_mpcore__ICCBPR); +set_reset_data( mpcore__ICCIAR, val_mpcore__ICCIAR); +set_reset_data( mpcore__ICCEOIR, val_mpcore__ICCEOIR); +set_reset_data( mpcore__ICCRPR, val_mpcore__ICCRPR); +set_reset_data( mpcore__ICCHPIR, val_mpcore__ICCHPIR); +set_reset_data( mpcore__ICCABPR, val_mpcore__ICCABPR); +set_reset_data( mpcore__ICCIDR, val_mpcore__ICCIDR); +set_reset_data( mpcore__Global_Timer_Counter_Register0, val_mpcore__Global_Timer_Counter_Register0); +set_reset_data( mpcore__Global_Timer_Counter_Register1, val_mpcore__Global_Timer_Counter_Register1); +set_reset_data( mpcore__Global_Timer_Control_Register, val_mpcore__Global_Timer_Control_Register); +set_reset_data( mpcore__Global_Timer_Interrupt_Status_Register, val_mpcore__Global_Timer_Interrupt_Status_Register); +set_reset_data( mpcore__Comparator_Value_Register0, val_mpcore__Comparator_Value_Register0); +set_reset_data( mpcore__Comparator_Value_Register1, val_mpcore__Comparator_Value_Register1); +set_reset_data( mpcore__Auto_increment_Register, val_mpcore__Auto_increment_Register); +set_reset_data( mpcore__Private_Timer_Load_Register, val_mpcore__Private_Timer_Load_Register); +set_reset_data( mpcore__Private_Timer_Counter_Register, val_mpcore__Private_Timer_Counter_Register); +set_reset_data( mpcore__Private_Timer_Control_Register, val_mpcore__Private_Timer_Control_Register); +set_reset_data( mpcore__Private_Timer_Interrupt_Status_Register, val_mpcore__Private_Timer_Interrupt_Status_Register); +set_reset_data( mpcore__Watchdog_Load_Register, val_mpcore__Watchdog_Load_Register); +set_reset_data( mpcore__Watchdog_Counter_Register, val_mpcore__Watchdog_Counter_Register); +set_reset_data( mpcore__Watchdog_Control_Register, val_mpcore__Watchdog_Control_Register); +set_reset_data( mpcore__Watchdog_Interrupt_Status_Register, val_mpcore__Watchdog_Interrupt_Status_Register); +set_reset_data( mpcore__Watchdog_Reset_Status_Register, val_mpcore__Watchdog_Reset_Status_Register); +set_reset_data( mpcore__Watchdog_Disable_Register, val_mpcore__Watchdog_Disable_Register); +set_reset_data( mpcore__ICDDCR, val_mpcore__ICDDCR); +set_reset_data( mpcore__ICDICTR, val_mpcore__ICDICTR); +set_reset_data( mpcore__ICDIIDR, val_mpcore__ICDIIDR); +set_reset_data( mpcore__ICDISR0, val_mpcore__ICDISR0); +set_reset_data( mpcore__ICDISR1, val_mpcore__ICDISR1); +set_reset_data( mpcore__ICDISR2, val_mpcore__ICDISR2); +set_reset_data( mpcore__ICDISER0, val_mpcore__ICDISER0); +set_reset_data( mpcore__ICDISER1, val_mpcore__ICDISER1); +set_reset_data( mpcore__ICDISER2, val_mpcore__ICDISER2); +set_reset_data( mpcore__ICDICER0, val_mpcore__ICDICER0); +set_reset_data( mpcore__ICDICER1, val_mpcore__ICDICER1); +set_reset_data( mpcore__ICDICER2, val_mpcore__ICDICER2); +set_reset_data( mpcore__ICDISPR0, val_mpcore__ICDISPR0); +set_reset_data( mpcore__ICDISPR1, val_mpcore__ICDISPR1); +set_reset_data( mpcore__ICDISPR2, val_mpcore__ICDISPR2); +set_reset_data( mpcore__ICDICPR0, val_mpcore__ICDICPR0); +set_reset_data( mpcore__ICDICPR1, val_mpcore__ICDICPR1); +set_reset_data( mpcore__ICDICPR2, val_mpcore__ICDICPR2); +set_reset_data( mpcore__ICDABR0, val_mpcore__ICDABR0); +set_reset_data( mpcore__ICDABR1, val_mpcore__ICDABR1); +set_reset_data( mpcore__ICDABR2, val_mpcore__ICDABR2); +set_reset_data( mpcore__ICDIPR0, val_mpcore__ICDIPR0); +set_reset_data( mpcore__ICDIPR1, val_mpcore__ICDIPR1); +set_reset_data( mpcore__ICDIPR2, val_mpcore__ICDIPR2); +set_reset_data( mpcore__ICDIPR3, val_mpcore__ICDIPR3); +set_reset_data( mpcore__ICDIPR4, val_mpcore__ICDIPR4); +set_reset_data( mpcore__ICDIPR5, val_mpcore__ICDIPR5); +set_reset_data( mpcore__ICDIPR6, val_mpcore__ICDIPR6); +set_reset_data( mpcore__ICDIPR7, val_mpcore__ICDIPR7); +set_reset_data( mpcore__ICDIPR8, val_mpcore__ICDIPR8); +set_reset_data( mpcore__ICDIPR9, val_mpcore__ICDIPR9); +set_reset_data( mpcore__ICDIPR10, val_mpcore__ICDIPR10); +set_reset_data( mpcore__ICDIPR11, val_mpcore__ICDIPR11); +set_reset_data( mpcore__ICDIPR12, val_mpcore__ICDIPR12); +set_reset_data( mpcore__ICDIPR13, val_mpcore__ICDIPR13); +set_reset_data( mpcore__ICDIPR14, val_mpcore__ICDIPR14); +set_reset_data( mpcore__ICDIPR15, val_mpcore__ICDIPR15); +set_reset_data( mpcore__ICDIPR16, val_mpcore__ICDIPR16); +set_reset_data( mpcore__ICDIPR17, val_mpcore__ICDIPR17); +set_reset_data( mpcore__ICDIPR18, val_mpcore__ICDIPR18); +set_reset_data( mpcore__ICDIPR19, val_mpcore__ICDIPR19); +set_reset_data( mpcore__ICDIPR20, val_mpcore__ICDIPR20); +set_reset_data( mpcore__ICDIPR21, val_mpcore__ICDIPR21); +set_reset_data( mpcore__ICDIPR22, val_mpcore__ICDIPR22); +set_reset_data( mpcore__ICDIPR23, val_mpcore__ICDIPR23); +set_reset_data( mpcore__ICDIPTR0, val_mpcore__ICDIPTR0); +set_reset_data( mpcore__ICDIPTR1, val_mpcore__ICDIPTR1); +set_reset_data( mpcore__ICDIPTR2, val_mpcore__ICDIPTR2); +set_reset_data( mpcore__ICDIPTR3, val_mpcore__ICDIPTR3); +set_reset_data( mpcore__ICDIPTR4, val_mpcore__ICDIPTR4); +set_reset_data( mpcore__ICDIPTR5, val_mpcore__ICDIPTR5); +set_reset_data( mpcore__ICDIPTR6, val_mpcore__ICDIPTR6); +set_reset_data( mpcore__ICDIPTR7, val_mpcore__ICDIPTR7); +set_reset_data( mpcore__ICDIPTR8, val_mpcore__ICDIPTR8); +set_reset_data( mpcore__ICDIPTR9, val_mpcore__ICDIPTR9); +set_reset_data( mpcore__ICDIPTR10, val_mpcore__ICDIPTR10); +set_reset_data( mpcore__ICDIPTR11, val_mpcore__ICDIPTR11); +set_reset_data( mpcore__ICDIPTR12, val_mpcore__ICDIPTR12); +set_reset_data( mpcore__ICDIPTR13, val_mpcore__ICDIPTR13); +set_reset_data( mpcore__ICDIPTR14, val_mpcore__ICDIPTR14); +set_reset_data( mpcore__ICDIPTR15, val_mpcore__ICDIPTR15); +set_reset_data( mpcore__ICDIPTR16, val_mpcore__ICDIPTR16); +set_reset_data( mpcore__ICDIPTR17, val_mpcore__ICDIPTR17); +set_reset_data( mpcore__ICDIPTR18, val_mpcore__ICDIPTR18); +set_reset_data( mpcore__ICDIPTR19, val_mpcore__ICDIPTR19); +set_reset_data( mpcore__ICDIPTR20, val_mpcore__ICDIPTR20); +set_reset_data( mpcore__ICDIPTR21, val_mpcore__ICDIPTR21); +set_reset_data( mpcore__ICDIPTR22, val_mpcore__ICDIPTR22); +set_reset_data( mpcore__ICDIPTR23, val_mpcore__ICDIPTR23); +set_reset_data( mpcore__ICDICFR0, val_mpcore__ICDICFR0); +set_reset_data( mpcore__ICDICFR1, val_mpcore__ICDICFR1); +set_reset_data( mpcore__ICDICFR2, val_mpcore__ICDICFR2); +set_reset_data( mpcore__ICDICFR3, val_mpcore__ICDICFR3); +set_reset_data( mpcore__ICDICFR4, val_mpcore__ICDICFR4); +set_reset_data( mpcore__ICDICFR5, val_mpcore__ICDICFR5); +set_reset_data( mpcore__ppi_status, val_mpcore__ppi_status); +set_reset_data( mpcore__spi_status_0, val_mpcore__spi_status_0); +set_reset_data( mpcore__spi_status_1, val_mpcore__spi_status_1); +set_reset_data( mpcore__ICDSGIR, val_mpcore__ICDSGIR); +set_reset_data( mpcore__ICPIDR4, val_mpcore__ICPIDR4); +set_reset_data( mpcore__ICPIDR5, val_mpcore__ICPIDR5); +set_reset_data( mpcore__ICPIDR6, val_mpcore__ICPIDR6); +set_reset_data( mpcore__ICPIDR7, val_mpcore__ICPIDR7); +set_reset_data( mpcore__ICPIDR0, val_mpcore__ICPIDR0); +set_reset_data( mpcore__ICPIDR1, val_mpcore__ICPIDR1); +set_reset_data( mpcore__ICPIDR2, val_mpcore__ICPIDR2); +set_reset_data( mpcore__ICPIDR3, val_mpcore__ICPIDR3); +set_reset_data( mpcore__ICCIDR0, val_mpcore__ICCIDR0); +set_reset_data( mpcore__ICCIDR1, val_mpcore__ICCIDR1); +set_reset_data( mpcore__ICCIDR2, val_mpcore__ICCIDR2); +set_reset_data( mpcore__ICCIDR3, val_mpcore__ICCIDR3); + +// ************************************************************ +// Module ocm ocm +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ocm__OCM_PARITY_CTRL, val_ocm__OCM_PARITY_CTRL); +set_reset_data( ocm__OCM_PARITY_ERRADDRESS, val_ocm__OCM_PARITY_ERRADDRESS); +set_reset_data( ocm__OCM_IRQ_STS, val_ocm__OCM_IRQ_STS); +set_reset_data( ocm__OCM_CONTROL, val_ocm__OCM_CONTROL); + +// ************************************************************ +// Module qspi qspi +// doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller +/// Design Specification document +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( qspi__Config_reg, val_qspi__Config_reg); +set_reset_data( qspi__Intr_status_REG, val_qspi__Intr_status_REG); +set_reset_data( qspi__Intrpt_en_REG, val_qspi__Intrpt_en_REG); +set_reset_data( qspi__Intrpt_dis_REG, val_qspi__Intrpt_dis_REG); +set_reset_data( qspi__Intrpt_mask_REG, val_qspi__Intrpt_mask_REG); +set_reset_data( qspi__En_REG, val_qspi__En_REG); +set_reset_data( qspi__Delay_REG, val_qspi__Delay_REG); +set_reset_data( qspi__TXD0, val_qspi__TXD0); +set_reset_data( qspi__Rx_data_REG, val_qspi__Rx_data_REG); +set_reset_data( qspi__Slave_Idle_count_REG, val_qspi__Slave_Idle_count_REG); +set_reset_data( qspi__TX_thres_REG, val_qspi__TX_thres_REG); +set_reset_data( qspi__RX_thres_REG, val_qspi__RX_thres_REG); +set_reset_data( qspi__GPIO, val_qspi__GPIO); +set_reset_data( qspi__LPBK_DLY_ADJ, val_qspi__LPBK_DLY_ADJ); +set_reset_data( qspi__TXD1, val_qspi__TXD1); +set_reset_data( qspi__TXD2, val_qspi__TXD2); +set_reset_data( qspi__TXD3, val_qspi__TXD3); +set_reset_data( qspi__LQSPI_CFG, val_qspi__LQSPI_CFG); +set_reset_data( qspi__LQSPI_STS, val_qspi__LQSPI_STS); +set_reset_data( qspi__MOD_ID, val_qspi__MOD_ID); + +// ************************************************************ +// Module sd0 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( sd0__SDMA_system_address_register, val_sd0__SDMA_system_address_register); +set_reset_data( sd0__Block_Size_Block_Count, val_sd0__Block_Size_Block_Count); +set_reset_data( sd0__Argument, val_sd0__Argument); +set_reset_data( sd0__Transfer_Mode_Command, val_sd0__Transfer_Mode_Command); +set_reset_data( sd0__Response0, val_sd0__Response0); +set_reset_data( sd0__Response1, val_sd0__Response1); +set_reset_data( sd0__Response2, val_sd0__Response2); +set_reset_data( sd0__Response3, val_sd0__Response3); +set_reset_data( sd0__Buffer_Data_Port, val_sd0__Buffer_Data_Port); +set_reset_data( sd0__Present_State, val_sd0__Present_State); +set_reset_data( sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control); +set_reset_data( sd0__Clock_Control_Timeout_control_Software_reset, val_sd0__Clock_Control_Timeout_control_Software_reset); +set_reset_data( sd0__Normal_interrupt_status_Error_interrupt_status, val_sd0__Normal_interrupt_status_Error_interrupt_status); +set_reset_data( sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable); +set_reset_data( sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable); +set_reset_data( sd0__Auto_CMD12_error_status, val_sd0__Auto_CMD12_error_status); +set_reset_data( sd0__Capabilities, val_sd0__Capabilities); +set_reset_data( sd0__Maximum_current_capabilities, val_sd0__Maximum_current_capabilities); +set_reset_data( sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status); +set_reset_data( sd0__ADMA_error_status, val_sd0__ADMA_error_status); +set_reset_data( sd0__ADMA_system_address, val_sd0__ADMA_system_address); +set_reset_data( sd0__Boot_Timeout_control, val_sd0__Boot_Timeout_control); +set_reset_data( sd0__Debug_Selection, val_sd0__Debug_Selection); +set_reset_data( sd0__SPI_interrupt_support, val_sd0__SPI_interrupt_support); +set_reset_data( sd0__Slot_interrupt_status_Host_controller_version, val_sd0__Slot_interrupt_status_Host_controller_version); + +// ************************************************************ +// Module sd1 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( sd1__SDMA_system_address_register, val_sd1__SDMA_system_address_register); +set_reset_data( sd1__Block_Size_Block_Count, val_sd1__Block_Size_Block_Count); +set_reset_data( sd1__Argument, val_sd1__Argument); +set_reset_data( sd1__Transfer_Mode_Command, val_sd1__Transfer_Mode_Command); +set_reset_data( sd1__Response0, val_sd1__Response0); +set_reset_data( sd1__Response1, val_sd1__Response1); +set_reset_data( sd1__Response2, val_sd1__Response2); +set_reset_data( sd1__Response3, val_sd1__Response3); +set_reset_data( sd1__Buffer_Data_Port, val_sd1__Buffer_Data_Port); +set_reset_data( sd1__Present_State, val_sd1__Present_State); +set_reset_data( sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control); +set_reset_data( sd1__Clock_Control_Timeout_control_Software_reset, val_sd1__Clock_Control_Timeout_control_Software_reset); +set_reset_data( sd1__Normal_interrupt_status_Error_interrupt_status, val_sd1__Normal_interrupt_status_Error_interrupt_status); +set_reset_data( sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable); +set_reset_data( sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable); +set_reset_data( sd1__Auto_CMD12_error_status, val_sd1__Auto_CMD12_error_status); +set_reset_data( sd1__Capabilities, val_sd1__Capabilities); +set_reset_data( sd1__Maximum_current_capabilities, val_sd1__Maximum_current_capabilities); +set_reset_data( sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status); +set_reset_data( sd1__ADMA_error_status, val_sd1__ADMA_error_status); +set_reset_data( sd1__ADMA_system_address, val_sd1__ADMA_system_address); +set_reset_data( sd1__Boot_Timeout_control, val_sd1__Boot_Timeout_control); +set_reset_data( sd1__Debug_Selection, val_sd1__Debug_Selection); +set_reset_data( sd1__SPI_interrupt_support, val_sd1__SPI_interrupt_support); +set_reset_data( sd1__Slot_interrupt_status_Host_controller_version, val_sd1__Slot_interrupt_status_Host_controller_version); + +// ************************************************************ +// Module slcr slcr +// doc version: 1.3, based on 11/18/2010 SLCR_spec.doc +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( slcr__SCL, val_slcr__SCL); +set_reset_data( slcr__SLCR_LOCK, val_slcr__SLCR_LOCK); +set_reset_data( slcr__SLCR_UNLOCK, val_slcr__SLCR_UNLOCK); +set_reset_data( slcr__SLCR_LOCKSTA, val_slcr__SLCR_LOCKSTA); +set_reset_data( slcr__ARM_PLL_CTRL, val_slcr__ARM_PLL_CTRL); +set_reset_data( slcr__DDR_PLL_CTRL, val_slcr__DDR_PLL_CTRL); +set_reset_data( slcr__IO_PLL_CTRL, val_slcr__IO_PLL_CTRL); +set_reset_data( slcr__PLL_STATUS, val_slcr__PLL_STATUS); +set_reset_data( slcr__ARM_PLL_CFG, val_slcr__ARM_PLL_CFG); +set_reset_data( slcr__DDR_PLL_CFG, val_slcr__DDR_PLL_CFG); +set_reset_data( slcr__IO_PLL_CFG, val_slcr__IO_PLL_CFG); +set_reset_data( slcr__PLL_BG_CTRL, val_slcr__PLL_BG_CTRL); +set_reset_data( slcr__ARM_CLK_CTRL, val_slcr__ARM_CLK_CTRL); +set_reset_data( slcr__DDR_CLK_CTRL, val_slcr__DDR_CLK_CTRL); +set_reset_data( slcr__DCI_CLK_CTRL, val_slcr__DCI_CLK_CTRL); +set_reset_data( slcr__APER_CLK_CTRL, val_slcr__APER_CLK_CTRL); +set_reset_data( slcr__USB0_CLK_CTRL, val_slcr__USB0_CLK_CTRL); +set_reset_data( slcr__USB1_CLK_CTRL, val_slcr__USB1_CLK_CTRL); +set_reset_data( slcr__GEM0_RCLK_CTRL, val_slcr__GEM0_RCLK_CTRL); +set_reset_data( slcr__GEM1_RCLK_CTRL, val_slcr__GEM1_RCLK_CTRL); +set_reset_data( slcr__GEM0_CLK_CTRL, val_slcr__GEM0_CLK_CTRL); +set_reset_data( slcr__GEM1_CLK_CTRL, val_slcr__GEM1_CLK_CTRL); +set_reset_data( slcr__SMC_CLK_CTRL, val_slcr__SMC_CLK_CTRL); +set_reset_data( slcr__LQSPI_CLK_CTRL, val_slcr__LQSPI_CLK_CTRL); +set_reset_data( slcr__SDIO_CLK_CTRL, val_slcr__SDIO_CLK_CTRL); +set_reset_data( slcr__UART_CLK_CTRL, val_slcr__UART_CLK_CTRL); +set_reset_data( slcr__SPI_CLK_CTRL, val_slcr__SPI_CLK_CTRL); +set_reset_data( slcr__CAN_CLK_CTRL, val_slcr__CAN_CLK_CTRL); +set_reset_data( slcr__CAN_MIOCLK_CTRL, val_slcr__CAN_MIOCLK_CTRL); +set_reset_data( slcr__DBG_CLK_CTRL, val_slcr__DBG_CLK_CTRL); +set_reset_data( slcr__PCAP_CLK_CTRL, val_slcr__PCAP_CLK_CTRL); +set_reset_data( slcr__TOPSW_CLK_CTRL, val_slcr__TOPSW_CLK_CTRL); +set_reset_data( slcr__FPGA0_CLK_CTRL, val_slcr__FPGA0_CLK_CTRL); +set_reset_data( slcr__FPGA0_THR_CTRL, val_slcr__FPGA0_THR_CTRL); +set_reset_data( slcr__FPGA0_THR_CNT, val_slcr__FPGA0_THR_CNT); +set_reset_data( slcr__FPGA0_THR_STA, val_slcr__FPGA0_THR_STA); +set_reset_data( slcr__FPGA1_CLK_CTRL, val_slcr__FPGA1_CLK_CTRL); +set_reset_data( slcr__FPGA1_THR_CTRL, val_slcr__FPGA1_THR_CTRL); +set_reset_data( slcr__FPGA1_THR_CNT, val_slcr__FPGA1_THR_CNT); +set_reset_data( slcr__FPGA1_THR_STA, val_slcr__FPGA1_THR_STA); +set_reset_data( slcr__FPGA2_CLK_CTRL, val_slcr__FPGA2_CLK_CTRL); +set_reset_data( slcr__FPGA2_THR_CTRL, val_slcr__FPGA2_THR_CTRL); +set_reset_data( slcr__FPGA2_THR_CNT, val_slcr__FPGA2_THR_CNT); +set_reset_data( slcr__FPGA2_THR_STA, val_slcr__FPGA2_THR_STA); +set_reset_data( slcr__FPGA3_CLK_CTRL, val_slcr__FPGA3_CLK_CTRL); +set_reset_data( slcr__FPGA3_THR_CTRL, val_slcr__FPGA3_THR_CTRL); +set_reset_data( slcr__FPGA3_THR_CNT, val_slcr__FPGA3_THR_CNT); +set_reset_data( slcr__FPGA3_THR_STA, val_slcr__FPGA3_THR_STA); +set_reset_data( slcr__SRST_UART_CTRL, val_slcr__SRST_UART_CTRL); +set_reset_data( slcr__BANDGAP_TRIM, val_slcr__BANDGAP_TRIM); +set_reset_data( slcr__CC_TEST, val_slcr__CC_TEST); +set_reset_data( slcr__PLL_PREDIVISOR, val_slcr__PLL_PREDIVISOR); +set_reset_data( slcr__CLK_621_TRUE, val_slcr__CLK_621_TRUE); +set_reset_data( slcr__PICTURE_DBG, val_slcr__PICTURE_DBG); +set_reset_data( slcr__PICTURE_DBG_UCNT, val_slcr__PICTURE_DBG_UCNT); +set_reset_data( slcr__PICTURE_DBG_LCNT, val_slcr__PICTURE_DBG_LCNT); +set_reset_data( slcr__PSS_RST_CTRL, val_slcr__PSS_RST_CTRL); +set_reset_data( slcr__DDR_RST_CTRL, val_slcr__DDR_RST_CTRL); +set_reset_data( slcr__TOPSW_RST_CTRL, val_slcr__TOPSW_RST_CTRL); +set_reset_data( slcr__DMAC_RST_CTRL, val_slcr__DMAC_RST_CTRL); +set_reset_data( slcr__USB_RST_CTRL, val_slcr__USB_RST_CTRL); +set_reset_data( slcr__GEM_RST_CTRL, val_slcr__GEM_RST_CTRL); +set_reset_data( slcr__SDIO_RST_CTRL, val_slcr__SDIO_RST_CTRL); +set_reset_data( slcr__SPI_RST_CTRL, val_slcr__SPI_RST_CTRL); +set_reset_data( slcr__CAN_RST_CTRL, val_slcr__CAN_RST_CTRL); +set_reset_data( slcr__I2C_RST_CTRL, val_slcr__I2C_RST_CTRL); +set_reset_data( slcr__UART_RST_CTRL, val_slcr__UART_RST_CTRL); +set_reset_data( slcr__GPIO_RST_CTRL, val_slcr__GPIO_RST_CTRL); +set_reset_data( slcr__LQSPI_RST_CTRL, val_slcr__LQSPI_RST_CTRL); +set_reset_data( slcr__SMC_RST_CTRL, val_slcr__SMC_RST_CTRL); +set_reset_data( slcr__OCM_RST_CTRL, val_slcr__OCM_RST_CTRL); +set_reset_data( slcr__DEVCI_RST_CTRL, val_slcr__DEVCI_RST_CTRL); +set_reset_data( slcr__FPGA_RST_CTRL, val_slcr__FPGA_RST_CTRL); +set_reset_data( slcr__A9_CPU_RST_CTRL, val_slcr__A9_CPU_RST_CTRL); +set_reset_data( slcr__RS_AWDT_CTRL, val_slcr__RS_AWDT_CTRL); +set_reset_data( slcr__RST_REASON, val_slcr__RST_REASON); +set_reset_data( slcr__RST_REASON_CLR, val_slcr__RST_REASON_CLR); +set_reset_data( slcr__REBOOT_STATUS, val_slcr__REBOOT_STATUS); +set_reset_data( slcr__BOOT_MODE, val_slcr__BOOT_MODE); +set_reset_data( slcr__APU_CTRL, val_slcr__APU_CTRL); +set_reset_data( slcr__WDT_CLK_SEL, val_slcr__WDT_CLK_SEL); +set_reset_data( slcr__TZ_OCM_RAM0, val_slcr__TZ_OCM_RAM0); +set_reset_data( slcr__TZ_OCM_RAM1, val_slcr__TZ_OCM_RAM1); +set_reset_data( slcr__TZ_OCM_ROM, val_slcr__TZ_OCM_ROM); +set_reset_data( slcr__TZ_DDR_RAM, val_slcr__TZ_DDR_RAM); +set_reset_data( slcr__TZ_DMA_NS, val_slcr__TZ_DMA_NS); +set_reset_data( slcr__TZ_DMA_IRQ_NS, val_slcr__TZ_DMA_IRQ_NS); +set_reset_data( slcr__TZ_DMA_PERIPH_NS, val_slcr__TZ_DMA_PERIPH_NS); +set_reset_data( slcr__TZ_GEM, val_slcr__TZ_GEM); +set_reset_data( slcr__TZ_SDIO, val_slcr__TZ_SDIO); +set_reset_data( slcr__TZ_USB, val_slcr__TZ_USB); +set_reset_data( slcr__TZ_FPGA_M, val_slcr__TZ_FPGA_M); +set_reset_data( slcr__TZ_FPGA_AFI, val_slcr__TZ_FPGA_AFI); +set_reset_data( slcr__DBG_CTRL, val_slcr__DBG_CTRL); +set_reset_data( slcr__PSS_IDCODE, val_slcr__PSS_IDCODE); +set_reset_data( slcr__DDR_URGENT, val_slcr__DDR_URGENT); +set_reset_data( slcr__DDR_CAL_START, val_slcr__DDR_CAL_START); +set_reset_data( slcr__DDR_REF_START, val_slcr__DDR_REF_START); +set_reset_data( slcr__DDR_CMD_STA, val_slcr__DDR_CMD_STA); +set_reset_data( slcr__DDR_URGENT_SEL, val_slcr__DDR_URGENT_SEL); +set_reset_data( slcr__DDR_DFI_STATUS, val_slcr__DDR_DFI_STATUS); +set_reset_data( slcr__MIO_PIN_00, val_slcr__MIO_PIN_00); +set_reset_data( slcr__MIO_PIN_01, val_slcr__MIO_PIN_01); +set_reset_data( slcr__MIO_PIN_02, val_slcr__MIO_PIN_02); +set_reset_data( slcr__MIO_PIN_03, val_slcr__MIO_PIN_03); +set_reset_data( slcr__MIO_PIN_04, val_slcr__MIO_PIN_04); +set_reset_data( slcr__MIO_PIN_05, val_slcr__MIO_PIN_05); +set_reset_data( slcr__MIO_PIN_06, val_slcr__MIO_PIN_06); +set_reset_data( slcr__MIO_PIN_07, val_slcr__MIO_PIN_07); +set_reset_data( slcr__MIO_PIN_08, val_slcr__MIO_PIN_08); +set_reset_data( slcr__MIO_PIN_09, val_slcr__MIO_PIN_09); +set_reset_data( slcr__MIO_PIN_10, val_slcr__MIO_PIN_10); +set_reset_data( slcr__MIO_PIN_11, val_slcr__MIO_PIN_11); +set_reset_data( slcr__MIO_PIN_12, val_slcr__MIO_PIN_12); +set_reset_data( slcr__MIO_PIN_13, val_slcr__MIO_PIN_13); +set_reset_data( slcr__MIO_PIN_14, val_slcr__MIO_PIN_14); +set_reset_data( slcr__MIO_PIN_15, val_slcr__MIO_PIN_15); +set_reset_data( slcr__MIO_PIN_16, val_slcr__MIO_PIN_16); +set_reset_data( slcr__MIO_PIN_17, val_slcr__MIO_PIN_17); +set_reset_data( slcr__MIO_PIN_18, val_slcr__MIO_PIN_18); +set_reset_data( slcr__MIO_PIN_19, val_slcr__MIO_PIN_19); +set_reset_data( slcr__MIO_PIN_20, val_slcr__MIO_PIN_20); +set_reset_data( slcr__MIO_PIN_21, val_slcr__MIO_PIN_21); +set_reset_data( slcr__MIO_PIN_22, val_slcr__MIO_PIN_22); +set_reset_data( slcr__MIO_PIN_23, val_slcr__MIO_PIN_23); +set_reset_data( slcr__MIO_PIN_24, val_slcr__MIO_PIN_24); +set_reset_data( slcr__MIO_PIN_25, val_slcr__MIO_PIN_25); +set_reset_data( slcr__MIO_PIN_26, val_slcr__MIO_PIN_26); +set_reset_data( slcr__MIO_PIN_27, val_slcr__MIO_PIN_27); +set_reset_data( slcr__MIO_PIN_28, val_slcr__MIO_PIN_28); +set_reset_data( slcr__MIO_PIN_29, val_slcr__MIO_PIN_29); +set_reset_data( slcr__MIO_PIN_30, val_slcr__MIO_PIN_30); +set_reset_data( slcr__MIO_PIN_31, val_slcr__MIO_PIN_31); +set_reset_data( slcr__MIO_PIN_32, val_slcr__MIO_PIN_32); +set_reset_data( slcr__MIO_PIN_33, val_slcr__MIO_PIN_33); +set_reset_data( slcr__MIO_PIN_34, val_slcr__MIO_PIN_34); +set_reset_data( slcr__MIO_PIN_35, val_slcr__MIO_PIN_35); +set_reset_data( slcr__MIO_PIN_36, val_slcr__MIO_PIN_36); +set_reset_data( slcr__MIO_PIN_37, val_slcr__MIO_PIN_37); +set_reset_data( slcr__MIO_PIN_38, val_slcr__MIO_PIN_38); +set_reset_data( slcr__MIO_PIN_39, val_slcr__MIO_PIN_39); +set_reset_data( slcr__MIO_PIN_40, val_slcr__MIO_PIN_40); +set_reset_data( slcr__MIO_PIN_41, val_slcr__MIO_PIN_41); +set_reset_data( slcr__MIO_PIN_42, val_slcr__MIO_PIN_42); +set_reset_data( slcr__MIO_PIN_43, val_slcr__MIO_PIN_43); +set_reset_data( slcr__MIO_PIN_44, val_slcr__MIO_PIN_44); +set_reset_data( slcr__MIO_PIN_45, val_slcr__MIO_PIN_45); +set_reset_data( slcr__MIO_PIN_46, val_slcr__MIO_PIN_46); +set_reset_data( slcr__MIO_PIN_47, val_slcr__MIO_PIN_47); +set_reset_data( slcr__MIO_PIN_48, val_slcr__MIO_PIN_48); +set_reset_data( slcr__MIO_PIN_49, val_slcr__MIO_PIN_49); +set_reset_data( slcr__MIO_PIN_50, val_slcr__MIO_PIN_50); +set_reset_data( slcr__MIO_PIN_51, val_slcr__MIO_PIN_51); +set_reset_data( slcr__MIO_PIN_52, val_slcr__MIO_PIN_52); +set_reset_data( slcr__MIO_PIN_53, val_slcr__MIO_PIN_53); +set_reset_data( slcr__MIO_FMIO_GEM_SEL, val_slcr__MIO_FMIO_GEM_SEL); +set_reset_data( slcr__MIO_LOOPBACK, val_slcr__MIO_LOOPBACK); +set_reset_data( slcr__MIO_MST_TRI0, val_slcr__MIO_MST_TRI0); +set_reset_data( slcr__MIO_MST_TRI1, val_slcr__MIO_MST_TRI1); +set_reset_data( slcr__SD0_WP_CD_SEL, val_slcr__SD0_WP_CD_SEL); +set_reset_data( slcr__SD1_WP_CD_SEL, val_slcr__SD1_WP_CD_SEL); +set_reset_data( slcr__LVL_SHFTR_EN, val_slcr__LVL_SHFTR_EN); +set_reset_data( slcr__OCM_CFG, val_slcr__OCM_CFG); +set_reset_data( slcr__CPU0_RAM0, val_slcr__CPU0_RAM0); +set_reset_data( slcr__CPU0_RAM1, val_slcr__CPU0_RAM1); +set_reset_data( slcr__CPU0_RAM2, val_slcr__CPU0_RAM2); +set_reset_data( slcr__CPU1_RAM0, val_slcr__CPU1_RAM0); +set_reset_data( slcr__CPU1_RAM1, val_slcr__CPU1_RAM1); +set_reset_data( slcr__CPU1_RAM2, val_slcr__CPU1_RAM2); +set_reset_data( slcr__SCU_RAM, val_slcr__SCU_RAM); +set_reset_data( slcr__L2C_RAM, val_slcr__L2C_RAM); +set_reset_data( slcr__IOU_RAM_GEM01, val_slcr__IOU_RAM_GEM01); +set_reset_data( slcr__IOU_RAM_USB01, val_slcr__IOU_RAM_USB01); +set_reset_data( slcr__IOU_RAM_SDIO0, val_slcr__IOU_RAM_SDIO0); +set_reset_data( slcr__IOU_RAM_SDIO1, val_slcr__IOU_RAM_SDIO1); +set_reset_data( slcr__IOU_RAM_CAN0, val_slcr__IOU_RAM_CAN0); +set_reset_data( slcr__IOU_RAM_CAN1, val_slcr__IOU_RAM_CAN1); +set_reset_data( slcr__IOU_RAM_LQSPI, val_slcr__IOU_RAM_LQSPI); +set_reset_data( slcr__DMAC_RAM, val_slcr__DMAC_RAM); +set_reset_data( slcr__AFI0_RAM0, val_slcr__AFI0_RAM0); +set_reset_data( slcr__AFI0_RAM1, val_slcr__AFI0_RAM1); +set_reset_data( slcr__AFI0_RAM2, val_slcr__AFI0_RAM2); +set_reset_data( slcr__AFI1_RAM0, val_slcr__AFI1_RAM0); +set_reset_data( slcr__AFI1_RAM1, val_slcr__AFI1_RAM1); +set_reset_data( slcr__AFI1_RAM2, val_slcr__AFI1_RAM2); +set_reset_data( slcr__AFI2_RAM0, val_slcr__AFI2_RAM0); +set_reset_data( slcr__AFI2_RAM1, val_slcr__AFI2_RAM1); +set_reset_data( slcr__AFI2_RAM2, val_slcr__AFI2_RAM2); +set_reset_data( slcr__AFI3_RAM0, val_slcr__AFI3_RAM0); +set_reset_data( slcr__AFI3_RAM1, val_slcr__AFI3_RAM1); +set_reset_data( slcr__AFI3_RAM2, val_slcr__AFI3_RAM2); +set_reset_data( slcr__OCM_RAM, val_slcr__OCM_RAM); +set_reset_data( slcr__OCM_ROM0, val_slcr__OCM_ROM0); +set_reset_data( slcr__OCM_ROM1, val_slcr__OCM_ROM1); +set_reset_data( slcr__DEVCI_RAM, val_slcr__DEVCI_RAM); +set_reset_data( slcr__CSG_RAM, val_slcr__CSG_RAM); +set_reset_data( slcr__GPIOB_CTRL, val_slcr__GPIOB_CTRL); +set_reset_data( slcr__GPIOB_CFG_CMOS18, val_slcr__GPIOB_CFG_CMOS18); +set_reset_data( slcr__GPIOB_CFG_CMOS25, val_slcr__GPIOB_CFG_CMOS25); +set_reset_data( slcr__GPIOB_CFG_CMOS33, val_slcr__GPIOB_CFG_CMOS33); +set_reset_data( slcr__GPIOB_CFG_LVTTL, val_slcr__GPIOB_CFG_LVTTL); +set_reset_data( slcr__GPIOB_CFG_HSTL, val_slcr__GPIOB_CFG_HSTL); +set_reset_data( slcr__GPIOB_DRVR_BIAS_CTRL, val_slcr__GPIOB_DRVR_BIAS_CTRL); +set_reset_data( slcr__DDRIOB_ADDR0, val_slcr__DDRIOB_ADDR0); +set_reset_data( slcr__DDRIOB_ADDR1, val_slcr__DDRIOB_ADDR1); +set_reset_data( slcr__DDRIOB_DATA0, val_slcr__DDRIOB_DATA0); +set_reset_data( slcr__DDRIOB_DATA1, val_slcr__DDRIOB_DATA1); +set_reset_data( slcr__DDRIOB_DIFF0, val_slcr__DDRIOB_DIFF0); +set_reset_data( slcr__DDRIOB_DIFF1, val_slcr__DDRIOB_DIFF1); +set_reset_data( slcr__DDRIOB_CLOCK, val_slcr__DDRIOB_CLOCK); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_ADDR, val_slcr__DDRIOB_DRIVE_SLEW_ADDR); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DATA, val_slcr__DDRIOB_DRIVE_SLEW_DATA); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DIFF, val_slcr__DDRIOB_DRIVE_SLEW_DIFF); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_CLOCK, val_slcr__DDRIOB_DRIVE_SLEW_CLOCK); +set_reset_data( slcr__DDRIOB_DDR_CTRL, val_slcr__DDRIOB_DDR_CTRL); +set_reset_data( slcr__DDRIOB_DCI_CTRL, val_slcr__DDRIOB_DCI_CTRL); +set_reset_data( slcr__DDRIOB_DCI_STATUS, val_slcr__DDRIOB_DCI_STATUS); + +// ************************************************************ +// Module smcc pl353 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( smcc__memc_status, val_smcc__memc_status); +set_reset_data( smcc__memif_cfg, val_smcc__memif_cfg); +set_reset_data( smcc__memc_cfg_set, val_smcc__memc_cfg_set); +set_reset_data( smcc__memc_cfg_clr, val_smcc__memc_cfg_clr); +set_reset_data( smcc__direct_cmd, val_smcc__direct_cmd); +set_reset_data( smcc__set_cycles, val_smcc__set_cycles); +set_reset_data( smcc__set_opmode, val_smcc__set_opmode); +set_reset_data( smcc__refresh_period_0, val_smcc__refresh_period_0); +set_reset_data( smcc__refresh_period_1, val_smcc__refresh_period_1); +set_reset_data( smcc__sram_cycles0_0, val_smcc__sram_cycles0_0); +set_reset_data( smcc__opmode0_0, val_smcc__opmode0_0); +set_reset_data( smcc__sram_cycles0_1, val_smcc__sram_cycles0_1); +set_reset_data( smcc__opmode0_1, val_smcc__opmode0_1); +set_reset_data( smcc__nand_cycles1_0, val_smcc__nand_cycles1_0); +set_reset_data( smcc__opmode1_0, val_smcc__opmode1_0); +set_reset_data( smcc__user_status, val_smcc__user_status); +set_reset_data( smcc__user_config, val_smcc__user_config); +set_reset_data( smcc__ecc_status_0, val_smcc__ecc_status_0); +set_reset_data( smcc__ecc_memcfg_0, val_smcc__ecc_memcfg_0); +set_reset_data( smcc__ecc_memcommand1_0, val_smcc__ecc_memcommand1_0); +set_reset_data( smcc__ecc_memcommand2_0, val_smcc__ecc_memcommand2_0); +set_reset_data( smcc__ecc_addr0_0, val_smcc__ecc_addr0_0); +set_reset_data( smcc__ecc_addr1_0, val_smcc__ecc_addr1_0); +set_reset_data( smcc__ecc_value0_0, val_smcc__ecc_value0_0); +set_reset_data( smcc__ecc_value1_0, val_smcc__ecc_value1_0); +set_reset_data( smcc__ecc_value2_0, val_smcc__ecc_value2_0); +set_reset_data( smcc__ecc_value3_0, val_smcc__ecc_value3_0); +set_reset_data( smcc__ecc_status_1, val_smcc__ecc_status_1); +set_reset_data( smcc__ecc_memcfg_1, val_smcc__ecc_memcfg_1); +set_reset_data( smcc__ecc_memcommand1_1, val_smcc__ecc_memcommand1_1); +set_reset_data( smcc__ecc_memcommand2_1, val_smcc__ecc_memcommand2_1); +set_reset_data( smcc__ecc_addr0_1, val_smcc__ecc_addr0_1); +set_reset_data( smcc__ecc_addr1_1, val_smcc__ecc_addr1_1); +set_reset_data( smcc__ecc_value0_1, val_smcc__ecc_value0_1); +set_reset_data( smcc__ecc_value1_1, val_smcc__ecc_value1_1); +set_reset_data( smcc__ecc_value2_1, val_smcc__ecc_value2_1); +set_reset_data( smcc__ecc_value3_1, val_smcc__ecc_value3_1); +set_reset_data( smcc__integration_test, val_smcc__integration_test); +set_reset_data( smcc__periph_id_0, val_smcc__periph_id_0); +set_reset_data( smcc__periph_id_1, val_smcc__periph_id_1); +set_reset_data( smcc__periph_id_2, val_smcc__periph_id_2); +set_reset_data( smcc__periph_id_3, val_smcc__periph_id_3); +set_reset_data( smcc__pcell_id_0, val_smcc__pcell_id_0); +set_reset_data( smcc__pcell_id_1, val_smcc__pcell_id_1); +set_reset_data( smcc__pcell_id_2, val_smcc__pcell_id_2); +set_reset_data( smcc__pcell_id_3, val_smcc__pcell_id_3); + +// ************************************************************ +// Module spi0 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( spi0__Config_reg0, val_spi0__Config_reg0); +set_reset_data( spi0__Intr_status_reg0, val_spi0__Intr_status_reg0); +set_reset_data( spi0__Intrpt_en_reg0, val_spi0__Intrpt_en_reg0); +set_reset_data( spi0__Intrpt_dis_reg0, val_spi0__Intrpt_dis_reg0); +set_reset_data( spi0__Intrpt_mask_reg0, val_spi0__Intrpt_mask_reg0); +set_reset_data( spi0__En_reg0, val_spi0__En_reg0); +set_reset_data( spi0__Delay_reg0, val_spi0__Delay_reg0); +set_reset_data( spi0__Tx_data_reg0, val_spi0__Tx_data_reg0); +set_reset_data( spi0__Rx_data_reg0, val_spi0__Rx_data_reg0); +set_reset_data( spi0__Slave_Idle_count_reg0, val_spi0__Slave_Idle_count_reg0); +set_reset_data( spi0__TX_thres_reg0, val_spi0__TX_thres_reg0); +set_reset_data( spi0__RX_thres_reg0, val_spi0__RX_thres_reg0); +set_reset_data( spi0__Mod_id_reg0, val_spi0__Mod_id_reg0); + +// ************************************************************ +// Module spi1 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( spi1__Config_reg0, val_spi1__Config_reg0); +set_reset_data( spi1__Intr_status_reg0, val_spi1__Intr_status_reg0); +set_reset_data( spi1__Intrpt_en_reg0, val_spi1__Intrpt_en_reg0); +set_reset_data( spi1__Intrpt_dis_reg0, val_spi1__Intrpt_dis_reg0); +set_reset_data( spi1__Intrpt_mask_reg0, val_spi1__Intrpt_mask_reg0); +set_reset_data( spi1__En_reg0, val_spi1__En_reg0); +set_reset_data( spi1__Delay_reg0, val_spi1__Delay_reg0); +set_reset_data( spi1__Tx_data_reg0, val_spi1__Tx_data_reg0); +set_reset_data( spi1__Rx_data_reg0, val_spi1__Rx_data_reg0); +set_reset_data( spi1__Slave_Idle_count_reg0, val_spi1__Slave_Idle_count_reg0); +set_reset_data( spi1__TX_thres_reg0, val_spi1__TX_thres_reg0); +set_reset_data( spi1__RX_thres_reg0, val_spi1__RX_thres_reg0); +set_reset_data( spi1__Mod_id_reg0, val_spi1__Mod_id_reg0); + +// ************************************************************ +// Module swdt swdt +// doc version: 2.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( swdt__MODE, val_swdt__MODE); +set_reset_data( swdt__CONTROL, val_swdt__CONTROL); +set_reset_data( swdt__RESTART, val_swdt__RESTART); +set_reset_data( swdt__STATUS, val_swdt__STATUS); + +// ************************************************************ +// Module ttc0 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ttc0__Clock_Control_1, val_ttc0__Clock_Control_1); +set_reset_data( ttc0__Clock_Control_2, val_ttc0__Clock_Control_2); +set_reset_data( ttc0__Clock_Control_3, val_ttc0__Clock_Control_3); +set_reset_data( ttc0__Counter_Control_1, val_ttc0__Counter_Control_1); +set_reset_data( ttc0__Counter_Control_2, val_ttc0__Counter_Control_2); +set_reset_data( ttc0__Counter_Control_3, val_ttc0__Counter_Control_3); +set_reset_data( ttc0__Counter_Value_1, val_ttc0__Counter_Value_1); +set_reset_data( ttc0__Counter_Value_2, val_ttc0__Counter_Value_2); +set_reset_data( ttc0__Counter_Value_3, val_ttc0__Counter_Value_3); +set_reset_data( ttc0__Interval_Counter_1, val_ttc0__Interval_Counter_1); +set_reset_data( ttc0__Interval_Counter_2, val_ttc0__Interval_Counter_2); +set_reset_data( ttc0__Interval_Counter_3, val_ttc0__Interval_Counter_3); +set_reset_data( ttc0__Match_1_Counter_1, val_ttc0__Match_1_Counter_1); +set_reset_data( ttc0__Match_1_Counter_2, val_ttc0__Match_1_Counter_2); +set_reset_data( ttc0__Match_1_Counter_3, val_ttc0__Match_1_Counter_3); +set_reset_data( ttc0__Match_2_Counter_1, val_ttc0__Match_2_Counter_1); +set_reset_data( ttc0__Match_2_Counter_2, val_ttc0__Match_2_Counter_2); +set_reset_data( ttc0__Match_2_Counter_3, val_ttc0__Match_2_Counter_3); +set_reset_data( ttc0__Match_3_Counter_1, val_ttc0__Match_3_Counter_1); +set_reset_data( ttc0__Match_3_Counter_2, val_ttc0__Match_3_Counter_2); +set_reset_data( ttc0__Match_3_Counter_3, val_ttc0__Match_3_Counter_3); +set_reset_data( ttc0__Interrupt_Register_1, val_ttc0__Interrupt_Register_1); +set_reset_data( ttc0__Interrupt_Register_2, val_ttc0__Interrupt_Register_2); +set_reset_data( ttc0__Interrupt_Register_3, val_ttc0__Interrupt_Register_3); +set_reset_data( ttc0__Interrupt_Enable_1, val_ttc0__Interrupt_Enable_1); +set_reset_data( ttc0__Interrupt_Enable_2, val_ttc0__Interrupt_Enable_2); +set_reset_data( ttc0__Interrupt_Enable_3, val_ttc0__Interrupt_Enable_3); +set_reset_data( ttc0__Event_Control_Timer_1, val_ttc0__Event_Control_Timer_1); +set_reset_data( ttc0__Event_Control_Timer_2, val_ttc0__Event_Control_Timer_2); +set_reset_data( ttc0__Event_Control_Timer_3, val_ttc0__Event_Control_Timer_3); +set_reset_data( ttc0__Event_Register_1, val_ttc0__Event_Register_1); +set_reset_data( ttc0__Event_Register_2, val_ttc0__Event_Register_2); +set_reset_data( ttc0__Event_Register_3, val_ttc0__Event_Register_3); + +// ************************************************************ +// Module ttc1 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ttc1__Clock_Control_1, val_ttc1__Clock_Control_1); +set_reset_data( ttc1__Clock_Control_2, val_ttc1__Clock_Control_2); +set_reset_data( ttc1__Clock_Control_3, val_ttc1__Clock_Control_3); +set_reset_data( ttc1__Counter_Control_1, val_ttc1__Counter_Control_1); +set_reset_data( ttc1__Counter_Control_2, val_ttc1__Counter_Control_2); +set_reset_data( ttc1__Counter_Control_3, val_ttc1__Counter_Control_3); +set_reset_data( ttc1__Counter_Value_1, val_ttc1__Counter_Value_1); +set_reset_data( ttc1__Counter_Value_2, val_ttc1__Counter_Value_2); +set_reset_data( ttc1__Counter_Value_3, val_ttc1__Counter_Value_3); +set_reset_data( ttc1__Interval_Counter_1, val_ttc1__Interval_Counter_1); +set_reset_data( ttc1__Interval_Counter_2, val_ttc1__Interval_Counter_2); +set_reset_data( ttc1__Interval_Counter_3, val_ttc1__Interval_Counter_3); +set_reset_data( ttc1__Match_1_Counter_1, val_ttc1__Match_1_Counter_1); +set_reset_data( ttc1__Match_1_Counter_2, val_ttc1__Match_1_Counter_2); +set_reset_data( ttc1__Match_1_Counter_3, val_ttc1__Match_1_Counter_3); +set_reset_data( ttc1__Match_2_Counter_1, val_ttc1__Match_2_Counter_1); +set_reset_data( ttc1__Match_2_Counter_2, val_ttc1__Match_2_Counter_2); +set_reset_data( ttc1__Match_2_Counter_3, val_ttc1__Match_2_Counter_3); +set_reset_data( ttc1__Match_3_Counter_1, val_ttc1__Match_3_Counter_1); +set_reset_data( ttc1__Match_3_Counter_2, val_ttc1__Match_3_Counter_2); +set_reset_data( ttc1__Match_3_Counter_3, val_ttc1__Match_3_Counter_3); +set_reset_data( ttc1__Interrupt_Register_1, val_ttc1__Interrupt_Register_1); +set_reset_data( ttc1__Interrupt_Register_2, val_ttc1__Interrupt_Register_2); +set_reset_data( ttc1__Interrupt_Register_3, val_ttc1__Interrupt_Register_3); +set_reset_data( ttc1__Interrupt_Enable_1, val_ttc1__Interrupt_Enable_1); +set_reset_data( ttc1__Interrupt_Enable_2, val_ttc1__Interrupt_Enable_2); +set_reset_data( ttc1__Interrupt_Enable_3, val_ttc1__Interrupt_Enable_3); +set_reset_data( ttc1__Event_Control_Timer_1, val_ttc1__Event_Control_Timer_1); +set_reset_data( ttc1__Event_Control_Timer_2, val_ttc1__Event_Control_Timer_2); +set_reset_data( ttc1__Event_Control_Timer_3, val_ttc1__Event_Control_Timer_3); +set_reset_data( ttc1__Event_Register_1, val_ttc1__Event_Register_1); +set_reset_data( ttc1__Event_Register_2, val_ttc1__Event_Register_2); +set_reset_data( ttc1__Event_Register_3, val_ttc1__Event_Register_3); + +// ************************************************************ +// Module uart0 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( uart0__Control_reg0, val_uart0__Control_reg0); +set_reset_data( uart0__mode_reg0, val_uart0__mode_reg0); +set_reset_data( uart0__Intrpt_en_reg0, val_uart0__Intrpt_en_reg0); +set_reset_data( uart0__Intrpt_dis_reg0, val_uart0__Intrpt_dis_reg0); +set_reset_data( uart0__Intrpt_mask_reg0, val_uart0__Intrpt_mask_reg0); +set_reset_data( uart0__Chnl_int_sts_reg0, val_uart0__Chnl_int_sts_reg0); +set_reset_data( uart0__Baud_rate_gen_reg0, val_uart0__Baud_rate_gen_reg0); +set_reset_data( uart0__Rcvr_timeout_reg0, val_uart0__Rcvr_timeout_reg0); +set_reset_data( uart0__Rcvr_FIFO_trigger_level0, val_uart0__Rcvr_FIFO_trigger_level0); +set_reset_data( uart0__Modem_ctrl_reg0, val_uart0__Modem_ctrl_reg0); +set_reset_data( uart0__Modem_sts_reg0, val_uart0__Modem_sts_reg0); +set_reset_data( uart0__Channel_sts_reg0, val_uart0__Channel_sts_reg0); +set_reset_data( uart0__TX_RX_FIFO0, val_uart0__TX_RX_FIFO0); +set_reset_data( uart0__Baud_rate_divider_reg0, val_uart0__Baud_rate_divider_reg0); +set_reset_data( uart0__Flow_delay_reg0, val_uart0__Flow_delay_reg0); +set_reset_data( uart0__IR_min_rcv_pulse_wdth0, val_uart0__IR_min_rcv_pulse_wdth0); +set_reset_data( uart0__IR_transmitted_pulse_wdth0, val_uart0__IR_transmitted_pulse_wdth0); +set_reset_data( uart0__Tx_FIFO_trigger_level0, val_uart0__Tx_FIFO_trigger_level0); + +// ************************************************************ +// Module uart1 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( uart1__Control_reg0, val_uart1__Control_reg0); +set_reset_data( uart1__mode_reg0, val_uart1__mode_reg0); +set_reset_data( uart1__Intrpt_en_reg0, val_uart1__Intrpt_en_reg0); +set_reset_data( uart1__Intrpt_dis_reg0, val_uart1__Intrpt_dis_reg0); +set_reset_data( uart1__Intrpt_mask_reg0, val_uart1__Intrpt_mask_reg0); +set_reset_data( uart1__Chnl_int_sts_reg0, val_uart1__Chnl_int_sts_reg0); +set_reset_data( uart1__Baud_rate_gen_reg0, val_uart1__Baud_rate_gen_reg0); +set_reset_data( uart1__Rcvr_timeout_reg0, val_uart1__Rcvr_timeout_reg0); +set_reset_data( uart1__Rcvr_FIFO_trigger_level0, val_uart1__Rcvr_FIFO_trigger_level0); +set_reset_data( uart1__Modem_ctrl_reg0, val_uart1__Modem_ctrl_reg0); +set_reset_data( uart1__Modem_sts_reg0, val_uart1__Modem_sts_reg0); +set_reset_data( uart1__Channel_sts_reg0, val_uart1__Channel_sts_reg0); +set_reset_data( uart1__TX_RX_FIFO0, val_uart1__TX_RX_FIFO0); +set_reset_data( uart1__Baud_rate_divider_reg0, val_uart1__Baud_rate_divider_reg0); +set_reset_data( uart1__Flow_delay_reg0, val_uart1__Flow_delay_reg0); +set_reset_data( uart1__IR_min_rcv_pulse_wdth0, val_uart1__IR_min_rcv_pulse_wdth0); +set_reset_data( uart1__IR_transmitted_pulse_wdth0, val_uart1__IR_transmitted_pulse_wdth0); +set_reset_data( uart1__Tx_FIFO_trigger_level0, val_uart1__Tx_FIFO_trigger_level0); + +// ************************************************************ +// Module usb0 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( usb0__ID, val_usb0__ID); +set_reset_data( usb0__HWGENERAL, val_usb0__HWGENERAL); +set_reset_data( usb0__HWHOST, val_usb0__HWHOST); +set_reset_data( usb0__HWDEVICE, val_usb0__HWDEVICE); +set_reset_data( usb0__HWTXBUF, val_usb0__HWTXBUF); +set_reset_data( usb0__HWRXBUF, val_usb0__HWRXBUF); +set_reset_data( usb0__GPTIMER0LD, val_usb0__GPTIMER0LD); +set_reset_data( usb0__GPTIMER0CTRL, val_usb0__GPTIMER0CTRL); +set_reset_data( usb0__GPTIMER1LD, val_usb0__GPTIMER1LD); +set_reset_data( usb0__GPTIMER1CTRL, val_usb0__GPTIMER1CTRL); +set_reset_data( usb0__SBUSCFG, val_usb0__SBUSCFG); +set_reset_data( usb0__CAPLENGTH_HCIVERSION, val_usb0__CAPLENGTH_HCIVERSION); +set_reset_data( usb0__HCSPARAMS, val_usb0__HCSPARAMS); +set_reset_data( usb0__HCCPARAMS, val_usb0__HCCPARAMS); +set_reset_data( usb0__DCIVERSION, val_usb0__DCIVERSION); +set_reset_data( usb0__DCCPARAMS, val_usb0__DCCPARAMS); +set_reset_data( usb0__USBCMD, val_usb0__USBCMD); +set_reset_data( usb0__USBSTS, val_usb0__USBSTS); +set_reset_data( usb0__USBINTR, val_usb0__USBINTR); +set_reset_data( usb0__FRINDEX, val_usb0__FRINDEX); +set_reset_data( usb0__PERIODICLISTBASE_DEVICEADDR, val_usb0__PERIODICLISTBASE_DEVICEADDR); +set_reset_data( usb0__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR); +set_reset_data( usb0__TTCTRL, val_usb0__TTCTRL); +set_reset_data( usb0__BURSTSIZE, val_usb0__BURSTSIZE); +set_reset_data( usb0__TXFILLTUNING, val_usb0__TXFILLTUNING); +set_reset_data( usb0__TXTTFILLTUNING, val_usb0__TXTTFILLTUNING); +set_reset_data( usb0__IC_USB, val_usb0__IC_USB); +set_reset_data( usb0__ULPI_VIEWPORT, val_usb0__ULPI_VIEWPORT); +set_reset_data( usb0__ENDPTNAK, val_usb0__ENDPTNAK); +set_reset_data( usb0__ENDPTNAKEN, val_usb0__ENDPTNAKEN); +set_reset_data( usb0__CONFIGFLAG, val_usb0__CONFIGFLAG); +set_reset_data( usb0__PORTSC1, val_usb0__PORTSC1); +set_reset_data( usb0__OTGSC, val_usb0__OTGSC); +set_reset_data( usb0__USBMODE, val_usb0__USBMODE); +set_reset_data( usb0__ENDPTSETUPSTAT, val_usb0__ENDPTSETUPSTAT); +set_reset_data( usb0__ENDPTPRIME, val_usb0__ENDPTPRIME); +set_reset_data( usb0__ENDPTFLUSH, val_usb0__ENDPTFLUSH); +set_reset_data( usb0__ENDPTSTAT, val_usb0__ENDPTSTAT); +set_reset_data( usb0__ENDPTCOMPLETE, val_usb0__ENDPTCOMPLETE); +set_reset_data( usb0__ENDPTCTRL0, val_usb0__ENDPTCTRL0); +set_reset_data( usb0__ENDPTCTRL1, val_usb0__ENDPTCTRL1); +set_reset_data( usb0__ENDPTCTRL2, val_usb0__ENDPTCTRL2); +set_reset_data( usb0__ENDPTCTRL3, val_usb0__ENDPTCTRL3); +set_reset_data( usb0__ENDPTCTRL4, val_usb0__ENDPTCTRL4); +set_reset_data( usb0__ENDPTCTRL5, val_usb0__ENDPTCTRL5); +set_reset_data( usb0__ENDPTCTRL6, val_usb0__ENDPTCTRL6); +set_reset_data( usb0__ENDPTCTRL7, val_usb0__ENDPTCTRL7); +set_reset_data( usb0__ENDPTCTRL8, val_usb0__ENDPTCTRL8); +set_reset_data( usb0__ENDPTCTRL9, val_usb0__ENDPTCTRL9); +set_reset_data( usb0__ENDPTCTRL10, val_usb0__ENDPTCTRL10); +set_reset_data( usb0__ENDPTCTRL11, val_usb0__ENDPTCTRL11); +set_reset_data( usb0__ENDPTCTRL12, val_usb0__ENDPTCTRL12); + +// ************************************************************ +// Module usb1 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( usb1__ID, val_usb1__ID); +set_reset_data( usb1__HWGENERAL, val_usb1__HWGENERAL); +set_reset_data( usb1__HWHOST, val_usb1__HWHOST); +set_reset_data( usb1__HWDEVICE, val_usb1__HWDEVICE); +set_reset_data( usb1__HWTXBUF, val_usb1__HWTXBUF); +set_reset_data( usb1__HWRXBUF, val_usb1__HWRXBUF); +set_reset_data( usb1__GPTIMER0LD, val_usb1__GPTIMER0LD); +set_reset_data( usb1__GPTIMER0CTRL, val_usb1__GPTIMER0CTRL); +set_reset_data( usb1__GPTIMER1LD, val_usb1__GPTIMER1LD); +set_reset_data( usb1__GPTIMER1CTRL, val_usb1__GPTIMER1CTRL); +set_reset_data( usb1__SBUSCFG, val_usb1__SBUSCFG); +set_reset_data( usb1__CAPLENGTH_HCIVERSION, val_usb1__CAPLENGTH_HCIVERSION); +set_reset_data( usb1__HCSPARAMS, val_usb1__HCSPARAMS); +set_reset_data( usb1__HCCPARAMS, val_usb1__HCCPARAMS); +set_reset_data( usb1__DCIVERSION, val_usb1__DCIVERSION); +set_reset_data( usb1__DCCPARAMS, val_usb1__DCCPARAMS); +set_reset_data( usb1__USBCMD, val_usb1__USBCMD); +set_reset_data( usb1__USBSTS, val_usb1__USBSTS); +set_reset_data( usb1__USBINTR, val_usb1__USBINTR); +set_reset_data( usb1__FRINDEX, val_usb1__FRINDEX); +set_reset_data( usb1__PERIODICLISTBASE_DEVICEADDR, val_usb1__PERIODICLISTBASE_DEVICEADDR); +set_reset_data( usb1__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR); +set_reset_data( usb1__TTCTRL, val_usb1__TTCTRL); +set_reset_data( usb1__BURSTSIZE, val_usb1__BURSTSIZE); +set_reset_data( usb1__TXFILLTUNING, val_usb1__TXFILLTUNING); +set_reset_data( usb1__TXTTFILLTUNING, val_usb1__TXTTFILLTUNING); +set_reset_data( usb1__IC_USB, val_usb1__IC_USB); +set_reset_data( usb1__ULPI_VIEWPORT, val_usb1__ULPI_VIEWPORT); +set_reset_data( usb1__ENDPTNAK, val_usb1__ENDPTNAK); +set_reset_data( usb1__ENDPTNAKEN, val_usb1__ENDPTNAKEN); +set_reset_data( usb1__CONFIGFLAG, val_usb1__CONFIGFLAG); +set_reset_data( usb1__PORTSC1, val_usb1__PORTSC1); +set_reset_data( usb1__OTGSC, val_usb1__OTGSC); +set_reset_data( usb1__USBMODE, val_usb1__USBMODE); +set_reset_data( usb1__ENDPTSETUPSTAT, val_usb1__ENDPTSETUPSTAT); +set_reset_data( usb1__ENDPTPRIME, val_usb1__ENDPTPRIME); +set_reset_data( usb1__ENDPTFLUSH, val_usb1__ENDPTFLUSH); +set_reset_data( usb1__ENDPTSTAT, val_usb1__ENDPTSTAT); +set_reset_data( usb1__ENDPTCOMPLETE, val_usb1__ENDPTCOMPLETE); +set_reset_data( usb1__ENDPTCTRL0, val_usb1__ENDPTCTRL0); +set_reset_data( usb1__ENDPTCTRL1, val_usb1__ENDPTCTRL1); +set_reset_data( usb1__ENDPTCTRL2, val_usb1__ENDPTCTRL2); +set_reset_data( usb1__ENDPTCTRL3, val_usb1__ENDPTCTRL3); +set_reset_data( usb1__ENDPTCTRL4, val_usb1__ENDPTCTRL4); +set_reset_data( usb1__ENDPTCTRL5, val_usb1__ENDPTCTRL5); +set_reset_data( usb1__ENDPTCTRL6, val_usb1__ENDPTCTRL6); +set_reset_data( usb1__ENDPTCTRL7, val_usb1__ENDPTCTRL7); +set_reset_data( usb1__ENDPTCTRL8, val_usb1__ENDPTCTRL8); +set_reset_data( usb1__ENDPTCTRL9, val_usb1__ENDPTCTRL9); +set_reset_data( usb1__ENDPTCTRL10, val_usb1__ENDPTCTRL10); +set_reset_data( usb1__ENDPTCTRL11, val_usb1__ENDPTCTRL11); +set_reset_data( usb1__ENDPTCTRL12, val_usb1__ENDPTCTRL12); diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_map.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_map.v new file mode 100644 index 0000000..2837683 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_map.v @@ -0,0 +1,156 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_reg_map.v + * + * Date : 2012-11 + * + * Description : Controller for Register Map Memory + * + *****************************************************************************/ +/*** WA for CR # 695818 ***/ +`ifdef XILINX_SIMULATOR + `define XSIM_ISIM +`endif +`ifdef XILINX_ISIM + `define XSIM_ISIM +`endif + + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_reg_map(); + +`include "processing_system7_bfm_v2_0_local_params.v" + +/* Register definitions */ +`include "processing_system7_bfm_v2_0_reg_params.v" + +parameter mem_size = 32'h2000_0000; ///as the memory is implemented 4 byte wide +parameter xsim_mem_size = 32'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB + +`ifdef XSIM_ISIM + reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + parameter addr_offset_bits = 26; +`else + reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; // 512 MB needed for reg space + parameter addr_offset_bits = 27; +`endif + +/* preload reset_values from file */ +task automatic pre_load_rst_values; +input dummy; +begin + `include "processing_system7_bfm_v2_0_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/ +end +endtask + +/* writes the reset data into the reg memory */ +task automatic set_reset_data; +input [addr_width-1:0] address; +input [data_width-1:0] data; +reg [addr_width-1:0] addr; +begin +addr = address >> 2; +`ifdef XSIM_ISIM + case(addr[addr_width-1:addr_offset_bits]) + 14 : reg_mem0[addr[addr_offset_bits-1:0]] = data; + 15 : reg_mem1[addr[addr_offset_bits-1:0]] = data; + endcase +`else + reg_mem[addr[addr_offset_bits-1:0]] = data; +`endif +end +endtask + +/* writes the data into the reg memory */ +task automatic set_data; +input [addr_width-1:0] addr; +input [data_width-1:0] data; +begin +`ifdef XSIM_ISIM + case(addr[addr_width-1:addr_offset_bits]) + 6'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data; + 6'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data; + endcase +`else + reg_mem[addr[addr_offset_bits-1:0]] = data; +`endif +end +endtask + +/* get the read data from reg mem */ +task automatic get_data; +input [addr_width-1:0] addr; +output [data_width-1:0] data; +begin +`ifdef XSIM_ISIM + case(addr[addr_width-1:addr_offset_bits]) + 6'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]]; + 6'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]]; + endcase +`else + data = reg_mem[addr[addr_offset_bits-1:0]]; +`endif +end +endtask + +/* read chunk of registers */ +task read_reg_mem; +output[max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +integer i; +reg [addr_width-1:0] addr; +reg [data_width-1:0] temp_rd_data; +reg [max_burst_bits-1:0] temp_data; +integer bytes_left; +begin +addr = start_addr >> shft_addr_bits; +bytes_left = no_of_bytes; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); +`endif + +/* Get first data ... if unaligned address */ +get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]); + +if(no_of_bytes < mem_width ) begin + repeat(max_burst_bytes - mem_width) + temp_data = temp_data >> 8; + +end else begin + bytes_left = bytes_left - mem_width; + addr = addr+1; + /* Got first data */ + while (bytes_left > (mem_width-1) ) begin + temp_data = temp_data >> data_width; + get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); + addr = addr+1; + bytes_left = bytes_left - mem_width; + end + + /* Get last valid data in the burst*/ + get_data(addr,temp_rd_data); + while(bytes_left > 0) begin + temp_data = temp_data >> 8; + temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; + temp_rd_data = temp_rd_data >> 8; + bytes_left = bytes_left - 1; + end + /* align to the brst_byte length */ + repeat(max_burst_bytes - no_of_bytes) + temp_data = temp_data >> 8; +end +data = temp_data; +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); +`endif +end +endtask + +initial +begin + pre_load_rst_values(1); +end + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_params.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_params.v new file mode 100644 index 0000000..e06e336 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_reg_params.v @@ -0,0 +1,10519 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_reg_params.v + * + * Date : 2012-11 + * + * Description : Parameters for Register Address and Default values. + * + *****************************************************************************/ + +// Register default value info for chip pele_ps +// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012 +// 54 modules, 2532 registers. + + +// ************************************************************ +// Module afi0 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi0__AFI_RDCHAN_CTRL = 32'hF8008000; +parameter val_afi0__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi0__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi0__AFI_RDCHAN_ISSUINGCAP = 32'hF8008004; +parameter val_afi0__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi0__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi0__AFI_RDQOS = 32'hF8008008; +parameter val_afi0__AFI_RDQOS = 32'h00000000; +parameter mask_afi0__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi0__AFI_RDDATAFIFO_LEVEL = 32'hF800800C; +parameter val_afi0__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi0__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi0__AFI_RDDEBUG = 32'hF8008010; +parameter val_afi0__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi0__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi0__AFI_WRCHAN_CTRL = 32'hF8008014; +parameter val_afi0__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi0__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi0__AFI_WRCHAN_ISSUINGCAP = 32'hF8008018; +parameter val_afi0__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi0__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi0__AFI_WRQOS = 32'hF800801C; +parameter val_afi0__AFI_WRQOS = 32'h00000000; +parameter mask_afi0__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi0__AFI_WRDATAFIFO_LEVEL = 32'hF8008020; +parameter val_afi0__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi0__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi0__AFI_WRDEBUG = 32'hF8008024; +parameter val_afi0__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi0__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi1 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi1__AFI_RDCHAN_CTRL = 32'hF8009000; +parameter val_afi1__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi1__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi1__AFI_RDCHAN_ISSUINGCAP = 32'hF8009004; +parameter val_afi1__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi1__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi1__AFI_RDQOS = 32'hF8009008; +parameter val_afi1__AFI_RDQOS = 32'h00000000; +parameter mask_afi1__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi1__AFI_RDDATAFIFO_LEVEL = 32'hF800900C; +parameter val_afi1__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi1__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi1__AFI_RDDEBUG = 32'hF8009010; +parameter val_afi1__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi1__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi1__AFI_WRCHAN_CTRL = 32'hF8009014; +parameter val_afi1__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi1__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi1__AFI_WRCHAN_ISSUINGCAP = 32'hF8009018; +parameter val_afi1__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi1__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi1__AFI_WRQOS = 32'hF800901C; +parameter val_afi1__AFI_WRQOS = 32'h00000000; +parameter mask_afi1__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi1__AFI_WRDATAFIFO_LEVEL = 32'hF8009020; +parameter val_afi1__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi1__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi1__AFI_WRDEBUG = 32'hF8009024; +parameter val_afi1__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi1__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi2 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi2__AFI_RDCHAN_CTRL = 32'hF800A000; +parameter val_afi2__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi2__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi2__AFI_RDCHAN_ISSUINGCAP = 32'hF800A004; +parameter val_afi2__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi2__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi2__AFI_RDQOS = 32'hF800A008; +parameter val_afi2__AFI_RDQOS = 32'h00000000; +parameter mask_afi2__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi2__AFI_RDDATAFIFO_LEVEL = 32'hF800A00C; +parameter val_afi2__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi2__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi2__AFI_RDDEBUG = 32'hF800A010; +parameter val_afi2__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi2__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi2__AFI_WRCHAN_CTRL = 32'hF800A014; +parameter val_afi2__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi2__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi2__AFI_WRCHAN_ISSUINGCAP = 32'hF800A018; +parameter val_afi2__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi2__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi2__AFI_WRQOS = 32'hF800A01C; +parameter val_afi2__AFI_WRQOS = 32'h00000000; +parameter mask_afi2__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi2__AFI_WRDATAFIFO_LEVEL = 32'hF800A020; +parameter val_afi2__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi2__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi2__AFI_WRDEBUG = 32'hF800A024; +parameter val_afi2__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi2__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi3 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi3__AFI_RDCHAN_CTRL = 32'hF800B000; +parameter val_afi3__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi3__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi3__AFI_RDCHAN_ISSUINGCAP = 32'hF800B004; +parameter val_afi3__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi3__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi3__AFI_RDQOS = 32'hF800B008; +parameter val_afi3__AFI_RDQOS = 32'h00000000; +parameter mask_afi3__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi3__AFI_RDDATAFIFO_LEVEL = 32'hF800B00C; +parameter val_afi3__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi3__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi3__AFI_RDDEBUG = 32'hF800B010; +parameter val_afi3__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi3__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi3__AFI_WRCHAN_CTRL = 32'hF800B014; +parameter val_afi3__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi3__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi3__AFI_WRCHAN_ISSUINGCAP = 32'hF800B018; +parameter val_afi3__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi3__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi3__AFI_WRQOS = 32'hF800B01C; +parameter val_afi3__AFI_WRQOS = 32'h00000000; +parameter mask_afi3__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi3__AFI_WRDATAFIFO_LEVEL = 32'hF800B020; +parameter val_afi3__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi3__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi3__AFI_WRDEBUG = 32'hF800B024; +parameter val_afi3__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi3__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module can0 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter can0__SRR = 32'hE0008000; +parameter val_can0__SRR = 32'h00000000; +parameter mask_can0__SRR = 32'hFFFFFFFF; + +parameter can0__MSR = 32'hE0008004; +parameter val_can0__MSR = 32'h00000000; +parameter mask_can0__MSR = 32'hFFFFFFFF; + +parameter can0__BRPR = 32'hE0008008; +parameter val_can0__BRPR = 32'h00000000; +parameter mask_can0__BRPR = 32'hFFFFFFFF; + +parameter can0__BTR = 32'hE000800C; +parameter val_can0__BTR = 32'h00000000; +parameter mask_can0__BTR = 32'hFFFFFFFF; + +parameter can0__ECR = 32'hE0008010; +parameter val_can0__ECR = 32'h00000000; +parameter mask_can0__ECR = 32'hFFFFFFFF; + +parameter can0__ESR = 32'hE0008014; +parameter val_can0__ESR = 32'h00000000; +parameter mask_can0__ESR = 32'hFFFFFFFF; + +parameter can0__SR = 32'hE0008018; +parameter val_can0__SR = 32'h00000001; +parameter mask_can0__SR = 32'hFFFFFFFF; + +parameter can0__ISR = 32'hE000801C; +parameter val_can0__ISR = 32'h00006000; +parameter mask_can0__ISR = 32'hFFFFFFFF; + +parameter can0__IER = 32'hE0008020; +parameter val_can0__IER = 32'h00000000; +parameter mask_can0__IER = 32'hFFFFFFFF; + +parameter can0__ICR = 32'hE0008024; +parameter val_can0__ICR = 32'h00000000; +parameter mask_can0__ICR = 32'hFFFFFFFF; + +parameter can0__TCR = 32'hE0008028; +parameter val_can0__TCR = 32'h00000000; +parameter mask_can0__TCR = 32'hFFFFFFFF; + +parameter can0__WIR = 32'hE000802C; +parameter val_can0__WIR = 32'h00003F3F; +parameter mask_can0__WIR = 32'hFFFFFFFF; + +parameter can0__TXFIFO_ID = 32'hE0008030; +parameter val_can0__TXFIFO_ID = 32'h00000000; +parameter mask_can0__TXFIFO_ID = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DLC = 32'hE0008034; +parameter val_can0__TXFIFO_DLC = 32'h00000000; +parameter mask_can0__TXFIFO_DLC = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DATA1 = 32'hE0008038; +parameter val_can0__TXFIFO_DATA1 = 32'h00000000; +parameter mask_can0__TXFIFO_DATA1 = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DATA2 = 32'hE000803C; +parameter val_can0__TXFIFO_DATA2 = 32'h00000000; +parameter mask_can0__TXFIFO_DATA2 = 32'hFFFFFFFF; + +parameter can0__TXHPB_ID = 32'hE0008040; +parameter val_can0__TXHPB_ID = 32'h00000000; +parameter mask_can0__TXHPB_ID = 32'hFFFFFFFF; + +parameter can0__TXHPB_DLC = 32'hE0008044; +parameter val_can0__TXHPB_DLC = 32'h00000000; +parameter mask_can0__TXHPB_DLC = 32'hFFFFFFFF; + +parameter can0__TXHPB_DATA1 = 32'hE0008048; +parameter val_can0__TXHPB_DATA1 = 32'h00000000; +parameter mask_can0__TXHPB_DATA1 = 32'hFFFFFFFF; + +parameter can0__TXHPB_DATA2 = 32'hE000804C; +parameter val_can0__TXHPB_DATA2 = 32'h00000000; +parameter mask_can0__TXHPB_DATA2 = 32'hFFFFFFFF; + +parameter can0__RXFIFO_ID = 32'hE0008050; +parameter val_can0__RXFIFO_ID = 32'h00000000; +parameter mask_can0__RXFIFO_ID = 32'h00000000; + +parameter can0__RXFIFO_DLC = 32'hE0008054; +parameter val_can0__RXFIFO_DLC = 32'h00000000; +parameter mask_can0__RXFIFO_DLC = 32'h00000000; + +parameter can0__RXFIFO_DATA1 = 32'hE0008058; +parameter val_can0__RXFIFO_DATA1 = 32'h00000000; +parameter mask_can0__RXFIFO_DATA1 = 32'h00000000; + +parameter can0__RXFIFO_DATA2 = 32'hE000805C; +parameter val_can0__RXFIFO_DATA2 = 32'h00000000; +parameter mask_can0__RXFIFO_DATA2 = 32'h00000000; + +parameter can0__AFR = 32'hE0008060; +parameter val_can0__AFR = 32'h00000000; +parameter mask_can0__AFR = 32'hFFFFFFFF; + +parameter can0__AFMR1 = 32'hE0008064; +parameter val_can0__AFMR1 = 32'h00000000; +parameter mask_can0__AFMR1 = 32'h00000000; + +parameter can0__AFIR1 = 32'hE0008068; +parameter val_can0__AFIR1 = 32'h00000000; +parameter mask_can0__AFIR1 = 32'h00000000; + +parameter can0__AFMR2 = 32'hE000806C; +parameter val_can0__AFMR2 = 32'h00000000; +parameter mask_can0__AFMR2 = 32'h00000000; + +parameter can0__AFIR2 = 32'hE0008070; +parameter val_can0__AFIR2 = 32'h00000000; +parameter mask_can0__AFIR2 = 32'h00000000; + +parameter can0__AFMR3 = 32'hE0008074; +parameter val_can0__AFMR3 = 32'h00000000; +parameter mask_can0__AFMR3 = 32'h00000000; + +parameter can0__AFIR3 = 32'hE0008078; +parameter val_can0__AFIR3 = 32'h00000000; +parameter mask_can0__AFIR3 = 32'h00000000; + +parameter can0__AFMR4 = 32'hE000807C; +parameter val_can0__AFMR4 = 32'h00000000; +parameter mask_can0__AFMR4 = 32'h00000000; + +parameter can0__AFIR4 = 32'hE0008080; +parameter val_can0__AFIR4 = 32'h00000000; +parameter mask_can0__AFIR4 = 32'h00000000; + + +// ************************************************************ +// Module can1 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter can1__SRR = 32'hE0009000; +parameter val_can1__SRR = 32'h00000000; +parameter mask_can1__SRR = 32'hFFFFFFFF; + +parameter can1__MSR = 32'hE0009004; +parameter val_can1__MSR = 32'h00000000; +parameter mask_can1__MSR = 32'hFFFFFFFF; + +parameter can1__BRPR = 32'hE0009008; +parameter val_can1__BRPR = 32'h00000000; +parameter mask_can1__BRPR = 32'hFFFFFFFF; + +parameter can1__BTR = 32'hE000900C; +parameter val_can1__BTR = 32'h00000000; +parameter mask_can1__BTR = 32'hFFFFFFFF; + +parameter can1__ECR = 32'hE0009010; +parameter val_can1__ECR = 32'h00000000; +parameter mask_can1__ECR = 32'hFFFFFFFF; + +parameter can1__ESR = 32'hE0009014; +parameter val_can1__ESR = 32'h00000000; +parameter mask_can1__ESR = 32'hFFFFFFFF; + +parameter can1__SR = 32'hE0009018; +parameter val_can1__SR = 32'h00000001; +parameter mask_can1__SR = 32'hFFFFFFFF; + +parameter can1__ISR = 32'hE000901C; +parameter val_can1__ISR = 32'h00006000; +parameter mask_can1__ISR = 32'hFFFFFFFF; + +parameter can1__IER = 32'hE0009020; +parameter val_can1__IER = 32'h00000000; +parameter mask_can1__IER = 32'hFFFFFFFF; + +parameter can1__ICR = 32'hE0009024; +parameter val_can1__ICR = 32'h00000000; +parameter mask_can1__ICR = 32'hFFFFFFFF; + +parameter can1__TCR = 32'hE0009028; +parameter val_can1__TCR = 32'h00000000; +parameter mask_can1__TCR = 32'hFFFFFFFF; + +parameter can1__WIR = 32'hE000902C; +parameter val_can1__WIR = 32'h00003F3F; +parameter mask_can1__WIR = 32'hFFFFFFFF; + +parameter can1__TXFIFO_ID = 32'hE0009030; +parameter val_can1__TXFIFO_ID = 32'h00000000; +parameter mask_can1__TXFIFO_ID = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DLC = 32'hE0009034; +parameter val_can1__TXFIFO_DLC = 32'h00000000; +parameter mask_can1__TXFIFO_DLC = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DATA1 = 32'hE0009038; +parameter val_can1__TXFIFO_DATA1 = 32'h00000000; +parameter mask_can1__TXFIFO_DATA1 = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DATA2 = 32'hE000903C; +parameter val_can1__TXFIFO_DATA2 = 32'h00000000; +parameter mask_can1__TXFIFO_DATA2 = 32'hFFFFFFFF; + +parameter can1__TXHPB_ID = 32'hE0009040; +parameter val_can1__TXHPB_ID = 32'h00000000; +parameter mask_can1__TXHPB_ID = 32'hFFFFFFFF; + +parameter can1__TXHPB_DLC = 32'hE0009044; +parameter val_can1__TXHPB_DLC = 32'h00000000; +parameter mask_can1__TXHPB_DLC = 32'hFFFFFFFF; + +parameter can1__TXHPB_DATA1 = 32'hE0009048; +parameter val_can1__TXHPB_DATA1 = 32'h00000000; +parameter mask_can1__TXHPB_DATA1 = 32'hFFFFFFFF; + +parameter can1__TXHPB_DATA2 = 32'hE000904C; +parameter val_can1__TXHPB_DATA2 = 32'h00000000; +parameter mask_can1__TXHPB_DATA2 = 32'hFFFFFFFF; + +parameter can1__RXFIFO_ID = 32'hE0009050; +parameter val_can1__RXFIFO_ID = 32'h00000000; +parameter mask_can1__RXFIFO_ID = 32'h00000000; + +parameter can1__RXFIFO_DLC = 32'hE0009054; +parameter val_can1__RXFIFO_DLC = 32'h00000000; +parameter mask_can1__RXFIFO_DLC = 32'h00000000; + +parameter can1__RXFIFO_DATA1 = 32'hE0009058; +parameter val_can1__RXFIFO_DATA1 = 32'h00000000; +parameter mask_can1__RXFIFO_DATA1 = 32'h00000000; + +parameter can1__RXFIFO_DATA2 = 32'hE000905C; +parameter val_can1__RXFIFO_DATA2 = 32'h00000000; +parameter mask_can1__RXFIFO_DATA2 = 32'h00000000; + +parameter can1__AFR = 32'hE0009060; +parameter val_can1__AFR = 32'h00000000; +parameter mask_can1__AFR = 32'hFFFFFFFF; + +parameter can1__AFMR1 = 32'hE0009064; +parameter val_can1__AFMR1 = 32'h00000000; +parameter mask_can1__AFMR1 = 32'h00000000; + +parameter can1__AFIR1 = 32'hE0009068; +parameter val_can1__AFIR1 = 32'h00000000; +parameter mask_can1__AFIR1 = 32'h00000000; + +parameter can1__AFMR2 = 32'hE000906C; +parameter val_can1__AFMR2 = 32'h00000000; +parameter mask_can1__AFMR2 = 32'h00000000; + +parameter can1__AFIR2 = 32'hE0009070; +parameter val_can1__AFIR2 = 32'h00000000; +parameter mask_can1__AFIR2 = 32'h00000000; + +parameter can1__AFMR3 = 32'hE0009074; +parameter val_can1__AFMR3 = 32'h00000000; +parameter mask_can1__AFMR3 = 32'h00000000; + +parameter can1__AFIR3 = 32'hE0009078; +parameter val_can1__AFIR3 = 32'h00000000; +parameter mask_can1__AFIR3 = 32'h00000000; + +parameter can1__AFMR4 = 32'hE000907C; +parameter val_can1__AFMR4 = 32'h00000000; +parameter mask_can1__AFMR4 = 32'h00000000; + +parameter can1__AFIR4 = 32'hE0009080; +parameter val_can1__AFIR4 = 32'h00000000; +parameter mask_can1__AFIR4 = 32'h00000000; + + +// ************************************************************ +// Module ddrc ddrc +// doc version: 1.25 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ddrc__ddrc_ctrl = 32'hF8006000; +parameter val_ddrc__ddrc_ctrl = 32'h00000200; +parameter mask_ddrc__ddrc_ctrl = 32'hFFFFFFFF; + +parameter ddrc__Two_rank_cfg = 32'hF8006004; +parameter val_ddrc__Two_rank_cfg = 32'h000C1076; +parameter mask_ddrc__Two_rank_cfg = 32'h1FFFFFFF; + +parameter ddrc__HPR_reg = 32'hF8006008; +parameter val_ddrc__HPR_reg = 32'h03C0780F; +parameter mask_ddrc__HPR_reg = 32'h03FFFFFF; + +parameter ddrc__LPR_reg = 32'hF800600C; +parameter val_ddrc__LPR_reg = 32'h03C0780F; +parameter mask_ddrc__LPR_reg = 32'h03FFFFFF; + +parameter ddrc__WR_reg = 32'hF8006010; +parameter val_ddrc__WR_reg = 32'h0007F80F; +parameter mask_ddrc__WR_reg = 32'h03FFFFFF; + +parameter ddrc__DRAM_param_reg0 = 32'hF8006014; +parameter val_ddrc__DRAM_param_reg0 = 32'h00041016; +parameter mask_ddrc__DRAM_param_reg0 = 32'h001FFFFF; + +parameter ddrc__DRAM_param_reg1 = 32'hF8006018; +parameter val_ddrc__DRAM_param_reg1 = 32'h351B48D9; +parameter mask_ddrc__DRAM_param_reg1 = 32'hF7FFFFFF; + +parameter ddrc__DRAM_param_reg2 = 32'hF800601C; +parameter val_ddrc__DRAM_param_reg2 = 32'h83015904; +parameter mask_ddrc__DRAM_param_reg2 = 32'hFFFFFFFF; + +parameter ddrc__DRAM_param_reg3 = 32'hF8006020; +parameter val_ddrc__DRAM_param_reg3 = 32'h250882D0; +parameter mask_ddrc__DRAM_param_reg3 = 32'hFFFFFFFF; + +parameter ddrc__DRAM_param_reg4 = 32'hF8006024; +parameter val_ddrc__DRAM_param_reg4 = 32'h0000003C; +parameter mask_ddrc__DRAM_param_reg4 = 32'h0FFFFFFF; + +parameter ddrc__DRAM_init_param = 32'hF8006028; +parameter val_ddrc__DRAM_init_param = 32'h00002007; +parameter mask_ddrc__DRAM_init_param = 32'h00003FFF; + +parameter ddrc__DRAM_EMR_reg = 32'hF800602C; +parameter val_ddrc__DRAM_EMR_reg = 32'h00000008; +parameter mask_ddrc__DRAM_EMR_reg = 32'hFFFFFFFF; + +parameter ddrc__DRAM_EMR_MR_reg = 32'hF8006030; +parameter val_ddrc__DRAM_EMR_MR_reg = 32'h00000940; +parameter mask_ddrc__DRAM_EMR_MR_reg = 32'hFFFFFFFF; + +parameter ddrc__DRAM_burst8_rdwr = 32'hF8006034; +parameter val_ddrc__DRAM_burst8_rdwr = 32'h00020034; +parameter mask_ddrc__DRAM_burst8_rdwr = 32'h1FFFFFFF; + +parameter ddrc__DRAM_disable_DQ = 32'hF8006038; +parameter val_ddrc__DRAM_disable_DQ = 32'h00000000; +parameter mask_ddrc__DRAM_disable_DQ = 32'h00001FFF; + +parameter ddrc__DRAM_addr_map_bank = 32'hF800603C; +parameter val_ddrc__DRAM_addr_map_bank = 32'h00000F77; +parameter mask_ddrc__DRAM_addr_map_bank = 32'h000FFFFF; + +parameter ddrc__DRAM_addr_map_col = 32'hF8006040; +parameter val_ddrc__DRAM_addr_map_col = 32'hFFF00000; +parameter mask_ddrc__DRAM_addr_map_col = 32'hFFFFFFFF; + +parameter ddrc__DRAM_addr_map_row = 32'hF8006044; +parameter val_ddrc__DRAM_addr_map_row = 32'h0FF55555; +parameter mask_ddrc__DRAM_addr_map_row = 32'h0FFFFFFF; + +parameter ddrc__DRAM_ODT_reg = 32'hF8006048; +parameter val_ddrc__DRAM_ODT_reg = 32'h00000249; +parameter mask_ddrc__DRAM_ODT_reg = 32'h3FFFFFFF; + +parameter ddrc__phy_dbg_reg = 32'hF800604C; +parameter val_ddrc__phy_dbg_reg = 32'h00000000; +parameter mask_ddrc__phy_dbg_reg = 32'h000FFFFF; + +parameter ddrc__phy_cmd_timeout_rddata_cpt = 32'hF8006050; +parameter val_ddrc__phy_cmd_timeout_rddata_cpt = 32'h00010200; +parameter mask_ddrc__phy_cmd_timeout_rddata_cpt = 32'hFFFFFFFF; + +parameter ddrc__mode_sts_reg = 32'hF8006054; +parameter val_ddrc__mode_sts_reg = 32'h00000000; +parameter mask_ddrc__mode_sts_reg = 32'h001FFFFF; + +parameter ddrc__DLL_calib = 32'hF8006058; +parameter val_ddrc__DLL_calib = 32'h00000101; +parameter mask_ddrc__DLL_calib = 32'h0001FFFF; + +parameter ddrc__ODT_delay_hold = 32'hF800605C; +parameter val_ddrc__ODT_delay_hold = 32'h00000023; +parameter mask_ddrc__ODT_delay_hold = 32'h0000FFFF; + +parameter ddrc__ctrl_reg1 = 32'hF8006060; +parameter val_ddrc__ctrl_reg1 = 32'h0000003E; +parameter mask_ddrc__ctrl_reg1 = 32'h00001FFF; + +parameter ddrc__ctrl_reg2 = 32'hF8006064; +parameter val_ddrc__ctrl_reg2 = 32'h00020000; +parameter mask_ddrc__ctrl_reg2 = 32'h0003FFFF; + +parameter ddrc__ctrl_reg3 = 32'hF8006068; +parameter val_ddrc__ctrl_reg3 = 32'h00284027; +parameter mask_ddrc__ctrl_reg3 = 32'h03FFFFFF; + +parameter ddrc__ctrl_reg4 = 32'hF800606C; +parameter val_ddrc__ctrl_reg4 = 32'h00001610; +parameter mask_ddrc__ctrl_reg4 = 32'h0000FFFF; + +parameter ddrc__ctrl_reg5 = 32'hF8006078; +parameter val_ddrc__ctrl_reg5 = 32'h00455111; +parameter mask_ddrc__ctrl_reg5 = 32'hFFFFFFFF; + +parameter ddrc__ctrl_reg6 = 32'hF800607C; +parameter val_ddrc__ctrl_reg6 = 32'h00032222; +parameter mask_ddrc__ctrl_reg6 = 32'hFFFFFFFF; + +parameter ddrc__CHE_REFRESH_TIMER01 = 32'hF80060A0; +parameter val_ddrc__CHE_REFRESH_TIMER01 = 32'h00008000; +parameter mask_ddrc__CHE_REFRESH_TIMER01 = 32'h00FFFFFF; + +parameter ddrc__CHE_T_ZQ = 32'hF80060A4; +parameter val_ddrc__CHE_T_ZQ = 32'h10300802; +parameter mask_ddrc__CHE_T_ZQ = 32'hFFFFFFFF; + +parameter ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'hF80060A8; +parameter val_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0020003A; +parameter mask_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0FFFFFFF; + +parameter ddrc__deep_pwrdwn_reg = 32'hF80060AC; +parameter val_ddrc__deep_pwrdwn_reg = 32'h00000000; +parameter mask_ddrc__deep_pwrdwn_reg = 32'h000001FF; + +parameter ddrc__reg_2c = 32'hF80060B0; +parameter val_ddrc__reg_2c = 32'h00000000; +parameter mask_ddrc__reg_2c = 32'h1FFFFFFF; + +parameter ddrc__reg_2d = 32'hF80060B4; +parameter val_ddrc__reg_2d = 32'h00000200; +parameter mask_ddrc__reg_2d = 32'h000007FF; + +parameter ddrc__dfi_timing = 32'hF80060B8; +parameter val_ddrc__dfi_timing = 32'h00200067; +parameter mask_ddrc__dfi_timing = 32'h01FFFFFF; + +parameter ddrc__refresh_timer_2 = 32'hF80060BC; +parameter val_ddrc__refresh_timer_2 = 32'h00000000; +parameter mask_ddrc__refresh_timer_2 = 32'h00FFFFFF; + +parameter ddrc__nc_timing = 32'hF80060C0; +parameter val_ddrc__nc_timing = 32'h00000000; +parameter mask_ddrc__nc_timing = 32'h003FFFFF; + +parameter ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'hF80060C4; +parameter val_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000003; + +parameter ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'hF80060C8; +parameter val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'hF80060CC; +parameter val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060D0; +parameter val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060D4; +parameter val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060D8; +parameter val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'hF80060DC; +parameter val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000001; + +parameter ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'hF80060E0; +parameter val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060E4; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060E8; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060EC; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_ECC_STATS_REG_OFFSET = 32'hF80060F0; +parameter val_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h0000FFFF; + +parameter ddrc__ECC_scrub = 32'hF80060F4; +parameter val_ddrc__ECC_scrub = 32'h00000008; +parameter mask_ddrc__ECC_scrub = 32'h0000000F; + +parameter ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hF80060F8; +parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hF80060FC; +parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__phy_rcvr_enable = 32'hF8006114; +parameter val_ddrc__phy_rcvr_enable = 32'h00000000; +parameter mask_ddrc__phy_rcvr_enable = 32'h000000FF; + +parameter ddrc__PHY_Config0 = 32'hF8006118; +parameter val_ddrc__PHY_Config0 = 32'h40000001; +parameter mask_ddrc__PHY_Config0 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config1 = 32'hF800611C; +parameter val_ddrc__PHY_Config1 = 32'h40000001; +parameter mask_ddrc__PHY_Config1 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config2 = 32'hF8006120; +parameter val_ddrc__PHY_Config2 = 32'h40000001; +parameter mask_ddrc__PHY_Config2 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config3 = 32'hF8006124; +parameter val_ddrc__PHY_Config3 = 32'h40000001; +parameter mask_ddrc__PHY_Config3 = 32'h7FFFFFFF; + +parameter ddrc__phy_init_ratio0 = 32'hF800612C; +parameter val_ddrc__phy_init_ratio0 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio0 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio1 = 32'hF8006130; +parameter val_ddrc__phy_init_ratio1 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio1 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio2 = 32'hF8006134; +parameter val_ddrc__phy_init_ratio2 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio2 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio3 = 32'hF8006138; +parameter val_ddrc__phy_init_ratio3 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio3 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg0 = 32'hF8006140; +parameter val_ddrc__phy_rd_dqs_cfg0 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg0 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg1 = 32'hF8006144; +parameter val_ddrc__phy_rd_dqs_cfg1 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg1 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg2 = 32'hF8006148; +parameter val_ddrc__phy_rd_dqs_cfg2 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg2 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg3 = 32'hF800614C; +parameter val_ddrc__phy_rd_dqs_cfg3 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg3 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg0 = 32'hF8006154; +parameter val_ddrc__phy_wr_dqs_cfg0 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg0 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg1 = 32'hF8006158; +parameter val_ddrc__phy_wr_dqs_cfg1 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg1 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg2 = 32'hF800615C; +parameter val_ddrc__phy_wr_dqs_cfg2 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg2 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg3 = 32'hF8006160; +parameter val_ddrc__phy_wr_dqs_cfg3 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg3 = 32'h000FFFFF; + +parameter ddrc__phy_we_cfg0 = 32'hF8006168; +parameter val_ddrc__phy_we_cfg0 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg0 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg1 = 32'hF800616C; +parameter val_ddrc__phy_we_cfg1 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg1 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg2 = 32'hF8006170; +parameter val_ddrc__phy_we_cfg2 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg2 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg3 = 32'hF8006174; +parameter val_ddrc__phy_we_cfg3 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg3 = 32'h001FFFFF; + +parameter ddrc__wr_data_slv0 = 32'hF800617C; +parameter val_ddrc__wr_data_slv0 = 32'h00000080; +parameter mask_ddrc__wr_data_slv0 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv1 = 32'hF8006180; +parameter val_ddrc__wr_data_slv1 = 32'h00000080; +parameter mask_ddrc__wr_data_slv1 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv2 = 32'hF8006184; +parameter val_ddrc__wr_data_slv2 = 32'h00000080; +parameter mask_ddrc__wr_data_slv2 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv3 = 32'hF8006188; +parameter val_ddrc__wr_data_slv3 = 32'h00000080; +parameter mask_ddrc__wr_data_slv3 = 32'h000FFFFF; + +parameter ddrc__reg_64 = 32'hF8006190; +parameter val_ddrc__reg_64 = 32'h10020000; +parameter mask_ddrc__reg_64 = 32'hFFFFFFFF; + +parameter ddrc__reg_65 = 32'hF8006194; +parameter val_ddrc__reg_65 = 32'h00000000; +parameter mask_ddrc__reg_65 = 32'h000FFFFF; + +parameter ddrc__reg69_6a0 = 32'hF80061A4; +parameter val_ddrc__reg69_6a0 = 32'h000F0000; +parameter mask_ddrc__reg69_6a0 = 32'h1FFFFFFF; + +parameter ddrc__reg69_6a1 = 32'hF80061A8; +parameter val_ddrc__reg69_6a1 = 32'h000F0000; +parameter mask_ddrc__reg69_6a1 = 32'h1FFFFFFF; + +parameter ddrc__reg6c_6d2 = 32'hF80061B0; +parameter val_ddrc__reg6c_6d2 = 32'h000F0000; +parameter mask_ddrc__reg6c_6d2 = 32'h1FFFFFFF; + +parameter ddrc__reg6c_6d3 = 32'hF80061B4; +parameter val_ddrc__reg6c_6d3 = 32'h000F0000; +parameter mask_ddrc__reg6c_6d3 = 32'h1FFFFFFF; + +parameter ddrc__reg6e_710 = 32'hF80061B8; +parameter val_ddrc__reg6e_710 = 32'h00000000; +parameter mask_ddrc__reg6e_710 = 32'h00000000; + +parameter ddrc__reg6e_711 = 32'hF80061BC; +parameter val_ddrc__reg6e_711 = 32'h00000000; +parameter mask_ddrc__reg6e_711 = 32'h00000000; + +parameter ddrc__reg6e_712 = 32'hF80061C0; +parameter val_ddrc__reg6e_712 = 32'h00000000; +parameter mask_ddrc__reg6e_712 = 32'h00000000; + +parameter ddrc__reg6e_713 = 32'hF80061C4; +parameter val_ddrc__reg6e_713 = 32'h00000000; +parameter mask_ddrc__reg6e_713 = 32'h00000000; + +parameter ddrc__phy_dll_sts0 = 32'hF80061CC; +parameter val_ddrc__phy_dll_sts0 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts0 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts1 = 32'hF80061D0; +parameter val_ddrc__phy_dll_sts1 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts1 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts2 = 32'hF80061D4; +parameter val_ddrc__phy_dll_sts2 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts2 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts3 = 32'hF80061D8; +parameter val_ddrc__phy_dll_sts3 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts3 = 32'h07FFFFFF; + +parameter ddrc__dll_lock_sts = 32'hF80061E0; +parameter val_ddrc__dll_lock_sts = 32'h00000000; +parameter mask_ddrc__dll_lock_sts = 32'h00FFFFFF; + +parameter ddrc__phy_ctrl_sts = 32'hF80061E4; +parameter val_ddrc__phy_ctrl_sts = 32'h00000000; +parameter mask_ddrc__phy_ctrl_sts = 32'h3FF80000; + +parameter ddrc__phy_ctrl_sts_reg2 = 32'hF80061E8; +parameter val_ddrc__phy_ctrl_sts_reg2 = 32'h00000000; +parameter mask_ddrc__phy_ctrl_sts_reg2 = 32'h07FFFFFF; + +parameter ddrc__axi_id = 32'hF8006200; +parameter val_ddrc__axi_id = 32'h00153042; +parameter mask_ddrc__axi_id = 32'h03FFFFFF; + +parameter ddrc__page_mask = 32'hF8006204; +parameter val_ddrc__page_mask = 32'h00000000; +parameter mask_ddrc__page_mask = 32'hFFFFFFFF; + +parameter ddrc__axi_priority_wr_port0 = 32'hF8006208; +parameter val_ddrc__axi_priority_wr_port0 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port0 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port1 = 32'hF800620C; +parameter val_ddrc__axi_priority_wr_port1 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port1 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port2 = 32'hF8006210; +parameter val_ddrc__axi_priority_wr_port2 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port2 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port3 = 32'hF8006214; +parameter val_ddrc__axi_priority_wr_port3 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port3 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port0 = 32'hF8006218; +parameter val_ddrc__axi_priority_rd_port0 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port0 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port1 = 32'hF800621C; +parameter val_ddrc__axi_priority_rd_port1 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port1 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port2 = 32'hF8006220; +parameter val_ddrc__axi_priority_rd_port2 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port2 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port3 = 32'hF8006224; +parameter val_ddrc__axi_priority_rd_port3 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port3 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg0 = 32'hF8006248; +parameter val_ddrc__AHB_priority_cfg0 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg0 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg1 = 32'hF800624C; +parameter val_ddrc__AHB_priority_cfg1 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg1 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg2 = 32'hF8006250; +parameter val_ddrc__AHB_priority_cfg2 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg2 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg3 = 32'hF8006254; +parameter val_ddrc__AHB_priority_cfg3 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg3 = 32'h000FFFFF; + +parameter ddrc__perf_mon0 = 32'hF8006260; +parameter val_ddrc__perf_mon0 = 32'h00000000; +parameter mask_ddrc__perf_mon0 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon1 = 32'hF8006264; +parameter val_ddrc__perf_mon1 = 32'h00000000; +parameter mask_ddrc__perf_mon1 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon2 = 32'hF8006268; +parameter val_ddrc__perf_mon2 = 32'h00000000; +parameter mask_ddrc__perf_mon2 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon3 = 32'hF800626C; +parameter val_ddrc__perf_mon3 = 32'h00000000; +parameter mask_ddrc__perf_mon3 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon20 = 32'hF8006270; +parameter val_ddrc__perf_mon20 = 32'h00000000; +parameter mask_ddrc__perf_mon20 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon21 = 32'hF8006274; +parameter val_ddrc__perf_mon21 = 32'h00000000; +parameter mask_ddrc__perf_mon21 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon22 = 32'hF8006278; +parameter val_ddrc__perf_mon22 = 32'h00000000; +parameter mask_ddrc__perf_mon22 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon23 = 32'hF800627C; +parameter val_ddrc__perf_mon23 = 32'h00000000; +parameter mask_ddrc__perf_mon23 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon30 = 32'hF8006280; +parameter val_ddrc__perf_mon30 = 32'h00000000; +parameter mask_ddrc__perf_mon30 = 32'h0000FFFF; + +parameter ddrc__perf_mon31 = 32'hF8006284; +parameter val_ddrc__perf_mon31 = 32'h00000000; +parameter mask_ddrc__perf_mon31 = 32'h0000FFFF; + +parameter ddrc__perf_mon32 = 32'hF8006288; +parameter val_ddrc__perf_mon32 = 32'h00000000; +parameter mask_ddrc__perf_mon32 = 32'h0000FFFF; + +parameter ddrc__perf_mon33 = 32'hF800628C; +parameter val_ddrc__perf_mon33 = 32'h00000000; +parameter mask_ddrc__perf_mon33 = 32'h0000FFFF; + +parameter ddrc__trusted_mem_cfg = 32'hF8006290; +parameter val_ddrc__trusted_mem_cfg = 32'h00000000; +parameter mask_ddrc__trusted_mem_cfg = 32'h0000FFFF; + +parameter ddrc__excl_access_cfg0 = 32'hF8006294; +parameter val_ddrc__excl_access_cfg0 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg0 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg1 = 32'hF8006298; +parameter val_ddrc__excl_access_cfg1 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg1 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg2 = 32'hF800629C; +parameter val_ddrc__excl_access_cfg2 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg2 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg3 = 32'hF80062A0; +parameter val_ddrc__excl_access_cfg3 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg3 = 32'h0003FFFF; + +parameter ddrc__mode_reg_read = 32'hF80062A4; +parameter val_ddrc__mode_reg_read = 32'h00000000; +parameter mask_ddrc__mode_reg_read = 32'hFFFFFFFF; + +parameter ddrc__lpddr_ctrl0 = 32'hF80062A8; +parameter val_ddrc__lpddr_ctrl0 = 32'h00000000; +parameter mask_ddrc__lpddr_ctrl0 = 32'h00000FFF; + +parameter ddrc__lpddr_ctrl1 = 32'hF80062AC; +parameter val_ddrc__lpddr_ctrl1 = 32'h00000000; +parameter mask_ddrc__lpddr_ctrl1 = 32'hFFFFFFFF; + +parameter ddrc__lpddr_ctrl2 = 32'hF80062B0; +parameter val_ddrc__lpddr_ctrl2 = 32'h003C0015; +parameter mask_ddrc__lpddr_ctrl2 = 32'h003FFFFF; + +parameter ddrc__lpddr_ctrl3 = 32'hF80062B4; +parameter val_ddrc__lpddr_ctrl3 = 32'h00000601; +parameter mask_ddrc__lpddr_ctrl3 = 32'h0003FFFF; + +parameter ddrc__phy_wr_lvl_fsm = 32'hF80062B8; +parameter val_ddrc__phy_wr_lvl_fsm = 32'h00004444; +parameter mask_ddrc__phy_wr_lvl_fsm = 32'h00007FFF; + +parameter ddrc__phy_rd_lvl_fsm = 32'hF80062BC; +parameter val_ddrc__phy_rd_lvl_fsm = 32'h00008888; +parameter mask_ddrc__phy_rd_lvl_fsm = 32'h0000FFFF; + +parameter ddrc__phy_gate_lvl_fsm = 32'hF80062C0; +parameter val_ddrc__phy_gate_lvl_fsm = 32'h00004444; +parameter mask_ddrc__phy_gate_lvl_fsm = 32'h00007FFF; + + +// ************************************************************ +// Module debug_axim axim +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_axim__GLOBAL_CTRL = 32'hF880C000; +parameter val_debug_axim__GLOBAL_CTRL = 32'h00000002; +parameter mask_debug_axim__GLOBAL_CTRL = 32'h00000003; + +parameter debug_axim__GLOBAL_STATUS = 32'hF880C004; +parameter val_debug_axim__GLOBAL_STATUS = 32'h00001000; +parameter mask_debug_axim__GLOBAL_STATUS = 32'h00001FC3; + +parameter debug_axim__FILTER_CTRL = 32'hF880C010; +parameter val_debug_axim__FILTER_CTRL = 32'h00000000; +parameter mask_debug_axim__FILTER_CTRL = 32'h0000007F; + +parameter debug_axim__TRIGGER_CTRL = 32'hF880C020; +parameter val_debug_axim__TRIGGER_CTRL = 32'h00000000; +parameter mask_debug_axim__TRIGGER_CTRL = 32'h0000FFFF; + +parameter debug_axim__TRIGGER_STATUS = 32'hF880C024; +parameter val_debug_axim__TRIGGER_STATUS = 32'h00000000; +parameter mask_debug_axim__TRIGGER_STATUS = 32'h00000003; + +parameter debug_axim__PACKET_CTRL = 32'hF880C030; +parameter val_debug_axim__PACKET_CTRL = 32'h00070000; +parameter mask_debug_axim__PACKET_CTRL = 32'h0007FFFF; + +parameter debug_axim__TOUT_CTRL = 32'hF880C040; +parameter val_debug_axim__TOUT_CTRL = 32'h00000000; +parameter mask_debug_axim__TOUT_CTRL = 32'h0000007F; + +parameter debug_axim__TOUT_THRESH = 32'hF880C044; +parameter val_debug_axim__TOUT_THRESH = 32'h00008000; +parameter mask_debug_axim__TOUT_THRESH = 32'hFFFFFFFF; + +parameter debug_axim__FIFO_CURRENT = 32'hF880C050; +parameter val_debug_axim__FIFO_CURRENT = 32'h80000000; +parameter mask_debug_axim__FIFO_CURRENT = 32'hFFFFFFFF; + +parameter debug_axim__FIFO_HYSTER = 32'hF880C054; +parameter val_debug_axim__FIFO_HYSTER = 32'h00000100; +parameter mask_debug_axim__FIFO_HYSTER = 32'h000003FF; + +parameter debug_axim__SYNC_CURRENT = 32'hF880C060; +parameter val_debug_axim__SYNC_CURRENT = 32'h00000000; +parameter mask_debug_axim__SYNC_CURRENT = 32'h00000FFF; + +parameter debug_axim__SYNC_RELOAD = 32'hF880C064; +parameter val_debug_axim__SYNC_RELOAD = 32'h00000800; +parameter mask_debug_axim__SYNC_RELOAD = 32'h00000FFF; + +parameter debug_axim__TSTMP_CURRENT = 32'hF880C070; +parameter val_debug_axim__TSTMP_CURRENT = 32'h00000000; +parameter mask_debug_axim__TSTMP_CURRENT = 32'h00000000; + +parameter debug_axim__ADDR0_MASK = 32'hF880C200; +parameter val_debug_axim__ADDR0_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR0_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_LOWER = 32'hF880C204; +parameter val_debug_axim__ADDR0_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR0_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_UPPER = 32'hF880C208; +parameter val_debug_axim__ADDR0_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR0_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_MISC = 32'hF880C20C; +parameter val_debug_axim__ADDR0_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR0_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR1_MASK = 32'hF880C210; +parameter val_debug_axim__ADDR1_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR1_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_LOWER = 32'hF880C214; +parameter val_debug_axim__ADDR1_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR1_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_UPPER = 32'hF880C218; +parameter val_debug_axim__ADDR1_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR1_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_MISC = 32'hF880C21C; +parameter val_debug_axim__ADDR1_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR1_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR2_MASK = 32'hF880C220; +parameter val_debug_axim__ADDR2_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR2_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_LOWER = 32'hF880C224; +parameter val_debug_axim__ADDR2_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR2_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_UPPER = 32'hF880C228; +parameter val_debug_axim__ADDR2_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR2_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_MISC = 32'hF880C22C; +parameter val_debug_axim__ADDR2_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR2_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR3_MASK = 32'hF880C230; +parameter val_debug_axim__ADDR3_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR3_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_LOWER = 32'hF880C234; +parameter val_debug_axim__ADDR3_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR3_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_UPPER = 32'hF880C238; +parameter val_debug_axim__ADDR3_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR3_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_MISC = 32'hF880C23C; +parameter val_debug_axim__ADDR3_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR3_MISC = 32'h00007FFF; + +parameter debug_axim__ID0_MASK = 32'hF880C300; +parameter val_debug_axim__ID0_MASK = 32'h000003FF; +parameter mask_debug_axim__ID0_MASK = 32'h000003FF; + +parameter debug_axim__ID0_LOWER = 32'hF880C304; +parameter val_debug_axim__ID0_LOWER = 32'h00000000; +parameter mask_debug_axim__ID0_LOWER = 32'h000003FF; + +parameter debug_axim__ID0_UPPER = 32'hF880C308; +parameter val_debug_axim__ID0_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID0_UPPER = 32'h000003FF; + +parameter debug_axim__ID0_MISC = 32'hF880C30C; +parameter val_debug_axim__ID0_MISC = 32'h00000000; +parameter mask_debug_axim__ID0_MISC = 32'h00003FFF; + +parameter debug_axim__ID1_MASK = 32'hF880C310; +parameter val_debug_axim__ID1_MASK = 32'h000003FF; +parameter mask_debug_axim__ID1_MASK = 32'h000003FF; + +parameter debug_axim__ID1_LOWER = 32'hF880C314; +parameter val_debug_axim__ID1_LOWER = 32'h00000000; +parameter mask_debug_axim__ID1_LOWER = 32'h000003FF; + +parameter debug_axim__ID1_UPPER = 32'hF880C318; +parameter val_debug_axim__ID1_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID1_UPPER = 32'h000003FF; + +parameter debug_axim__ID1_MISC = 32'hF880C31C; +parameter val_debug_axim__ID1_MISC = 32'h00000000; +parameter mask_debug_axim__ID1_MISC = 32'h00003FFF; + +parameter debug_axim__ID2_MASK = 32'hF880C320; +parameter val_debug_axim__ID2_MASK = 32'h000003FF; +parameter mask_debug_axim__ID2_MASK = 32'h000003FF; + +parameter debug_axim__ID2_LOWER = 32'hF880C324; +parameter val_debug_axim__ID2_LOWER = 32'h00000000; +parameter mask_debug_axim__ID2_LOWER = 32'h000003FF; + +parameter debug_axim__ID2_UPPER = 32'hF880C328; +parameter val_debug_axim__ID2_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID2_UPPER = 32'h000003FF; + +parameter debug_axim__ID2_MISC = 32'hF880C32C; +parameter val_debug_axim__ID2_MISC = 32'h00000000; +parameter mask_debug_axim__ID2_MISC = 32'h00003FFF; + +parameter debug_axim__ID3_MASK = 32'hF880C330; +parameter val_debug_axim__ID3_MASK = 32'h000003FF; +parameter mask_debug_axim__ID3_MASK = 32'h000003FF; + +parameter debug_axim__ID3_LOWER = 32'hF880C334; +parameter val_debug_axim__ID3_LOWER = 32'h00000000; +parameter mask_debug_axim__ID3_LOWER = 32'h000003FF; + +parameter debug_axim__ID3_UPPER = 32'hF880C338; +parameter val_debug_axim__ID3_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID3_UPPER = 32'h000003FF; + +parameter debug_axim__ID3_MISC = 32'hF880C33C; +parameter val_debug_axim__ID3_MISC = 32'h00000000; +parameter mask_debug_axim__ID3_MISC = 32'h00003FFF; + +parameter debug_axim__AXI_SEL = 32'hF880C800; +parameter val_debug_axim__AXI_SEL = 32'h00000000; +parameter mask_debug_axim__AXI_SEL = 32'h00000007; + +parameter debug_axim__IT_TRIGOUT = 32'hF880CED0; +parameter val_debug_axim__IT_TRIGOUT = 32'h00000000; +parameter mask_debug_axim__IT_TRIGOUT = 32'h00000001; + +parameter debug_axim__IT_TRIGOUTACK = 32'hF880CED4; +parameter val_debug_axim__IT_TRIGOUTACK = 32'h00000000; +parameter mask_debug_axim__IT_TRIGOUTACK = 32'h00000000; + +parameter debug_axim__IT_TRIGIN = 32'hF880CED8; +parameter val_debug_axim__IT_TRIGIN = 32'h00000000; +parameter mask_debug_axim__IT_TRIGIN = 32'h00000000; + +parameter debug_axim__IT_TRIGINACK = 32'hF880CEDC; +parameter val_debug_axim__IT_TRIGINACK = 32'h00000000; +parameter mask_debug_axim__IT_TRIGINACK = 32'h00000001; + +parameter debug_axim__IT_ATBDATA = 32'hF880CEEC; +parameter val_debug_axim__IT_ATBDATA = 32'h00000000; +parameter mask_debug_axim__IT_ATBDATA = 32'h0000001F; + +parameter debug_axim__IT_ATBSTATUS = 32'hF880CEF0; +parameter val_debug_axim__IT_ATBSTATUS = 32'h00000000; +parameter mask_debug_axim__IT_ATBSTATUS = 32'h00000000; + +parameter debug_axim__IT_ATBCTRL1 = 32'hF880CEF4; +parameter val_debug_axim__IT_ATBCTRL1 = 32'h00000000; +parameter mask_debug_axim__IT_ATBCTRL1 = 32'h0000007F; + +parameter debug_axim__IT_ATBCTRL0 = 32'hF880CEF8; +parameter val_debug_axim__IT_ATBCTRL0 = 32'h00000000; +parameter mask_debug_axim__IT_ATBCTRL0 = 32'h000003FF; + +parameter debug_axim__IT_CTRL = 32'hF880CF00; +parameter val_debug_axim__IT_CTRL = 32'h00000000; +parameter mask_debug_axim__IT_CTRL = 32'h00000001; + +parameter debug_axim__CLAIM_SET = 32'hF880CFA0; +parameter val_debug_axim__CLAIM_SET = 32'h00000001; +parameter mask_debug_axim__CLAIM_SET = 32'h0000000F; + +parameter debug_axim__CLAIM_CLEAR = 32'hF880CFA4; +parameter val_debug_axim__CLAIM_CLEAR = 32'h00000000; +parameter mask_debug_axim__CLAIM_CLEAR = 32'h0000000F; + +parameter debug_axim__LOCK_ACCESS = 32'hF880CFB0; +parameter val_debug_axim__LOCK_ACCESS = 32'h00000000; +parameter mask_debug_axim__LOCK_ACCESS = 32'hFFFFFFFF; + +parameter debug_axim__LOCK_STATUS = 32'hF880CFB4; +parameter val_debug_axim__LOCK_STATUS = 32'h00000003; +parameter mask_debug_axim__LOCK_STATUS = 32'h00000007; + +parameter debug_axim__AUTH_STATUS = 32'hF880CFB8; +parameter val_debug_axim__AUTH_STATUS = 32'h00000000; +parameter mask_debug_axim__AUTH_STATUS = 32'h00000033; + +parameter debug_axim__DEV_ID = 32'hF880CFC8; +parameter val_debug_axim__DEV_ID = 32'h00000000; +parameter mask_debug_axim__DEV_ID = 32'hFFFFFFFF; + +parameter debug_axim__DEV_TYPE = 32'hF880CFCC; +parameter val_debug_axim__DEV_TYPE = 32'h00000043; +parameter mask_debug_axim__DEV_TYPE = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID4 = 32'hF880CFD0; +parameter val_debug_axim__PERIPHID4 = 32'h00000003; +parameter mask_debug_axim__PERIPHID4 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID5 = 32'hF880CFD4; +parameter val_debug_axim__PERIPHID5 = 32'h00000000; +parameter mask_debug_axim__PERIPHID5 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID6 = 32'hF880CFD8; +parameter val_debug_axim__PERIPHID6 = 32'h00000000; +parameter mask_debug_axim__PERIPHID6 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID7 = 32'hF880CFDC; +parameter val_debug_axim__PERIPHID7 = 32'h00000000; +parameter mask_debug_axim__PERIPHID7 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID0 = 32'hF880CFE0; +parameter val_debug_axim__PERIPHID0 = 32'h000000B2; +parameter mask_debug_axim__PERIPHID0 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID1 = 32'hF880CFE4; +parameter val_debug_axim__PERIPHID1 = 32'h00000093; +parameter mask_debug_axim__PERIPHID1 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID2 = 32'hF880CFE8; +parameter val_debug_axim__PERIPHID2 = 32'h00000008; +parameter mask_debug_axim__PERIPHID2 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID3 = 32'hF880CFEC; +parameter val_debug_axim__PERIPHID3 = 32'h00000002; +parameter mask_debug_axim__PERIPHID3 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID0 = 32'hF880CFF0; +parameter val_debug_axim__COMPID0 = 32'h0000000D; +parameter mask_debug_axim__COMPID0 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID1 = 32'hF880CFF4; +parameter val_debug_axim__COMPID1 = 32'h00000090; +parameter mask_debug_axim__COMPID1 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID2 = 32'hF880CFF8; +parameter val_debug_axim__COMPID2 = 32'h00000005; +parameter mask_debug_axim__COMPID2 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID3 = 32'hF880CFFC; +parameter val_debug_axim__COMPID3 = 32'h000000B1; +parameter mask_debug_axim__COMPID3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_cti0 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_cti0__CTICONTROL = 32'hF8898000; +parameter val_debug_cpu_cti0__CTICONTROL = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICONTROL = 32'h00000001; + +parameter debug_cpu_cti0__CTIINTACK = 32'hF8898010; +parameter val_debug_cpu_cti0__CTIINTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINTACK = 32'h000000FF; + +parameter debug_cpu_cti0__CTIAPPSET = 32'hF8898014; +parameter val_debug_cpu_cti0__CTIAPPSET = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPSET = 32'h0000000F; + +parameter debug_cpu_cti0__CTIAPPCLEAR = 32'hF8898018; +parameter val_debug_cpu_cti0__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cpu_cti0__CTIAPPPULSE = 32'hF889801C; +parameter val_debug_cpu_cti0__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN0 = 32'hF8898020; +parameter val_debug_cpu_cti0__CTIINEN0 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN0 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN1 = 32'hF8898024; +parameter val_debug_cpu_cti0__CTIINEN1 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN1 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN2 = 32'hF8898028; +parameter val_debug_cpu_cti0__CTIINEN2 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN2 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN3 = 32'hF889802C; +parameter val_debug_cpu_cti0__CTIINEN3 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN3 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN4 = 32'hF8898030; +parameter val_debug_cpu_cti0__CTIINEN4 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN4 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN5 = 32'hF8898034; +parameter val_debug_cpu_cti0__CTIINEN5 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN5 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN6 = 32'hF8898038; +parameter val_debug_cpu_cti0__CTIINEN6 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN6 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN7 = 32'hF889803C; +parameter val_debug_cpu_cti0__CTIINEN7 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN7 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN0 = 32'hF88980A0; +parameter val_debug_cpu_cti0__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN1 = 32'hF88980A4; +parameter val_debug_cpu_cti0__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN2 = 32'hF88980A8; +parameter val_debug_cpu_cti0__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN3 = 32'hF88980AC; +parameter val_debug_cpu_cti0__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN4 = 32'hF88980B0; +parameter val_debug_cpu_cti0__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN5 = 32'hF88980B4; +parameter val_debug_cpu_cti0__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN6 = 32'hF88980B8; +parameter val_debug_cpu_cti0__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN7 = 32'hF88980BC; +parameter val_debug_cpu_cti0__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cpu_cti0__CTITRIGINSTATUS = 32'hF8898130; +parameter val_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cpu_cti0__CTITRIGOUTSTATUS = 32'hF8898134; +parameter val_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cpu_cti0__CTICHINSTATUS = 32'hF8898138; +parameter val_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000; + +parameter debug_cpu_cti0__CTICHOUTSTATUS = 32'hF889813C; +parameter val_debug_cpu_cti0__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cpu_cti0__CTIGATE = 32'hF8898140; +parameter val_debug_cpu_cti0__CTIGATE = 32'h0000000F; +parameter mask_debug_cpu_cti0__CTIGATE = 32'h0000000F; + +parameter debug_cpu_cti0__ASICCTL = 32'hF8898144; +parameter val_debug_cpu_cti0__ASICCTL = 32'h00000000; +parameter mask_debug_cpu_cti0__ASICCTL = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHINACK = 32'hF8898EDC; +parameter val_debug_cpu_cti0__ITCHINACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHINACK = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGINACK = 32'hF8898EE0; +parameter val_debug_cpu_cti0__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGINACK = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHOUT = 32'hF8898EE4; +parameter val_debug_cpu_cti0__ITCHOUT = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHOUT = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGOUT = 32'hF8898EE8; +parameter val_debug_cpu_cti0__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGOUT = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHOUTACK = 32'hF8898EEC; +parameter val_debug_cpu_cti0__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHOUTACK = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGOUTACK = 32'hF8898EF0; +parameter val_debug_cpu_cti0__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHIN = 32'hF8898EF4; +parameter val_debug_cpu_cti0__ITCHIN = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHIN = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGIN = 32'hF8898EF8; +parameter val_debug_cpu_cti0__ITTRIGIN = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGIN = 32'h000000FF; + +parameter debug_cpu_cti0__ITCTRL = 32'hF8898F00; +parameter val_debug_cpu_cti0__ITCTRL = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCTRL = 32'h00000001; + +parameter debug_cpu_cti0__CTSR = 32'hF8898FA0; +parameter val_debug_cpu_cti0__CTSR = 32'h0000000F; +parameter mask_debug_cpu_cti0__CTSR = 32'h0000000F; + +parameter debug_cpu_cti0__CTCR = 32'hF8898FA4; +parameter val_debug_cpu_cti0__CTCR = 32'h00000000; +parameter mask_debug_cpu_cti0__CTCR = 32'h0000000F; + +parameter debug_cpu_cti0__LAR = 32'hF8898FB0; +parameter val_debug_cpu_cti0__LAR = 32'h00000000; +parameter mask_debug_cpu_cti0__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_cti0__LSR = 32'hF8898FB4; +parameter val_debug_cpu_cti0__LSR = 32'h00000003; +parameter mask_debug_cpu_cti0__LSR = 32'h00000007; + +parameter debug_cpu_cti0__ASR = 32'hF8898FB8; +parameter val_debug_cpu_cti0__ASR = 32'h00000005; +parameter mask_debug_cpu_cti0__ASR = 32'h00000005; + +parameter debug_cpu_cti0__DEVID = 32'hF8898FC8; +parameter val_debug_cpu_cti0__DEVID = 32'h00040800; +parameter mask_debug_cpu_cti0__DEVID = 32'h000FFFFF; + +parameter debug_cpu_cti0__DTIR = 32'hF8898FCC; +parameter val_debug_cpu_cti0__DTIR = 32'h00000014; +parameter mask_debug_cpu_cti0__DTIR = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID4 = 32'hF8898FD0; +parameter val_debug_cpu_cti0__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_cti0__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID5 = 32'hF8898FD4; +parameter val_debug_cpu_cti0__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID6 = 32'hF8898FD8; +parameter val_debug_cpu_cti0__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID7 = 32'hF8898FDC; +parameter val_debug_cpu_cti0__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID0 = 32'hF8898FE0; +parameter val_debug_cpu_cti0__PERIPHID0 = 32'h00000006; +parameter mask_debug_cpu_cti0__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID1 = 32'hF8898FE4; +parameter val_debug_cpu_cti0__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_cti0__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID2 = 32'hF8898FE8; +parameter val_debug_cpu_cti0__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cpu_cti0__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID3 = 32'hF8898FEC; +parameter val_debug_cpu_cti0__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID0 = 32'hF8898FF0; +parameter val_debug_cpu_cti0__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_cti0__COMPID0 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID1 = 32'hF8898FF4; +parameter val_debug_cpu_cti0__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_cti0__COMPID1 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID2 = 32'hF8898FF8; +parameter val_debug_cpu_cti0__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_cti0__COMPID2 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID3 = 32'hF8898FFC; +parameter val_debug_cpu_cti0__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_cti0__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_cti1 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_cti1__CTICONTROL = 32'hF8899000; +parameter val_debug_cpu_cti1__CTICONTROL = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICONTROL = 32'h00000001; + +parameter debug_cpu_cti1__CTIINTACK = 32'hF8899010; +parameter val_debug_cpu_cti1__CTIINTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINTACK = 32'h000000FF; + +parameter debug_cpu_cti1__CTIAPPSET = 32'hF8899014; +parameter val_debug_cpu_cti1__CTIAPPSET = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPSET = 32'h0000000F; + +parameter debug_cpu_cti1__CTIAPPCLEAR = 32'hF8899018; +parameter val_debug_cpu_cti1__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cpu_cti1__CTIAPPPULSE = 32'hF889901C; +parameter val_debug_cpu_cti1__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN0 = 32'hF8899020; +parameter val_debug_cpu_cti1__CTIINEN0 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN0 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN1 = 32'hF8899024; +parameter val_debug_cpu_cti1__CTIINEN1 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN1 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN2 = 32'hF8899028; +parameter val_debug_cpu_cti1__CTIINEN2 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN2 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN3 = 32'hF889902C; +parameter val_debug_cpu_cti1__CTIINEN3 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN3 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN4 = 32'hF8899030; +parameter val_debug_cpu_cti1__CTIINEN4 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN4 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN5 = 32'hF8899034; +parameter val_debug_cpu_cti1__CTIINEN5 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN5 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN6 = 32'hF8899038; +parameter val_debug_cpu_cti1__CTIINEN6 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN6 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN7 = 32'hF889903C; +parameter val_debug_cpu_cti1__CTIINEN7 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN7 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN0 = 32'hF88990A0; +parameter val_debug_cpu_cti1__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN1 = 32'hF88990A4; +parameter val_debug_cpu_cti1__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN2 = 32'hF88990A8; +parameter val_debug_cpu_cti1__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN3 = 32'hF88990AC; +parameter val_debug_cpu_cti1__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN4 = 32'hF88990B0; +parameter val_debug_cpu_cti1__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN5 = 32'hF88990B4; +parameter val_debug_cpu_cti1__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN6 = 32'hF88990B8; +parameter val_debug_cpu_cti1__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN7 = 32'hF88990BC; +parameter val_debug_cpu_cti1__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cpu_cti1__CTITRIGINSTATUS = 32'hF8899130; +parameter val_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cpu_cti1__CTITRIGOUTSTATUS = 32'hF8899134; +parameter val_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cpu_cti1__CTICHINSTATUS = 32'hF8899138; +parameter val_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000; + +parameter debug_cpu_cti1__CTICHOUTSTATUS = 32'hF889913C; +parameter val_debug_cpu_cti1__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cpu_cti1__CTIGATE = 32'hF8899140; +parameter val_debug_cpu_cti1__CTIGATE = 32'h0000000F; +parameter mask_debug_cpu_cti1__CTIGATE = 32'h0000000F; + +parameter debug_cpu_cti1__ASICCTL = 32'hF8899144; +parameter val_debug_cpu_cti1__ASICCTL = 32'h00000000; +parameter mask_debug_cpu_cti1__ASICCTL = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHINACK = 32'hF8899EDC; +parameter val_debug_cpu_cti1__ITCHINACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHINACK = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGINACK = 32'hF8899EE0; +parameter val_debug_cpu_cti1__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGINACK = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHOUT = 32'hF8899EE4; +parameter val_debug_cpu_cti1__ITCHOUT = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHOUT = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGOUT = 32'hF8899EE8; +parameter val_debug_cpu_cti1__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGOUT = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHOUTACK = 32'hF8899EEC; +parameter val_debug_cpu_cti1__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHOUTACK = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGOUTACK = 32'hF8899EF0; +parameter val_debug_cpu_cti1__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHIN = 32'hF8899EF4; +parameter val_debug_cpu_cti1__ITCHIN = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHIN = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGIN = 32'hF8899EF8; +parameter val_debug_cpu_cti1__ITTRIGIN = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGIN = 32'h000000FF; + +parameter debug_cpu_cti1__ITCTRL = 32'hF8899F00; +parameter val_debug_cpu_cti1__ITCTRL = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCTRL = 32'h00000001; + +parameter debug_cpu_cti1__CTSR = 32'hF8899FA0; +parameter val_debug_cpu_cti1__CTSR = 32'h0000000F; +parameter mask_debug_cpu_cti1__CTSR = 32'h0000000F; + +parameter debug_cpu_cti1__CTCR = 32'hF8899FA4; +parameter val_debug_cpu_cti1__CTCR = 32'h00000000; +parameter mask_debug_cpu_cti1__CTCR = 32'h0000000F; + +parameter debug_cpu_cti1__LAR = 32'hF8899FB0; +parameter val_debug_cpu_cti1__LAR = 32'h00000000; +parameter mask_debug_cpu_cti1__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_cti1__LSR = 32'hF8899FB4; +parameter val_debug_cpu_cti1__LSR = 32'h00000003; +parameter mask_debug_cpu_cti1__LSR = 32'h00000007; + +parameter debug_cpu_cti1__ASR = 32'hF8899FB8; +parameter val_debug_cpu_cti1__ASR = 32'h00000005; +parameter mask_debug_cpu_cti1__ASR = 32'h00000005; + +parameter debug_cpu_cti1__DEVID = 32'hF8899FC8; +parameter val_debug_cpu_cti1__DEVID = 32'h00040800; +parameter mask_debug_cpu_cti1__DEVID = 32'h000FFFFF; + +parameter debug_cpu_cti1__DTIR = 32'hF8899FCC; +parameter val_debug_cpu_cti1__DTIR = 32'h00000014; +parameter mask_debug_cpu_cti1__DTIR = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID4 = 32'hF8899FD0; +parameter val_debug_cpu_cti1__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_cti1__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID5 = 32'hF8899FD4; +parameter val_debug_cpu_cti1__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID6 = 32'hF8899FD8; +parameter val_debug_cpu_cti1__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID7 = 32'hF8899FDC; +parameter val_debug_cpu_cti1__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID0 = 32'hF8899FE0; +parameter val_debug_cpu_cti1__PERIPHID0 = 32'h00000006; +parameter mask_debug_cpu_cti1__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID1 = 32'hF8899FE4; +parameter val_debug_cpu_cti1__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_cti1__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID2 = 32'hF8899FE8; +parameter val_debug_cpu_cti1__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cpu_cti1__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID3 = 32'hF8899FEC; +parameter val_debug_cpu_cti1__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID0 = 32'hF8899FF0; +parameter val_debug_cpu_cti1__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_cti1__COMPID0 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID1 = 32'hF8899FF4; +parameter val_debug_cpu_cti1__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_cti1__COMPID1 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID2 = 32'hF8899FF8; +parameter val_debug_cpu_cti1__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_cti1__COMPID2 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID3 = 32'hF8899FFC; +parameter val_debug_cpu_cti1__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_cti1__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_pmu0 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_pmu0__PMXEVCNTR0 = 32'hF8891000; +parameter val_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR1 = 32'hF8891004; +parameter val_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR2 = 32'hF8891008; +parameter val_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR3 = 32'hF889100C; +parameter val_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR4 = 32'hF8891010; +parameter val_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR5 = 32'hF8891014; +parameter val_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000; + +parameter debug_cpu_pmu0__PMCCNTR = 32'hF889107C; +parameter val_debug_cpu_pmu0__PMCCNTR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCCNTR = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER0 = 32'hF8891400; +parameter val_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER1 = 32'hF8891404; +parameter val_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER2 = 32'hF8891408; +parameter val_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER3 = 32'hF889140C; +parameter val_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER4 = 32'hF8891410; +parameter val_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER5 = 32'hF8891414; +parameter val_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000; + +parameter debug_cpu_pmu0__PMCNTENSET = 32'hF8891C00; +parameter val_debug_cpu_pmu0__PMCNTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCNTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMCNTENCLR = 32'hF8891C20; +parameter val_debug_cpu_pmu0__PMCNTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCNTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMINTENSET = 32'hF8891C40; +parameter val_debug_cpu_pmu0__PMINTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMINTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMINTENCLR = 32'hF8891C60; +parameter val_debug_cpu_pmu0__PMINTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMINTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMOVSR = 32'hF8891C80; +parameter val_debug_cpu_pmu0__PMOVSR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMOVSR = 32'h00000000; + +parameter debug_cpu_pmu0__PMSWINC = 32'hF8891CA0; +parameter val_debug_cpu_pmu0__PMSWINC = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMSWINC = 32'h00000000; + +parameter debug_cpu_pmu0__PMCR = 32'hF8891E04; +parameter val_debug_cpu_pmu0__PMCR = 32'h41093000; +parameter mask_debug_cpu_pmu0__PMCR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMUSERENR = 32'hF8891E08; +parameter val_debug_cpu_pmu0__PMUSERENR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMUSERENR = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_pmu1 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_pmu1__PMXEVCNTR0 = 32'hF8893000; +parameter val_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR1 = 32'hF8893004; +parameter val_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR2 = 32'hF8893008; +parameter val_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR3 = 32'hF889300C; +parameter val_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR4 = 32'hF8893010; +parameter val_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR5 = 32'hF8893014; +parameter val_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000; + +parameter debug_cpu_pmu1__PMCCNTR = 32'hF889307C; +parameter val_debug_cpu_pmu1__PMCCNTR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCCNTR = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER0 = 32'hF8893400; +parameter val_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER1 = 32'hF8893404; +parameter val_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER2 = 32'hF8893408; +parameter val_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER3 = 32'hF889340C; +parameter val_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER4 = 32'hF8893410; +parameter val_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER5 = 32'hF8893414; +parameter val_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000; + +parameter debug_cpu_pmu1__PMCNTENSET = 32'hF8893C00; +parameter val_debug_cpu_pmu1__PMCNTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCNTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMCNTENCLR = 32'hF8893C20; +parameter val_debug_cpu_pmu1__PMCNTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCNTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMINTENSET = 32'hF8893C40; +parameter val_debug_cpu_pmu1__PMINTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMINTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMINTENCLR = 32'hF8893C60; +parameter val_debug_cpu_pmu1__PMINTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMINTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMOVSR = 32'hF8893C80; +parameter val_debug_cpu_pmu1__PMOVSR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMOVSR = 32'h00000000; + +parameter debug_cpu_pmu1__PMSWINC = 32'hF8893CA0; +parameter val_debug_cpu_pmu1__PMSWINC = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMSWINC = 32'h00000000; + +parameter debug_cpu_pmu1__PMCR = 32'hF8893E04; +parameter val_debug_cpu_pmu1__PMCR = 32'h41093000; +parameter mask_debug_cpu_pmu1__PMCR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMUSERENR = 32'hF8893E08; +parameter val_debug_cpu_pmu1__PMUSERENR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMUSERENR = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_ptm0 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_ptm0__ETMCR = 32'hF889C000; +parameter val_debug_cpu_ptm0__ETMCR = 32'h00000400; +parameter mask_debug_cpu_ptm0__ETMCR = 32'h3FFFFFFF; + +parameter debug_cpu_ptm0__ETMCCR = 32'hF889C004; +parameter val_debug_cpu_ptm0__ETMCCR = 32'h8D294004; +parameter mask_debug_cpu_ptm0__ETMCCR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMTRIGGER = 32'hF889C008; +parameter val_debug_cpu_ptm0__ETMTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTRIGGER = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSR = 32'hF889C010; +parameter val_debug_cpu_ptm0__ETMSR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSR = 32'h0000000F; + +parameter debug_cpu_ptm0__ETMSCR = 32'hF889C014; +parameter val_debug_cpu_ptm0__ETMSCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSCR = 32'h00007FFF; + +parameter debug_cpu_ptm0__ETMTSSCR = 32'hF889C018; +parameter val_debug_cpu_ptm0__ETMTSSCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTSSCR = 32'h00FFFFFF; + +parameter debug_cpu_ptm0__ETMTECR1 = 32'hF889C024; +parameter val_debug_cpu_ptm0__ETMTECR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTECR1 = 32'h03FFFFFF; + +parameter debug_cpu_ptm0__ETMACVR1 = 32'hF889C040; +parameter val_debug_cpu_ptm0__ETMACVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR2 = 32'hF889C044; +parameter val_debug_cpu_ptm0__ETMACVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR2 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR3 = 32'hF889C048; +parameter val_debug_cpu_ptm0__ETMACVR3 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR3 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR4 = 32'hF889C04C; +parameter val_debug_cpu_ptm0__ETMACVR4 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR4 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR5 = 32'hF889C050; +parameter val_debug_cpu_ptm0__ETMACVR5 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR5 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR6 = 32'hF889C054; +parameter val_debug_cpu_ptm0__ETMACVR6 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR6 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR7 = 32'hF889C058; +parameter val_debug_cpu_ptm0__ETMACVR7 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR7 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR8 = 32'hF889C05C; +parameter val_debug_cpu_ptm0__ETMACVR8 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR8 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACTR1 = 32'hF889C080; +parameter val_debug_cpu_ptm0__ETMACTR1 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR1 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR2 = 32'hF889C084; +parameter val_debug_cpu_ptm0__ETMACTR2 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR2 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR3 = 32'hF889C088; +parameter val_debug_cpu_ptm0__ETMACTR3 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR3 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR4 = 32'hF889C08C; +parameter val_debug_cpu_ptm0__ETMACTR4 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR4 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR5 = 32'hF889C090; +parameter val_debug_cpu_ptm0__ETMACTR5 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR5 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR6 = 32'hF889C094; +parameter val_debug_cpu_ptm0__ETMACTR6 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR6 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR7 = 32'hF889C098; +parameter val_debug_cpu_ptm0__ETMACTR7 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR7 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR8 = 32'hF889C09C; +parameter val_debug_cpu_ptm0__ETMACTR8 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR8 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMCNTRLDVR1 = 32'hF889C140; +parameter val_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDVR2 = 32'hF889C144; +parameter val_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTENR1 = 32'hF889C150; +parameter val_debug_cpu_ptm0__ETMCNTENR1 = 32'h00020000; +parameter mask_debug_cpu_ptm0__ETMCNTENR1 = 32'h0003FFFF; + +parameter debug_cpu_ptm0__ETMCNTENR2 = 32'hF889C154; +parameter val_debug_cpu_ptm0__ETMCNTENR2 = 32'h00020000; +parameter mask_debug_cpu_ptm0__ETMCNTENR2 = 32'h0003FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'hF889C160; +parameter val_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'hF889C164; +parameter val_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCNTVR1 = 32'hF889C170; +parameter val_debug_cpu_ptm0__ETMCNTVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTVR2 = 32'hF889C174; +parameter val_debug_cpu_ptm0__ETMCNTVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMSQ12EVR = 32'hF889C180; +parameter val_debug_cpu_ptm0__ETMSQ12EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ12EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ21EVR = 32'hF889C184; +parameter val_debug_cpu_ptm0__ETMSQ21EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ21EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ23EVR = 32'hF889C188; +parameter val_debug_cpu_ptm0__ETMSQ23EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ23EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ31EVR = 32'hF889C18C; +parameter val_debug_cpu_ptm0__ETMSQ31EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ31EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ32EVR = 32'hF889C190; +parameter val_debug_cpu_ptm0__ETMSQ32EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ32EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ13EVR = 32'hF889C194; +parameter val_debug_cpu_ptm0__ETMSQ13EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ13EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQR = 32'hF889C19C; +parameter val_debug_cpu_ptm0__ETMSQR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQR = 32'h00000003; + +parameter debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'hF889C1A0; +parameter val_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'hF889C1A4; +parameter val_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCIDCVR1 = 32'hF889C1B0; +parameter val_debug_cpu_ptm0__ETMCIDCVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCIDCVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMCIDCMR = 32'hF889C1BC; +parameter val_debug_cpu_ptm0__ETMCIDCMR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCIDCMR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMSYNCFR = 32'hF889C1E0; +parameter val_debug_cpu_ptm0__ETMSYNCFR = 32'h00000400; +parameter mask_debug_cpu_ptm0__ETMSYNCFR = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMIDR = 32'hF889C1E4; +parameter val_debug_cpu_ptm0__ETMIDR = 32'h411CF300; +parameter mask_debug_cpu_ptm0__ETMIDR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMCCER = 32'hF889C1E8; +parameter val_debug_cpu_ptm0__ETMCCER = 32'h00C019A2; +parameter mask_debug_cpu_ptm0__ETMCCER = 32'h03FFFFFF; + +parameter debug_cpu_ptm0__ETMEXTINSELR = 32'hF889C1EC; +parameter val_debug_cpu_ptm0__ETMEXTINSELR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTINSELR = 32'h00003FFF; + +parameter debug_cpu_ptm0__ETMAUXCR = 32'hF889C1FC; +parameter val_debug_cpu_ptm0__ETMAUXCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMAUXCR = 32'h0000000F; + +parameter debug_cpu_ptm0__ETMTRACEIDR = 32'hF889C200; +parameter val_debug_cpu_ptm0__ETMTRACEIDR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTRACEIDR = 32'h0000007F; + +parameter debug_cpu_ptm0__OSLSR = 32'hF889C304; +parameter val_debug_cpu_ptm0__OSLSR = 32'h00000000; +parameter mask_debug_cpu_ptm0__OSLSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMPDSR = 32'hF889C314; +parameter val_debug_cpu_ptm0__ETMPDSR = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMPDSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ITMISCOUT = 32'hF889CEDC; +parameter val_debug_cpu_ptm0__ITMISCOUT = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITMISCOUT = 32'h000003FF; + +parameter debug_cpu_ptm0__ITMISCIN = 32'hF889CEE0; +parameter val_debug_cpu_ptm0__ITMISCIN = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITMISCIN = 32'h00000020; + +parameter debug_cpu_ptm0__ITTRIGGER = 32'hF889CEE8; +parameter val_debug_cpu_ptm0__ITTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITTRIGGER = 32'h00000001; + +parameter debug_cpu_ptm0__ITATBDATA0 = 32'hF889CEEC; +parameter val_debug_cpu_ptm0__ITATBDATA0 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBDATA0 = 32'h0000001F; + +parameter debug_cpu_ptm0__ITATBCTR2 = 32'hF889CEF0; +parameter val_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000; + +parameter debug_cpu_ptm0__ITATBID = 32'hF889CEF4; +parameter val_debug_cpu_ptm0__ITATBID = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBID = 32'h0000007F; + +parameter debug_cpu_ptm0__ITATBCTR0 = 32'hF889CEF8; +parameter val_debug_cpu_ptm0__ITATBCTR0 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBCTR0 = 32'h000003FF; + +parameter debug_cpu_ptm0__ETMITCTRL = 32'hF889CF00; +parameter val_debug_cpu_ptm0__ETMITCTRL = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMITCTRL = 32'h00000001; + +parameter debug_cpu_ptm0__CTSR = 32'hF889CFA0; +parameter val_debug_cpu_ptm0__CTSR = 32'h000000FF; +parameter mask_debug_cpu_ptm0__CTSR = 32'h000000FF; + +parameter debug_cpu_ptm0__CTCR = 32'hF889CFA4; +parameter val_debug_cpu_ptm0__CTCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__CTCR = 32'h000000FF; + +parameter debug_cpu_ptm0__LAR = 32'hF889CFB0; +parameter val_debug_cpu_ptm0__LAR = 32'h00000000; +parameter mask_debug_cpu_ptm0__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__LSR = 32'hF889CFB4; +parameter val_debug_cpu_ptm0__LSR = 32'h00000003; +parameter mask_debug_cpu_ptm0__LSR = 32'h00000007; + +parameter debug_cpu_ptm0__ASR = 32'hF889CFB8; +parameter val_debug_cpu_ptm0__ASR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ASR = 32'h000000F3; + +parameter debug_cpu_ptm0__DEVID = 32'hF889CFC8; +parameter val_debug_cpu_ptm0__DEVID = 32'h00000000; +parameter mask_debug_cpu_ptm0__DEVID = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__DTIR = 32'hF889CFCC; +parameter val_debug_cpu_ptm0__DTIR = 32'h00000013; +parameter mask_debug_cpu_ptm0__DTIR = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID4 = 32'hF889CFD0; +parameter val_debug_cpu_ptm0__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_ptm0__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID5 = 32'hF889CFD4; +parameter val_debug_cpu_ptm0__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID6 = 32'hF889CFD8; +parameter val_debug_cpu_ptm0__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID7 = 32'hF889CFDC; +parameter val_debug_cpu_ptm0__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID0 = 32'hF889CFE0; +parameter val_debug_cpu_ptm0__PERIPHID0 = 32'h00000050; +parameter mask_debug_cpu_ptm0__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID1 = 32'hF889CFE4; +parameter val_debug_cpu_ptm0__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_ptm0__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID2 = 32'hF889CFE8; +parameter val_debug_cpu_ptm0__PERIPHID2 = 32'h0000001B; +parameter mask_debug_cpu_ptm0__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID3 = 32'hF889CFEC; +parameter val_debug_cpu_ptm0__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID0 = 32'hF889CFF0; +parameter val_debug_cpu_ptm0__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_ptm0__COMPID0 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID1 = 32'hF889CFF4; +parameter val_debug_cpu_ptm0__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_ptm0__COMPID1 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID2 = 32'hF889CFF8; +parameter val_debug_cpu_ptm0__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_ptm0__COMPID2 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID3 = 32'hF889CFFC; +parameter val_debug_cpu_ptm0__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_ptm0__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_ptm1 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_ptm1__ETMCR = 32'hF889D000; +parameter val_debug_cpu_ptm1__ETMCR = 32'h00000400; +parameter mask_debug_cpu_ptm1__ETMCR = 32'h3FFFFFFF; + +parameter debug_cpu_ptm1__ETMCCR = 32'hF889D004; +parameter val_debug_cpu_ptm1__ETMCCR = 32'h8D294004; +parameter mask_debug_cpu_ptm1__ETMCCR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMTRIGGER = 32'hF889D008; +parameter val_debug_cpu_ptm1__ETMTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTRIGGER = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSR = 32'hF889D010; +parameter val_debug_cpu_ptm1__ETMSR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSR = 32'h0000000F; + +parameter debug_cpu_ptm1__ETMSCR = 32'hF889D014; +parameter val_debug_cpu_ptm1__ETMSCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSCR = 32'h00007FFF; + +parameter debug_cpu_ptm1__ETMTSSCR = 32'hF889D018; +parameter val_debug_cpu_ptm1__ETMTSSCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTSSCR = 32'h00FFFFFF; + +parameter debug_cpu_ptm1__ETMTECR1 = 32'hF889D024; +parameter val_debug_cpu_ptm1__ETMTECR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTECR1 = 32'h03FFFFFF; + +parameter debug_cpu_ptm1__ETMACVR1 = 32'hF889D040; +parameter val_debug_cpu_ptm1__ETMACVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR2 = 32'hF889D044; +parameter val_debug_cpu_ptm1__ETMACVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR2 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR3 = 32'hF889D048; +parameter val_debug_cpu_ptm1__ETMACVR3 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR3 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR4 = 32'hF889D04C; +parameter val_debug_cpu_ptm1__ETMACVR4 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR4 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR5 = 32'hF889D050; +parameter val_debug_cpu_ptm1__ETMACVR5 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR5 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR6 = 32'hF889D054; +parameter val_debug_cpu_ptm1__ETMACVR6 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR6 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR7 = 32'hF889D058; +parameter val_debug_cpu_ptm1__ETMACVR7 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR7 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR8 = 32'hF889D05C; +parameter val_debug_cpu_ptm1__ETMACVR8 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR8 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACTR1 = 32'hF889D080; +parameter val_debug_cpu_ptm1__ETMACTR1 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR1 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR2 = 32'hF889D084; +parameter val_debug_cpu_ptm1__ETMACTR2 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR2 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR3 = 32'hF889D088; +parameter val_debug_cpu_ptm1__ETMACTR3 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR3 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR4 = 32'hF889D08C; +parameter val_debug_cpu_ptm1__ETMACTR4 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR4 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR5 = 32'hF889D090; +parameter val_debug_cpu_ptm1__ETMACTR5 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR5 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR6 = 32'hF889D094; +parameter val_debug_cpu_ptm1__ETMACTR6 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR6 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR7 = 32'hF889D098; +parameter val_debug_cpu_ptm1__ETMACTR7 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR7 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR8 = 32'hF889D09C; +parameter val_debug_cpu_ptm1__ETMACTR8 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR8 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMCNTRLDVR1 = 32'hF889D140; +parameter val_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDVR2 = 32'hF889D144; +parameter val_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTENR1 = 32'hF889D150; +parameter val_debug_cpu_ptm1__ETMCNTENR1 = 32'h00020000; +parameter mask_debug_cpu_ptm1__ETMCNTENR1 = 32'h0003FFFF; + +parameter debug_cpu_ptm1__ETMCNTENR2 = 32'hF889D154; +parameter val_debug_cpu_ptm1__ETMCNTENR2 = 32'h00020000; +parameter mask_debug_cpu_ptm1__ETMCNTENR2 = 32'h0003FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'hF889D160; +parameter val_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'hF889D164; +parameter val_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCNTVR1 = 32'hF889D170; +parameter val_debug_cpu_ptm1__ETMCNTVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTVR2 = 32'hF889D174; +parameter val_debug_cpu_ptm1__ETMCNTVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMSQ12EVR = 32'hF889D180; +parameter val_debug_cpu_ptm1__ETMSQ12EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ12EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ21EVR = 32'hF889D184; +parameter val_debug_cpu_ptm1__ETMSQ21EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ21EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ23EVR = 32'hF889D188; +parameter val_debug_cpu_ptm1__ETMSQ23EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ23EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ31EVR = 32'hF889D18C; +parameter val_debug_cpu_ptm1__ETMSQ31EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ31EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ32EVR = 32'hF889D190; +parameter val_debug_cpu_ptm1__ETMSQ32EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ32EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ13EVR = 32'hF889D194; +parameter val_debug_cpu_ptm1__ETMSQ13EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ13EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQR = 32'hF889D19C; +parameter val_debug_cpu_ptm1__ETMSQR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQR = 32'h00000003; + +parameter debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'hF889D1A0; +parameter val_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'hF889D1A4; +parameter val_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCIDCVR1 = 32'hF889D1B0; +parameter val_debug_cpu_ptm1__ETMCIDCVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCIDCVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMCIDCMR = 32'hF889D1BC; +parameter val_debug_cpu_ptm1__ETMCIDCMR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCIDCMR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMSYNCFR = 32'hF889D1E0; +parameter val_debug_cpu_ptm1__ETMSYNCFR = 32'h00000400; +parameter mask_debug_cpu_ptm1__ETMSYNCFR = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMIDR = 32'hF889D1E4; +parameter val_debug_cpu_ptm1__ETMIDR = 32'h411CF300; +parameter mask_debug_cpu_ptm1__ETMIDR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMCCER = 32'hF889D1E8; +parameter val_debug_cpu_ptm1__ETMCCER = 32'h00C019A2; +parameter mask_debug_cpu_ptm1__ETMCCER = 32'h03FFFFFF; + +parameter debug_cpu_ptm1__ETMEXTINSELR = 32'hF889D1EC; +parameter val_debug_cpu_ptm1__ETMEXTINSELR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTINSELR = 32'h00003FFF; + +parameter debug_cpu_ptm1__ETMAUXCR = 32'hF889D1FC; +parameter val_debug_cpu_ptm1__ETMAUXCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMAUXCR = 32'h0000000F; + +parameter debug_cpu_ptm1__ETMTRACEIDR = 32'hF889D200; +parameter val_debug_cpu_ptm1__ETMTRACEIDR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTRACEIDR = 32'h0000007F; + +parameter debug_cpu_ptm1__OSLSR = 32'hF889D304; +parameter val_debug_cpu_ptm1__OSLSR = 32'h00000000; +parameter mask_debug_cpu_ptm1__OSLSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMPDSR = 32'hF889D314; +parameter val_debug_cpu_ptm1__ETMPDSR = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMPDSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ITMISCOUT = 32'hF889DEDC; +parameter val_debug_cpu_ptm1__ITMISCOUT = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITMISCOUT = 32'h000003FF; + +parameter debug_cpu_ptm1__ITMISCIN = 32'hF889DEE0; +parameter val_debug_cpu_ptm1__ITMISCIN = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITMISCIN = 32'h00000020; + +parameter debug_cpu_ptm1__ITTRIGGER = 32'hF889DEE8; +parameter val_debug_cpu_ptm1__ITTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITTRIGGER = 32'h00000001; + +parameter debug_cpu_ptm1__ITATBDATA0 = 32'hF889DEEC; +parameter val_debug_cpu_ptm1__ITATBDATA0 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBDATA0 = 32'h0000001F; + +parameter debug_cpu_ptm1__ITATBCTR2 = 32'hF889DEF0; +parameter val_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000; + +parameter debug_cpu_ptm1__ITATBID = 32'hF889DEF4; +parameter val_debug_cpu_ptm1__ITATBID = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBID = 32'h0000007F; + +parameter debug_cpu_ptm1__ITATBCTR0 = 32'hF889DEF8; +parameter val_debug_cpu_ptm1__ITATBCTR0 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBCTR0 = 32'h000003FF; + +parameter debug_cpu_ptm1__ETMITCTRL = 32'hF889DF00; +parameter val_debug_cpu_ptm1__ETMITCTRL = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMITCTRL = 32'h00000001; + +parameter debug_cpu_ptm1__CTSR = 32'hF889DFA0; +parameter val_debug_cpu_ptm1__CTSR = 32'h000000FF; +parameter mask_debug_cpu_ptm1__CTSR = 32'h000000FF; + +parameter debug_cpu_ptm1__CTCR = 32'hF889DFA4; +parameter val_debug_cpu_ptm1__CTCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__CTCR = 32'h000000FF; + +parameter debug_cpu_ptm1__LAR = 32'hF889DFB0; +parameter val_debug_cpu_ptm1__LAR = 32'h00000000; +parameter mask_debug_cpu_ptm1__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__LSR = 32'hF889DFB4; +parameter val_debug_cpu_ptm1__LSR = 32'h00000003; +parameter mask_debug_cpu_ptm1__LSR = 32'h00000007; + +parameter debug_cpu_ptm1__ASR = 32'hF889DFB8; +parameter val_debug_cpu_ptm1__ASR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ASR = 32'h000000F3; + +parameter debug_cpu_ptm1__DEVID = 32'hF889DFC8; +parameter val_debug_cpu_ptm1__DEVID = 32'h00000000; +parameter mask_debug_cpu_ptm1__DEVID = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__DTIR = 32'hF889DFCC; +parameter val_debug_cpu_ptm1__DTIR = 32'h00000013; +parameter mask_debug_cpu_ptm1__DTIR = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID4 = 32'hF889DFD0; +parameter val_debug_cpu_ptm1__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_ptm1__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID5 = 32'hF889DFD4; +parameter val_debug_cpu_ptm1__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID6 = 32'hF889DFD8; +parameter val_debug_cpu_ptm1__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID7 = 32'hF889DFDC; +parameter val_debug_cpu_ptm1__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID0 = 32'hF889DFE0; +parameter val_debug_cpu_ptm1__PERIPHID0 = 32'h00000050; +parameter mask_debug_cpu_ptm1__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID1 = 32'hF889DFE4; +parameter val_debug_cpu_ptm1__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_ptm1__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID2 = 32'hF889DFE8; +parameter val_debug_cpu_ptm1__PERIPHID2 = 32'h0000001B; +parameter mask_debug_cpu_ptm1__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID3 = 32'hF889DFEC; +parameter val_debug_cpu_ptm1__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID0 = 32'hF889DFF0; +parameter val_debug_cpu_ptm1__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_ptm1__COMPID0 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID1 = 32'hF889DFF4; +parameter val_debug_cpu_ptm1__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_ptm1__COMPID1 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID2 = 32'hF889DFF8; +parameter val_debug_cpu_ptm1__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_ptm1__COMPID2 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID3 = 32'hF889DFFC; +parameter val_debug_cpu_ptm1__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_ptm1__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_axim cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_axim__CTICONTROL = 32'hF880A000; +parameter val_debug_cti_axim__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_axim__CTICONTROL = 32'h00000001; + +parameter debug_cti_axim__CTIINTACK = 32'hF880A010; +parameter val_debug_cti_axim__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_axim__CTIINTACK = 32'h000000FF; + +parameter debug_cti_axim__CTIAPPSET = 32'hF880A014; +parameter val_debug_cti_axim__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_axim__CTIAPPCLEAR = 32'hF880A018; +parameter val_debug_cti_axim__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_axim__CTIAPPPULSE = 32'hF880A01C; +parameter val_debug_cti_axim__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN0 = 32'hF880A020; +parameter val_debug_cti_axim__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN1 = 32'hF880A024; +parameter val_debug_cti_axim__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN2 = 32'hF880A028; +parameter val_debug_cti_axim__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN3 = 32'hF880A02C; +parameter val_debug_cti_axim__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN4 = 32'hF880A030; +parameter val_debug_cti_axim__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN5 = 32'hF880A034; +parameter val_debug_cti_axim__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN6 = 32'hF880A038; +parameter val_debug_cti_axim__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN7 = 32'hF880A03C; +parameter val_debug_cti_axim__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN0 = 32'hF880A0A0; +parameter val_debug_cti_axim__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN1 = 32'hF880A0A4; +parameter val_debug_cti_axim__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN2 = 32'hF880A0A8; +parameter val_debug_cti_axim__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN3 = 32'hF880A0AC; +parameter val_debug_cti_axim__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN4 = 32'hF880A0B0; +parameter val_debug_cti_axim__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN5 = 32'hF880A0B4; +parameter val_debug_cti_axim__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN6 = 32'hF880A0B8; +parameter val_debug_cti_axim__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN7 = 32'hF880A0BC; +parameter val_debug_cti_axim__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_axim__CTITRIGINSTATUS = 32'hF880A130; +parameter val_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_axim__CTITRIGOUTSTATUS = 32'hF880A134; +parameter val_debug_cti_axim__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_axim__CTICHINSTATUS = 32'hF880A138; +parameter val_debug_cti_axim__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_axim__CTICHOUTSTATUS = 32'hF880A13C; +parameter val_debug_cti_axim__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_axim__CTIGATE = 32'hF880A140; +parameter val_debug_cti_axim__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_axim__CTIGATE = 32'h0000000F; + +parameter debug_cti_axim__ASICCTL = 32'hF880A144; +parameter val_debug_cti_axim__ASICCTL = 32'h00000000; +parameter mask_debug_cti_axim__ASICCTL = 32'h000000FF; + +parameter debug_cti_axim__ITCHINACK = 32'hF880AEDC; +parameter val_debug_cti_axim__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_axim__ITCHINACK = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGINACK = 32'hF880AEE0; +parameter val_debug_cti_axim__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_axim__ITCHOUT = 32'hF880AEE4; +parameter val_debug_cti_axim__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_axim__ITCHOUT = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGOUT = 32'hF880AEE8; +parameter val_debug_cti_axim__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_axim__ITCHOUTACK = 32'hF880AEEC; +parameter val_debug_cti_axim__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_axim__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGOUTACK = 32'hF880AEF0; +parameter val_debug_cti_axim__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_axim__ITCHIN = 32'hF880AEF4; +parameter val_debug_cti_axim__ITCHIN = 32'h00000000; +parameter mask_debug_cti_axim__ITCHIN = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGIN = 32'hF880AEF8; +parameter val_debug_cti_axim__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_axim__ITCTRL = 32'hF880AF00; +parameter val_debug_cti_axim__ITCTRL = 32'h00000000; +parameter mask_debug_cti_axim__ITCTRL = 32'h00000001; + +parameter debug_cti_axim__CTSR = 32'hF880AFA0; +parameter val_debug_cti_axim__CTSR = 32'h0000000F; +parameter mask_debug_cti_axim__CTSR = 32'h0000000F; + +parameter debug_cti_axim__CTCR = 32'hF880AFA4; +parameter val_debug_cti_axim__CTCR = 32'h00000000; +parameter mask_debug_cti_axim__CTCR = 32'h0000000F; + +parameter debug_cti_axim__LAR = 32'hF880AFB0; +parameter val_debug_cti_axim__LAR = 32'h00000000; +parameter mask_debug_cti_axim__LAR = 32'hFFFFFFFF; + +parameter debug_cti_axim__LSR = 32'hF880AFB4; +parameter val_debug_cti_axim__LSR = 32'h00000003; +parameter mask_debug_cti_axim__LSR = 32'h00000007; + +parameter debug_cti_axim__ASR = 32'hF880AFB8; +parameter val_debug_cti_axim__ASR = 32'h00000005; +parameter mask_debug_cti_axim__ASR = 32'h00000005; + +parameter debug_cti_axim__DEVID = 32'hF880AFC8; +parameter val_debug_cti_axim__DEVID = 32'h00040800; +parameter mask_debug_cti_axim__DEVID = 32'h000FFFFF; + +parameter debug_cti_axim__DTIR = 32'hF880AFCC; +parameter val_debug_cti_axim__DTIR = 32'h00000014; +parameter mask_debug_cti_axim__DTIR = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID4 = 32'hF880AFD0; +parameter val_debug_cti_axim__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_axim__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID5 = 32'hF880AFD4; +parameter val_debug_cti_axim__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID6 = 32'hF880AFD8; +parameter val_debug_cti_axim__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID7 = 32'hF880AFDC; +parameter val_debug_cti_axim__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID0 = 32'hF880AFE0; +parameter val_debug_cti_axim__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_axim__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID1 = 32'hF880AFE4; +parameter val_debug_cti_axim__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_axim__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID2 = 32'hF880AFE8; +parameter val_debug_cti_axim__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_axim__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID3 = 32'hF880AFEC; +parameter val_debug_cti_axim__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_axim__COMPID0 = 32'hF880AFF0; +parameter val_debug_cti_axim__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_axim__COMPID0 = 32'h000000FF; + +parameter debug_cti_axim__COMPID1 = 32'hF880AFF4; +parameter val_debug_cti_axim__COMPID1 = 32'h00000090; +parameter mask_debug_cti_axim__COMPID1 = 32'h000000FF; + +parameter debug_cti_axim__COMPID2 = 32'hF880AFF8; +parameter val_debug_cti_axim__COMPID2 = 32'h00000005; +parameter mask_debug_cti_axim__COMPID2 = 32'h000000FF; + +parameter debug_cti_axim__COMPID3 = 32'hF880AFFC; +parameter val_debug_cti_axim__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_axim__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_etb_tpiu cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_etb_tpiu__CTICONTROL = 32'hF8802000; +parameter val_debug_cti_etb_tpiu__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICONTROL = 32'h00000001; + +parameter debug_cti_etb_tpiu__CTIINTACK = 32'hF8802010; +parameter val_debug_cti_etb_tpiu__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINTACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__CTIAPPSET = 32'hF8802014; +parameter val_debug_cti_etb_tpiu__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIAPPCLEAR = 32'hF8802018; +parameter val_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIAPPPULSE = 32'hF880201C; +parameter val_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN0 = 32'hF8802020; +parameter val_debug_cti_etb_tpiu__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN1 = 32'hF8802024; +parameter val_debug_cti_etb_tpiu__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN2 = 32'hF8802028; +parameter val_debug_cti_etb_tpiu__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN3 = 32'hF880202C; +parameter val_debug_cti_etb_tpiu__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN4 = 32'hF8802030; +parameter val_debug_cti_etb_tpiu__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN5 = 32'hF8802034; +parameter val_debug_cti_etb_tpiu__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN6 = 32'hF8802038; +parameter val_debug_cti_etb_tpiu__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN7 = 32'hF880203C; +parameter val_debug_cti_etb_tpiu__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN0 = 32'hF88020A0; +parameter val_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN1 = 32'hF88020A4; +parameter val_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN2 = 32'hF88020A8; +parameter val_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN3 = 32'hF88020AC; +parameter val_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN4 = 32'hF88020B0; +parameter val_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN5 = 32'hF88020B4; +parameter val_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN6 = 32'hF88020B8; +parameter val_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN7 = 32'hF88020BC; +parameter val_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'hF8802130; +parameter val_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'hF8802134; +parameter val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_etb_tpiu__CTICHINSTATUS = 32'hF8802138; +parameter val_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'hF880213C; +parameter val_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIGATE = 32'hF8802140; +parameter val_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ASICCTL = 32'hF8802144; +parameter val_debug_cti_etb_tpiu__ASICCTL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ASICCTL = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHINACK = 32'hF8802EDC; +parameter val_debug_cti_etb_tpiu__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHINACK = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGINACK = 32'hF8802EE0; +parameter val_debug_cti_etb_tpiu__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHOUT = 32'hF8802EE4; +parameter val_debug_cti_etb_tpiu__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHOUT = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGOUT = 32'hF8802EE8; +parameter val_debug_cti_etb_tpiu__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHOUTACK = 32'hF8802EEC; +parameter val_debug_cti_etb_tpiu__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGOUTACK = 32'hF8802EF0; +parameter val_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHIN = 32'hF8802EF4; +parameter val_debug_cti_etb_tpiu__ITCHIN = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHIN = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGIN = 32'hF8802EF8; +parameter val_debug_cti_etb_tpiu__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCTRL = 32'hF8802F00; +parameter val_debug_cti_etb_tpiu__ITCTRL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCTRL = 32'h00000001; + +parameter debug_cti_etb_tpiu__CTSR = 32'hF8802FA0; +parameter val_debug_cti_etb_tpiu__CTSR = 32'h0000000F; +parameter mask_debug_cti_etb_tpiu__CTSR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTCR = 32'hF8802FA4; +parameter val_debug_cti_etb_tpiu__CTCR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTCR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__LAR = 32'hF8802FB0; +parameter val_debug_cti_etb_tpiu__LAR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__LAR = 32'hFFFFFFFF; + +parameter debug_cti_etb_tpiu__LSR = 32'hF8802FB4; +parameter val_debug_cti_etb_tpiu__LSR = 32'h00000003; +parameter mask_debug_cti_etb_tpiu__LSR = 32'h00000007; + +parameter debug_cti_etb_tpiu__ASR = 32'hF8802FB8; +parameter val_debug_cti_etb_tpiu__ASR = 32'h00000005; +parameter mask_debug_cti_etb_tpiu__ASR = 32'h00000005; + +parameter debug_cti_etb_tpiu__DEVID = 32'hF8802FC8; +parameter val_debug_cti_etb_tpiu__DEVID = 32'h00040800; +parameter mask_debug_cti_etb_tpiu__DEVID = 32'h000FFFFF; + +parameter debug_cti_etb_tpiu__DTIR = 32'hF8802FCC; +parameter val_debug_cti_etb_tpiu__DTIR = 32'h00000014; +parameter mask_debug_cti_etb_tpiu__DTIR = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID4 = 32'hF8802FD0; +parameter val_debug_cti_etb_tpiu__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_etb_tpiu__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID5 = 32'hF8802FD4; +parameter val_debug_cti_etb_tpiu__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID6 = 32'hF8802FD8; +parameter val_debug_cti_etb_tpiu__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID7 = 32'hF8802FDC; +parameter val_debug_cti_etb_tpiu__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID0 = 32'hF8802FE0; +parameter val_debug_cti_etb_tpiu__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_etb_tpiu__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID1 = 32'hF8802FE4; +parameter val_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID2 = 32'hF8802FE8; +parameter val_debug_cti_etb_tpiu__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_etb_tpiu__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID3 = 32'hF8802FEC; +parameter val_debug_cti_etb_tpiu__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID0 = 32'hF8802FF0; +parameter val_debug_cti_etb_tpiu__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_etb_tpiu__COMPID0 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID1 = 32'hF8802FF4; +parameter val_debug_cti_etb_tpiu__COMPID1 = 32'h00000090; +parameter mask_debug_cti_etb_tpiu__COMPID1 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID2 = 32'hF8802FF8; +parameter val_debug_cti_etb_tpiu__COMPID2 = 32'h00000005; +parameter mask_debug_cti_etb_tpiu__COMPID2 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID3 = 32'hF8802FFC; +parameter val_debug_cti_etb_tpiu__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_etb_tpiu__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_ftm cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_ftm__CTICONTROL = 32'hF8809000; +parameter val_debug_cti_ftm__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_ftm__CTICONTROL = 32'h00000001; + +parameter debug_cti_ftm__CTIINTACK = 32'hF8809010; +parameter val_debug_cti_ftm__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINTACK = 32'h000000FF; + +parameter debug_cti_ftm__CTIAPPSET = 32'hF8809014; +parameter val_debug_cti_ftm__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_ftm__CTIAPPCLEAR = 32'hF8809018; +parameter val_debug_cti_ftm__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_ftm__CTIAPPPULSE = 32'hF880901C; +parameter val_debug_cti_ftm__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN0 = 32'hF8809020; +parameter val_debug_cti_ftm__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN1 = 32'hF8809024; +parameter val_debug_cti_ftm__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN2 = 32'hF8809028; +parameter val_debug_cti_ftm__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN3 = 32'hF880902C; +parameter val_debug_cti_ftm__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN4 = 32'hF8809030; +parameter val_debug_cti_ftm__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN5 = 32'hF8809034; +parameter val_debug_cti_ftm__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN6 = 32'hF8809038; +parameter val_debug_cti_ftm__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN7 = 32'hF880903C; +parameter val_debug_cti_ftm__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN0 = 32'hF88090A0; +parameter val_debug_cti_ftm__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN1 = 32'hF88090A4; +parameter val_debug_cti_ftm__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN2 = 32'hF88090A8; +parameter val_debug_cti_ftm__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN3 = 32'hF88090AC; +parameter val_debug_cti_ftm__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN4 = 32'hF88090B0; +parameter val_debug_cti_ftm__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN5 = 32'hF88090B4; +parameter val_debug_cti_ftm__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN6 = 32'hF88090B8; +parameter val_debug_cti_ftm__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN7 = 32'hF88090BC; +parameter val_debug_cti_ftm__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_ftm__CTITRIGINSTATUS = 32'hF8809130; +parameter val_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_ftm__CTITRIGOUTSTATUS = 32'hF8809134; +parameter val_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_ftm__CTICHINSTATUS = 32'hF8809138; +parameter val_debug_cti_ftm__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_ftm__CTICHOUTSTATUS = 32'hF880913C; +parameter val_debug_cti_ftm__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_ftm__CTIGATE = 32'hF8809140; +parameter val_debug_cti_ftm__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_ftm__CTIGATE = 32'h0000000F; + +parameter debug_cti_ftm__ASICCTL = 32'hF8809144; +parameter val_debug_cti_ftm__ASICCTL = 32'h00000000; +parameter mask_debug_cti_ftm__ASICCTL = 32'h000000FF; + +parameter debug_cti_ftm__ITCHINACK = 32'hF8809EDC; +parameter val_debug_cti_ftm__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHINACK = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGINACK = 32'hF8809EE0; +parameter val_debug_cti_ftm__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_ftm__ITCHOUT = 32'hF8809EE4; +parameter val_debug_cti_ftm__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHOUT = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGOUT = 32'hF8809EE8; +parameter val_debug_cti_ftm__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_ftm__ITCHOUTACK = 32'hF8809EEC; +parameter val_debug_cti_ftm__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGOUTACK = 32'hF8809EF0; +parameter val_debug_cti_ftm__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_ftm__ITCHIN = 32'hF8809EF4; +parameter val_debug_cti_ftm__ITCHIN = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHIN = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGIN = 32'hF8809EF8; +parameter val_debug_cti_ftm__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_ftm__ITCTRL = 32'hF8809F00; +parameter val_debug_cti_ftm__ITCTRL = 32'h00000000; +parameter mask_debug_cti_ftm__ITCTRL = 32'h00000001; + +parameter debug_cti_ftm__CTSR = 32'hF8809FA0; +parameter val_debug_cti_ftm__CTSR = 32'h0000000F; +parameter mask_debug_cti_ftm__CTSR = 32'h0000000F; + +parameter debug_cti_ftm__CTCR = 32'hF8809FA4; +parameter val_debug_cti_ftm__CTCR = 32'h00000000; +parameter mask_debug_cti_ftm__CTCR = 32'h0000000F; + +parameter debug_cti_ftm__LAR = 32'hF8809FB0; +parameter val_debug_cti_ftm__LAR = 32'h00000000; +parameter mask_debug_cti_ftm__LAR = 32'hFFFFFFFF; + +parameter debug_cti_ftm__LSR = 32'hF8809FB4; +parameter val_debug_cti_ftm__LSR = 32'h00000003; +parameter mask_debug_cti_ftm__LSR = 32'h00000007; + +parameter debug_cti_ftm__ASR = 32'hF8809FB8; +parameter val_debug_cti_ftm__ASR = 32'h00000005; +parameter mask_debug_cti_ftm__ASR = 32'h00000005; + +parameter debug_cti_ftm__DEVID = 32'hF8809FC8; +parameter val_debug_cti_ftm__DEVID = 32'h00040800; +parameter mask_debug_cti_ftm__DEVID = 32'h000FFFFF; + +parameter debug_cti_ftm__DTIR = 32'hF8809FCC; +parameter val_debug_cti_ftm__DTIR = 32'h00000014; +parameter mask_debug_cti_ftm__DTIR = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID4 = 32'hF8809FD0; +parameter val_debug_cti_ftm__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_ftm__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID5 = 32'hF8809FD4; +parameter val_debug_cti_ftm__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID6 = 32'hF8809FD8; +parameter val_debug_cti_ftm__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID7 = 32'hF8809FDC; +parameter val_debug_cti_ftm__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID0 = 32'hF8809FE0; +parameter val_debug_cti_ftm__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_ftm__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID1 = 32'hF8809FE4; +parameter val_debug_cti_ftm__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_ftm__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID2 = 32'hF8809FE8; +parameter val_debug_cti_ftm__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_ftm__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID3 = 32'hF8809FEC; +parameter val_debug_cti_ftm__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID0 = 32'hF8809FF0; +parameter val_debug_cti_ftm__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_ftm__COMPID0 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID1 = 32'hF8809FF4; +parameter val_debug_cti_ftm__COMPID1 = 32'h00000090; +parameter mask_debug_cti_ftm__COMPID1 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID2 = 32'hF8809FF8; +parameter val_debug_cti_ftm__COMPID2 = 32'h00000005; +parameter mask_debug_cti_ftm__COMPID2 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID3 = 32'hF8809FFC; +parameter val_debug_cti_ftm__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_ftm__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_dap_rom dap +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_dap_rom__ROMENTRY00 = 32'hF8800000; +parameter val_debug_dap_rom__ROMENTRY00 = 32'h00001003; +parameter mask_debug_dap_rom__ROMENTRY00 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY01 = 32'hF8800004; +parameter val_debug_dap_rom__ROMENTRY01 = 32'h00002003; +parameter mask_debug_dap_rom__ROMENTRY01 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY02 = 32'hF8800008; +parameter val_debug_dap_rom__ROMENTRY02 = 32'h00003003; +parameter mask_debug_dap_rom__ROMENTRY02 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY03 = 32'hF880000C; +parameter val_debug_dap_rom__ROMENTRY03 = 32'h00004003; +parameter mask_debug_dap_rom__ROMENTRY03 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY04 = 32'hF8800010; +parameter val_debug_dap_rom__ROMENTRY04 = 32'h00005003; +parameter mask_debug_dap_rom__ROMENTRY04 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY05 = 32'hF8800014; +parameter val_debug_dap_rom__ROMENTRY05 = 32'h00009003; +parameter mask_debug_dap_rom__ROMENTRY05 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY06 = 32'hF8800018; +parameter val_debug_dap_rom__ROMENTRY06 = 32'h0000A003; +parameter mask_debug_dap_rom__ROMENTRY06 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY07 = 32'hF880001C; +parameter val_debug_dap_rom__ROMENTRY07 = 32'h0000B003; +parameter mask_debug_dap_rom__ROMENTRY07 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY08 = 32'hF8800020; +parameter val_debug_dap_rom__ROMENTRY08 = 32'h0000C003; +parameter mask_debug_dap_rom__ROMENTRY08 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY09 = 32'hF8800024; +parameter val_debug_dap_rom__ROMENTRY09 = 32'h00080003; +parameter mask_debug_dap_rom__ROMENTRY09 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY10 = 32'hF8800028; +parameter val_debug_dap_rom__ROMENTRY10 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY10 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY11 = 32'hF880002C; +parameter val_debug_dap_rom__ROMENTRY11 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY11 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY12 = 32'hF8800030; +parameter val_debug_dap_rom__ROMENTRY12 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY12 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY13 = 32'hF8800034; +parameter val_debug_dap_rom__ROMENTRY13 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY13 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY14 = 32'hF8800038; +parameter val_debug_dap_rom__ROMENTRY14 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY14 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY15 = 32'hF880003C; +parameter val_debug_dap_rom__ROMENTRY15 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY15 = 32'hFFFFFFFF; + +parameter debug_dap_rom__PERIPHID4 = 32'hF8800FD0; +parameter val_debug_dap_rom__PERIPHID4 = 32'h00000003; +parameter mask_debug_dap_rom__PERIPHID4 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID5 = 32'hF8800FD4; +parameter val_debug_dap_rom__PERIPHID5 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID5 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID6 = 32'hF8800FD8; +parameter val_debug_dap_rom__PERIPHID6 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID6 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID7 = 32'hF8800FDC; +parameter val_debug_dap_rom__PERIPHID7 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID7 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID0 = 32'hF8800FE0; +parameter val_debug_dap_rom__PERIPHID0 = 32'h000000B2; +parameter mask_debug_dap_rom__PERIPHID0 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID1 = 32'hF8800FE4; +parameter val_debug_dap_rom__PERIPHID1 = 32'h00000093; +parameter mask_debug_dap_rom__PERIPHID1 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID2 = 32'hF8800FE8; +parameter val_debug_dap_rom__PERIPHID2 = 32'h00000008; +parameter mask_debug_dap_rom__PERIPHID2 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID3 = 32'hF8800FEC; +parameter val_debug_dap_rom__PERIPHID3 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID3 = 32'h000000FF; + +parameter debug_dap_rom__COMPID0 = 32'hF8800FF0; +parameter val_debug_dap_rom__COMPID0 = 32'h0000000D; +parameter mask_debug_dap_rom__COMPID0 = 32'h000000FF; + +parameter debug_dap_rom__COMPID1 = 32'hF8800FF4; +parameter val_debug_dap_rom__COMPID1 = 32'h00000010; +parameter mask_debug_dap_rom__COMPID1 = 32'h000000FF; + +parameter debug_dap_rom__COMPID2 = 32'hF8800FF8; +parameter val_debug_dap_rom__COMPID2 = 32'h00000005; +parameter mask_debug_dap_rom__COMPID2 = 32'h000000FF; + +parameter debug_dap_rom__COMPID3 = 32'hF8800FFC; +parameter val_debug_dap_rom__COMPID3 = 32'h000000B1; +parameter mask_debug_dap_rom__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_etb etb +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_etb__RDP = 32'hF8801004; +parameter val_debug_etb__RDP = 32'h00000400; +parameter mask_debug_etb__RDP = 32'hFFFFFFFF; + +parameter debug_etb__STS = 32'hF880100C; +parameter val_debug_etb__STS = 32'h00000000; +parameter mask_debug_etb__STS = 32'h0000000F; + +parameter debug_etb__RRD = 32'hF8801010; +parameter val_debug_etb__RRD = 32'h00000000; +parameter mask_debug_etb__RRD = 32'hFFFFFFFF; + +parameter debug_etb__RRP = 32'hF8801014; +parameter val_debug_etb__RRP = 32'h00000000; +parameter mask_debug_etb__RRP = 32'h000003FF; + +parameter debug_etb__RWP = 32'hF8801018; +parameter val_debug_etb__RWP = 32'h00000000; +parameter mask_debug_etb__RWP = 32'h000003FF; + +parameter debug_etb__TRG = 32'hF880101C; +parameter val_debug_etb__TRG = 32'h00000000; +parameter mask_debug_etb__TRG = 32'h000003FF; + +parameter debug_etb__CTL = 32'hF8801020; +parameter val_debug_etb__CTL = 32'h00000000; +parameter mask_debug_etb__CTL = 32'h00000001; + +parameter debug_etb__RWD = 32'hF8801024; +parameter val_debug_etb__RWD = 32'h00000000; +parameter mask_debug_etb__RWD = 32'hFFFFFFFF; + +parameter debug_etb__FFSR = 32'hF8801300; +parameter val_debug_etb__FFSR = 32'h00000000; +parameter mask_debug_etb__FFSR = 32'h00000003; + +parameter debug_etb__FFCR = 32'hF8801304; +parameter val_debug_etb__FFCR = 32'h00000200; +parameter mask_debug_etb__FFCR = 32'h00003FFF; + +parameter debug_etb__ITMISCOP0 = 32'hF8801EE0; +parameter val_debug_etb__ITMISCOP0 = 32'h00000000; +parameter mask_debug_etb__ITMISCOP0 = 32'h00000003; + +parameter debug_etb__ITTRFLINACK = 32'hF8801EE4; +parameter val_debug_etb__ITTRFLINACK = 32'h00000000; +parameter mask_debug_etb__ITTRFLINACK = 32'h00000003; + +parameter debug_etb__ITTRFLIN = 32'hF8801EE8; +parameter val_debug_etb__ITTRFLIN = 32'h00000000; +parameter mask_debug_etb__ITTRFLIN = 32'h00000003; + +parameter debug_etb__ITATBDATA0 = 32'hF8801EEC; +parameter val_debug_etb__ITATBDATA0 = 32'h00000000; +parameter mask_debug_etb__ITATBDATA0 = 32'h0000001F; + +parameter debug_etb__ITATBCTR2 = 32'hF8801EF0; +parameter val_debug_etb__ITATBCTR2 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR2 = 32'h00000003; + +parameter debug_etb__ITATBCTR1 = 32'hF8801EF4; +parameter val_debug_etb__ITATBCTR1 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR1 = 32'h0000007F; + +parameter debug_etb__ITATBCTR0 = 32'hF8801EF8; +parameter val_debug_etb__ITATBCTR0 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR0 = 32'h000003FF; + +parameter debug_etb__IMCR = 32'hF8801F00; +parameter val_debug_etb__IMCR = 32'h00000000; +parameter mask_debug_etb__IMCR = 32'h00000001; + +parameter debug_etb__CTSR = 32'hF8801FA0; +parameter val_debug_etb__CTSR = 32'h0000000F; +parameter mask_debug_etb__CTSR = 32'h0000000F; + +parameter debug_etb__CTCR = 32'hF8801FA4; +parameter val_debug_etb__CTCR = 32'h00000000; +parameter mask_debug_etb__CTCR = 32'h0000000F; + +parameter debug_etb__LAR = 32'hF8801FB0; +parameter val_debug_etb__LAR = 32'h00000000; +parameter mask_debug_etb__LAR = 32'hFFFFFFFF; + +parameter debug_etb__LSR = 32'hF8801FB4; +parameter val_debug_etb__LSR = 32'h00000003; +parameter mask_debug_etb__LSR = 32'h00000007; + +parameter debug_etb__ASR = 32'hF8801FB8; +parameter val_debug_etb__ASR = 32'h00000000; +parameter mask_debug_etb__ASR = 32'h000000FF; + +parameter debug_etb__DEVID = 32'hF8801FC8; +parameter val_debug_etb__DEVID = 32'h00000000; +parameter mask_debug_etb__DEVID = 32'h0000003F; + +parameter debug_etb__DTIR = 32'hF8801FCC; +parameter val_debug_etb__DTIR = 32'h00000021; +parameter mask_debug_etb__DTIR = 32'h000000FF; + +parameter debug_etb__PERIPHID4 = 32'hF8801FD0; +parameter val_debug_etb__PERIPHID4 = 32'h00000004; +parameter mask_debug_etb__PERIPHID4 = 32'h000000FF; + +parameter debug_etb__PERIPHID5 = 32'hF8801FD4; +parameter val_debug_etb__PERIPHID5 = 32'h00000000; +parameter mask_debug_etb__PERIPHID5 = 32'h000000FF; + +parameter debug_etb__PERIPHID6 = 32'hF8801FD8; +parameter val_debug_etb__PERIPHID6 = 32'h00000000; +parameter mask_debug_etb__PERIPHID6 = 32'h000000FF; + +parameter debug_etb__PERIPHID7 = 32'hF8801FDC; +parameter val_debug_etb__PERIPHID7 = 32'h00000000; +parameter mask_debug_etb__PERIPHID7 = 32'h000000FF; + +parameter debug_etb__PERIPHID0 = 32'hF8801FE0; +parameter val_debug_etb__PERIPHID0 = 32'h00000007; +parameter mask_debug_etb__PERIPHID0 = 32'h000000FF; + +parameter debug_etb__PERIPHID1 = 32'hF8801FE4; +parameter val_debug_etb__PERIPHID1 = 32'h000000B9; +parameter mask_debug_etb__PERIPHID1 = 32'h000000FF; + +parameter debug_etb__PERIPHID2 = 32'hF8801FE8; +parameter val_debug_etb__PERIPHID2 = 32'h0000002B; +parameter mask_debug_etb__PERIPHID2 = 32'h000000FF; + +parameter debug_etb__PERIPHID3 = 32'hF8801FEC; +parameter val_debug_etb__PERIPHID3 = 32'h00000000; +parameter mask_debug_etb__PERIPHID3 = 32'h000000FF; + +parameter debug_etb__COMPID0 = 32'hF8801FF0; +parameter val_debug_etb__COMPID0 = 32'h0000000D; +parameter mask_debug_etb__COMPID0 = 32'h000000FF; + +parameter debug_etb__COMPID1 = 32'hF8801FF4; +parameter val_debug_etb__COMPID1 = 32'h00000090; +parameter mask_debug_etb__COMPID1 = 32'h000000FF; + +parameter debug_etb__COMPID2 = 32'hF8801FF8; +parameter val_debug_etb__COMPID2 = 32'h00000005; +parameter mask_debug_etb__COMPID2 = 32'h000000FF; + +parameter debug_etb__COMPID3 = 32'hF8801FFC; +parameter val_debug_etb__COMPID3 = 32'h000000B1; +parameter mask_debug_etb__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_ftm ftm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_ftm__FTMGLBCTRL = 32'hF880B000; +parameter val_debug_ftm__FTMGLBCTRL = 32'h00000000; +parameter mask_debug_ftm__FTMGLBCTRL = 32'h00000001; + +parameter debug_ftm__FTMSTATUS = 32'hF880B004; +parameter val_debug_ftm__FTMSTATUS = 32'h00000082; +parameter mask_debug_ftm__FTMSTATUS = 32'h000000FF; + +parameter debug_ftm__FTMCONTROL = 32'hF880B008; +parameter val_debug_ftm__FTMCONTROL = 32'h00000000; +parameter mask_debug_ftm__FTMCONTROL = 32'h00000007; + +parameter debug_ftm__FTMP2FDBG0 = 32'hF880B00C; +parameter val_debug_ftm__FTMP2FDBG0 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG0 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG1 = 32'hF880B010; +parameter val_debug_ftm__FTMP2FDBG1 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG1 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG2 = 32'hF880B014; +parameter val_debug_ftm__FTMP2FDBG2 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG2 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG3 = 32'hF880B018; +parameter val_debug_ftm__FTMP2FDBG3 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG3 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG0 = 32'hF880B01C; +parameter val_debug_ftm__FTMF2PDBG0 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG0 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG1 = 32'hF880B020; +parameter val_debug_ftm__FTMF2PDBG1 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG1 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG2 = 32'hF880B024; +parameter val_debug_ftm__FTMF2PDBG2 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG2 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG3 = 32'hF880B028; +parameter val_debug_ftm__FTMF2PDBG3 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG3 = 32'h000000FF; + +parameter debug_ftm__CYCOUNTPRE = 32'hF880B02C; +parameter val_debug_ftm__CYCOUNTPRE = 32'h00000000; +parameter mask_debug_ftm__CYCOUNTPRE = 32'h0000000F; + +parameter debug_ftm__FTMSYNCRELOAD = 32'hF880B030; +parameter val_debug_ftm__FTMSYNCRELOAD = 32'h00000000; +parameter mask_debug_ftm__FTMSYNCRELOAD = 32'h00000FFF; + +parameter debug_ftm__FTMSYNCCOUT = 32'hF880B034; +parameter val_debug_ftm__FTMSYNCCOUT = 32'h00000000; +parameter mask_debug_ftm__FTMSYNCCOUT = 32'h00000FFF; + +parameter debug_ftm__FTMATID = 32'hF880B400; +parameter val_debug_ftm__FTMATID = 32'h00000000; +parameter mask_debug_ftm__FTMATID = 32'h0000007F; + +parameter debug_ftm__FTMITTRIGOUTACK = 32'hF880BED0; +parameter val_debug_ftm__FTMITTRIGOUTACK = 32'h00000000; +parameter mask_debug_ftm__FTMITTRIGOUTACK = 32'h0000000F; + +parameter debug_ftm__FTMITTRIGGER = 32'hF880BED4; +parameter val_debug_ftm__FTMITTRIGGER = 32'h00000000; +parameter mask_debug_ftm__FTMITTRIGGER = 32'h0000000F; + +parameter debug_ftm__FTMITTRACEDIS = 32'hF880BED8; +parameter val_debug_ftm__FTMITTRACEDIS = 32'h00000000; +parameter mask_debug_ftm__FTMITTRACEDIS = 32'h00000001; + +parameter debug_ftm__FTMITCYCCOUNT = 32'hF880BEDC; +parameter val_debug_ftm__FTMITCYCCOUNT = 32'h00000001; +parameter mask_debug_ftm__FTMITCYCCOUNT = 32'hFFFFFFFF; + +parameter debug_ftm__FTMITATBDATA0 = 32'hF880BEEC; +parameter val_debug_ftm__FTMITATBDATA0 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBDATA0 = 32'h0000001F; + +parameter debug_ftm__FTMITATBCTR2 = 32'hF880BEF0; +parameter val_debug_ftm__FTMITATBCTR2 = 32'h00000001; +parameter mask_debug_ftm__FTMITATBCTR2 = 32'h00000003; + +parameter debug_ftm__FTMITATBCTR1 = 32'hF880BEF4; +parameter val_debug_ftm__FTMITATBCTR1 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBCTR1 = 32'h0000007F; + +parameter debug_ftm__FTMITATBCTR0 = 32'hF880BEF8; +parameter val_debug_ftm__FTMITATBCTR0 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBCTR0 = 32'h000003FF; + +parameter debug_ftm__FTMITCR = 32'hF880BF00; +parameter val_debug_ftm__FTMITCR = 32'h00000000; +parameter mask_debug_ftm__FTMITCR = 32'h00000001; + +parameter debug_ftm__CLAIMTAGSET = 32'hF880BFA0; +parameter val_debug_ftm__CLAIMTAGSET = 32'h000000FF; +parameter mask_debug_ftm__CLAIMTAGSET = 32'h000000FF; + +parameter debug_ftm__CLAIMTAGCLR = 32'hF880BFA4; +parameter val_debug_ftm__CLAIMTAGCLR = 32'h000000FF; +parameter mask_debug_ftm__CLAIMTAGCLR = 32'h000000FF; + +parameter debug_ftm__LOCK_ACCESS = 32'hF880BFB0; +parameter val_debug_ftm__LOCK_ACCESS = 32'h00000000; +parameter mask_debug_ftm__LOCK_ACCESS = 32'hFFFFFFFF; + +parameter debug_ftm__LOCK_STATUS = 32'hF880BFB4; +parameter val_debug_ftm__LOCK_STATUS = 32'h00000003; +parameter mask_debug_ftm__LOCK_STATUS = 32'h00000007; + +parameter debug_ftm__FTMAUTHSTATUS = 32'hF880BFB8; +parameter val_debug_ftm__FTMAUTHSTATUS = 32'h00000088; +parameter mask_debug_ftm__FTMAUTHSTATUS = 32'h000000FF; + +parameter debug_ftm__FTMDEVID = 32'hF880BFC8; +parameter val_debug_ftm__FTMDEVID = 32'h00000000; +parameter mask_debug_ftm__FTMDEVID = 32'h00000001; + +parameter debug_ftm__FTMDEV_TYPE = 32'hF880BFCC; +parameter val_debug_ftm__FTMDEV_TYPE = 32'h00000033; +parameter mask_debug_ftm__FTMDEV_TYPE = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID4 = 32'hF880BFD0; +parameter val_debug_ftm__FTMPERIPHID4 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID4 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID5 = 32'hF880BFD4; +parameter val_debug_ftm__FTMPERIPHID5 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID5 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID6 = 32'hF880BFD8; +parameter val_debug_ftm__FTMPERIPHID6 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID6 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID7 = 32'hF880BFDC; +parameter val_debug_ftm__FTMPERIPHID7 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID7 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID0 = 32'hF880BFE0; +parameter val_debug_ftm__FTMPERIPHID0 = 32'h00000001; +parameter mask_debug_ftm__FTMPERIPHID0 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID1 = 32'hF880BFE4; +parameter val_debug_ftm__FTMPERIPHID1 = 32'h00000090; +parameter mask_debug_ftm__FTMPERIPHID1 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID2 = 32'hF880BFE8; +parameter val_debug_ftm__FTMPERIPHID2 = 32'h0000000C; +parameter mask_debug_ftm__FTMPERIPHID2 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID3 = 32'hF880BFEC; +parameter val_debug_ftm__FTMPERIPHID3 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID3 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID0 = 32'hF880BFF0; +parameter val_debug_ftm__FTMCOMPONID0 = 32'h0000000D; +parameter mask_debug_ftm__FTMCOMPONID0 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID1 = 32'hF880BFF4; +parameter val_debug_ftm__FTMCOMPONID1 = 32'h00000090; +parameter mask_debug_ftm__FTMCOMPONID1 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID2 = 32'hF880BFF8; +parameter val_debug_ftm__FTMCOMPONID2 = 32'h00000005; +parameter mask_debug_ftm__FTMCOMPONID2 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID3 = 32'hF880BFFC; +parameter val_debug_ftm__FTMCOMPONID3 = 32'h000000B1; +parameter mask_debug_ftm__FTMCOMPONID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_funnel funnel +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_funnel__Control = 32'hF8804000; +parameter val_debug_funnel__Control = 32'h00000300; +parameter mask_debug_funnel__Control = 32'h00000FFF; + +parameter debug_funnel__PriControl = 32'hF8804004; +parameter val_debug_funnel__PriControl = 32'h00FAC688; +parameter mask_debug_funnel__PriControl = 32'h00FFFFFF; + +parameter debug_funnel__ITATBDATA0 = 32'hF8804EEC; +parameter val_debug_funnel__ITATBDATA0 = 32'h00000000; +parameter mask_debug_funnel__ITATBDATA0 = 32'h0000001F; + +parameter debug_funnel__ITATBCTR2 = 32'hF8804EF0; +parameter val_debug_funnel__ITATBCTR2 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR2 = 32'h00000003; + +parameter debug_funnel__ITATBCTR1 = 32'hF8804EF4; +parameter val_debug_funnel__ITATBCTR1 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR1 = 32'h0000007F; + +parameter debug_funnel__ITATBCTR0 = 32'hF8804EF8; +parameter val_debug_funnel__ITATBCTR0 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR0 = 32'h000003FF; + +parameter debug_funnel__IMCR = 32'hF8804F00; +parameter val_debug_funnel__IMCR = 32'h00000000; +parameter mask_debug_funnel__IMCR = 32'h00000001; + +parameter debug_funnel__CTSR = 32'hF8804FA0; +parameter val_debug_funnel__CTSR = 32'h0000000F; +parameter mask_debug_funnel__CTSR = 32'h0000000F; + +parameter debug_funnel__CTCR = 32'hF8804FA4; +parameter val_debug_funnel__CTCR = 32'h00000000; +parameter mask_debug_funnel__CTCR = 32'h0000000F; + +parameter debug_funnel__LAR = 32'hF8804FB0; +parameter val_debug_funnel__LAR = 32'h00000000; +parameter mask_debug_funnel__LAR = 32'hFFFFFFFF; + +parameter debug_funnel__LSR = 32'hF8804FB4; +parameter val_debug_funnel__LSR = 32'h00000003; +parameter mask_debug_funnel__LSR = 32'h00000007; + +parameter debug_funnel__ASR = 32'hF8804FB8; +parameter val_debug_funnel__ASR = 32'h00000000; +parameter mask_debug_funnel__ASR = 32'h000000FF; + +parameter debug_funnel__DEVID = 32'hF8804FC8; +parameter val_debug_funnel__DEVID = 32'h00000028; +parameter mask_debug_funnel__DEVID = 32'h000000FF; + +parameter debug_funnel__DTIR = 32'hF8804FCC; +parameter val_debug_funnel__DTIR = 32'h00000012; +parameter mask_debug_funnel__DTIR = 32'h000000FF; + +parameter debug_funnel__PERIPHID4 = 32'hF8804FD0; +parameter val_debug_funnel__PERIPHID4 = 32'h00000004; +parameter mask_debug_funnel__PERIPHID4 = 32'h000000FF; + +parameter debug_funnel__PERIPHID5 = 32'hF8804FD4; +parameter val_debug_funnel__PERIPHID5 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID5 = 32'h000000FF; + +parameter debug_funnel__PERIPHID6 = 32'hF8804FD8; +parameter val_debug_funnel__PERIPHID6 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID6 = 32'h000000FF; + +parameter debug_funnel__PERIPHID7 = 32'hF8804FDC; +parameter val_debug_funnel__PERIPHID7 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID7 = 32'h000000FF; + +parameter debug_funnel__PERIPHID0 = 32'hF8804FE0; +parameter val_debug_funnel__PERIPHID0 = 32'h00000008; +parameter mask_debug_funnel__PERIPHID0 = 32'h000000FF; + +parameter debug_funnel__PERIPHID1 = 32'hF8804FE4; +parameter val_debug_funnel__PERIPHID1 = 32'h000000B9; +parameter mask_debug_funnel__PERIPHID1 = 32'h000000FF; + +parameter debug_funnel__PERIPHID2 = 32'hF8804FE8; +parameter val_debug_funnel__PERIPHID2 = 32'h0000001B; +parameter mask_debug_funnel__PERIPHID2 = 32'h000000FF; + +parameter debug_funnel__PERIPHID3 = 32'hF8804FEC; +parameter val_debug_funnel__PERIPHID3 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID3 = 32'h000000FF; + +parameter debug_funnel__COMPID0 = 32'hF8804FF0; +parameter val_debug_funnel__COMPID0 = 32'h0000000D; +parameter mask_debug_funnel__COMPID0 = 32'h000000FF; + +parameter debug_funnel__COMPID1 = 32'hF8804FF4; +parameter val_debug_funnel__COMPID1 = 32'h00000090; +parameter mask_debug_funnel__COMPID1 = 32'h000000FF; + +parameter debug_funnel__COMPID2 = 32'hF8804FF8; +parameter val_debug_funnel__COMPID2 = 32'h00000005; +parameter mask_debug_funnel__COMPID2 = 32'h000000FF; + +parameter debug_funnel__COMPID3 = 32'hF8804FFC; +parameter val_debug_funnel__COMPID3 = 32'h000000B1; +parameter mask_debug_funnel__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_itm itm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_itm__StimPort00 = 32'hF8805000; +parameter val_debug_itm__StimPort00 = 32'h00000000; +parameter mask_debug_itm__StimPort00 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort01 = 32'hF8805004; +parameter val_debug_itm__StimPort01 = 32'h00000000; +parameter mask_debug_itm__StimPort01 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort02 = 32'hF8805008; +parameter val_debug_itm__StimPort02 = 32'h00000000; +parameter mask_debug_itm__StimPort02 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort03 = 32'hF880500C; +parameter val_debug_itm__StimPort03 = 32'h00000000; +parameter mask_debug_itm__StimPort03 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort04 = 32'hF8805010; +parameter val_debug_itm__StimPort04 = 32'h00000000; +parameter mask_debug_itm__StimPort04 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort05 = 32'hF8805014; +parameter val_debug_itm__StimPort05 = 32'h00000000; +parameter mask_debug_itm__StimPort05 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort06 = 32'hF8805018; +parameter val_debug_itm__StimPort06 = 32'h00000000; +parameter mask_debug_itm__StimPort06 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort07 = 32'hF880501C; +parameter val_debug_itm__StimPort07 = 32'h00000000; +parameter mask_debug_itm__StimPort07 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort08 = 32'hF8805020; +parameter val_debug_itm__StimPort08 = 32'h00000000; +parameter mask_debug_itm__StimPort08 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort09 = 32'hF8805024; +parameter val_debug_itm__StimPort09 = 32'h00000000; +parameter mask_debug_itm__StimPort09 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort10 = 32'hF8805028; +parameter val_debug_itm__StimPort10 = 32'h00000000; +parameter mask_debug_itm__StimPort10 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort11 = 32'hF880502C; +parameter val_debug_itm__StimPort11 = 32'h00000000; +parameter mask_debug_itm__StimPort11 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort12 = 32'hF8805030; +parameter val_debug_itm__StimPort12 = 32'h00000000; +parameter mask_debug_itm__StimPort12 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort13 = 32'hF8805034; +parameter val_debug_itm__StimPort13 = 32'h00000000; +parameter mask_debug_itm__StimPort13 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort14 = 32'hF8805038; +parameter val_debug_itm__StimPort14 = 32'h00000000; +parameter mask_debug_itm__StimPort14 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort15 = 32'hF880503C; +parameter val_debug_itm__StimPort15 = 32'h00000000; +parameter mask_debug_itm__StimPort15 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort16 = 32'hF8805040; +parameter val_debug_itm__StimPort16 = 32'h00000000; +parameter mask_debug_itm__StimPort16 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort17 = 32'hF8805044; +parameter val_debug_itm__StimPort17 = 32'h00000000; +parameter mask_debug_itm__StimPort17 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort18 = 32'hF8805048; +parameter val_debug_itm__StimPort18 = 32'h00000000; +parameter mask_debug_itm__StimPort18 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort19 = 32'hF880504C; +parameter val_debug_itm__StimPort19 = 32'h00000000; +parameter mask_debug_itm__StimPort19 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort20 = 32'hF8805050; +parameter val_debug_itm__StimPort20 = 32'h00000000; +parameter mask_debug_itm__StimPort20 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort21 = 32'hF8805054; +parameter val_debug_itm__StimPort21 = 32'h00000000; +parameter mask_debug_itm__StimPort21 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort22 = 32'hF8805058; +parameter val_debug_itm__StimPort22 = 32'h00000000; +parameter mask_debug_itm__StimPort22 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort23 = 32'hF880505C; +parameter val_debug_itm__StimPort23 = 32'h00000000; +parameter mask_debug_itm__StimPort23 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort24 = 32'hF8805060; +parameter val_debug_itm__StimPort24 = 32'h00000000; +parameter mask_debug_itm__StimPort24 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort25 = 32'hF8805064; +parameter val_debug_itm__StimPort25 = 32'h00000000; +parameter mask_debug_itm__StimPort25 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort26 = 32'hF8805068; +parameter val_debug_itm__StimPort26 = 32'h00000000; +parameter mask_debug_itm__StimPort26 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort27 = 32'hF880506C; +parameter val_debug_itm__StimPort27 = 32'h00000000; +parameter mask_debug_itm__StimPort27 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort28 = 32'hF8805070; +parameter val_debug_itm__StimPort28 = 32'h00000000; +parameter mask_debug_itm__StimPort28 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort29 = 32'hF8805074; +parameter val_debug_itm__StimPort29 = 32'h00000000; +parameter mask_debug_itm__StimPort29 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort30 = 32'hF8805078; +parameter val_debug_itm__StimPort30 = 32'h00000000; +parameter mask_debug_itm__StimPort30 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort31 = 32'hF880507C; +parameter val_debug_itm__StimPort31 = 32'h00000000; +parameter mask_debug_itm__StimPort31 = 32'hFFFFFFFF; + +parameter debug_itm__TER = 32'hF8805E00; +parameter val_debug_itm__TER = 32'h00000000; +parameter mask_debug_itm__TER = 32'hFFFFFFFF; + +parameter debug_itm__TTR = 32'hF8805E20; +parameter val_debug_itm__TTR = 32'h00000000; +parameter mask_debug_itm__TTR = 32'hFFFFFFFF; + +parameter debug_itm__CR = 32'hF8805E80; +parameter val_debug_itm__CR = 32'h00000004; +parameter mask_debug_itm__CR = 32'h00FFFFFF; + +parameter debug_itm__SCR = 32'hF8805E90; +parameter val_debug_itm__SCR = 32'h00000400; +parameter mask_debug_itm__SCR = 32'h00000FFF; + +parameter debug_itm__ITTRIGOUTACK = 32'hF8805EE4; +parameter val_debug_itm__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_itm__ITTRIGOUTACK = 32'h00000001; + +parameter debug_itm__ITTRIGOUT = 32'hF8805EE8; +parameter val_debug_itm__ITTRIGOUT = 32'h00000000; +parameter mask_debug_itm__ITTRIGOUT = 32'h00000001; + +parameter debug_itm__ITATBDATA0 = 32'hF8805EEC; +parameter val_debug_itm__ITATBDATA0 = 32'h00000000; +parameter mask_debug_itm__ITATBDATA0 = 32'h00000003; + +parameter debug_itm__ITATBCTR2 = 32'hF8805EF0; +parameter val_debug_itm__ITATBCTR2 = 32'h00000001; +parameter mask_debug_itm__ITATBCTR2 = 32'h00000001; + +parameter debug_itm__ITATABCTR1 = 32'hF8805EF4; +parameter val_debug_itm__ITATABCTR1 = 32'h00000000; +parameter mask_debug_itm__ITATABCTR1 = 32'h0000007F; + +parameter debug_itm__ITATBCTR0 = 32'hF8805EF8; +parameter val_debug_itm__ITATBCTR0 = 32'h00000000; +parameter mask_debug_itm__ITATBCTR0 = 32'h00000003; + +parameter debug_itm__IMCR = 32'hF8805F00; +parameter val_debug_itm__IMCR = 32'h00000000; +parameter mask_debug_itm__IMCR = 32'h00000001; + +parameter debug_itm__CTSR = 32'hF8805FA0; +parameter val_debug_itm__CTSR = 32'h000000FF; +parameter mask_debug_itm__CTSR = 32'h000000FF; + +parameter debug_itm__CTCR = 32'hF8805FA4; +parameter val_debug_itm__CTCR = 32'h00000000; +parameter mask_debug_itm__CTCR = 32'h000000FF; + +parameter debug_itm__LAR = 32'hF8805FB0; +parameter val_debug_itm__LAR = 32'h00000000; +parameter mask_debug_itm__LAR = 32'hFFFFFFFF; + +parameter debug_itm__LSR = 32'hF8805FB4; +parameter val_debug_itm__LSR = 32'h00000003; +parameter mask_debug_itm__LSR = 32'h00000007; + +parameter debug_itm__ASR = 32'hF8805FB8; +parameter val_debug_itm__ASR = 32'h00000088; +parameter mask_debug_itm__ASR = 32'h000000FF; + +parameter debug_itm__DEVID = 32'hF8805FC8; +parameter val_debug_itm__DEVID = 32'h00000020; +parameter mask_debug_itm__DEVID = 32'h00001FFF; + +parameter debug_itm__DTIR = 32'hF8805FCC; +parameter val_debug_itm__DTIR = 32'h00000043; +parameter mask_debug_itm__DTIR = 32'h000000FF; + +parameter debug_itm__PERIPHID4 = 32'hF8805FD0; +parameter val_debug_itm__PERIPHID4 = 32'h00000004; +parameter mask_debug_itm__PERIPHID4 = 32'h000000FF; + +parameter debug_itm__PERIPHID5 = 32'hF8805FD4; +parameter val_debug_itm__PERIPHID5 = 32'h00000000; +parameter mask_debug_itm__PERIPHID5 = 32'h000000FF; + +parameter debug_itm__PERIPHID6 = 32'hF8805FD8; +parameter val_debug_itm__PERIPHID6 = 32'h00000000; +parameter mask_debug_itm__PERIPHID6 = 32'h000000FF; + +parameter debug_itm__PERIPHID7 = 32'hF8805FDC; +parameter val_debug_itm__PERIPHID7 = 32'h00000000; +parameter mask_debug_itm__PERIPHID7 = 32'h000000FF; + +parameter debug_itm__PERIPHID0 = 32'hF8805FE0; +parameter val_debug_itm__PERIPHID0 = 32'h00000013; +parameter mask_debug_itm__PERIPHID0 = 32'h000000FF; + +parameter debug_itm__PERIPHID1 = 32'hF8805FE4; +parameter val_debug_itm__PERIPHID1 = 32'h000000B9; +parameter mask_debug_itm__PERIPHID1 = 32'h000000FF; + +parameter debug_itm__PERIPHID2 = 32'hF8805FE8; +parameter val_debug_itm__PERIPHID2 = 32'h0000002B; +parameter mask_debug_itm__PERIPHID2 = 32'h000000FF; + +parameter debug_itm__PERIPHID3 = 32'hF8805FEC; +parameter val_debug_itm__PERIPHID3 = 32'h00000000; +parameter mask_debug_itm__PERIPHID3 = 32'h000000FF; + +parameter debug_itm__COMPID0 = 32'hF8805FF0; +parameter val_debug_itm__COMPID0 = 32'h0000000D; +parameter mask_debug_itm__COMPID0 = 32'h000000FF; + +parameter debug_itm__COMPID1 = 32'hF8805FF4; +parameter val_debug_itm__COMPID1 = 32'h00000090; +parameter mask_debug_itm__COMPID1 = 32'h000000FF; + +parameter debug_itm__COMPID2 = 32'hF8805FF8; +parameter val_debug_itm__COMPID2 = 32'h00000005; +parameter mask_debug_itm__COMPID2 = 32'h000000FF; + +parameter debug_itm__COMPID3 = 32'hF8805FFC; +parameter val_debug_itm__COMPID3 = 32'h000000B1; +parameter mask_debug_itm__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_tpiu tpiu +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_tpiu__SuppSize = 32'hF8803000; +parameter val_debug_tpiu__SuppSize = 32'hFFFFFFFF; +parameter mask_debug_tpiu__SuppSize = 32'hFFFFFFFF; + +parameter debug_tpiu__CurrentSize = 32'hF8803004; +parameter val_debug_tpiu__CurrentSize = 32'h00000001; +parameter mask_debug_tpiu__CurrentSize = 32'hFFFFFFFF; + +parameter debug_tpiu__SuppTrigMode = 32'hF8803100; +parameter val_debug_tpiu__SuppTrigMode = 32'h0000011F; +parameter mask_debug_tpiu__SuppTrigMode = 32'h0003FFFF; + +parameter debug_tpiu__TrigCount = 32'hF8803104; +parameter val_debug_tpiu__TrigCount = 32'h00000000; +parameter mask_debug_tpiu__TrigCount = 32'h000000FF; + +parameter debug_tpiu__TrigMult = 32'hF8803108; +parameter val_debug_tpiu__TrigMult = 32'h00000000; +parameter mask_debug_tpiu__TrigMult = 32'h0000001F; + +parameter debug_tpiu__SuppTest = 32'hF8803200; +parameter val_debug_tpiu__SuppTest = 32'h0003000F; +parameter mask_debug_tpiu__SuppTest = 32'h0003FFFF; + +parameter debug_tpiu__CurrentTest = 32'hF8803204; +parameter val_debug_tpiu__CurrentTest = 32'h00000000; +parameter mask_debug_tpiu__CurrentTest = 32'h0003FFFF; + +parameter debug_tpiu__TestRepeatCount = 32'hF8803208; +parameter val_debug_tpiu__TestRepeatCount = 32'h00000000; +parameter mask_debug_tpiu__TestRepeatCount = 32'h000000FF; + +parameter debug_tpiu__FFSR = 32'hF8803300; +parameter val_debug_tpiu__FFSR = 32'h00000006; +parameter mask_debug_tpiu__FFSR = 32'h00000007; + +parameter debug_tpiu__FFCR = 32'hF8803304; +parameter val_debug_tpiu__FFCR = 32'h00000000; +parameter mask_debug_tpiu__FFCR = 32'h00003FFF; + +parameter debug_tpiu__FormatSyncCount = 32'hF8803308; +parameter val_debug_tpiu__FormatSyncCount = 32'h00000040; +parameter mask_debug_tpiu__FormatSyncCount = 32'h00000FFF; + +parameter debug_tpiu__EXTCTLIn = 32'hF8803400; +parameter val_debug_tpiu__EXTCTLIn = 32'h00000000; +parameter mask_debug_tpiu__EXTCTLIn = 32'h000000FF; + +parameter debug_tpiu__EXTCTLOut = 32'hF8803404; +parameter val_debug_tpiu__EXTCTLOut = 32'h00000000; +parameter mask_debug_tpiu__EXTCTLOut = 32'h000000FF; + +parameter debug_tpiu__ITTRFLINACK = 32'hF8803EE4; +parameter val_debug_tpiu__ITTRFLINACK = 32'h00000000; +parameter mask_debug_tpiu__ITTRFLINACK = 32'h00000003; + +parameter debug_tpiu__ITTRFLIN = 32'hF8803EE8; +parameter val_debug_tpiu__ITTRFLIN = 32'h00000000; +parameter mask_debug_tpiu__ITTRFLIN = 32'h00000000; + +parameter debug_tpiu__ITATBDATA0 = 32'hF8803EEC; +parameter val_debug_tpiu__ITATBDATA0 = 32'h00000000; +parameter mask_debug_tpiu__ITATBDATA0 = 32'h00000000; + +parameter debug_tpiu__ITATBCTR2 = 32'hF8803EF0; +parameter val_debug_tpiu__ITATBCTR2 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR2 = 32'h00000003; + +parameter debug_tpiu__ITATBCTR1 = 32'hF8803EF4; +parameter val_debug_tpiu__ITATBCTR1 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR1 = 32'h00000000; + +parameter debug_tpiu__ITATBCTR0 = 32'hF8803EF8; +parameter val_debug_tpiu__ITATBCTR0 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR0 = 32'h00000000; + +parameter debug_tpiu__IMCR = 32'hF8803F00; +parameter val_debug_tpiu__IMCR = 32'h00000000; +parameter mask_debug_tpiu__IMCR = 32'h00000001; + +parameter debug_tpiu__CTSR = 32'hF8803FA0; +parameter val_debug_tpiu__CTSR = 32'h0000000F; +parameter mask_debug_tpiu__CTSR = 32'h0000000F; + +parameter debug_tpiu__CTCR = 32'hF8803FA4; +parameter val_debug_tpiu__CTCR = 32'h00000000; +parameter mask_debug_tpiu__CTCR = 32'h0000000F; + +parameter debug_tpiu__LAR = 32'hF8803FB0; +parameter val_debug_tpiu__LAR = 32'h00000000; +parameter mask_debug_tpiu__LAR = 32'hFFFFFFFF; + +parameter debug_tpiu__LSR = 32'hF8803FB4; +parameter val_debug_tpiu__LSR = 32'h00000003; +parameter mask_debug_tpiu__LSR = 32'h00000007; + +parameter debug_tpiu__ASR = 32'hF8803FB8; +parameter val_debug_tpiu__ASR = 32'h00000000; +parameter mask_debug_tpiu__ASR = 32'h000000FF; + +parameter debug_tpiu__DEVID = 32'hF8803FC8; +parameter val_debug_tpiu__DEVID = 32'h000000A0; +parameter mask_debug_tpiu__DEVID = 32'h00000FFF; + +parameter debug_tpiu__DTIR = 32'hF8803FCC; +parameter val_debug_tpiu__DTIR = 32'h00000011; +parameter mask_debug_tpiu__DTIR = 32'h000000FF; + +parameter debug_tpiu__PERIPHID4 = 32'hF8803FD0; +parameter val_debug_tpiu__PERIPHID4 = 32'h00000004; +parameter mask_debug_tpiu__PERIPHID4 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID5 = 32'hF8803FD4; +parameter val_debug_tpiu__PERIPHID5 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID5 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID6 = 32'hF8803FD8; +parameter val_debug_tpiu__PERIPHID6 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID6 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID7 = 32'hF8803FDC; +parameter val_debug_tpiu__PERIPHID7 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID7 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID0 = 32'hF8803FE0; +parameter val_debug_tpiu__PERIPHID0 = 32'h00000012; +parameter mask_debug_tpiu__PERIPHID0 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID1 = 32'hF8803FE4; +parameter val_debug_tpiu__PERIPHID1 = 32'h000000B9; +parameter mask_debug_tpiu__PERIPHID1 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID2 = 32'hF8803FE8; +parameter val_debug_tpiu__PERIPHID2 = 32'h0000004B; +parameter mask_debug_tpiu__PERIPHID2 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID3 = 32'hF8803FEC; +parameter val_debug_tpiu__PERIPHID3 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID3 = 32'h000000FF; + +parameter debug_tpiu__COMPID0 = 32'hF8803FF0; +parameter val_debug_tpiu__COMPID0 = 32'h0000000D; +parameter mask_debug_tpiu__COMPID0 = 32'h000000FF; + +parameter debug_tpiu__COMPID1 = 32'hF8803FF4; +parameter val_debug_tpiu__COMPID1 = 32'h00000090; +parameter mask_debug_tpiu__COMPID1 = 32'h000000FF; + +parameter debug_tpiu__COMPID2 = 32'hF8803FF8; +parameter val_debug_tpiu__COMPID2 = 32'h00000005; +parameter mask_debug_tpiu__COMPID2 = 32'h000000FF; + +parameter debug_tpiu__COMPID3 = 32'hF8803FFC; +parameter val_debug_tpiu__COMPID3 = 32'h000000B1; +parameter mask_debug_tpiu__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module devcfg devcfg +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter devcfg__CTRL = 32'hF8007000; +parameter val_devcfg__CTRL = 32'h0C000000; +parameter mask_devcfg__CTRL = 32'hFFFFFFFF; + +parameter devcfg__LOCK = 32'hF8007004; +parameter val_devcfg__LOCK = 32'h00000000; +parameter mask_devcfg__LOCK = 32'hFFFFFFFF; + +parameter devcfg__CFG = 32'hF8007008; +parameter val_devcfg__CFG = 32'h0000050B; +parameter mask_devcfg__CFG = 32'hFFFFFFFF; + +parameter devcfg__INT_STS = 32'hF800700C; +parameter val_devcfg__INT_STS = 32'h00000000; +parameter mask_devcfg__INT_STS = 32'hFFFFFFFF; + +parameter devcfg__INT_MASK = 32'hF8007010; +parameter val_devcfg__INT_MASK = 32'hFFFFFFFF; +parameter mask_devcfg__INT_MASK = 32'hFFFFFFFF; + +parameter devcfg__STATUS = 32'hF8007014; +parameter val_devcfg__STATUS = 32'h40000820; +parameter mask_devcfg__STATUS = 32'hFFFFFFFF; + +parameter devcfg__DMA_SRC_ADDR = 32'hF8007018; +parameter val_devcfg__DMA_SRC_ADDR = 32'h00000000; +parameter mask_devcfg__DMA_SRC_ADDR = 32'hFFFFFFFF; + +parameter devcfg__DMA_DST_ADDR = 32'hF800701C; +parameter val_devcfg__DMA_DST_ADDR = 32'h00000000; +parameter mask_devcfg__DMA_DST_ADDR = 32'hFFFFFFFF; + +parameter devcfg__DMA_SRC_LEN = 32'hF8007020; +parameter val_devcfg__DMA_SRC_LEN = 32'h00000000; +parameter mask_devcfg__DMA_SRC_LEN = 32'hFFFFFFFF; + +parameter devcfg__DMA_DEST_LEN = 32'hF8007024; +parameter val_devcfg__DMA_DEST_LEN = 32'h00000000; +parameter mask_devcfg__DMA_DEST_LEN = 32'hFFFFFFFF; + +parameter devcfg__ROM_SHADOW = 32'hF8007028; +parameter val_devcfg__ROM_SHADOW = 32'h00000000; +parameter mask_devcfg__ROM_SHADOW = 32'hFFFFFFFF; + +parameter devcfg__MULTIBOOT_ADDR = 32'hF800702C; +parameter val_devcfg__MULTIBOOT_ADDR = 32'h00000000; +parameter mask_devcfg__MULTIBOOT_ADDR = 32'hFFFFFFFF; + +parameter devcfg__SW_ID = 32'hF8007030; +parameter val_devcfg__SW_ID = 32'h00000000; +parameter mask_devcfg__SW_ID = 32'hFFFFFFFF; + +parameter devcfg__UNLOCK = 32'hF8007034; +parameter val_devcfg__UNLOCK = 32'h00000000; +parameter mask_devcfg__UNLOCK = 32'hFFFFFFFF; + +parameter devcfg__MCTRL = 32'hF8007080; +parameter val_devcfg__MCTRL = 32'h00800000; +parameter mask_devcfg__MCTRL = 32'h0FFFFFFF; + +parameter devcfg__XADCIF_CFG = 32'hF8007100; +parameter val_devcfg__XADCIF_CFG = 32'h00001114; +parameter mask_devcfg__XADCIF_CFG = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_INT_STS = 32'hF8007104; +parameter val_devcfg__XADCIF_INT_STS = 32'h00000200; +parameter mask_devcfg__XADCIF_INT_STS = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_INT_MASK = 32'hF8007108; +parameter val_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF; +parameter mask_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_MSTS = 32'hF800710C; +parameter val_devcfg__XADCIF_MSTS = 32'h00000500; +parameter mask_devcfg__XADCIF_MSTS = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_CMDFIFO = 32'hF8007110; +parameter val_devcfg__XADCIF_CMDFIFO = 32'h00000000; +parameter mask_devcfg__XADCIF_CMDFIFO = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_RDFIFO = 32'hF8007114; +parameter val_devcfg__XADCIF_RDFIFO = 32'h00000000; +parameter mask_devcfg__XADCIF_RDFIFO = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_MCTL = 32'hF8007118; +parameter val_devcfg__XADCIF_MCTL = 32'h00000010; +parameter mask_devcfg__XADCIF_MCTL = 32'hFFFFFFFF; + + +// ************************************************************ +// Module dmac0_ns dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter dmac0_ns__DSR = 32'hF8004000; +parameter val_dmac0_ns__DSR = 32'h00000000; +parameter mask_dmac0_ns__DSR = 32'hFFFFFFFF; + +parameter dmac0_ns__DPC = 32'hF8004004; +parameter val_dmac0_ns__DPC = 32'h00000000; +parameter mask_dmac0_ns__DPC = 32'hFFFFFFFF; + +parameter dmac0_ns__INTEN = 32'hF8004020; +parameter val_dmac0_ns__INTEN = 32'h00000000; +parameter mask_dmac0_ns__INTEN = 32'hFFFFFFFF; + +parameter dmac0_ns__INT_EVENT_RIS = 32'hF8004024; +parameter val_dmac0_ns__INT_EVENT_RIS = 32'h00000000; +parameter mask_dmac0_ns__INT_EVENT_RIS = 32'hFFFFFFFF; + +parameter dmac0_ns__INTMIS = 32'hF8004028; +parameter val_dmac0_ns__INTMIS = 32'h00000000; +parameter mask_dmac0_ns__INTMIS = 32'hFFFFFFFF; + +parameter dmac0_ns__INTCLR = 32'hF800402C; +parameter val_dmac0_ns__INTCLR = 32'h00000000; +parameter mask_dmac0_ns__INTCLR = 32'hFFFFFFFF; + +parameter dmac0_ns__FSRD = 32'hF8004030; +parameter val_dmac0_ns__FSRD = 32'h00000000; +parameter mask_dmac0_ns__FSRD = 32'hFFFFFFFF; + +parameter dmac0_ns__FSRC = 32'hF8004034; +parameter val_dmac0_ns__FSRC = 32'h00000000; +parameter mask_dmac0_ns__FSRC = 32'hFFFFFFFF; + +parameter dmac0_ns__FTRD = 32'hF8004038; +parameter val_dmac0_ns__FTRD = 32'h00000000; +parameter mask_dmac0_ns__FTRD = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR0 = 32'hF8004040; +parameter val_dmac0_ns__FTR0 = 32'h00000000; +parameter mask_dmac0_ns__FTR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR1 = 32'hF8004044; +parameter val_dmac0_ns__FTR1 = 32'h00000000; +parameter mask_dmac0_ns__FTR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR2 = 32'hF8004048; +parameter val_dmac0_ns__FTR2 = 32'h00000000; +parameter mask_dmac0_ns__FTR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR3 = 32'hF800404C; +parameter val_dmac0_ns__FTR3 = 32'h00000000; +parameter mask_dmac0_ns__FTR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR4 = 32'hF8004050; +parameter val_dmac0_ns__FTR4 = 32'h00000000; +parameter mask_dmac0_ns__FTR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR5 = 32'hF8004054; +parameter val_dmac0_ns__FTR5 = 32'h00000000; +parameter mask_dmac0_ns__FTR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR6 = 32'hF8004058; +parameter val_dmac0_ns__FTR6 = 32'h00000000; +parameter mask_dmac0_ns__FTR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR7 = 32'hF800405C; +parameter val_dmac0_ns__FTR7 = 32'h00000000; +parameter mask_dmac0_ns__FTR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR0 = 32'hF8004100; +parameter val_dmac0_ns__CSR0 = 32'h00000000; +parameter mask_dmac0_ns__CSR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC0 = 32'hF8004104; +parameter val_dmac0_ns__CPC0 = 32'h00000000; +parameter mask_dmac0_ns__CPC0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR1 = 32'hF8004108; +parameter val_dmac0_ns__CSR1 = 32'h00000000; +parameter mask_dmac0_ns__CSR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC1 = 32'hF800410C; +parameter val_dmac0_ns__CPC1 = 32'h00000000; +parameter mask_dmac0_ns__CPC1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR2 = 32'hF8004110; +parameter val_dmac0_ns__CSR2 = 32'h00000000; +parameter mask_dmac0_ns__CSR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC2 = 32'hF8004114; +parameter val_dmac0_ns__CPC2 = 32'h00000000; +parameter mask_dmac0_ns__CPC2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR3 = 32'hF8004118; +parameter val_dmac0_ns__CSR3 = 32'h00000000; +parameter mask_dmac0_ns__CSR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC3 = 32'hF800411C; +parameter val_dmac0_ns__CPC3 = 32'h00000000; +parameter mask_dmac0_ns__CPC3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR4 = 32'hF8004120; +parameter val_dmac0_ns__CSR4 = 32'h00000000; +parameter mask_dmac0_ns__CSR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC4 = 32'hF8004124; +parameter val_dmac0_ns__CPC4 = 32'h00000000; +parameter mask_dmac0_ns__CPC4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR5 = 32'hF8004128; +parameter val_dmac0_ns__CSR5 = 32'h00000000; +parameter mask_dmac0_ns__CSR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC5 = 32'hF800412C; +parameter val_dmac0_ns__CPC5 = 32'h00000000; +parameter mask_dmac0_ns__CPC5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR6 = 32'hF8004130; +parameter val_dmac0_ns__CSR6 = 32'h00000000; +parameter mask_dmac0_ns__CSR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC6 = 32'hF8004134; +parameter val_dmac0_ns__CPC6 = 32'h00000000; +parameter mask_dmac0_ns__CPC6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR7 = 32'hF8004138; +parameter val_dmac0_ns__CSR7 = 32'h00000000; +parameter mask_dmac0_ns__CSR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC7 = 32'hF800413C; +parameter val_dmac0_ns__CPC7 = 32'h00000000; +parameter mask_dmac0_ns__CPC7 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR0 = 32'hF8004400; +parameter val_dmac0_ns__SAR0 = 32'h00000000; +parameter mask_dmac0_ns__SAR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR0 = 32'hF8004404; +parameter val_dmac0_ns__DAR0 = 32'h00000000; +parameter mask_dmac0_ns__DAR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR0 = 32'hF8004408; +parameter val_dmac0_ns__CCR0 = 32'h00000000; +parameter mask_dmac0_ns__CCR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_0 = 32'hF800440C; +parameter val_dmac0_ns__LC0_0 = 32'h00000000; +parameter mask_dmac0_ns__LC0_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_0 = 32'hF8004410; +parameter val_dmac0_ns__LC1_0 = 32'h00000000; +parameter mask_dmac0_ns__LC1_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR1 = 32'hF8004420; +parameter val_dmac0_ns__SAR1 = 32'h00000000; +parameter mask_dmac0_ns__SAR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR1 = 32'hF8004424; +parameter val_dmac0_ns__DAR1 = 32'h00000000; +parameter mask_dmac0_ns__DAR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR1 = 32'hF8004428; +parameter val_dmac0_ns__CCR1 = 32'h00000000; +parameter mask_dmac0_ns__CCR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_1 = 32'hF800442C; +parameter val_dmac0_ns__LC0_1 = 32'h00000000; +parameter mask_dmac0_ns__LC0_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_1 = 32'hF8004430; +parameter val_dmac0_ns__LC1_1 = 32'h00000000; +parameter mask_dmac0_ns__LC1_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR2 = 32'hF8004440; +parameter val_dmac0_ns__SAR2 = 32'h00000000; +parameter mask_dmac0_ns__SAR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR2 = 32'hF8004444; +parameter val_dmac0_ns__DAR2 = 32'h00000000; +parameter mask_dmac0_ns__DAR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR2 = 32'hF8004448; +parameter val_dmac0_ns__CCR2 = 32'h00000000; +parameter mask_dmac0_ns__CCR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_2 = 32'hF800444C; +parameter val_dmac0_ns__LC0_2 = 32'h00000000; +parameter mask_dmac0_ns__LC0_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_2 = 32'hF8004450; +parameter val_dmac0_ns__LC1_2 = 32'h00000000; +parameter mask_dmac0_ns__LC1_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR3 = 32'hF8004460; +parameter val_dmac0_ns__SAR3 = 32'h00000000; +parameter mask_dmac0_ns__SAR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR3 = 32'hF8004464; +parameter val_dmac0_ns__DAR3 = 32'h00000000; +parameter mask_dmac0_ns__DAR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR3 = 32'hF8004468; +parameter val_dmac0_ns__CCR3 = 32'h00000000; +parameter mask_dmac0_ns__CCR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_3 = 32'hF800446C; +parameter val_dmac0_ns__LC0_3 = 32'h00000000; +parameter mask_dmac0_ns__LC0_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_3 = 32'hF8004470; +parameter val_dmac0_ns__LC1_3 = 32'h00000000; +parameter mask_dmac0_ns__LC1_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR4 = 32'hF8004480; +parameter val_dmac0_ns__SAR4 = 32'h00000000; +parameter mask_dmac0_ns__SAR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR4 = 32'hF8004484; +parameter val_dmac0_ns__DAR4 = 32'h00000000; +parameter mask_dmac0_ns__DAR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR4 = 32'hF8004488; +parameter val_dmac0_ns__CCR4 = 32'h00000000; +parameter mask_dmac0_ns__CCR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_4 = 32'hF800448C; +parameter val_dmac0_ns__LC0_4 = 32'h00000000; +parameter mask_dmac0_ns__LC0_4 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_4 = 32'hF8004490; +parameter val_dmac0_ns__LC1_4 = 32'h00000000; +parameter mask_dmac0_ns__LC1_4 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR5 = 32'hF80044A0; +parameter val_dmac0_ns__SAR5 = 32'h00000000; +parameter mask_dmac0_ns__SAR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR5 = 32'hF80044A4; +parameter val_dmac0_ns__DAR5 = 32'h00000000; +parameter mask_dmac0_ns__DAR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR5 = 32'hF80044A8; +parameter val_dmac0_ns__CCR5 = 32'h00000000; +parameter mask_dmac0_ns__CCR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_5 = 32'hF80044AC; +parameter val_dmac0_ns__LC0_5 = 32'h00000000; +parameter mask_dmac0_ns__LC0_5 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_5 = 32'hF80044B0; +parameter val_dmac0_ns__LC1_5 = 32'h00000000; +parameter mask_dmac0_ns__LC1_5 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR6 = 32'hF80044C0; +parameter val_dmac0_ns__SAR6 = 32'h00000000; +parameter mask_dmac0_ns__SAR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR6 = 32'hF80044C4; +parameter val_dmac0_ns__DAR6 = 32'h00000000; +parameter mask_dmac0_ns__DAR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR6 = 32'hF80044C8; +parameter val_dmac0_ns__CCR6 = 32'h00000000; +parameter mask_dmac0_ns__CCR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_6 = 32'hF80044CC; +parameter val_dmac0_ns__LC0_6 = 32'h00000000; +parameter mask_dmac0_ns__LC0_6 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_6 = 32'hF80044D0; +parameter val_dmac0_ns__LC1_6 = 32'h00000000; +parameter mask_dmac0_ns__LC1_6 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR7 = 32'hF80044E0; +parameter val_dmac0_ns__SAR7 = 32'h00000000; +parameter mask_dmac0_ns__SAR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR7 = 32'hF80044E4; +parameter val_dmac0_ns__DAR7 = 32'h00000000; +parameter mask_dmac0_ns__DAR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR7 = 32'hF80044E8; +parameter val_dmac0_ns__CCR7 = 32'h00000000; +parameter mask_dmac0_ns__CCR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_7 = 32'hF80044EC; +parameter val_dmac0_ns__LC0_7 = 32'h00000000; +parameter mask_dmac0_ns__LC0_7 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_7 = 32'hF80044F0; +parameter val_dmac0_ns__LC1_7 = 32'h00000000; +parameter mask_dmac0_ns__LC1_7 = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGSTATUS = 32'hF8004D00; +parameter val_dmac0_ns__DBGSTATUS = 32'h00000000; +parameter mask_dmac0_ns__DBGSTATUS = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGCMD = 32'hF8004D04; +parameter val_dmac0_ns__DBGCMD = 32'h00000000; +parameter mask_dmac0_ns__DBGCMD = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGINST0 = 32'hF8004D08; +parameter val_dmac0_ns__DBGINST0 = 32'h00000000; +parameter mask_dmac0_ns__DBGINST0 = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGINST1 = 32'hF8004D0C; +parameter val_dmac0_ns__DBGINST1 = 32'h00000000; +parameter mask_dmac0_ns__DBGINST1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR0 = 32'hF8004E00; +parameter val_dmac0_ns__CR0 = 32'h00000000; +parameter mask_dmac0_ns__CR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR1 = 32'hF8004E04; +parameter val_dmac0_ns__CR1 = 32'h00000000; +parameter mask_dmac0_ns__CR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR2 = 32'hF8004E08; +parameter val_dmac0_ns__CR2 = 32'h00000000; +parameter mask_dmac0_ns__CR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR3 = 32'hF8004E0C; +parameter val_dmac0_ns__CR3 = 32'h00000000; +parameter mask_dmac0_ns__CR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR4 = 32'hF8004E10; +parameter val_dmac0_ns__CR4 = 32'h00000000; +parameter mask_dmac0_ns__CR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CRD = 32'hF8004E14; +parameter val_dmac0_ns__CRD = 32'h00000000; +parameter mask_dmac0_ns__CRD = 32'hFFFFFFFF; + +parameter dmac0_ns__WD = 32'hF8004E80; +parameter val_dmac0_ns__WD = 32'h00000000; +parameter mask_dmac0_ns__WD = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_0 = 32'hF8004FE0; +parameter val_dmac0_ns__periph_id_0 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_1 = 32'hF8004FE4; +parameter val_dmac0_ns__periph_id_1 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_2 = 32'hF8004FE8; +parameter val_dmac0_ns__periph_id_2 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_3 = 32'hF8004FEC; +parameter val_dmac0_ns__periph_id_3 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_0 = 32'hF8004FF0; +parameter val_dmac0_ns__pcell_id_0 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_1 = 32'hF8004FF4; +parameter val_dmac0_ns__pcell_id_1 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_2 = 32'hF8004FF8; +parameter val_dmac0_ns__pcell_id_2 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_3 = 32'hF8004FFC; +parameter val_dmac0_ns__pcell_id_3 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module dmac0_s dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter dmac0_s__DSR = 32'hF8003000; +parameter val_dmac0_s__DSR = 32'h00000000; +parameter mask_dmac0_s__DSR = 32'hFFFFFFFF; + +parameter dmac0_s__DPC = 32'hF8003004; +parameter val_dmac0_s__DPC = 32'h00000000; +parameter mask_dmac0_s__DPC = 32'hFFFFFFFF; + +parameter dmac0_s__INTEN = 32'hF8003020; +parameter val_dmac0_s__INTEN = 32'h00000000; +parameter mask_dmac0_s__INTEN = 32'hFFFFFFFF; + +parameter dmac0_s__INT_EVENT_RIS = 32'hF8003024; +parameter val_dmac0_s__INT_EVENT_RIS = 32'h00000000; +parameter mask_dmac0_s__INT_EVENT_RIS = 32'hFFFFFFFF; + +parameter dmac0_s__INTMIS = 32'hF8003028; +parameter val_dmac0_s__INTMIS = 32'h00000000; +parameter mask_dmac0_s__INTMIS = 32'hFFFFFFFF; + +parameter dmac0_s__INTCLR = 32'hF800302C; +parameter val_dmac0_s__INTCLR = 32'h00000000; +parameter mask_dmac0_s__INTCLR = 32'hFFFFFFFF; + +parameter dmac0_s__FSRD = 32'hF8003030; +parameter val_dmac0_s__FSRD = 32'h00000000; +parameter mask_dmac0_s__FSRD = 32'hFFFFFFFF; + +parameter dmac0_s__FSRC = 32'hF8003034; +parameter val_dmac0_s__FSRC = 32'h00000000; +parameter mask_dmac0_s__FSRC = 32'hFFFFFFFF; + +parameter dmac0_s__FTRD = 32'hF8003038; +parameter val_dmac0_s__FTRD = 32'h00000000; +parameter mask_dmac0_s__FTRD = 32'hFFFFFFFF; + +parameter dmac0_s__FTR0 = 32'hF8003040; +parameter val_dmac0_s__FTR0 = 32'h00000000; +parameter mask_dmac0_s__FTR0 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR1 = 32'hF8003044; +parameter val_dmac0_s__FTR1 = 32'h00000000; +parameter mask_dmac0_s__FTR1 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR2 = 32'hF8003048; +parameter val_dmac0_s__FTR2 = 32'h00000000; +parameter mask_dmac0_s__FTR2 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR3 = 32'hF800304C; +parameter val_dmac0_s__FTR3 = 32'h00000000; +parameter mask_dmac0_s__FTR3 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR4 = 32'hF8003050; +parameter val_dmac0_s__FTR4 = 32'h00000000; +parameter mask_dmac0_s__FTR4 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR5 = 32'hF8003054; +parameter val_dmac0_s__FTR5 = 32'h00000000; +parameter mask_dmac0_s__FTR5 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR6 = 32'hF8003058; +parameter val_dmac0_s__FTR6 = 32'h00000000; +parameter mask_dmac0_s__FTR6 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR7 = 32'hF800305C; +parameter val_dmac0_s__FTR7 = 32'h00000000; +parameter mask_dmac0_s__FTR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR0 = 32'hF8003100; +parameter val_dmac0_s__CSR0 = 32'h00000000; +parameter mask_dmac0_s__CSR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC0 = 32'hF8003104; +parameter val_dmac0_s__CPC0 = 32'h00000000; +parameter mask_dmac0_s__CPC0 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR1 = 32'hF8003108; +parameter val_dmac0_s__CSR1 = 32'h00000000; +parameter mask_dmac0_s__CSR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC1 = 32'hF800310C; +parameter val_dmac0_s__CPC1 = 32'h00000000; +parameter mask_dmac0_s__CPC1 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR2 = 32'hF8003110; +parameter val_dmac0_s__CSR2 = 32'h00000000; +parameter mask_dmac0_s__CSR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC2 = 32'hF8003114; +parameter val_dmac0_s__CPC2 = 32'h00000000; +parameter mask_dmac0_s__CPC2 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR3 = 32'hF8003118; +parameter val_dmac0_s__CSR3 = 32'h00000000; +parameter mask_dmac0_s__CSR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC3 = 32'hF800311C; +parameter val_dmac0_s__CPC3 = 32'h00000000; +parameter mask_dmac0_s__CPC3 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR4 = 32'hF8003120; +parameter val_dmac0_s__CSR4 = 32'h00000000; +parameter mask_dmac0_s__CSR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC4 = 32'hF8003124; +parameter val_dmac0_s__CPC4 = 32'h00000000; +parameter mask_dmac0_s__CPC4 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR5 = 32'hF8003128; +parameter val_dmac0_s__CSR5 = 32'h00000000; +parameter mask_dmac0_s__CSR5 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC5 = 32'hF800312C; +parameter val_dmac0_s__CPC5 = 32'h00000000; +parameter mask_dmac0_s__CPC5 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR6 = 32'hF8003130; +parameter val_dmac0_s__CSR6 = 32'h00000000; +parameter mask_dmac0_s__CSR6 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC6 = 32'hF8003134; +parameter val_dmac0_s__CPC6 = 32'h00000000; +parameter mask_dmac0_s__CPC6 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR7 = 32'hF8003138; +parameter val_dmac0_s__CSR7 = 32'h00000000; +parameter mask_dmac0_s__CSR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC7 = 32'hF800313C; +parameter val_dmac0_s__CPC7 = 32'h00000000; +parameter mask_dmac0_s__CPC7 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR0 = 32'hF8003400; +parameter val_dmac0_s__SAR0 = 32'h00000000; +parameter mask_dmac0_s__SAR0 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR0 = 32'hF8003404; +parameter val_dmac0_s__DAR0 = 32'h00000000; +parameter mask_dmac0_s__DAR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR0 = 32'hF8003408; +parameter val_dmac0_s__CCR0 = 32'h00800200; +parameter mask_dmac0_s__CCR0 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_0 = 32'hF800340C; +parameter val_dmac0_s__LC0_0 = 32'h00000000; +parameter mask_dmac0_s__LC0_0 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_0 = 32'hF8003410; +parameter val_dmac0_s__LC1_0 = 32'h00000000; +parameter mask_dmac0_s__LC1_0 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR1 = 32'hF8003420; +parameter val_dmac0_s__SAR1 = 32'h00000000; +parameter mask_dmac0_s__SAR1 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR1 = 32'hF8003424; +parameter val_dmac0_s__DAR1 = 32'h00000000; +parameter mask_dmac0_s__DAR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR1 = 32'hF8003428; +parameter val_dmac0_s__CCR1 = 32'h00800200; +parameter mask_dmac0_s__CCR1 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_1 = 32'hF800342C; +parameter val_dmac0_s__LC0_1 = 32'h00000000; +parameter mask_dmac0_s__LC0_1 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_1 = 32'hF8003430; +parameter val_dmac0_s__LC1_1 = 32'h00000000; +parameter mask_dmac0_s__LC1_1 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR2 = 32'hF8003440; +parameter val_dmac0_s__SAR2 = 32'h00000000; +parameter mask_dmac0_s__SAR2 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR2 = 32'hF8003444; +parameter val_dmac0_s__DAR2 = 32'h00000000; +parameter mask_dmac0_s__DAR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR2 = 32'hF8003448; +parameter val_dmac0_s__CCR2 = 32'h00800200; +parameter mask_dmac0_s__CCR2 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_2 = 32'hF800344C; +parameter val_dmac0_s__LC0_2 = 32'h00000000; +parameter mask_dmac0_s__LC0_2 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_2 = 32'hF8003450; +parameter val_dmac0_s__LC1_2 = 32'h00000000; +parameter mask_dmac0_s__LC1_2 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR3 = 32'hF8003460; +parameter val_dmac0_s__SAR3 = 32'h00000000; +parameter mask_dmac0_s__SAR3 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR3 = 32'hF8003464; +parameter val_dmac0_s__DAR3 = 32'h00000000; +parameter mask_dmac0_s__DAR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR3 = 32'hF8003468; +parameter val_dmac0_s__CCR3 = 32'h00800200; +parameter mask_dmac0_s__CCR3 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_3 = 32'hF800346C; +parameter val_dmac0_s__LC0_3 = 32'h00000000; +parameter mask_dmac0_s__LC0_3 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_3 = 32'hF8003470; +parameter val_dmac0_s__LC1_3 = 32'h00000000; +parameter mask_dmac0_s__LC1_3 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR4 = 32'hF8003480; +parameter val_dmac0_s__SAR4 = 32'h00000000; +parameter mask_dmac0_s__SAR4 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR4 = 32'hF8003484; +parameter val_dmac0_s__DAR4 = 32'h00000000; +parameter mask_dmac0_s__DAR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR4 = 32'hF8003488; +parameter val_dmac0_s__CCR4 = 32'h00800200; +parameter mask_dmac0_s__CCR4 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_4 = 32'hF800348C; +parameter val_dmac0_s__LC0_4 = 32'h00000000; +parameter mask_dmac0_s__LC0_4 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_4 = 32'hF8003490; +parameter val_dmac0_s__LC1_4 = 32'h00000000; +parameter mask_dmac0_s__LC1_4 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR5 = 32'hF80034A0; +parameter val_dmac0_s__SAR5 = 32'h00000000; +parameter mask_dmac0_s__SAR5 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR5 = 32'hF80034A4; +parameter val_dmac0_s__DAR5 = 32'h00000000; +parameter mask_dmac0_s__DAR5 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR5 = 32'hF80034A8; +parameter val_dmac0_s__CCR5 = 32'h00800200; +parameter mask_dmac0_s__CCR5 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_5 = 32'hF80034AC; +parameter val_dmac0_s__LC0_5 = 32'h00000000; +parameter mask_dmac0_s__LC0_5 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_5 = 32'hF80034B0; +parameter val_dmac0_s__LC1_5 = 32'h00000000; +parameter mask_dmac0_s__LC1_5 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR6 = 32'hF80034C0; +parameter val_dmac0_s__SAR6 = 32'h00000000; +parameter mask_dmac0_s__SAR6 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR6 = 32'hF80034C4; +parameter val_dmac0_s__DAR6 = 32'h00000000; +parameter mask_dmac0_s__DAR6 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR6 = 32'hF80034C8; +parameter val_dmac0_s__CCR6 = 32'h00800200; +parameter mask_dmac0_s__CCR6 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_6 = 32'hF80034CC; +parameter val_dmac0_s__LC0_6 = 32'h00000000; +parameter mask_dmac0_s__LC0_6 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_6 = 32'hF80034D0; +parameter val_dmac0_s__LC1_6 = 32'h00000000; +parameter mask_dmac0_s__LC1_6 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR7 = 32'hF80034E0; +parameter val_dmac0_s__SAR7 = 32'h00000000; +parameter mask_dmac0_s__SAR7 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR7 = 32'hF80034E4; +parameter val_dmac0_s__DAR7 = 32'h00000000; +parameter mask_dmac0_s__DAR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR7 = 32'hF80034E8; +parameter val_dmac0_s__CCR7 = 32'h00800200; +parameter mask_dmac0_s__CCR7 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_7 = 32'hF80034EC; +parameter val_dmac0_s__LC0_7 = 32'h00000000; +parameter mask_dmac0_s__LC0_7 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_7 = 32'hF80034F0; +parameter val_dmac0_s__LC1_7 = 32'h00000000; +parameter mask_dmac0_s__LC1_7 = 32'hFFFFFFFF; + +parameter dmac0_s__DBGSTATUS = 32'hF8003D00; +parameter val_dmac0_s__DBGSTATUS = 32'h00000000; +parameter mask_dmac0_s__DBGSTATUS = 32'hFFFFFFFF; + +parameter dmac0_s__DBGCMD = 32'hF8003D04; +parameter val_dmac0_s__DBGCMD = 32'h00000000; +parameter mask_dmac0_s__DBGCMD = 32'hFFFFFFFF; + +parameter dmac0_s__DBGINST0 = 32'hF8003D08; +parameter val_dmac0_s__DBGINST0 = 32'h00000000; +parameter mask_dmac0_s__DBGINST0 = 32'hFFFFFFFF; + +parameter dmac0_s__DBGINST1 = 32'hF8003D0C; +parameter val_dmac0_s__DBGINST1 = 32'h00000000; +parameter mask_dmac0_s__DBGINST1 = 32'hFFFFFFFF; + +parameter dmac0_s__CR0 = 32'hF8003E00; +parameter val_dmac0_s__CR0 = 32'h001E3071; +parameter mask_dmac0_s__CR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CR1 = 32'hF8003E04; +parameter val_dmac0_s__CR1 = 32'h00000074; +parameter mask_dmac0_s__CR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CR2 = 32'hF8003E08; +parameter val_dmac0_s__CR2 = 32'h00000000; +parameter mask_dmac0_s__CR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CR3 = 32'hF8003E0C; +parameter val_dmac0_s__CR3 = 32'h00000000; +parameter mask_dmac0_s__CR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CR4 = 32'hF8003E10; +parameter val_dmac0_s__CR4 = 32'h00000000; +parameter mask_dmac0_s__CR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CRD = 32'hF8003E14; +parameter val_dmac0_s__CRD = 32'h07FF7F73; +parameter mask_dmac0_s__CRD = 32'hFFFFFFFF; + +parameter dmac0_s__WD = 32'hF8003E80; +parameter val_dmac0_s__WD = 32'h00000000; +parameter mask_dmac0_s__WD = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_0 = 32'hF8003FE0; +parameter val_dmac0_s__periph_id_0 = 32'h00000030; +parameter mask_dmac0_s__periph_id_0 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_1 = 32'hF8003FE4; +parameter val_dmac0_s__periph_id_1 = 32'h00000013; +parameter mask_dmac0_s__periph_id_1 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_2 = 32'hF8003FE8; +parameter val_dmac0_s__periph_id_2 = 32'h00000024; +parameter mask_dmac0_s__periph_id_2 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_3 = 32'hF8003FEC; +parameter val_dmac0_s__periph_id_3 = 32'h00000000; +parameter mask_dmac0_s__periph_id_3 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_0 = 32'hF8003FF0; +parameter val_dmac0_s__pcell_id_0 = 32'h0000000D; +parameter mask_dmac0_s__pcell_id_0 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_1 = 32'hF8003FF4; +parameter val_dmac0_s__pcell_id_1 = 32'h000000F0; +parameter mask_dmac0_s__pcell_id_1 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_2 = 32'hF8003FF8; +parameter val_dmac0_s__pcell_id_2 = 32'h00000005; +parameter mask_dmac0_s__pcell_id_2 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_3 = 32'hF8003FFC; +parameter val_dmac0_s__pcell_id_3 = 32'h000000B1; +parameter mask_dmac0_s__pcell_id_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module efuse_ctrl efuse_ctrl +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter efuse_ctrl__WR_LOCK = 32'hF800D000; +parameter val_efuse_ctrl__WR_LOCK = 32'h00000000; +parameter mask_efuse_ctrl__WR_LOCK = 32'hFFFFFFFF; + +parameter efuse_ctrl__WR_UNLOCK = 32'hF800D004; +parameter val_efuse_ctrl__WR_UNLOCK = 32'h00000000; +parameter mask_efuse_ctrl__WR_UNLOCK = 32'hFFFFFFFF; + +parameter efuse_ctrl__WR_LOCKSTA = 32'hF800D008; +parameter val_efuse_ctrl__WR_LOCKSTA = 32'h00000001; +parameter mask_efuse_ctrl__WR_LOCKSTA = 32'hFFFFFFFF; + +parameter efuse_ctrl__CFG = 32'hF800D00C; +parameter val_efuse_ctrl__CFG = 32'h00010F00; +parameter mask_efuse_ctrl__CFG = 32'hFFFFFFFF; + +parameter efuse_ctrl__STATUS = 32'hF800D010; +parameter val_efuse_ctrl__STATUS = 32'h00100000; +parameter mask_efuse_ctrl__STATUS = 32'hFFFFFFFF; + +parameter efuse_ctrl__CONTROL = 32'hF800D014; +parameter val_efuse_ctrl__CONTROL = 32'h00000003; +parameter mask_efuse_ctrl__CONTROL = 32'hFFFFFFFF; + +parameter efuse_ctrl__PGM_STBW = 32'hF800D018; +parameter val_efuse_ctrl__PGM_STBW = 32'h000002D0; +parameter mask_efuse_ctrl__PGM_STBW = 32'hFFFFFFFF; + +parameter efuse_ctrl__RD_STBW = 32'hF800D01C; +parameter val_efuse_ctrl__RD_STBW = 32'h0000000B; +parameter mask_efuse_ctrl__RD_STBW = 32'hFFFFFFFF; + + +// ************************************************************ +// Module gem0 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gem0__net_ctrl = 32'hE000B000; +parameter val_gem0__net_ctrl = 32'h00000000; +parameter mask_gem0__net_ctrl = 32'hFFFFFFFF; + +parameter gem0__net_cfg = 32'hE000B004; +parameter val_gem0__net_cfg = 32'h00080000; +parameter mask_gem0__net_cfg = 32'hFFFFFFFF; + +parameter gem0__net_status = 32'hE000B008; +parameter val_gem0__net_status = 32'h00000004; +parameter mask_gem0__net_status = 32'hFFFFFFFD; + +parameter gem0__user_io = 32'hE000B00C; +parameter val_gem0__user_io = 32'h00000000; +parameter mask_gem0__user_io = 32'h0000FFFF; + +parameter gem0__dma_cfg = 32'hE000B010; +parameter val_gem0__dma_cfg = 32'h00020784; +parameter mask_gem0__dma_cfg = 32'hFFFFFFFF; + +parameter gem0__tx_status = 32'hE000B014; +parameter val_gem0__tx_status = 32'h00000000; +parameter mask_gem0__tx_status = 32'hFFFFFFFF; + +parameter gem0__rx_qbar = 32'hE000B018; +parameter val_gem0__rx_qbar = 32'h00000000; +parameter mask_gem0__rx_qbar = 32'hFFFFFFFF; + +parameter gem0__tx_qbar = 32'hE000B01C; +parameter val_gem0__tx_qbar = 32'h00000000; +parameter mask_gem0__tx_qbar = 32'hFFFFFFFF; + +parameter gem0__rx_status = 32'hE000B020; +parameter val_gem0__rx_status = 32'h00000000; +parameter mask_gem0__rx_status = 32'hFFFFFFFF; + +parameter gem0__intr_status = 32'hE000B024; +parameter val_gem0__intr_status = 32'h00000000; +parameter mask_gem0__intr_status = 32'hFFFFFFFF; + +parameter gem0__intr_en = 32'hE000B028; +parameter val_gem0__intr_en = 32'h00000000; +parameter mask_gem0__intr_en = 32'h00000000; + +parameter gem0__intr_dis = 32'hE000B02C; +parameter val_gem0__intr_dis = 32'h00000000; +parameter mask_gem0__intr_dis = 32'h00000000; + +parameter gem0__intr_mask = 32'hE000B030; +parameter val_gem0__intr_mask = 32'h0001FFFF; +parameter mask_gem0__intr_mask = 32'hFC01FFFF; + +parameter gem0__phy_maint = 32'hE000B034; +parameter val_gem0__phy_maint = 32'h00000000; +parameter mask_gem0__phy_maint = 32'hFFFFFFFF; + +parameter gem0__rx_pauseq = 32'hE000B038; +parameter val_gem0__rx_pauseq = 32'h00000000; +parameter mask_gem0__rx_pauseq = 32'hFFFFFFFF; + +parameter gem0__tx_pauseq = 32'hE000B03C; +parameter val_gem0__tx_pauseq = 32'h0000FFFF; +parameter mask_gem0__tx_pauseq = 32'hFFFFFFFF; + +parameter gem0__tx_partial_st_fwd = 32'hE000B040; +parameter val_gem0__tx_partial_st_fwd = 32'h000003FF; +parameter mask_gem0__tx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem0__rx_partial_st_fwd = 32'hE000B044; +parameter val_gem0__rx_partial_st_fwd = 32'h000003FF; +parameter mask_gem0__rx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem0__hash_bot = 32'hE000B080; +parameter val_gem0__hash_bot = 32'h00000000; +parameter mask_gem0__hash_bot = 32'hFFFFFFFF; + +parameter gem0__hash_top = 32'hE000B084; +parameter val_gem0__hash_top = 32'h00000000; +parameter mask_gem0__hash_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_bot = 32'hE000B088; +parameter val_gem0__spec_addr1_bot = 32'h00000000; +parameter mask_gem0__spec_addr1_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_top = 32'hE000B08C; +parameter val_gem0__spec_addr1_top = 32'h00000000; +parameter mask_gem0__spec_addr1_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr2_bot = 32'hE000B090; +parameter val_gem0__spec_addr2_bot = 32'h00000000; +parameter mask_gem0__spec_addr2_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr2_top = 32'hE000B094; +parameter val_gem0__spec_addr2_top = 32'h00000000; +parameter mask_gem0__spec_addr2_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr3_bot = 32'hE000B098; +parameter val_gem0__spec_addr3_bot = 32'h00000000; +parameter mask_gem0__spec_addr3_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr3_top = 32'hE000B09C; +parameter val_gem0__spec_addr3_top = 32'h00000000; +parameter mask_gem0__spec_addr3_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr4_bot = 32'hE000B0A0; +parameter val_gem0__spec_addr4_bot = 32'h00000000; +parameter mask_gem0__spec_addr4_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr4_top = 32'hE000B0A4; +parameter val_gem0__spec_addr4_top = 32'h00000000; +parameter mask_gem0__spec_addr4_top = 32'hFFFFFFFF; + +parameter gem0__type_id_match1 = 32'hE000B0A8; +parameter val_gem0__type_id_match1 = 32'h00000000; +parameter mask_gem0__type_id_match1 = 32'hFFFFFFFF; + +parameter gem0__type_id_match2 = 32'hE000B0AC; +parameter val_gem0__type_id_match2 = 32'h00000000; +parameter mask_gem0__type_id_match2 = 32'hFFFFFFFF; + +parameter gem0__type_id_match3 = 32'hE000B0B0; +parameter val_gem0__type_id_match3 = 32'h00000000; +parameter mask_gem0__type_id_match3 = 32'hFFFFFFFF; + +parameter gem0__type_id_match4 = 32'hE000B0B4; +parameter val_gem0__type_id_match4 = 32'h00000000; +parameter mask_gem0__type_id_match4 = 32'hFFFFFFFF; + +parameter gem0__wake_on_lan = 32'hE000B0B8; +parameter val_gem0__wake_on_lan = 32'h00000000; +parameter mask_gem0__wake_on_lan = 32'hFFFFFFFF; + +parameter gem0__ipg_stretch = 32'hE000B0BC; +parameter val_gem0__ipg_stretch = 32'h00000000; +parameter mask_gem0__ipg_stretch = 32'hFFFFFFFF; + +parameter gem0__stacked_vlan = 32'hE000B0C0; +parameter val_gem0__stacked_vlan = 32'h00000000; +parameter mask_gem0__stacked_vlan = 32'hFFFFFFFF; + +parameter gem0__tx_pfc_pause = 32'hE000B0C4; +parameter val_gem0__tx_pfc_pause = 32'h00000000; +parameter mask_gem0__tx_pfc_pause = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_mask_bot = 32'hE000B0C8; +parameter val_gem0__spec_addr1_mask_bot = 32'h00000000; +parameter mask_gem0__spec_addr1_mask_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_mask_top = 32'hE000B0CC; +parameter val_gem0__spec_addr1_mask_top = 32'h00000000; +parameter mask_gem0__spec_addr1_mask_top = 32'hFFFFFFFF; + +parameter gem0__module_id = 32'hE000B0FC; +parameter val_gem0__module_id = 32'h00020118; +parameter mask_gem0__module_id = 32'hFFFFFFFF; + +parameter gem0__octets_tx_bot = 32'hE000B100; +parameter val_gem0__octets_tx_bot = 32'h00000000; +parameter mask_gem0__octets_tx_bot = 32'hFFFFFFFF; + +parameter gem0__octets_tx_top = 32'hE000B104; +parameter val_gem0__octets_tx_top = 32'h00000000; +parameter mask_gem0__octets_tx_top = 32'hFFFFFFFF; + +parameter gem0__frames_tx = 32'hE000B108; +parameter val_gem0__frames_tx = 32'h00000000; +parameter mask_gem0__frames_tx = 32'hFFFFFFFF; + +parameter gem0__broadcast_frames_tx = 32'hE000B10C; +parameter val_gem0__broadcast_frames_tx = 32'h00000000; +parameter mask_gem0__broadcast_frames_tx = 32'hFFFFFFFF; + +parameter gem0__multi_frames_tx = 32'hE000B110; +parameter val_gem0__multi_frames_tx = 32'h00000000; +parameter mask_gem0__multi_frames_tx = 32'hFFFFFFFF; + +parameter gem0__pause_frames_tx = 32'hE000B114; +parameter val_gem0__pause_frames_tx = 32'h00000000; +parameter mask_gem0__pause_frames_tx = 32'hFFFFFFFF; + +parameter gem0__frames_64b_tx = 32'hE000B118; +parameter val_gem0__frames_64b_tx = 32'h00000000; +parameter mask_gem0__frames_64b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_65to127b_tx = 32'hE000B11C; +parameter val_gem0__frames_65to127b_tx = 32'h00000000; +parameter mask_gem0__frames_65to127b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_128to255b_tx = 32'hE000B120; +parameter val_gem0__frames_128to255b_tx = 32'h00000000; +parameter mask_gem0__frames_128to255b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_256to511b_tx = 32'hE000B124; +parameter val_gem0__frames_256to511b_tx = 32'h00000000; +parameter mask_gem0__frames_256to511b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_512to1023b_tx = 32'hE000B128; +parameter val_gem0__frames_512to1023b_tx = 32'h00000000; +parameter mask_gem0__frames_512to1023b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_1024to1518b_tx = 32'hE000B12C; +parameter val_gem0__frames_1024to1518b_tx = 32'h00000000; +parameter mask_gem0__frames_1024to1518b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_gt1518b_tx = 32'hE000B130; +parameter val_gem0__frames_gt1518b_tx = 32'h00000000; +parameter mask_gem0__frames_gt1518b_tx = 32'hFFFFFFFF; + +parameter gem0__tx_under_runs = 32'hE000B134; +parameter val_gem0__tx_under_runs = 32'h00000000; +parameter mask_gem0__tx_under_runs = 32'hFFFFFFFF; + +parameter gem0__single_collisn_frames = 32'hE000B138; +parameter val_gem0__single_collisn_frames = 32'h00000000; +parameter mask_gem0__single_collisn_frames = 32'hFFFFFFFF; + +parameter gem0__multi_collisn_frames = 32'hE000B13C; +parameter val_gem0__multi_collisn_frames = 32'h00000000; +parameter mask_gem0__multi_collisn_frames = 32'hFFFFFFFF; + +parameter gem0__excessive_collisns = 32'hE000B140; +parameter val_gem0__excessive_collisns = 32'h00000000; +parameter mask_gem0__excessive_collisns = 32'hFFFFFFFF; + +parameter gem0__late_collisns = 32'hE000B144; +parameter val_gem0__late_collisns = 32'h00000000; +parameter mask_gem0__late_collisns = 32'hFFFFFFFF; + +parameter gem0__deferred_tx_frames = 32'hE000B148; +parameter val_gem0__deferred_tx_frames = 32'h00000000; +parameter mask_gem0__deferred_tx_frames = 32'hFFFFFFFF; + +parameter gem0__carrier_sense_errs = 32'hE000B14C; +parameter val_gem0__carrier_sense_errs = 32'h00000000; +parameter mask_gem0__carrier_sense_errs = 32'hFFFFFFFF; + +parameter gem0__octets_rx_bot = 32'hE000B150; +parameter val_gem0__octets_rx_bot = 32'h00000000; +parameter mask_gem0__octets_rx_bot = 32'hFFFFFFFF; + +parameter gem0__octets_rx_top = 32'hE000B154; +parameter val_gem0__octets_rx_top = 32'h00000000; +parameter mask_gem0__octets_rx_top = 32'hFFFFFFFF; + +parameter gem0__frames_rx = 32'hE000B158; +parameter val_gem0__frames_rx = 32'h00000000; +parameter mask_gem0__frames_rx = 32'hFFFFFFFF; + +parameter gem0__bdcast_fames_rx = 32'hE000B15C; +parameter val_gem0__bdcast_fames_rx = 32'h00000000; +parameter mask_gem0__bdcast_fames_rx = 32'hFFFFFFFF; + +parameter gem0__multi_frames_rx = 32'hE000B160; +parameter val_gem0__multi_frames_rx = 32'h00000000; +parameter mask_gem0__multi_frames_rx = 32'hFFFFFFFF; + +parameter gem0__pause_rx = 32'hE000B164; +parameter val_gem0__pause_rx = 32'h00000000; +parameter mask_gem0__pause_rx = 32'hFFFFFFFF; + +parameter gem0__frames_64b_rx = 32'hE000B168; +parameter val_gem0__frames_64b_rx = 32'h00000000; +parameter mask_gem0__frames_64b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_65to127b_rx = 32'hE000B16C; +parameter val_gem0__frames_65to127b_rx = 32'h00000000; +parameter mask_gem0__frames_65to127b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_128to255b_rx = 32'hE000B170; +parameter val_gem0__frames_128to255b_rx = 32'h00000000; +parameter mask_gem0__frames_128to255b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_256to511b_rx = 32'hE000B174; +parameter val_gem0__frames_256to511b_rx = 32'h00000000; +parameter mask_gem0__frames_256to511b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_512to1023b_rx = 32'hE000B178; +parameter val_gem0__frames_512to1023b_rx = 32'h00000000; +parameter mask_gem0__frames_512to1023b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_1024to1518b_rx = 32'hE000B17C; +parameter val_gem0__frames_1024to1518b_rx = 32'h00000000; +parameter mask_gem0__frames_1024to1518b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_gt1518b_rx = 32'hE000B180; +parameter val_gem0__frames_gt1518b_rx = 32'h00000000; +parameter mask_gem0__frames_gt1518b_rx = 32'hFFFFFFFF; + +parameter gem0__undersz_rx = 32'hE000B184; +parameter val_gem0__undersz_rx = 32'h00000000; +parameter mask_gem0__undersz_rx = 32'hFFFFFFFF; + +parameter gem0__oversz_rx = 32'hE000B188; +parameter val_gem0__oversz_rx = 32'h00000000; +parameter mask_gem0__oversz_rx = 32'hFFFFFFFF; + +parameter gem0__jab_rx = 32'hE000B18C; +parameter val_gem0__jab_rx = 32'h00000000; +parameter mask_gem0__jab_rx = 32'hFFFFFFFF; + +parameter gem0__fcs_errors = 32'hE000B190; +parameter val_gem0__fcs_errors = 32'h00000000; +parameter mask_gem0__fcs_errors = 32'hFFFFFFFF; + +parameter gem0__length_field_errors = 32'hE000B194; +parameter val_gem0__length_field_errors = 32'h00000000; +parameter mask_gem0__length_field_errors = 32'hFFFFFFFF; + +parameter gem0__rx_symbol_errors = 32'hE000B198; +parameter val_gem0__rx_symbol_errors = 32'h00000000; +parameter mask_gem0__rx_symbol_errors = 32'hFFFFFFFF; + +parameter gem0__align_errors = 32'hE000B19C; +parameter val_gem0__align_errors = 32'h00000000; +parameter mask_gem0__align_errors = 32'hFFFFFFFF; + +parameter gem0__rx_resource_errors = 32'hE000B1A0; +parameter val_gem0__rx_resource_errors = 32'h00000000; +parameter mask_gem0__rx_resource_errors = 32'hFFFFFFFF; + +parameter gem0__rx_overrun_errors = 32'hE000B1A4; +parameter val_gem0__rx_overrun_errors = 32'h00000000; +parameter mask_gem0__rx_overrun_errors = 32'hFFFFFFFF; + +parameter gem0__ip_hdr_csum_errors = 32'hE000B1A8; +parameter val_gem0__ip_hdr_csum_errors = 32'h00000000; +parameter mask_gem0__ip_hdr_csum_errors = 32'hFFFFFFFF; + +parameter gem0__tcp_csum_errors = 32'hE000B1AC; +parameter val_gem0__tcp_csum_errors = 32'h00000000; +parameter mask_gem0__tcp_csum_errors = 32'hFFFFFFFF; + +parameter gem0__udp_csum_errors = 32'hE000B1B0; +parameter val_gem0__udp_csum_errors = 32'h00000000; +parameter mask_gem0__udp_csum_errors = 32'hFFFFFFFF; + +parameter gem0__timer_strobe_s = 32'hE000B1C8; +parameter val_gem0__timer_strobe_s = 32'h00000000; +parameter mask_gem0__timer_strobe_s = 32'hFFFFFFFF; + +parameter gem0__timer_strobe_ns = 32'hE000B1CC; +parameter val_gem0__timer_strobe_ns = 32'h00000000; +parameter mask_gem0__timer_strobe_ns = 32'hFFFFFFFF; + +parameter gem0__timer_s = 32'hE000B1D0; +parameter val_gem0__timer_s = 32'h00000000; +parameter mask_gem0__timer_s = 32'hFFFFFFFF; + +parameter gem0__timer_ns = 32'hE000B1D4; +parameter val_gem0__timer_ns = 32'h00000000; +parameter mask_gem0__timer_ns = 32'hFFFFFFFF; + +parameter gem0__timer_adjust = 32'hE000B1D8; +parameter val_gem0__timer_adjust = 32'h00000000; +parameter mask_gem0__timer_adjust = 32'hFFFFFFFF; + +parameter gem0__timer_incr = 32'hE000B1DC; +parameter val_gem0__timer_incr = 32'h00000000; +parameter mask_gem0__timer_incr = 32'hFFFFFFFF; + +parameter gem0__ptp_tx_s = 32'hE000B1E0; +parameter val_gem0__ptp_tx_s = 32'h00000000; +parameter mask_gem0__ptp_tx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_tx_ns = 32'hE000B1E4; +parameter val_gem0__ptp_tx_ns = 32'h00000000; +parameter mask_gem0__ptp_tx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_rx_s = 32'hE000B1E8; +parameter val_gem0__ptp_rx_s = 32'h00000000; +parameter mask_gem0__ptp_rx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_rx_ns = 32'hE000B1EC; +parameter val_gem0__ptp_rx_ns = 32'h00000000; +parameter mask_gem0__ptp_rx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_tx_s = 32'hE000B1F0; +parameter val_gem0__ptp_peer_tx_s = 32'h00000000; +parameter mask_gem0__ptp_peer_tx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_tx_ns = 32'hE000B1F4; +parameter val_gem0__ptp_peer_tx_ns = 32'h00000000; +parameter mask_gem0__ptp_peer_tx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_rx_s = 32'hE000B1F8; +parameter val_gem0__ptp_peer_rx_s = 32'h00000000; +parameter mask_gem0__ptp_peer_rx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_rx_ns = 32'hE000B1FC; +parameter val_gem0__ptp_peer_rx_ns = 32'h00000000; +parameter mask_gem0__ptp_peer_rx_ns = 32'hFFFFFFFF; + +parameter gem0__pcs_ctrl = 32'hE000B200; +parameter val_gem0__pcs_ctrl = 32'h00000000; +parameter mask_gem0__pcs_ctrl = 32'h00000000; + +parameter gem0__pcs_status = 32'hE000B204; +parameter val_gem0__pcs_status = 32'h00000000; +parameter mask_gem0__pcs_status = 32'h00000000; + +parameter gem0__pcs_upper_phy_id = 32'hE000B208; +parameter val_gem0__pcs_upper_phy_id = 32'h00000000; +parameter mask_gem0__pcs_upper_phy_id = 32'h00000000; + +parameter gem0__pcs_lower_phy_id = 32'hE000B20C; +parameter val_gem0__pcs_lower_phy_id = 32'h00000000; +parameter mask_gem0__pcs_lower_phy_id = 32'h00000000; + +parameter gem0__pcs_autoneg_ad = 32'hE000B210; +parameter val_gem0__pcs_autoneg_ad = 32'h00000000; +parameter mask_gem0__pcs_autoneg_ad = 32'h00000000; + +parameter gem0__pcs_autoneg_ability = 32'hE000B214; +parameter val_gem0__pcs_autoneg_ability = 32'h00000000; +parameter mask_gem0__pcs_autoneg_ability = 32'h00000000; + +parameter gem0__pcs_autonec_exp = 32'hE000B218; +parameter val_gem0__pcs_autonec_exp = 32'h00000000; +parameter mask_gem0__pcs_autonec_exp = 32'h00000000; + +parameter gem0__pcs_autoneg_next_pg = 32'hE000B21C; +parameter val_gem0__pcs_autoneg_next_pg = 32'h00000000; +parameter mask_gem0__pcs_autoneg_next_pg = 32'h00000000; + +parameter gem0__pcs_autoneg_pnext_pg = 32'hE000B220; +parameter val_gem0__pcs_autoneg_pnext_pg = 32'h00000000; +parameter mask_gem0__pcs_autoneg_pnext_pg = 32'h00000000; + +parameter gem0__pcs_extended_status = 32'hE000B23C; +parameter val_gem0__pcs_extended_status = 32'h00000000; +parameter mask_gem0__pcs_extended_status = 32'h00000000; + +parameter gem0__design_cfg1 = 32'hE000B280; +parameter val_gem0__design_cfg1 = 32'h02000000; +parameter mask_gem0__design_cfg1 = 32'h0E000000; + +parameter gem0__design_cfg2 = 32'hE000B284; +parameter val_gem0__design_cfg2 = 32'h2A813FFF; +parameter mask_gem0__design_cfg2 = 32'h3FCFFFFF; + +parameter gem0__design_cfg3 = 32'hE000B288; +parameter val_gem0__design_cfg3 = 32'h00000000; +parameter mask_gem0__design_cfg3 = 32'hFFFFFFFF; + +parameter gem0__design_cfg4 = 32'hE000B28C; +parameter val_gem0__design_cfg4 = 32'h00000000; +parameter mask_gem0__design_cfg4 = 32'hFFFFFFFF; + +parameter gem0__design_cfg5 = 32'hE000B290; +parameter val_gem0__design_cfg5 = 32'h002F2045; +parameter mask_gem0__design_cfg5 = 32'h0FFFFCFF; + +parameter gem0__design_cfg6 = 32'hE000B294; +parameter val_gem0__design_cfg6 = 32'h00000000; +parameter mask_gem0__design_cfg6 = 32'h00000000; + +parameter gem0__design_cfg7 = 32'hE000B298; +parameter val_gem0__design_cfg7 = 32'h00000000; +parameter mask_gem0__design_cfg7 = 32'h00000000; + +parameter gem0__isr_pq1 = 32'hE000B400; +parameter val_gem0__isr_pq1 = 32'h00000000; +parameter mask_gem0__isr_pq1 = 32'h00000000; + +parameter gem0__isr_pq2 = 32'hE000B404; +parameter val_gem0__isr_pq2 = 32'h00000000; +parameter mask_gem0__isr_pq2 = 32'h00000000; + +parameter gem0__isr_pq3 = 32'hE000B408; +parameter val_gem0__isr_pq3 = 32'h00000000; +parameter mask_gem0__isr_pq3 = 32'h00000000; + +parameter gem0__isr_pq4 = 32'hE000B40C; +parameter val_gem0__isr_pq4 = 32'h00000000; +parameter mask_gem0__isr_pq4 = 32'h00000000; + +parameter gem0__isr_pq5 = 32'hE000B410; +parameter val_gem0__isr_pq5 = 32'h00000000; +parameter mask_gem0__isr_pq5 = 32'h00000000; + +parameter gem0__isr_pq6 = 32'hE000B414; +parameter val_gem0__isr_pq6 = 32'h00000000; +parameter mask_gem0__isr_pq6 = 32'h00000000; + +parameter gem0__isr_pq7 = 32'hE000B418; +parameter val_gem0__isr_pq7 = 32'h00000000; +parameter mask_gem0__isr_pq7 = 32'h00000000; + +parameter gem0__tx_qbar_q1 = 32'hE000B440; +parameter val_gem0__tx_qbar_q1 = 32'h00000000; +parameter mask_gem0__tx_qbar_q1 = 32'h00000000; + +parameter gem0__tx_qbar_q2 = 32'hE000B444; +parameter val_gem0__tx_qbar_q2 = 32'h00000000; +parameter mask_gem0__tx_qbar_q2 = 32'h00000000; + +parameter gem0__tx_qbar_q3 = 32'hE000B448; +parameter val_gem0__tx_qbar_q3 = 32'h00000000; +parameter mask_gem0__tx_qbar_q3 = 32'h00000000; + +parameter gem0__tx_qbar_q4 = 32'hE000B44C; +parameter val_gem0__tx_qbar_q4 = 32'h00000000; +parameter mask_gem0__tx_qbar_q4 = 32'h00000000; + +parameter gem0__tx_qbar_q5 = 32'hE000B450; +parameter val_gem0__tx_qbar_q5 = 32'h00000000; +parameter mask_gem0__tx_qbar_q5 = 32'h00000000; + +parameter gem0__tx_qbar_q6 = 32'hE000B454; +parameter val_gem0__tx_qbar_q6 = 32'h00000000; +parameter mask_gem0__tx_qbar_q6 = 32'h00000000; + +parameter gem0__tx_qbar_q7 = 32'hE000B458; +parameter val_gem0__tx_qbar_q7 = 32'h00000000; +parameter mask_gem0__tx_qbar_q7 = 32'h00000000; + +parameter gem0__rx_qbar_q1 = 32'hE000B480; +parameter val_gem0__rx_qbar_q1 = 32'h00000000; +parameter mask_gem0__rx_qbar_q1 = 32'h00000000; + +parameter gem0__rx_qbar_q2 = 32'hE000B484; +parameter val_gem0__rx_qbar_q2 = 32'h00000000; +parameter mask_gem0__rx_qbar_q2 = 32'h00000000; + +parameter gem0__rx_qbar_q3 = 32'hE000B488; +parameter val_gem0__rx_qbar_q3 = 32'h00000000; +parameter mask_gem0__rx_qbar_q3 = 32'h00000000; + +parameter gem0__rx_qbar_q4 = 32'hE000B48C; +parameter val_gem0__rx_qbar_q4 = 32'h00000000; +parameter mask_gem0__rx_qbar_q4 = 32'h00000000; + +parameter gem0__rx_qbar_q5 = 32'hE000B490; +parameter val_gem0__rx_qbar_q5 = 32'h00000000; +parameter mask_gem0__rx_qbar_q5 = 32'h00000000; + +parameter gem0__rx_qbar_q6 = 32'hE000B494; +parameter val_gem0__rx_qbar_q6 = 32'h00000000; +parameter mask_gem0__rx_qbar_q6 = 32'h00000000; + +parameter gem0__rx_qbar_q7 = 32'hE000B498; +parameter val_gem0__rx_qbar_q7 = 32'h00000000; +parameter mask_gem0__rx_qbar_q7 = 32'h00000000; + +parameter gem0__rx_bufsz_q1 = 32'hE000B4A0; +parameter val_gem0__rx_bufsz_q1 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q1 = 32'h00000000; + +parameter gem0__rx_bufsz_q2 = 32'hE000B4A4; +parameter val_gem0__rx_bufsz_q2 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q2 = 32'h00000000; + +parameter gem0__rx_bufsz_q3 = 32'hE000B4A8; +parameter val_gem0__rx_bufsz_q3 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q3 = 32'h00000000; + +parameter gem0__rx_bufsz_q4 = 32'hE000B4AC; +parameter val_gem0__rx_bufsz_q4 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q4 = 32'h00000000; + +parameter gem0__rx_bufsz_q5 = 32'hE000B4B0; +parameter val_gem0__rx_bufsz_q5 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q5 = 32'h00000000; + +parameter gem0__rx_bufsz_q6 = 32'hE000B4B4; +parameter val_gem0__rx_bufsz_q6 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q6 = 32'h00000000; + +parameter gem0__rx_bufsz_q7 = 32'hE000B4B8; +parameter val_gem0__rx_bufsz_q7 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q7 = 32'h00000000; + +parameter gem0__screen_t1_r0 = 32'hE000B500; +parameter val_gem0__screen_t1_r0 = 32'h00000000; +parameter mask_gem0__screen_t1_r0 = 32'h00000000; + +parameter gem0__screen_t1_r1 = 32'hE000B504; +parameter val_gem0__screen_t1_r1 = 32'h00000000; +parameter mask_gem0__screen_t1_r1 = 32'h00000000; + +parameter gem0__screen_t1_r2 = 32'hE000B508; +parameter val_gem0__screen_t1_r2 = 32'h00000000; +parameter mask_gem0__screen_t1_r2 = 32'h00000000; + +parameter gem0__screen_t1_r3 = 32'hE000B50C; +parameter val_gem0__screen_t1_r3 = 32'h00000000; +parameter mask_gem0__screen_t1_r3 = 32'h00000000; + +parameter gem0__screen_t1_r4 = 32'hE000B510; +parameter val_gem0__screen_t1_r4 = 32'h00000000; +parameter mask_gem0__screen_t1_r4 = 32'h00000000; + +parameter gem0__screen_t1_r5 = 32'hE000B514; +parameter val_gem0__screen_t1_r5 = 32'h00000000; +parameter mask_gem0__screen_t1_r5 = 32'h00000000; + +parameter gem0__screen_t1_r6 = 32'hE000B518; +parameter val_gem0__screen_t1_r6 = 32'h00000000; +parameter mask_gem0__screen_t1_r6 = 32'h00000000; + +parameter gem0__screen_t1_r7 = 32'hE000B51C; +parameter val_gem0__screen_t1_r7 = 32'h00000000; +parameter mask_gem0__screen_t1_r7 = 32'h00000000; + +parameter gem0__screen_t1_r8 = 32'hE000B520; +parameter val_gem0__screen_t1_r8 = 32'h00000000; +parameter mask_gem0__screen_t1_r8 = 32'h00000000; + +parameter gem0__screen_t1_r9 = 32'hE000B524; +parameter val_gem0__screen_t1_r9 = 32'h00000000; +parameter mask_gem0__screen_t1_r9 = 32'h00000000; + +parameter gem0__screen_t1_r10 = 32'hE000B528; +parameter val_gem0__screen_t1_r10 = 32'h00000000; +parameter mask_gem0__screen_t1_r10 = 32'h00000000; + +parameter gem0__screen_t1_r11 = 32'hE000B52C; +parameter val_gem0__screen_t1_r11 = 32'h00000000; +parameter mask_gem0__screen_t1_r11 = 32'h00000000; + +parameter gem0__screen_t1_r12 = 32'hE000B530; +parameter val_gem0__screen_t1_r12 = 32'h00000000; +parameter mask_gem0__screen_t1_r12 = 32'h00000000; + +parameter gem0__screen_t1_r13 = 32'hE000B534; +parameter val_gem0__screen_t1_r13 = 32'h00000000; +parameter mask_gem0__screen_t1_r13 = 32'h00000000; + +parameter gem0__screen_t1_r14 = 32'hE000B538; +parameter val_gem0__screen_t1_r14 = 32'h00000000; +parameter mask_gem0__screen_t1_r14 = 32'h00000000; + +parameter gem0__screen_t1_r15 = 32'hE000B53C; +parameter val_gem0__screen_t1_r15 = 32'h00000000; +parameter mask_gem0__screen_t1_r15 = 32'h00000000; + +parameter gem0__screen_t2_r0 = 32'hE000B540; +parameter val_gem0__screen_t2_r0 = 32'h00000000; +parameter mask_gem0__screen_t2_r0 = 32'h00000000; + +parameter gem0__screen_t2_r1 = 32'hE000B544; +parameter val_gem0__screen_t2_r1 = 32'h00000000; +parameter mask_gem0__screen_t2_r1 = 32'h00000000; + +parameter gem0__screen_t2_r2 = 32'hE000B548; +parameter val_gem0__screen_t2_r2 = 32'h00000000; +parameter mask_gem0__screen_t2_r2 = 32'h00000000; + +parameter gem0__screen_t2_r3 = 32'hE000B54C; +parameter val_gem0__screen_t2_r3 = 32'h00000000; +parameter mask_gem0__screen_t2_r3 = 32'h00000000; + +parameter gem0__screen_t2_r4 = 32'hE000B550; +parameter val_gem0__screen_t2_r4 = 32'h00000000; +parameter mask_gem0__screen_t2_r4 = 32'h00000000; + +parameter gem0__screen_t2_r5 = 32'hE000B554; +parameter val_gem0__screen_t2_r5 = 32'h00000000; +parameter mask_gem0__screen_t2_r5 = 32'h00000000; + +parameter gem0__screen_t2_r6 = 32'hE000B558; +parameter val_gem0__screen_t2_r6 = 32'h00000000; +parameter mask_gem0__screen_t2_r6 = 32'h00000000; + +parameter gem0__screen_t2_r7 = 32'hE000B55C; +parameter val_gem0__screen_t2_r7 = 32'h00000000; +parameter mask_gem0__screen_t2_r7 = 32'h00000000; + +parameter gem0__screen_t2_r8 = 32'hE000B560; +parameter val_gem0__screen_t2_r8 = 32'h00000000; +parameter mask_gem0__screen_t2_r8 = 32'h00000000; + +parameter gem0__screen_t2_r9 = 32'hE000B564; +parameter val_gem0__screen_t2_r9 = 32'h00000000; +parameter mask_gem0__screen_t2_r9 = 32'h00000000; + +parameter gem0__screen_t2_r10 = 32'hE000B568; +parameter val_gem0__screen_t2_r10 = 32'h00000000; +parameter mask_gem0__screen_t2_r10 = 32'h00000000; + +parameter gem0__screen_t2_r11 = 32'hE000B56C; +parameter val_gem0__screen_t2_r11 = 32'h00000000; +parameter mask_gem0__screen_t2_r11 = 32'h00000000; + +parameter gem0__screen_t2_r12 = 32'hE000B570; +parameter val_gem0__screen_t2_r12 = 32'h00000000; +parameter mask_gem0__screen_t2_r12 = 32'h00000000; + +parameter gem0__screen_t2_r13 = 32'hE000B574; +parameter val_gem0__screen_t2_r13 = 32'h00000000; +parameter mask_gem0__screen_t2_r13 = 32'h00000000; + +parameter gem0__screen_t2_r14 = 32'hE000B578; +parameter val_gem0__screen_t2_r14 = 32'h00000000; +parameter mask_gem0__screen_t2_r14 = 32'h00000000; + +parameter gem0__screen_t2_r15 = 32'hE000B57C; +parameter val_gem0__screen_t2_r15 = 32'h00000000; +parameter mask_gem0__screen_t2_r15 = 32'h00000000; + +parameter gem0__intr_en_pq1 = 32'hE000B600; +parameter val_gem0__intr_en_pq1 = 32'h00000000; +parameter mask_gem0__intr_en_pq1 = 32'h00000000; + +parameter gem0__intr_en_pq2 = 32'hE000B604; +parameter val_gem0__intr_en_pq2 = 32'h00000000; +parameter mask_gem0__intr_en_pq2 = 32'h00000000; + +parameter gem0__intr_en_pq3 = 32'hE000B608; +parameter val_gem0__intr_en_pq3 = 32'h00000000; +parameter mask_gem0__intr_en_pq3 = 32'h00000000; + +parameter gem0__intr_en_pq4 = 32'hE000B60C; +parameter val_gem0__intr_en_pq4 = 32'h00000000; +parameter mask_gem0__intr_en_pq4 = 32'h00000000; + +parameter gem0__intr_en_pq5 = 32'hE000B610; +parameter val_gem0__intr_en_pq5 = 32'h00000000; +parameter mask_gem0__intr_en_pq5 = 32'h00000000; + +parameter gem0__intr_en_pq6 = 32'hE000B614; +parameter val_gem0__intr_en_pq6 = 32'h00000000; +parameter mask_gem0__intr_en_pq6 = 32'h00000000; + +parameter gem0__intr_en_pq7 = 32'hE000B618; +parameter val_gem0__intr_en_pq7 = 32'h00000000; +parameter mask_gem0__intr_en_pq7 = 32'h00000000; + +parameter gem0__intr_dis_pq1 = 32'hE000B620; +parameter val_gem0__intr_dis_pq1 = 32'h00000000; +parameter mask_gem0__intr_dis_pq1 = 32'h00000000; + +parameter gem0__intr_dis_pq2 = 32'hE000B624; +parameter val_gem0__intr_dis_pq2 = 32'h00000000; +parameter mask_gem0__intr_dis_pq2 = 32'h00000000; + +parameter gem0__intr_dis_pq3 = 32'hE000B628; +parameter val_gem0__intr_dis_pq3 = 32'h00000000; +parameter mask_gem0__intr_dis_pq3 = 32'h00000000; + +parameter gem0__intr_dis_pq4 = 32'hE000B62C; +parameter val_gem0__intr_dis_pq4 = 32'h00000000; +parameter mask_gem0__intr_dis_pq4 = 32'h00000000; + +parameter gem0__intr_dis_pq5 = 32'hE000B630; +parameter val_gem0__intr_dis_pq5 = 32'h00000000; +parameter mask_gem0__intr_dis_pq5 = 32'h00000000; + +parameter gem0__intr_dis_pq6 = 32'hE000B634; +parameter val_gem0__intr_dis_pq6 = 32'h00000000; +parameter mask_gem0__intr_dis_pq6 = 32'h00000000; + +parameter gem0__intr_dis_pq7 = 32'hE000B638; +parameter val_gem0__intr_dis_pq7 = 32'h00000000; +parameter mask_gem0__intr_dis_pq7 = 32'h00000000; + +parameter gem0__intr_mask_pq1 = 32'hE000B640; +parameter val_gem0__intr_mask_pq1 = 32'h00000000; +parameter mask_gem0__intr_mask_pq1 = 32'h00000000; + +parameter gem0__intr_mask_pq2 = 32'hE000B644; +parameter val_gem0__intr_mask_pq2 = 32'h00000000; +parameter mask_gem0__intr_mask_pq2 = 32'h00000000; + +parameter gem0__intr_mask_pq3 = 32'hE000B648; +parameter val_gem0__intr_mask_pq3 = 32'h00000000; +parameter mask_gem0__intr_mask_pq3 = 32'h00000000; + +parameter gem0__intr_mask_pq4 = 32'hE000B64C; +parameter val_gem0__intr_mask_pq4 = 32'h00000000; +parameter mask_gem0__intr_mask_pq4 = 32'h00000000; + +parameter gem0__intr_mask_pq5 = 32'hE000B650; +parameter val_gem0__intr_mask_pq5 = 32'h00000000; +parameter mask_gem0__intr_mask_pq5 = 32'h00000000; + +parameter gem0__intr_mask_pq6 = 32'hE000B654; +parameter val_gem0__intr_mask_pq6 = 32'h00000000; +parameter mask_gem0__intr_mask_pq6 = 32'h00000000; + +parameter gem0__intr_mask_pq7 = 32'hE000B658; +parameter val_gem0__intr_mask_pq7 = 32'h00000000; +parameter mask_gem0__intr_mask_pq7 = 32'h00000000; + + +// ************************************************************ +// Module gem1 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gem1__net_ctrl = 32'hE000C000; +parameter val_gem1__net_ctrl = 32'h00000000; +parameter mask_gem1__net_ctrl = 32'hFFFFFFFF; + +parameter gem1__net_cfg = 32'hE000C004; +parameter val_gem1__net_cfg = 32'h00080000; +parameter mask_gem1__net_cfg = 32'hFFFFFFFF; + +parameter gem1__net_status = 32'hE000C008; +parameter val_gem1__net_status = 32'h00000004; +parameter mask_gem1__net_status = 32'hFFFFFFFD; + +parameter gem1__user_io = 32'hE000C00C; +parameter val_gem1__user_io = 32'h00000000; +parameter mask_gem1__user_io = 32'h0000FFFF; + +parameter gem1__dma_cfg = 32'hE000C010; +parameter val_gem1__dma_cfg = 32'h00020784; +parameter mask_gem1__dma_cfg = 32'hFFFFFFFF; + +parameter gem1__tx_status = 32'hE000C014; +parameter val_gem1__tx_status = 32'h00000000; +parameter mask_gem1__tx_status = 32'hFFFFFFFF; + +parameter gem1__rx_qbar = 32'hE000C018; +parameter val_gem1__rx_qbar = 32'h00000000; +parameter mask_gem1__rx_qbar = 32'hFFFFFFFF; + +parameter gem1__tx_qbar = 32'hE000C01C; +parameter val_gem1__tx_qbar = 32'h00000000; +parameter mask_gem1__tx_qbar = 32'hFFFFFFFF; + +parameter gem1__rx_status = 32'hE000C020; +parameter val_gem1__rx_status = 32'h00000000; +parameter mask_gem1__rx_status = 32'hFFFFFFFF; + +parameter gem1__intr_status = 32'hE000C024; +parameter val_gem1__intr_status = 32'h00000000; +parameter mask_gem1__intr_status = 32'hFFFFFFFF; + +parameter gem1__intr_en = 32'hE000C028; +parameter val_gem1__intr_en = 32'h00000000; +parameter mask_gem1__intr_en = 32'h00000000; + +parameter gem1__intr_dis = 32'hE000C02C; +parameter val_gem1__intr_dis = 32'h00000000; +parameter mask_gem1__intr_dis = 32'h00000000; + +parameter gem1__intr_mask = 32'hE000C030; +parameter val_gem1__intr_mask = 32'h0001FFFF; +parameter mask_gem1__intr_mask = 32'hFC01FFFF; + +parameter gem1__phy_maint = 32'hE000C034; +parameter val_gem1__phy_maint = 32'h00000000; +parameter mask_gem1__phy_maint = 32'hFFFFFFFF; + +parameter gem1__rx_pauseq = 32'hE000C038; +parameter val_gem1__rx_pauseq = 32'h00000000; +parameter mask_gem1__rx_pauseq = 32'hFFFFFFFF; + +parameter gem1__tx_pauseq = 32'hE000C03C; +parameter val_gem1__tx_pauseq = 32'h0000FFFF; +parameter mask_gem1__tx_pauseq = 32'hFFFFFFFF; + +parameter gem1__tx_partial_st_fwd = 32'hE000C040; +parameter val_gem1__tx_partial_st_fwd = 32'h000003FF; +parameter mask_gem1__tx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem1__rx_partial_st_fwd = 32'hE000C044; +parameter val_gem1__rx_partial_st_fwd = 32'h000003FF; +parameter mask_gem1__rx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem1__hash_bot = 32'hE000C080; +parameter val_gem1__hash_bot = 32'h00000000; +parameter mask_gem1__hash_bot = 32'hFFFFFFFF; + +parameter gem1__hash_top = 32'hE000C084; +parameter val_gem1__hash_top = 32'h00000000; +parameter mask_gem1__hash_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_bot = 32'hE000C088; +parameter val_gem1__spec_addr1_bot = 32'h00000000; +parameter mask_gem1__spec_addr1_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_top = 32'hE000C08C; +parameter val_gem1__spec_addr1_top = 32'h00000000; +parameter mask_gem1__spec_addr1_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr2_bot = 32'hE000C090; +parameter val_gem1__spec_addr2_bot = 32'h00000000; +parameter mask_gem1__spec_addr2_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr2_top = 32'hE000C094; +parameter val_gem1__spec_addr2_top = 32'h00000000; +parameter mask_gem1__spec_addr2_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr3_bot = 32'hE000C098; +parameter val_gem1__spec_addr3_bot = 32'h00000000; +parameter mask_gem1__spec_addr3_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr3_top = 32'hE000C09C; +parameter val_gem1__spec_addr3_top = 32'h00000000; +parameter mask_gem1__spec_addr3_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr4_bot = 32'hE000C0A0; +parameter val_gem1__spec_addr4_bot = 32'h00000000; +parameter mask_gem1__spec_addr4_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr4_top = 32'hE000C0A4; +parameter val_gem1__spec_addr4_top = 32'h00000000; +parameter mask_gem1__spec_addr4_top = 32'hFFFFFFFF; + +parameter gem1__type_id_match1 = 32'hE000C0A8; +parameter val_gem1__type_id_match1 = 32'h00000000; +parameter mask_gem1__type_id_match1 = 32'hFFFFFFFF; + +parameter gem1__type_id_match2 = 32'hE000C0AC; +parameter val_gem1__type_id_match2 = 32'h00000000; +parameter mask_gem1__type_id_match2 = 32'hFFFFFFFF; + +parameter gem1__type_id_match3 = 32'hE000C0B0; +parameter val_gem1__type_id_match3 = 32'h00000000; +parameter mask_gem1__type_id_match3 = 32'hFFFFFFFF; + +parameter gem1__type_id_match4 = 32'hE000C0B4; +parameter val_gem1__type_id_match4 = 32'h00000000; +parameter mask_gem1__type_id_match4 = 32'hFFFFFFFF; + +parameter gem1__wake_on_lan = 32'hE000C0B8; +parameter val_gem1__wake_on_lan = 32'h00000000; +parameter mask_gem1__wake_on_lan = 32'hFFFFFFFF; + +parameter gem1__ipg_stretch = 32'hE000C0BC; +parameter val_gem1__ipg_stretch = 32'h00000000; +parameter mask_gem1__ipg_stretch = 32'hFFFFFFFF; + +parameter gem1__stacked_vlan = 32'hE000C0C0; +parameter val_gem1__stacked_vlan = 32'h00000000; +parameter mask_gem1__stacked_vlan = 32'hFFFFFFFF; + +parameter gem1__tx_pfc_pause = 32'hE000C0C4; +parameter val_gem1__tx_pfc_pause = 32'h00000000; +parameter mask_gem1__tx_pfc_pause = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_mask_bot = 32'hE000C0C8; +parameter val_gem1__spec_addr1_mask_bot = 32'h00000000; +parameter mask_gem1__spec_addr1_mask_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_mask_top = 32'hE000C0CC; +parameter val_gem1__spec_addr1_mask_top = 32'h00000000; +parameter mask_gem1__spec_addr1_mask_top = 32'hFFFFFFFF; + +parameter gem1__module_id = 32'hE000C0FC; +parameter val_gem1__module_id = 32'h00020118; +parameter mask_gem1__module_id = 32'hFFFFFFFF; + +parameter gem1__octets_tx_bot = 32'hE000C100; +parameter val_gem1__octets_tx_bot = 32'h00000000; +parameter mask_gem1__octets_tx_bot = 32'hFFFFFFFF; + +parameter gem1__octets_tx_top = 32'hE000C104; +parameter val_gem1__octets_tx_top = 32'h00000000; +parameter mask_gem1__octets_tx_top = 32'hFFFFFFFF; + +parameter gem1__frames_tx = 32'hE000C108; +parameter val_gem1__frames_tx = 32'h00000000; +parameter mask_gem1__frames_tx = 32'hFFFFFFFF; + +parameter gem1__broadcast_frames_tx = 32'hE000C10C; +parameter val_gem1__broadcast_frames_tx = 32'h00000000; +parameter mask_gem1__broadcast_frames_tx = 32'hFFFFFFFF; + +parameter gem1__multi_frames_tx = 32'hE000C110; +parameter val_gem1__multi_frames_tx = 32'h00000000; +parameter mask_gem1__multi_frames_tx = 32'hFFFFFFFF; + +parameter gem1__pause_frames_tx = 32'hE000C114; +parameter val_gem1__pause_frames_tx = 32'h00000000; +parameter mask_gem1__pause_frames_tx = 32'hFFFFFFFF; + +parameter gem1__frames_64b_tx = 32'hE000C118; +parameter val_gem1__frames_64b_tx = 32'h00000000; +parameter mask_gem1__frames_64b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_65to127b_tx = 32'hE000C11C; +parameter val_gem1__frames_65to127b_tx = 32'h00000000; +parameter mask_gem1__frames_65to127b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_128to255b_tx = 32'hE000C120; +parameter val_gem1__frames_128to255b_tx = 32'h00000000; +parameter mask_gem1__frames_128to255b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_256to511b_tx = 32'hE000C124; +parameter val_gem1__frames_256to511b_tx = 32'h00000000; +parameter mask_gem1__frames_256to511b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_512to1023b_tx = 32'hE000C128; +parameter val_gem1__frames_512to1023b_tx = 32'h00000000; +parameter mask_gem1__frames_512to1023b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_1024to1518b_tx = 32'hE000C12C; +parameter val_gem1__frames_1024to1518b_tx = 32'h00000000; +parameter mask_gem1__frames_1024to1518b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_gt1518b_tx = 32'hE000C130; +parameter val_gem1__frames_gt1518b_tx = 32'h00000000; +parameter mask_gem1__frames_gt1518b_tx = 32'hFFFFFFFF; + +parameter gem1__tx_under_runs = 32'hE000C134; +parameter val_gem1__tx_under_runs = 32'h00000000; +parameter mask_gem1__tx_under_runs = 32'hFFFFFFFF; + +parameter gem1__single_collisn_frames = 32'hE000C138; +parameter val_gem1__single_collisn_frames = 32'h00000000; +parameter mask_gem1__single_collisn_frames = 32'hFFFFFFFF; + +parameter gem1__multi_collisn_frames = 32'hE000C13C; +parameter val_gem1__multi_collisn_frames = 32'h00000000; +parameter mask_gem1__multi_collisn_frames = 32'hFFFFFFFF; + +parameter gem1__excessive_collisns = 32'hE000C140; +parameter val_gem1__excessive_collisns = 32'h00000000; +parameter mask_gem1__excessive_collisns = 32'hFFFFFFFF; + +parameter gem1__late_collisns = 32'hE000C144; +parameter val_gem1__late_collisns = 32'h00000000; +parameter mask_gem1__late_collisns = 32'hFFFFFFFF; + +parameter gem1__deferred_tx_frames = 32'hE000C148; +parameter val_gem1__deferred_tx_frames = 32'h00000000; +parameter mask_gem1__deferred_tx_frames = 32'hFFFFFFFF; + +parameter gem1__carrier_sense_errs = 32'hE000C14C; +parameter val_gem1__carrier_sense_errs = 32'h00000000; +parameter mask_gem1__carrier_sense_errs = 32'hFFFFFFFF; + +parameter gem1__octets_rx_bot = 32'hE000C150; +parameter val_gem1__octets_rx_bot = 32'h00000000; +parameter mask_gem1__octets_rx_bot = 32'hFFFFFFFF; + +parameter gem1__octets_rx_top = 32'hE000C154; +parameter val_gem1__octets_rx_top = 32'h00000000; +parameter mask_gem1__octets_rx_top = 32'hFFFFFFFF; + +parameter gem1__frames_rx = 32'hE000C158; +parameter val_gem1__frames_rx = 32'h00000000; +parameter mask_gem1__frames_rx = 32'hFFFFFFFF; + +parameter gem1__bdcast_fames_rx = 32'hE000C15C; +parameter val_gem1__bdcast_fames_rx = 32'h00000000; +parameter mask_gem1__bdcast_fames_rx = 32'hFFFFFFFF; + +parameter gem1__multi_frames_rx = 32'hE000C160; +parameter val_gem1__multi_frames_rx = 32'h00000000; +parameter mask_gem1__multi_frames_rx = 32'hFFFFFFFF; + +parameter gem1__pause_rx = 32'hE000C164; +parameter val_gem1__pause_rx = 32'h00000000; +parameter mask_gem1__pause_rx = 32'hFFFFFFFF; + +parameter gem1__frames_64b_rx = 32'hE000C168; +parameter val_gem1__frames_64b_rx = 32'h00000000; +parameter mask_gem1__frames_64b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_65to127b_rx = 32'hE000C16C; +parameter val_gem1__frames_65to127b_rx = 32'h00000000; +parameter mask_gem1__frames_65to127b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_128to255b_rx = 32'hE000C170; +parameter val_gem1__frames_128to255b_rx = 32'h00000000; +parameter mask_gem1__frames_128to255b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_256to511b_rx = 32'hE000C174; +parameter val_gem1__frames_256to511b_rx = 32'h00000000; +parameter mask_gem1__frames_256to511b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_512to1023b_rx = 32'hE000C178; +parameter val_gem1__frames_512to1023b_rx = 32'h00000000; +parameter mask_gem1__frames_512to1023b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_1024to1518b_rx = 32'hE000C17C; +parameter val_gem1__frames_1024to1518b_rx = 32'h00000000; +parameter mask_gem1__frames_1024to1518b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_gt1518b_rx = 32'hE000C180; +parameter val_gem1__frames_gt1518b_rx = 32'h00000000; +parameter mask_gem1__frames_gt1518b_rx = 32'hFFFFFFFF; + +parameter gem1__undersz_rx = 32'hE000C184; +parameter val_gem1__undersz_rx = 32'h00000000; +parameter mask_gem1__undersz_rx = 32'hFFFFFFFF; + +parameter gem1__oversz_rx = 32'hE000C188; +parameter val_gem1__oversz_rx = 32'h00000000; +parameter mask_gem1__oversz_rx = 32'hFFFFFFFF; + +parameter gem1__jab_rx = 32'hE000C18C; +parameter val_gem1__jab_rx = 32'h00000000; +parameter mask_gem1__jab_rx = 32'hFFFFFFFF; + +parameter gem1__fcs_errors = 32'hE000C190; +parameter val_gem1__fcs_errors = 32'h00000000; +parameter mask_gem1__fcs_errors = 32'hFFFFFFFF; + +parameter gem1__length_field_errors = 32'hE000C194; +parameter val_gem1__length_field_errors = 32'h00000000; +parameter mask_gem1__length_field_errors = 32'hFFFFFFFF; + +parameter gem1__rx_symbol_errors = 32'hE000C198; +parameter val_gem1__rx_symbol_errors = 32'h00000000; +parameter mask_gem1__rx_symbol_errors = 32'hFFFFFFFF; + +parameter gem1__align_errors = 32'hE000C19C; +parameter val_gem1__align_errors = 32'h00000000; +parameter mask_gem1__align_errors = 32'hFFFFFFFF; + +parameter gem1__rx_resource_errors = 32'hE000C1A0; +parameter val_gem1__rx_resource_errors = 32'h00000000; +parameter mask_gem1__rx_resource_errors = 32'hFFFFFFFF; + +parameter gem1__rx_overrun_errors = 32'hE000C1A4; +parameter val_gem1__rx_overrun_errors = 32'h00000000; +parameter mask_gem1__rx_overrun_errors = 32'hFFFFFFFF; + +parameter gem1__ip_hdr_csum_errors = 32'hE000C1A8; +parameter val_gem1__ip_hdr_csum_errors = 32'h00000000; +parameter mask_gem1__ip_hdr_csum_errors = 32'hFFFFFFFF; + +parameter gem1__tcp_csum_errors = 32'hE000C1AC; +parameter val_gem1__tcp_csum_errors = 32'h00000000; +parameter mask_gem1__tcp_csum_errors = 32'hFFFFFFFF; + +parameter gem1__udp_csum_errors = 32'hE000C1B0; +parameter val_gem1__udp_csum_errors = 32'h00000000; +parameter mask_gem1__udp_csum_errors = 32'hFFFFFFFF; + +parameter gem1__timer_strobe_s = 32'hE000C1C8; +parameter val_gem1__timer_strobe_s = 32'h00000000; +parameter mask_gem1__timer_strobe_s = 32'hFFFFFFFF; + +parameter gem1__timer_strobe_ns = 32'hE000C1CC; +parameter val_gem1__timer_strobe_ns = 32'h00000000; +parameter mask_gem1__timer_strobe_ns = 32'hFFFFFFFF; + +parameter gem1__timer_s = 32'hE000C1D0; +parameter val_gem1__timer_s = 32'h00000000; +parameter mask_gem1__timer_s = 32'hFFFFFFFF; + +parameter gem1__timer_ns = 32'hE000C1D4; +parameter val_gem1__timer_ns = 32'h00000000; +parameter mask_gem1__timer_ns = 32'hFFFFFFFF; + +parameter gem1__timer_adjust = 32'hE000C1D8; +parameter val_gem1__timer_adjust = 32'h00000000; +parameter mask_gem1__timer_adjust = 32'hFFFFFFFF; + +parameter gem1__timer_incr = 32'hE000C1DC; +parameter val_gem1__timer_incr = 32'h00000000; +parameter mask_gem1__timer_incr = 32'hFFFFFFFF; + +parameter gem1__ptp_tx_s = 32'hE000C1E0; +parameter val_gem1__ptp_tx_s = 32'h00000000; +parameter mask_gem1__ptp_tx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_tx_ns = 32'hE000C1E4; +parameter val_gem1__ptp_tx_ns = 32'h00000000; +parameter mask_gem1__ptp_tx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_rx_s = 32'hE000C1E8; +parameter val_gem1__ptp_rx_s = 32'h00000000; +parameter mask_gem1__ptp_rx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_rx_ns = 32'hE000C1EC; +parameter val_gem1__ptp_rx_ns = 32'h00000000; +parameter mask_gem1__ptp_rx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_tx_s = 32'hE000C1F0; +parameter val_gem1__ptp_peer_tx_s = 32'h00000000; +parameter mask_gem1__ptp_peer_tx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_tx_ns = 32'hE000C1F4; +parameter val_gem1__ptp_peer_tx_ns = 32'h00000000; +parameter mask_gem1__ptp_peer_tx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_rx_s = 32'hE000C1F8; +parameter val_gem1__ptp_peer_rx_s = 32'h00000000; +parameter mask_gem1__ptp_peer_rx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_rx_ns = 32'hE000C1FC; +parameter val_gem1__ptp_peer_rx_ns = 32'h00000000; +parameter mask_gem1__ptp_peer_rx_ns = 32'hFFFFFFFF; + +parameter gem1__pcs_ctrl = 32'hE000C200; +parameter val_gem1__pcs_ctrl = 32'h00000000; +parameter mask_gem1__pcs_ctrl = 32'h00000000; + +parameter gem1__pcs_status = 32'hE000C204; +parameter val_gem1__pcs_status = 32'h00000000; +parameter mask_gem1__pcs_status = 32'h00000000; + +parameter gem1__pcs_upper_phy_id = 32'hE000C208; +parameter val_gem1__pcs_upper_phy_id = 32'h00000000; +parameter mask_gem1__pcs_upper_phy_id = 32'h00000000; + +parameter gem1__pcs_lower_phy_id = 32'hE000C20C; +parameter val_gem1__pcs_lower_phy_id = 32'h00000000; +parameter mask_gem1__pcs_lower_phy_id = 32'h00000000; + +parameter gem1__pcs_autoneg_ad = 32'hE000C210; +parameter val_gem1__pcs_autoneg_ad = 32'h00000000; +parameter mask_gem1__pcs_autoneg_ad = 32'h00000000; + +parameter gem1__pcs_autoneg_ability = 32'hE000C214; +parameter val_gem1__pcs_autoneg_ability = 32'h00000000; +parameter mask_gem1__pcs_autoneg_ability = 32'h00000000; + +parameter gem1__pcs_autonec_exp = 32'hE000C218; +parameter val_gem1__pcs_autonec_exp = 32'h00000000; +parameter mask_gem1__pcs_autonec_exp = 32'h00000000; + +parameter gem1__pcs_autoneg_next_pg = 32'hE000C21C; +parameter val_gem1__pcs_autoneg_next_pg = 32'h00000000; +parameter mask_gem1__pcs_autoneg_next_pg = 32'h00000000; + +parameter gem1__pcs_autoneg_pnext_pg = 32'hE000C220; +parameter val_gem1__pcs_autoneg_pnext_pg = 32'h00000000; +parameter mask_gem1__pcs_autoneg_pnext_pg = 32'h00000000; + +parameter gem1__pcs_extended_status = 32'hE000C23C; +parameter val_gem1__pcs_extended_status = 32'h00000000; +parameter mask_gem1__pcs_extended_status = 32'h00000000; + +parameter gem1__design_cfg1 = 32'hE000C280; +parameter val_gem1__design_cfg1 = 32'h02000000; +parameter mask_gem1__design_cfg1 = 32'h0E000000; + +parameter gem1__design_cfg2 = 32'hE000C284; +parameter val_gem1__design_cfg2 = 32'h2A813FFF; +parameter mask_gem1__design_cfg2 = 32'h3FCFFFFF; + +parameter gem1__design_cfg3 = 32'hE000C288; +parameter val_gem1__design_cfg3 = 32'h00000000; +parameter mask_gem1__design_cfg3 = 32'hFFFFFFFF; + +parameter gem1__design_cfg4 = 32'hE000C28C; +parameter val_gem1__design_cfg4 = 32'h00000000; +parameter mask_gem1__design_cfg4 = 32'hFFFFFFFF; + +parameter gem1__design_cfg5 = 32'hE000C290; +parameter val_gem1__design_cfg5 = 32'h002F2045; +parameter mask_gem1__design_cfg5 = 32'h0FFFFCFF; + +parameter gem1__design_cfg6 = 32'hE000C294; +parameter val_gem1__design_cfg6 = 32'h00000000; +parameter mask_gem1__design_cfg6 = 32'h00000000; + +parameter gem1__design_cfg7 = 32'hE000C298; +parameter val_gem1__design_cfg7 = 32'h00000000; +parameter mask_gem1__design_cfg7 = 32'h00000000; + +parameter gem1__isr_pq1 = 32'hE000C400; +parameter val_gem1__isr_pq1 = 32'h00000000; +parameter mask_gem1__isr_pq1 = 32'h00000000; + +parameter gem1__isr_pq2 = 32'hE000C404; +parameter val_gem1__isr_pq2 = 32'h00000000; +parameter mask_gem1__isr_pq2 = 32'h00000000; + +parameter gem1__isr_pq3 = 32'hE000C408; +parameter val_gem1__isr_pq3 = 32'h00000000; +parameter mask_gem1__isr_pq3 = 32'h00000000; + +parameter gem1__isr_pq4 = 32'hE000C40C; +parameter val_gem1__isr_pq4 = 32'h00000000; +parameter mask_gem1__isr_pq4 = 32'h00000000; + +parameter gem1__isr_pq5 = 32'hE000C410; +parameter val_gem1__isr_pq5 = 32'h00000000; +parameter mask_gem1__isr_pq5 = 32'h00000000; + +parameter gem1__isr_pq6 = 32'hE000C414; +parameter val_gem1__isr_pq6 = 32'h00000000; +parameter mask_gem1__isr_pq6 = 32'h00000000; + +parameter gem1__isr_pq7 = 32'hE000C418; +parameter val_gem1__isr_pq7 = 32'h00000000; +parameter mask_gem1__isr_pq7 = 32'h00000000; + +parameter gem1__tx_qbar_q1 = 32'hE000C440; +parameter val_gem1__tx_qbar_q1 = 32'h00000000; +parameter mask_gem1__tx_qbar_q1 = 32'h00000000; + +parameter gem1__tx_qbar_q2 = 32'hE000C444; +parameter val_gem1__tx_qbar_q2 = 32'h00000000; +parameter mask_gem1__tx_qbar_q2 = 32'h00000000; + +parameter gem1__tx_qbar_q3 = 32'hE000C448; +parameter val_gem1__tx_qbar_q3 = 32'h00000000; +parameter mask_gem1__tx_qbar_q3 = 32'h00000000; + +parameter gem1__tx_qbar_q4 = 32'hE000C44C; +parameter val_gem1__tx_qbar_q4 = 32'h00000000; +parameter mask_gem1__tx_qbar_q4 = 32'h00000000; + +parameter gem1__tx_qbar_q5 = 32'hE000C450; +parameter val_gem1__tx_qbar_q5 = 32'h00000000; +parameter mask_gem1__tx_qbar_q5 = 32'h00000000; + +parameter gem1__tx_qbar_q6 = 32'hE000C454; +parameter val_gem1__tx_qbar_q6 = 32'h00000000; +parameter mask_gem1__tx_qbar_q6 = 32'h00000000; + +parameter gem1__tx_qbar_q7 = 32'hE000C458; +parameter val_gem1__tx_qbar_q7 = 32'h00000000; +parameter mask_gem1__tx_qbar_q7 = 32'h00000000; + +parameter gem1__rx_qbar_q1 = 32'hE000C480; +parameter val_gem1__rx_qbar_q1 = 32'h00000000; +parameter mask_gem1__rx_qbar_q1 = 32'h00000000; + +parameter gem1__rx_qbar_q2 = 32'hE000C484; +parameter val_gem1__rx_qbar_q2 = 32'h00000000; +parameter mask_gem1__rx_qbar_q2 = 32'h00000000; + +parameter gem1__rx_qbar_q3 = 32'hE000C488; +parameter val_gem1__rx_qbar_q3 = 32'h00000000; +parameter mask_gem1__rx_qbar_q3 = 32'h00000000; + +parameter gem1__rx_qbar_q4 = 32'hE000C48C; +parameter val_gem1__rx_qbar_q4 = 32'h00000000; +parameter mask_gem1__rx_qbar_q4 = 32'h00000000; + +parameter gem1__rx_qbar_q5 = 32'hE000C490; +parameter val_gem1__rx_qbar_q5 = 32'h00000000; +parameter mask_gem1__rx_qbar_q5 = 32'h00000000; + +parameter gem1__rx_qbar_q6 = 32'hE000C494; +parameter val_gem1__rx_qbar_q6 = 32'h00000000; +parameter mask_gem1__rx_qbar_q6 = 32'h00000000; + +parameter gem1__rx_qbar_q7 = 32'hE000C498; +parameter val_gem1__rx_qbar_q7 = 32'h00000000; +parameter mask_gem1__rx_qbar_q7 = 32'h00000000; + +parameter gem1__rx_bufsz_q1 = 32'hE000C4A0; +parameter val_gem1__rx_bufsz_q1 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q1 = 32'h00000000; + +parameter gem1__rx_bufsz_q2 = 32'hE000C4A4; +parameter val_gem1__rx_bufsz_q2 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q2 = 32'h00000000; + +parameter gem1__rx_bufsz_q3 = 32'hE000C4A8; +parameter val_gem1__rx_bufsz_q3 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q3 = 32'h00000000; + +parameter gem1__rx_bufsz_q4 = 32'hE000C4AC; +parameter val_gem1__rx_bufsz_q4 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q4 = 32'h00000000; + +parameter gem1__rx_bufsz_q5 = 32'hE000C4B0; +parameter val_gem1__rx_bufsz_q5 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q5 = 32'h00000000; + +parameter gem1__rx_bufsz_q6 = 32'hE000C4B4; +parameter val_gem1__rx_bufsz_q6 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q6 = 32'h00000000; + +parameter gem1__rx_bufsz_q7 = 32'hE000C4B8; +parameter val_gem1__rx_bufsz_q7 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q7 = 32'h00000000; + +parameter gem1__screen_t1_r0 = 32'hE000C500; +parameter val_gem1__screen_t1_r0 = 32'h00000000; +parameter mask_gem1__screen_t1_r0 = 32'h00000000; + +parameter gem1__screen_t1_r1 = 32'hE000C504; +parameter val_gem1__screen_t1_r1 = 32'h00000000; +parameter mask_gem1__screen_t1_r1 = 32'h00000000; + +parameter gem1__screen_t1_r2 = 32'hE000C508; +parameter val_gem1__screen_t1_r2 = 32'h00000000; +parameter mask_gem1__screen_t1_r2 = 32'h00000000; + +parameter gem1__screen_t1_r3 = 32'hE000C50C; +parameter val_gem1__screen_t1_r3 = 32'h00000000; +parameter mask_gem1__screen_t1_r3 = 32'h00000000; + +parameter gem1__screen_t1_r4 = 32'hE000C510; +parameter val_gem1__screen_t1_r4 = 32'h00000000; +parameter mask_gem1__screen_t1_r4 = 32'h00000000; + +parameter gem1__screen_t1_r5 = 32'hE000C514; +parameter val_gem1__screen_t1_r5 = 32'h00000000; +parameter mask_gem1__screen_t1_r5 = 32'h00000000; + +parameter gem1__screen_t1_r6 = 32'hE000C518; +parameter val_gem1__screen_t1_r6 = 32'h00000000; +parameter mask_gem1__screen_t1_r6 = 32'h00000000; + +parameter gem1__screen_t1_r7 = 32'hE000C51C; +parameter val_gem1__screen_t1_r7 = 32'h00000000; +parameter mask_gem1__screen_t1_r7 = 32'h00000000; + +parameter gem1__screen_t1_r8 = 32'hE000C520; +parameter val_gem1__screen_t1_r8 = 32'h00000000; +parameter mask_gem1__screen_t1_r8 = 32'h00000000; + +parameter gem1__screen_t1_r9 = 32'hE000C524; +parameter val_gem1__screen_t1_r9 = 32'h00000000; +parameter mask_gem1__screen_t1_r9 = 32'h00000000; + +parameter gem1__screen_t1_r10 = 32'hE000C528; +parameter val_gem1__screen_t1_r10 = 32'h00000000; +parameter mask_gem1__screen_t1_r10 = 32'h00000000; + +parameter gem1__screen_t1_r11 = 32'hE000C52C; +parameter val_gem1__screen_t1_r11 = 32'h00000000; +parameter mask_gem1__screen_t1_r11 = 32'h00000000; + +parameter gem1__screen_t1_r12 = 32'hE000C530; +parameter val_gem1__screen_t1_r12 = 32'h00000000; +parameter mask_gem1__screen_t1_r12 = 32'h00000000; + +parameter gem1__screen_t1_r13 = 32'hE000C534; +parameter val_gem1__screen_t1_r13 = 32'h00000000; +parameter mask_gem1__screen_t1_r13 = 32'h00000000; + +parameter gem1__screen_t1_r14 = 32'hE000C538; +parameter val_gem1__screen_t1_r14 = 32'h00000000; +parameter mask_gem1__screen_t1_r14 = 32'h00000000; + +parameter gem1__screen_t1_r15 = 32'hE000C53C; +parameter val_gem1__screen_t1_r15 = 32'h00000000; +parameter mask_gem1__screen_t1_r15 = 32'h00000000; + +parameter gem1__screen_t2_r0 = 32'hE000C540; +parameter val_gem1__screen_t2_r0 = 32'h00000000; +parameter mask_gem1__screen_t2_r0 = 32'h00000000; + +parameter gem1__screen_t2_r1 = 32'hE000C544; +parameter val_gem1__screen_t2_r1 = 32'h00000000; +parameter mask_gem1__screen_t2_r1 = 32'h00000000; + +parameter gem1__screen_t2_r2 = 32'hE000C548; +parameter val_gem1__screen_t2_r2 = 32'h00000000; +parameter mask_gem1__screen_t2_r2 = 32'h00000000; + +parameter gem1__screen_t2_r3 = 32'hE000C54C; +parameter val_gem1__screen_t2_r3 = 32'h00000000; +parameter mask_gem1__screen_t2_r3 = 32'h00000000; + +parameter gem1__screen_t2_r4 = 32'hE000C550; +parameter val_gem1__screen_t2_r4 = 32'h00000000; +parameter mask_gem1__screen_t2_r4 = 32'h00000000; + +parameter gem1__screen_t2_r5 = 32'hE000C554; +parameter val_gem1__screen_t2_r5 = 32'h00000000; +parameter mask_gem1__screen_t2_r5 = 32'h00000000; + +parameter gem1__screen_t2_r6 = 32'hE000C558; +parameter val_gem1__screen_t2_r6 = 32'h00000000; +parameter mask_gem1__screen_t2_r6 = 32'h00000000; + +parameter gem1__screen_t2_r7 = 32'hE000C55C; +parameter val_gem1__screen_t2_r7 = 32'h00000000; +parameter mask_gem1__screen_t2_r7 = 32'h00000000; + +parameter gem1__screen_t2_r8 = 32'hE000C560; +parameter val_gem1__screen_t2_r8 = 32'h00000000; +parameter mask_gem1__screen_t2_r8 = 32'h00000000; + +parameter gem1__screen_t2_r9 = 32'hE000C564; +parameter val_gem1__screen_t2_r9 = 32'h00000000; +parameter mask_gem1__screen_t2_r9 = 32'h00000000; + +parameter gem1__screen_t2_r10 = 32'hE000C568; +parameter val_gem1__screen_t2_r10 = 32'h00000000; +parameter mask_gem1__screen_t2_r10 = 32'h00000000; + +parameter gem1__screen_t2_r11 = 32'hE000C56C; +parameter val_gem1__screen_t2_r11 = 32'h00000000; +parameter mask_gem1__screen_t2_r11 = 32'h00000000; + +parameter gem1__screen_t2_r12 = 32'hE000C570; +parameter val_gem1__screen_t2_r12 = 32'h00000000; +parameter mask_gem1__screen_t2_r12 = 32'h00000000; + +parameter gem1__screen_t2_r13 = 32'hE000C574; +parameter val_gem1__screen_t2_r13 = 32'h00000000; +parameter mask_gem1__screen_t2_r13 = 32'h00000000; + +parameter gem1__screen_t2_r14 = 32'hE000C578; +parameter val_gem1__screen_t2_r14 = 32'h00000000; +parameter mask_gem1__screen_t2_r14 = 32'h00000000; + +parameter gem1__screen_t2_r15 = 32'hE000C57C; +parameter val_gem1__screen_t2_r15 = 32'h00000000; +parameter mask_gem1__screen_t2_r15 = 32'h00000000; + +parameter gem1__intr_en_pq1 = 32'hE000C600; +parameter val_gem1__intr_en_pq1 = 32'h00000000; +parameter mask_gem1__intr_en_pq1 = 32'h00000000; + +parameter gem1__intr_en_pq2 = 32'hE000C604; +parameter val_gem1__intr_en_pq2 = 32'h00000000; +parameter mask_gem1__intr_en_pq2 = 32'h00000000; + +parameter gem1__intr_en_pq3 = 32'hE000C608; +parameter val_gem1__intr_en_pq3 = 32'h00000000; +parameter mask_gem1__intr_en_pq3 = 32'h00000000; + +parameter gem1__intr_en_pq4 = 32'hE000C60C; +parameter val_gem1__intr_en_pq4 = 32'h00000000; +parameter mask_gem1__intr_en_pq4 = 32'h00000000; + +parameter gem1__intr_en_pq5 = 32'hE000C610; +parameter val_gem1__intr_en_pq5 = 32'h00000000; +parameter mask_gem1__intr_en_pq5 = 32'h00000000; + +parameter gem1__intr_en_pq6 = 32'hE000C614; +parameter val_gem1__intr_en_pq6 = 32'h00000000; +parameter mask_gem1__intr_en_pq6 = 32'h00000000; + +parameter gem1__intr_en_pq7 = 32'hE000C618; +parameter val_gem1__intr_en_pq7 = 32'h00000000; +parameter mask_gem1__intr_en_pq7 = 32'h00000000; + +parameter gem1__intr_dis_pq1 = 32'hE000C620; +parameter val_gem1__intr_dis_pq1 = 32'h00000000; +parameter mask_gem1__intr_dis_pq1 = 32'h00000000; + +parameter gem1__intr_dis_pq2 = 32'hE000C624; +parameter val_gem1__intr_dis_pq2 = 32'h00000000; +parameter mask_gem1__intr_dis_pq2 = 32'h00000000; + +parameter gem1__intr_dis_pq3 = 32'hE000C628; +parameter val_gem1__intr_dis_pq3 = 32'h00000000; +parameter mask_gem1__intr_dis_pq3 = 32'h00000000; + +parameter gem1__intr_dis_pq4 = 32'hE000C62C; +parameter val_gem1__intr_dis_pq4 = 32'h00000000; +parameter mask_gem1__intr_dis_pq4 = 32'h00000000; + +parameter gem1__intr_dis_pq5 = 32'hE000C630; +parameter val_gem1__intr_dis_pq5 = 32'h00000000; +parameter mask_gem1__intr_dis_pq5 = 32'h00000000; + +parameter gem1__intr_dis_pq6 = 32'hE000C634; +parameter val_gem1__intr_dis_pq6 = 32'h00000000; +parameter mask_gem1__intr_dis_pq6 = 32'h00000000; + +parameter gem1__intr_dis_pq7 = 32'hE000C638; +parameter val_gem1__intr_dis_pq7 = 32'h00000000; +parameter mask_gem1__intr_dis_pq7 = 32'h00000000; + +parameter gem1__intr_mask_pq1 = 32'hE000C640; +parameter val_gem1__intr_mask_pq1 = 32'h00000000; +parameter mask_gem1__intr_mask_pq1 = 32'h00000000; + +parameter gem1__intr_mask_pq2 = 32'hE000C644; +parameter val_gem1__intr_mask_pq2 = 32'h00000000; +parameter mask_gem1__intr_mask_pq2 = 32'h00000000; + +parameter gem1__intr_mask_pq3 = 32'hE000C648; +parameter val_gem1__intr_mask_pq3 = 32'h00000000; +parameter mask_gem1__intr_mask_pq3 = 32'h00000000; + +parameter gem1__intr_mask_pq4 = 32'hE000C64C; +parameter val_gem1__intr_mask_pq4 = 32'h00000000; +parameter mask_gem1__intr_mask_pq4 = 32'h00000000; + +parameter gem1__intr_mask_pq5 = 32'hE000C650; +parameter val_gem1__intr_mask_pq5 = 32'h00000000; +parameter mask_gem1__intr_mask_pq5 = 32'h00000000; + +parameter gem1__intr_mask_pq6 = 32'hE000C654; +parameter val_gem1__intr_mask_pq6 = 32'h00000000; +parameter mask_gem1__intr_mask_pq6 = 32'h00000000; + +parameter gem1__intr_mask_pq7 = 32'hE000C658; +parameter val_gem1__intr_mask_pq7 = 32'h00000000; +parameter mask_gem1__intr_mask_pq7 = 32'h00000000; + + +// ************************************************************ +// Module gpio gpio +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpio__MASK_DATA_0_LSW = 32'hE000A000; +parameter val_gpio__MASK_DATA_0_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_0_LSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_0_MSW = 32'hE000A004; +parameter val_gpio__MASK_DATA_0_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_0_MSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_1_LSW = 32'hE000A008; +parameter val_gpio__MASK_DATA_1_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_1_LSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_1_MSW = 32'hE000A00C; +parameter val_gpio__MASK_DATA_1_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_1_MSW = 32'h003FFFC0; + +parameter gpio__MASK_DATA_2_LSW = 32'hE000A010; +parameter val_gpio__MASK_DATA_2_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_2_LSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_2_MSW = 32'hE000A014; +parameter val_gpio__MASK_DATA_2_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_2_MSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_3_LSW = 32'hE000A018; +parameter val_gpio__MASK_DATA_3_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_3_LSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_3_MSW = 32'hE000A01C; +parameter val_gpio__MASK_DATA_3_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_3_MSW = 32'hFFFFFFFF; + +parameter gpio__DATA_0 = 32'hE000A040; +parameter val_gpio__DATA_0 = 32'h00000000; +parameter mask_gpio__DATA_0 = 32'h00000000; + +parameter gpio__DATA_1 = 32'hE000A044; +parameter val_gpio__DATA_1 = 32'h00000000; +parameter mask_gpio__DATA_1 = 32'h00000000; + +parameter gpio__DATA_2 = 32'hE000A048; +parameter val_gpio__DATA_2 = 32'h00000000; +parameter mask_gpio__DATA_2 = 32'hFFFFFFFF; + +parameter gpio__DATA_3 = 32'hE000A04C; +parameter val_gpio__DATA_3 = 32'h00000000; +parameter mask_gpio__DATA_3 = 32'hFFFFFFFF; + +parameter gpio__DATA_0_RO = 32'hE000A060; +parameter val_gpio__DATA_0_RO = 32'h00000000; +parameter mask_gpio__DATA_0_RO = 32'h00000000; + +parameter gpio__DATA_1_RO = 32'hE000A064; +parameter val_gpio__DATA_1_RO = 32'h00000000; +parameter mask_gpio__DATA_1_RO = 32'h00000000; + +parameter gpio__DATA_2_RO = 32'hE000A068; +parameter val_gpio__DATA_2_RO = 32'h00000000; +parameter mask_gpio__DATA_2_RO = 32'hFFFFFFFF; + +parameter gpio__DATA_3_RO = 32'hE000A06C; +parameter val_gpio__DATA_3_RO = 32'h00000000; +parameter mask_gpio__DATA_3_RO = 32'hFFFFFFFF; + +parameter gpio__BYPM_0 = 32'hE000A200; +parameter val_gpio__BYPM_0 = 32'h00000000; +parameter mask_gpio__BYPM_0 = 32'hFFFFFFFF; + +parameter gpio__DIRM_0 = 32'hE000A204; +parameter val_gpio__DIRM_0 = 32'h00000000; +parameter mask_gpio__DIRM_0 = 32'hFFFFFFFF; + +parameter gpio__OEN_0 = 32'hE000A208; +parameter val_gpio__OEN_0 = 32'h00000000; +parameter mask_gpio__OEN_0 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_0 = 32'hE000A20C; +parameter val_gpio__INT_MASK_0 = 32'h00000000; +parameter mask_gpio__INT_MASK_0 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_0 = 32'hE000A210; +parameter val_gpio__INT_EN_0 = 32'h00000000; +parameter mask_gpio__INT_EN_0 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_0 = 32'hE000A214; +parameter val_gpio__INT_DIS_0 = 32'h00000000; +parameter mask_gpio__INT_DIS_0 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_0 = 32'hE000A218; +parameter val_gpio__INT_STAT_0 = 32'h00000000; +parameter mask_gpio__INT_STAT_0 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_0 = 32'hE000A21C; +parameter val_gpio__INT_TYPE_0 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_0 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_0 = 32'hE000A220; +parameter val_gpio__INT_POLARITY_0 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_0 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_0 = 32'hE000A224; +parameter val_gpio__INT_ANY_0 = 32'h00000000; +parameter mask_gpio__INT_ANY_0 = 32'hFFFFFFFF; + +parameter gpio__BYPM_1 = 32'hE000A240; +parameter val_gpio__BYPM_1 = 32'h00000000; +parameter mask_gpio__BYPM_1 = 32'h003FFFFF; + +parameter gpio__DIRM_1 = 32'hE000A244; +parameter val_gpio__DIRM_1 = 32'h00000000; +parameter mask_gpio__DIRM_1 = 32'h003FFFFF; + +parameter gpio__OEN_1 = 32'hE000A248; +parameter val_gpio__OEN_1 = 32'h00000000; +parameter mask_gpio__OEN_1 = 32'h003FFFFF; + +parameter gpio__INT_MASK_1 = 32'hE000A24C; +parameter val_gpio__INT_MASK_1 = 32'h00000000; +parameter mask_gpio__INT_MASK_1 = 32'h003FFFFF; + +parameter gpio__INT_EN_1 = 32'hE000A250; +parameter val_gpio__INT_EN_1 = 32'h00000000; +parameter mask_gpio__INT_EN_1 = 32'h003FFFFF; + +parameter gpio__INT_DIS_1 = 32'hE000A254; +parameter val_gpio__INT_DIS_1 = 32'h00000000; +parameter mask_gpio__INT_DIS_1 = 32'h003FFFFF; + +parameter gpio__INT_STAT_1 = 32'hE000A258; +parameter val_gpio__INT_STAT_1 = 32'h00000000; +parameter mask_gpio__INT_STAT_1 = 32'h003FFFFF; + +parameter gpio__INT_TYPE_1 = 32'hE000A25C; +parameter val_gpio__INT_TYPE_1 = 32'h003FFFFF; +parameter mask_gpio__INT_TYPE_1 = 32'h003FFFFF; + +parameter gpio__INT_POLARITY_1 = 32'hE000A260; +parameter val_gpio__INT_POLARITY_1 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_1 = 32'h003FFFFF; + +parameter gpio__INT_ANY_1 = 32'hE000A264; +parameter val_gpio__INT_ANY_1 = 32'h00000000; +parameter mask_gpio__INT_ANY_1 = 32'h003FFFFF; + +parameter gpio__BYPM_2 = 32'hE000A280; +parameter val_gpio__BYPM_2 = 32'h00000000; +parameter mask_gpio__BYPM_2 = 32'hFFFFFFFF; + +parameter gpio__DIRM_2 = 32'hE000A284; +parameter val_gpio__DIRM_2 = 32'h00000000; +parameter mask_gpio__DIRM_2 = 32'hFFFFFFFF; + +parameter gpio__OEN_2 = 32'hE000A288; +parameter val_gpio__OEN_2 = 32'h00000000; +parameter mask_gpio__OEN_2 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_2 = 32'hE000A28C; +parameter val_gpio__INT_MASK_2 = 32'h00000000; +parameter mask_gpio__INT_MASK_2 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_2 = 32'hE000A290; +parameter val_gpio__INT_EN_2 = 32'h00000000; +parameter mask_gpio__INT_EN_2 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_2 = 32'hE000A294; +parameter val_gpio__INT_DIS_2 = 32'h00000000; +parameter mask_gpio__INT_DIS_2 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_2 = 32'hE000A298; +parameter val_gpio__INT_STAT_2 = 32'h00000000; +parameter mask_gpio__INT_STAT_2 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_2 = 32'hE000A29C; +parameter val_gpio__INT_TYPE_2 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_2 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_2 = 32'hE000A2A0; +parameter val_gpio__INT_POLARITY_2 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_2 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_2 = 32'hE000A2A4; +parameter val_gpio__INT_ANY_2 = 32'h00000000; +parameter mask_gpio__INT_ANY_2 = 32'hFFFFFFFF; + +parameter gpio__BYPM_3 = 32'hE000A2C0; +parameter val_gpio__BYPM_3 = 32'h00000000; +parameter mask_gpio__BYPM_3 = 32'hFFFFFFFF; + +parameter gpio__DIRM_3 = 32'hE000A2C4; +parameter val_gpio__DIRM_3 = 32'h00000000; +parameter mask_gpio__DIRM_3 = 32'hFFFFFFFF; + +parameter gpio__OEN_3 = 32'hE000A2C8; +parameter val_gpio__OEN_3 = 32'h00000000; +parameter mask_gpio__OEN_3 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_3 = 32'hE000A2CC; +parameter val_gpio__INT_MASK_3 = 32'h00000000; +parameter mask_gpio__INT_MASK_3 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_3 = 32'hE000A2D0; +parameter val_gpio__INT_EN_3 = 32'h00000000; +parameter mask_gpio__INT_EN_3 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_3 = 32'hE000A2D4; +parameter val_gpio__INT_DIS_3 = 32'h00000000; +parameter mask_gpio__INT_DIS_3 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_3 = 32'hE000A2D8; +parameter val_gpio__INT_STAT_3 = 32'h00000000; +parameter mask_gpio__INT_STAT_3 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_3 = 32'hE000A2DC; +parameter val_gpio__INT_TYPE_3 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_3 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_3 = 32'hE000A2E0; +parameter val_gpio__INT_POLARITY_3 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_3 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_3 = 32'hE000A2E4; +parameter val_gpio__INT_ANY_3 = 32'h00000000; +parameter mask_gpio__INT_ANY_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module gpv_iou_switch gpv_iou_switch +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_iou_switch__Remap = 32'hE0200000; +parameter val_gpv_iou_switch__Remap = 32'h00000000; +parameter mask_gpv_iou_switch__Remap = 32'h000000FF; + +parameter gpv_iou_switch__security2_sdio0 = 32'hE0200008; +parameter val_gpv_iou_switch__security2_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__security2_sdio0 = 32'h00000001; + +parameter gpv_iou_switch__security3_sdio1 = 32'hE020000C; +parameter val_gpv_iou_switch__security3_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__security3_sdio1 = 32'h00000001; + +parameter gpv_iou_switch__security4_qspi = 32'hE0200010; +parameter val_gpv_iou_switch__security4_qspi = 32'h00000000; +parameter mask_gpv_iou_switch__security4_qspi = 32'h00000001; + +parameter gpv_iou_switch__security5_miou = 32'hE0200014; +parameter val_gpv_iou_switch__security5_miou = 32'h00000000; +parameter mask_gpv_iou_switch__security5_miou = 32'h00000001; + +parameter gpv_iou_switch__security6_apb_slaves = 32'hE0200018; +parameter val_gpv_iou_switch__security6_apb_slaves = 32'h00000000; +parameter mask_gpv_iou_switch__security6_apb_slaves = 32'h00007FFF; + +parameter gpv_iou_switch__security7_smc = 32'hE020001C; +parameter val_gpv_iou_switch__security7_smc = 32'h00000000; +parameter mask_gpv_iou_switch__security7_smc = 32'h00000001; + +parameter gpv_iou_switch__peripheral_id4 = 32'hE0201FD0; +parameter val_gpv_iou_switch__peripheral_id4 = 32'h00000004; +parameter mask_gpv_iou_switch__peripheral_id4 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id5 = 32'hE0201FD4; +parameter val_gpv_iou_switch__peripheral_id5 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id5 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id6 = 32'hE0201FD8; +parameter val_gpv_iou_switch__peripheral_id6 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id6 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id7 = 32'hE0201FDC; +parameter val_gpv_iou_switch__peripheral_id7 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id7 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id0 = 32'hE0201FE0; +parameter val_gpv_iou_switch__peripheral_id0 = 32'h00000001; +parameter mask_gpv_iou_switch__peripheral_id0 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id1 = 32'hE0201FE4; +parameter val_gpv_iou_switch__peripheral_id1 = 32'h000000B3; +parameter mask_gpv_iou_switch__peripheral_id1 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id2 = 32'hE0201FE8; +parameter val_gpv_iou_switch__peripheral_id2 = 32'h0000005B; +parameter mask_gpv_iou_switch__peripheral_id2 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id3 = 32'hE0201FEC; +parameter val_gpv_iou_switch__peripheral_id3 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id3 = 32'h000000FF; + +parameter gpv_iou_switch__component_id0 = 32'hE0201FF0; +parameter val_gpv_iou_switch__component_id0 = 32'h0000000D; +parameter mask_gpv_iou_switch__component_id0 = 32'h000000FF; + +parameter gpv_iou_switch__component_id1 = 32'hE0201FF4; +parameter val_gpv_iou_switch__component_id1 = 32'h000000F0; +parameter mask_gpv_iou_switch__component_id1 = 32'h000000FF; + +parameter gpv_iou_switch__component_id2 = 32'hE0201FF8; +parameter val_gpv_iou_switch__component_id2 = 32'h00000005; +parameter mask_gpv_iou_switch__component_id2 = 32'h000000FF; + +parameter gpv_iou_switch__component_id3 = 32'hE0201FFC; +parameter val_gpv_iou_switch__component_id3 = 32'h000000B1; +parameter mask_gpv_iou_switch__component_id3 = 32'h000000FF; + +parameter gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'hE0202008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000003; + +parameter gpv_iou_switch__ahb_cntl_sdio0 = 32'hE0202044; +parameter val_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000; + +parameter gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'hE0203008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000003; + +parameter gpv_iou_switch__ahb_cntl_sdio1 = 32'hE0203044; +parameter val_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000; + +parameter gpv_iou_switch__fn_mod_bm_iss_qspi = 32'hE0204008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_bm_iss_miou = 32'hE0205008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_bm_iss_smc = 32'hE0207008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_gem0 = 32'hE0242028; +parameter val_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_gem0 = 32'hE0242100; +parameter val_gpv_iou_switch__read_qos_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_gem0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_gem0 = 32'hE0242104; +parameter val_gpv_iou_switch__write_qos_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_gem0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_gem0 = 32'hE0242108; +parameter val_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_gem1 = 32'hE0243028; +parameter val_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_gem1 = 32'hE0243100; +parameter val_gpv_iou_switch__read_qos_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_gem1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_gem1 = 32'hE0243104; +parameter val_gpv_iou_switch__write_qos_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_gem1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_gem1 = 32'hE0243108; +parameter val_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_usb0 = 32'hE0244028; +parameter val_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_usb0 = 32'hE0244100; +parameter val_gpv_iou_switch__read_qos_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_usb0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_usb0 = 32'hE0244104; +parameter val_gpv_iou_switch__write_qos_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_usb0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_usb0 = 32'hE0244108; +parameter val_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_usb1 = 32'hE0245028; +parameter val_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_usb1 = 32'hE0245100; +parameter val_gpv_iou_switch__read_qos_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_usb1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_usb1 = 32'hE0245104; +parameter val_gpv_iou_switch__write_qos_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_usb1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_usb1 = 32'hE0245108; +parameter val_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_sdio0 = 32'hE0246028; +parameter val_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_sdio0 = 32'hE0246100; +parameter val_gpv_iou_switch__read_qos_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_sdio0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_sdio0 = 32'hE0246104; +parameter val_gpv_iou_switch__write_qos_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_sdio0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_sdio0 = 32'hE0246108; +parameter val_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_sdio1 = 32'hE0247028; +parameter val_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_sdio1 = 32'hE0247100; +parameter val_gpv_iou_switch__read_qos_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_sdio1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_sdio1 = 32'hE0247104; +parameter val_gpv_iou_switch__write_qos_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_sdio1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_sdio1 = 32'hE0247108; +parameter val_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_iss_siou = 32'hE0249108; +parameter val_gpv_iou_switch__fn_mod_iss_siou = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_siou = 32'h00000003; + + +// ************************************************************ +// Module gpv_qos301_cpu qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_cpu__qos_cntl = 32'hF894610C; +parameter val_gpv_qos301_cpu__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_cpu__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_cpu__max_ot = 32'hF8946110; +parameter val_gpv_qos301_cpu__max_ot = 32'h00000000; +parameter mask_gpv_qos301_cpu__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_cpu__max_comb_ot = 32'hF8946114; +parameter val_gpv_qos301_cpu__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_cpu__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_cpu__aw_p = 32'hF8946118; +parameter val_gpv_qos301_cpu__aw_p = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_p = 32'hFF000000; + +parameter gpv_qos301_cpu__aw_b = 32'hF894611C; +parameter val_gpv_qos301_cpu__aw_b = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_cpu__aw_r = 32'hF8946120; +parameter val_gpv_qos301_cpu__aw_r = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_r = 32'hFFF00000; + +parameter gpv_qos301_cpu__ar_p = 32'hF8946124; +parameter val_gpv_qos301_cpu__ar_p = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_p = 32'hFF000000; + +parameter gpv_qos301_cpu__ar_b = 32'hF8946128; +parameter val_gpv_qos301_cpu__ar_b = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_cpu__ar_r = 32'hF894612C; +parameter val_gpv_qos301_cpu__ar_r = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_qos301_dmac qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_dmac__qos_cntl = 32'hF894710C; +parameter val_gpv_qos301_dmac__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_dmac__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_dmac__max_ot = 32'hF8947110; +parameter val_gpv_qos301_dmac__max_ot = 32'h00000000; +parameter mask_gpv_qos301_dmac__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_dmac__max_comb_ot = 32'hF8947114; +parameter val_gpv_qos301_dmac__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_dmac__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_dmac__aw_p = 32'hF8947118; +parameter val_gpv_qos301_dmac__aw_p = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_p = 32'hFF000000; + +parameter gpv_qos301_dmac__aw_b = 32'hF894711C; +parameter val_gpv_qos301_dmac__aw_b = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_dmac__aw_r = 32'hF8947120; +parameter val_gpv_qos301_dmac__aw_r = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_r = 32'hFFF00000; + +parameter gpv_qos301_dmac__ar_p = 32'hF8947124; +parameter val_gpv_qos301_dmac__ar_p = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_p = 32'hFF000000; + +parameter gpv_qos301_dmac__ar_b = 32'hF8947128; +parameter val_gpv_qos301_dmac__ar_b = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_dmac__ar_r = 32'hF894712C; +parameter val_gpv_qos301_dmac__ar_r = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_qos301_iou qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_iou__qos_cntl = 32'hF894810C; +parameter val_gpv_qos301_iou__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_iou__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_iou__max_ot = 32'hF8948110; +parameter val_gpv_qos301_iou__max_ot = 32'h00000000; +parameter mask_gpv_qos301_iou__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_iou__max_comb_ot = 32'hF8948114; +parameter val_gpv_qos301_iou__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_iou__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_iou__aw_p = 32'hF8948118; +parameter val_gpv_qos301_iou__aw_p = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_p = 32'hFF000000; + +parameter gpv_qos301_iou__aw_b = 32'hF894811C; +parameter val_gpv_qos301_iou__aw_b = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_iou__aw_r = 32'hF8948120; +parameter val_gpv_qos301_iou__aw_r = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_r = 32'hFFF00000; + +parameter gpv_qos301_iou__ar_p = 32'hF8948124; +parameter val_gpv_qos301_iou__ar_p = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_p = 32'hFF000000; + +parameter gpv_qos301_iou__ar_b = 32'hF8948128; +parameter val_gpv_qos301_iou__ar_b = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_iou__ar_r = 32'hF894812C; +parameter val_gpv_qos301_iou__ar_r = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_trustzone nic301_addr_region_ctrl_registers +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_trustzone__Remap = 32'hF8900000; +parameter val_gpv_trustzone__Remap = 32'h00000000; +parameter mask_gpv_trustzone__Remap = 32'h000000C0; + +parameter gpv_trustzone__security_fssw_s0 = 32'hF890001C; +parameter val_gpv_trustzone__security_fssw_s0 = 32'h00000000; +parameter mask_gpv_trustzone__security_fssw_s0 = 32'h00000001; + +parameter gpv_trustzone__security_fssw_s1 = 32'hF8900020; +parameter val_gpv_trustzone__security_fssw_s1 = 32'h00000000; +parameter mask_gpv_trustzone__security_fssw_s1 = 32'h00000001; + +parameter gpv_trustzone__security_apb = 32'hF8900028; +parameter val_gpv_trustzone__security_apb = 32'h00000000; +parameter mask_gpv_trustzone__security_apb = 32'h0000003F; + + +// ************************************************************ +// Module i2c0 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter i2c0__Control_reg0 = 32'hE0004000; +parameter val_i2c0__Control_reg0 = 32'h00000000; +parameter mask_i2c0__Control_reg0 = 32'h0000FFFF; + +parameter i2c0__Status_reg0 = 32'hE0004004; +parameter val_i2c0__Status_reg0 = 32'h00000000; +parameter mask_i2c0__Status_reg0 = 32'h0000FFFF; + +parameter i2c0__I2C_address_reg0 = 32'hE0004008; +parameter val_i2c0__I2C_address_reg0 = 32'h00000000; +parameter mask_i2c0__I2C_address_reg0 = 32'h0000FFFF; + +parameter i2c0__I2C_data_reg0 = 32'hE000400C; +parameter val_i2c0__I2C_data_reg0 = 32'h00000000; +parameter mask_i2c0__I2C_data_reg0 = 32'h0000FFFF; + +parameter i2c0__Interrupt_status_reg0 = 32'hE0004010; +parameter val_i2c0__Interrupt_status_reg0 = 32'h00000000; +parameter mask_i2c0__Interrupt_status_reg0 = 32'h0000FFFF; + +parameter i2c0__Transfer_size_reg0 = 32'hE0004014; +parameter val_i2c0__Transfer_size_reg0 = 32'h00000000; +parameter mask_i2c0__Transfer_size_reg0 = 32'h000000FF; + +parameter i2c0__Slave_mon_pause_reg0 = 32'hE0004018; +parameter val_i2c0__Slave_mon_pause_reg0 = 32'h00000000; +parameter mask_i2c0__Slave_mon_pause_reg0 = 32'h000000FF; + +parameter i2c0__Time_out_reg0 = 32'hE000401C; +parameter val_i2c0__Time_out_reg0 = 32'h0000001F; +parameter mask_i2c0__Time_out_reg0 = 32'h000000FF; + +parameter i2c0__Intrpt_mask_reg0 = 32'hE0004020; +parameter val_i2c0__Intrpt_mask_reg0 = 32'h000002FF; +parameter mask_i2c0__Intrpt_mask_reg0 = 32'h0000FFFF; + +parameter i2c0__Intrpt_enable_reg0 = 32'hE0004024; +parameter val_i2c0__Intrpt_enable_reg0 = 32'h00000000; +parameter mask_i2c0__Intrpt_enable_reg0 = 32'h0000FFFF; + +parameter i2c0__Intrpt_disable_reg0 = 32'hE0004028; +parameter val_i2c0__Intrpt_disable_reg0 = 32'h00000000; +parameter mask_i2c0__Intrpt_disable_reg0 = 32'h0000FFFF; + + +// ************************************************************ +// Module i2c1 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter i2c1__Control_reg0 = 32'hE0005000; +parameter val_i2c1__Control_reg0 = 32'h00000000; +parameter mask_i2c1__Control_reg0 = 32'h0000FFFF; + +parameter i2c1__Status_reg0 = 32'hE0005004; +parameter val_i2c1__Status_reg0 = 32'h00000000; +parameter mask_i2c1__Status_reg0 = 32'h0000FFFF; + +parameter i2c1__I2C_address_reg0 = 32'hE0005008; +parameter val_i2c1__I2C_address_reg0 = 32'h00000000; +parameter mask_i2c1__I2C_address_reg0 = 32'h0000FFFF; + +parameter i2c1__I2C_data_reg0 = 32'hE000500C; +parameter val_i2c1__I2C_data_reg0 = 32'h00000000; +parameter mask_i2c1__I2C_data_reg0 = 32'h0000FFFF; + +parameter i2c1__Interrupt_status_reg0 = 32'hE0005010; +parameter val_i2c1__Interrupt_status_reg0 = 32'h00000000; +parameter mask_i2c1__Interrupt_status_reg0 = 32'h0000FFFF; + +parameter i2c1__Transfer_size_reg0 = 32'hE0005014; +parameter val_i2c1__Transfer_size_reg0 = 32'h00000000; +parameter mask_i2c1__Transfer_size_reg0 = 32'h000000FF; + +parameter i2c1__Slave_mon_pause_reg0 = 32'hE0005018; +parameter val_i2c1__Slave_mon_pause_reg0 = 32'h00000000; +parameter mask_i2c1__Slave_mon_pause_reg0 = 32'h000000FF; + +parameter i2c1__Time_out_reg0 = 32'hE000501C; +parameter val_i2c1__Time_out_reg0 = 32'h0000001F; +parameter mask_i2c1__Time_out_reg0 = 32'h000000FF; + +parameter i2c1__Intrpt_mask_reg0 = 32'hE0005020; +parameter val_i2c1__Intrpt_mask_reg0 = 32'h000002FF; +parameter mask_i2c1__Intrpt_mask_reg0 = 32'h0000FFFF; + +parameter i2c1__Intrpt_enable_reg0 = 32'hE0005024; +parameter val_i2c1__Intrpt_enable_reg0 = 32'h00000000; +parameter mask_i2c1__Intrpt_enable_reg0 = 32'h0000FFFF; + +parameter i2c1__Intrpt_disable_reg0 = 32'hE0005028; +parameter val_i2c1__Intrpt_disable_reg0 = 32'h00000000; +parameter mask_i2c1__Intrpt_disable_reg0 = 32'h0000FFFF; + + +// ************************************************************ +// Module l2cache L2Cpl310 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter l2cache__reg0_cache_id = 32'hF8F02000; +parameter val_l2cache__reg0_cache_id = 32'h410000C8; +parameter mask_l2cache__reg0_cache_id = 32'hFFFFFFFF; + +parameter l2cache__reg0_cache_type = 32'hF8F02004; +parameter val_l2cache__reg0_cache_type = 32'h9E300300; +parameter mask_l2cache__reg0_cache_type = 32'hFFFFFFFF; + +parameter l2cache__reg1_control = 32'hF8F02100; +parameter val_l2cache__reg1_control = 32'h00000000; +parameter mask_l2cache__reg1_control = 32'h7FFFFFFF; + +parameter l2cache__reg1_aux_control = 32'hF8F02104; +parameter val_l2cache__reg1_aux_control = 32'h02050000; +parameter mask_l2cache__reg1_aux_control = 32'hFFFFFFFF; + +parameter l2cache__reg1_tag_ram_control = 32'hF8F02108; +parameter val_l2cache__reg1_tag_ram_control = 32'h00000777; +parameter mask_l2cache__reg1_tag_ram_control = 32'hFFFFFFFF; + +parameter l2cache__reg1_data_ram_control = 32'hF8F0210C; +parameter val_l2cache__reg1_data_ram_control = 32'h00000777; +parameter mask_l2cache__reg1_data_ram_control = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter_ctrl = 32'hF8F02200; +parameter val_l2cache__reg2_ev_counter_ctrl = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter1_cfg = 32'hF8F02204; +parameter val_l2cache__reg2_ev_counter1_cfg = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter1_cfg = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter0_cfg = 32'hF8F02208; +parameter val_l2cache__reg2_ev_counter0_cfg = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter0_cfg = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter1 = 32'hF8F0220C; +parameter val_l2cache__reg2_ev_counter1 = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter1 = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter0 = 32'hF8F02210; +parameter val_l2cache__reg2_ev_counter0 = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter0 = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_mask = 32'hF8F02214; +parameter val_l2cache__reg2_int_mask = 32'h00000000; +parameter mask_l2cache__reg2_int_mask = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_mask_status = 32'hF8F02218; +parameter val_l2cache__reg2_int_mask_status = 32'h00000000; +parameter mask_l2cache__reg2_int_mask_status = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_raw_status = 32'hF8F0221C; +parameter val_l2cache__reg2_int_raw_status = 32'h00000000; +parameter mask_l2cache__reg2_int_raw_status = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_clear = 32'hF8F02220; +parameter val_l2cache__reg2_int_clear = 32'h00000000; +parameter mask_l2cache__reg2_int_clear = 32'hFFFFFFFF; + +parameter l2cache__reg7_cache_sync = 32'hF8F02730; +parameter val_l2cache__reg7_cache_sync = 32'h00000000; +parameter mask_l2cache__reg7_cache_sync = 32'hFFFFFFFF; + +parameter l2cache__reg7_inv_pa = 32'hF8F02770; +parameter val_l2cache__reg7_inv_pa = 32'h00000000; +parameter mask_l2cache__reg7_inv_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_inv_way = 32'hF8F0277C; +parameter val_l2cache__reg7_inv_way = 32'h00000000; +parameter mask_l2cache__reg7_inv_way = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_pa = 32'hF8F027B0; +parameter val_l2cache__reg7_clean_pa = 32'h00000000; +parameter mask_l2cache__reg7_clean_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_index = 32'hF8F027B8; +parameter val_l2cache__reg7_clean_index = 32'h00000000; +parameter mask_l2cache__reg7_clean_index = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_way = 32'hF8F027BC; +parameter val_l2cache__reg7_clean_way = 32'h00000000; +parameter mask_l2cache__reg7_clean_way = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_pa = 32'hF8F027F0; +parameter val_l2cache__reg7_clean_inv_pa = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_index = 32'hF8F027F8; +parameter val_l2cache__reg7_clean_inv_index = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_index = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_way = 32'hF8F027FC; +parameter val_l2cache__reg7_clean_inv_way = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_way = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown0 = 32'hF8F02900; +parameter val_l2cache__reg9_d_lockdown0 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown0 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown0 = 32'hF8F02904; +parameter val_l2cache__reg9_i_lockdown0 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown0 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown1 = 32'hF8F02908; +parameter val_l2cache__reg9_d_lockdown1 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown1 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown1 = 32'hF8F0290C; +parameter val_l2cache__reg9_i_lockdown1 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown1 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown2 = 32'hF8F02910; +parameter val_l2cache__reg9_d_lockdown2 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown2 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown2 = 32'hF8F02914; +parameter val_l2cache__reg9_i_lockdown2 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown2 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown3 = 32'hF8F02918; +parameter val_l2cache__reg9_d_lockdown3 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown3 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown3 = 32'hF8F0291C; +parameter val_l2cache__reg9_i_lockdown3 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown3 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown4 = 32'hF8F02920; +parameter val_l2cache__reg9_d_lockdown4 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown4 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown4 = 32'hF8F02924; +parameter val_l2cache__reg9_i_lockdown4 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown4 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown5 = 32'hF8F02928; +parameter val_l2cache__reg9_d_lockdown5 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown5 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown5 = 32'hF8F0292C; +parameter val_l2cache__reg9_i_lockdown5 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown5 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown6 = 32'hF8F02930; +parameter val_l2cache__reg9_d_lockdown6 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown6 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown6 = 32'hF8F02934; +parameter val_l2cache__reg9_i_lockdown6 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown6 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown7 = 32'hF8F02938; +parameter val_l2cache__reg9_d_lockdown7 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown7 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown7 = 32'hF8F0293C; +parameter val_l2cache__reg9_i_lockdown7 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown7 = 32'hFFFFFFFF; + +parameter l2cache__reg9_lock_line_en = 32'hF8F02950; +parameter val_l2cache__reg9_lock_line_en = 32'h00000000; +parameter mask_l2cache__reg9_lock_line_en = 32'hFFFFFFFF; + +parameter l2cache__reg9_unlock_way = 32'hF8F02954; +parameter val_l2cache__reg9_unlock_way = 32'h00000000; +parameter mask_l2cache__reg9_unlock_way = 32'hFFFFFFFF; + +parameter l2cache__reg12_addr_filtering_start = 32'hF8F02C00; +parameter val_l2cache__reg12_addr_filtering_start = 32'h40000001; +parameter mask_l2cache__reg12_addr_filtering_start = 32'hFFFFFFFF; + +parameter l2cache__reg12_addr_filtering_end = 32'hF8F02C04; +parameter val_l2cache__reg12_addr_filtering_end = 32'hFFF00000; +parameter mask_l2cache__reg12_addr_filtering_end = 32'hFFFFFFFF; + +parameter l2cache__reg15_debug_ctrl = 32'hF8F02F40; +parameter val_l2cache__reg15_debug_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_debug_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg15_prefetch_ctrl = 32'hF8F02F60; +parameter val_l2cache__reg15_prefetch_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_prefetch_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg15_power_ctrl = 32'hF8F02F80; +parameter val_l2cache__reg15_power_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_power_ctrl = 32'hFFFFFFFF; + + +// ************************************************************ +// Module mpcore mpcore +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter mpcore__SCU_CONTROL_REGISTER = 32'hF8F00000; +parameter val_mpcore__SCU_CONTROL_REGISTER = 32'h00000002; +parameter mask_mpcore__SCU_CONTROL_REGISTER = 32'hFFFFFFFF; + +parameter mpcore__SCU_CONFIGURATION_REGISTER = 32'hF8F00004; +parameter val_mpcore__SCU_CONFIGURATION_REGISTER = 32'h00000501; +parameter mask_mpcore__SCU_CONFIGURATION_REGISTER = 32'hFFFFFFFF; + +parameter mpcore__SCU_CPU_Power_Status_Register = 32'hF8F00008; +parameter val_mpcore__SCU_CPU_Power_Status_Register = 32'h00000000; +parameter mask_mpcore__SCU_CPU_Power_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hF8F0000C; +parameter val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'h00000000; +parameter mask_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hFFFFFFFF; + +parameter mpcore__Filtering_Start_Address_Register = 32'hF8F00040; +parameter val_mpcore__Filtering_Start_Address_Register = 32'h00100000; +parameter mask_mpcore__Filtering_Start_Address_Register = 32'hFFFFFFFF; + +parameter mpcore__Filtering_End_Address_Register = 32'hF8F00044; +parameter val_mpcore__Filtering_End_Address_Register = 32'h00000000; +parameter mask_mpcore__Filtering_End_Address_Register = 32'hFFFFFFFF; + +parameter mpcore__SCU_Access_Control_Register_SAC = 32'hF8F00050; +parameter val_mpcore__SCU_Access_Control_Register_SAC = 32'h0000000F; +parameter mask_mpcore__SCU_Access_Control_Register_SAC = 32'hFFFFFFFF; + +parameter mpcore__SCU_Non_secure_Access_Control_Register = 32'hF8F00054; +parameter val_mpcore__SCU_Non_secure_Access_Control_Register = 32'h00000000; +parameter mask_mpcore__SCU_Non_secure_Access_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__ICCICR = 32'hF8F00100; +parameter val_mpcore__ICCICR = 32'h00000000; +parameter mask_mpcore__ICCICR = 32'hFFFFFFFF; + +parameter mpcore__ICCPMR = 32'hF8F00104; +parameter val_mpcore__ICCPMR = 32'h00000000; +parameter mask_mpcore__ICCPMR = 32'hFFFFFFFF; + +parameter mpcore__ICCBPR = 32'hF8F00108; +parameter val_mpcore__ICCBPR = 32'h00000002; +parameter mask_mpcore__ICCBPR = 32'hFFFFFFFF; + +parameter mpcore__ICCIAR = 32'hF8F0010C; +parameter val_mpcore__ICCIAR = 32'h000003FF; +parameter mask_mpcore__ICCIAR = 32'hFFFFFFFF; + +parameter mpcore__ICCEOIR = 32'hF8F00110; +parameter val_mpcore__ICCEOIR = 32'h00000000; +parameter mask_mpcore__ICCEOIR = 32'hFFFFFFFF; + +parameter mpcore__ICCRPR = 32'hF8F00114; +parameter val_mpcore__ICCRPR = 32'h000000FF; +parameter mask_mpcore__ICCRPR = 32'hFFFFFFFF; + +parameter mpcore__ICCHPIR = 32'hF8F00118; +parameter val_mpcore__ICCHPIR = 32'h000003FF; +parameter mask_mpcore__ICCHPIR = 32'hFFFFFFFF; + +parameter mpcore__ICCABPR = 32'hF8F0011C; +parameter val_mpcore__ICCABPR = 32'h00000003; +parameter mask_mpcore__ICCABPR = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR = 32'hF8F001FC; +parameter val_mpcore__ICCIDR = 32'h3901243B; +parameter mask_mpcore__ICCIDR = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Counter_Register0 = 32'hF8F00200; +parameter val_mpcore__Global_Timer_Counter_Register0 = 32'h00000000; +parameter mask_mpcore__Global_Timer_Counter_Register0 = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Counter_Register1 = 32'hF8F00204; +parameter val_mpcore__Global_Timer_Counter_Register1 = 32'h00000000; +parameter mask_mpcore__Global_Timer_Counter_Register1 = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Control_Register = 32'hF8F00208; +parameter val_mpcore__Global_Timer_Control_Register = 32'h00000000; +parameter mask_mpcore__Global_Timer_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Interrupt_Status_Register = 32'hF8F0020C; +parameter val_mpcore__Global_Timer_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Global_Timer_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Comparator_Value_Register0 = 32'hF8F00210; +parameter val_mpcore__Comparator_Value_Register0 = 32'h00000000; +parameter mask_mpcore__Comparator_Value_Register0 = 32'hFFFFFFFF; + +parameter mpcore__Comparator_Value_Register1 = 32'hF8F00214; +parameter val_mpcore__Comparator_Value_Register1 = 32'h00000000; +parameter mask_mpcore__Comparator_Value_Register1 = 32'hFFFFFFFF; + +parameter mpcore__Auto_increment_Register = 32'hF8F00218; +parameter val_mpcore__Auto_increment_Register = 32'h00000000; +parameter mask_mpcore__Auto_increment_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Load_Register = 32'hF8F00600; +parameter val_mpcore__Private_Timer_Load_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Load_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Counter_Register = 32'hF8F00604; +parameter val_mpcore__Private_Timer_Counter_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Counter_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Control_Register = 32'hF8F00608; +parameter val_mpcore__Private_Timer_Control_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Interrupt_Status_Register = 32'hF8F0060C; +parameter val_mpcore__Private_Timer_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Load_Register = 32'hF8F00620; +parameter val_mpcore__Watchdog_Load_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Load_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Counter_Register = 32'hF8F00624; +parameter val_mpcore__Watchdog_Counter_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Counter_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Control_Register = 32'hF8F00628; +parameter val_mpcore__Watchdog_Control_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Interrupt_Status_Register = 32'hF8F0062C; +parameter val_mpcore__Watchdog_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Reset_Status_Register = 32'hF8F00630; +parameter val_mpcore__Watchdog_Reset_Status_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Reset_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Disable_Register = 32'hF8F00634; +parameter val_mpcore__Watchdog_Disable_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Disable_Register = 32'hFFFFFFFF; + +parameter mpcore__ICDDCR = 32'hF8F01000; +parameter val_mpcore__ICDDCR = 32'h00000000; +parameter mask_mpcore__ICDDCR = 32'hFFFFFFFF; + +parameter mpcore__ICDICTR = 32'hF8F01004; +parameter val_mpcore__ICDICTR = 32'h00000C22; +parameter mask_mpcore__ICDICTR = 32'hE000FFFF; + +parameter mpcore__ICDIIDR = 32'hF8F01008; +parameter val_mpcore__ICDIIDR = 32'h0102043B; +parameter mask_mpcore__ICDIIDR = 32'hFFFFFFFF; + +parameter mpcore__ICDISR0 = 32'hF8F01080; +parameter val_mpcore__ICDISR0 = 32'h00000000; +parameter mask_mpcore__ICDISR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISR1 = 32'hF8F01084; +parameter val_mpcore__ICDISR1 = 32'h00000000; +parameter mask_mpcore__ICDISR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISR2 = 32'hF8F01088; +parameter val_mpcore__ICDISR2 = 32'h00000000; +parameter mask_mpcore__ICDISR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER0 = 32'hF8F01100; +parameter val_mpcore__ICDISER0 = 32'h0000FFFF; +parameter mask_mpcore__ICDISER0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER1 = 32'hF8F01104; +parameter val_mpcore__ICDISER1 = 32'h00000000; +parameter mask_mpcore__ICDISER1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER2 = 32'hF8F01108; +parameter val_mpcore__ICDISER2 = 32'h00000000; +parameter mask_mpcore__ICDISER2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER0 = 32'hF8F01180; +parameter val_mpcore__ICDICER0 = 32'h0000FFFF; +parameter mask_mpcore__ICDICER0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER1 = 32'hF8F01184; +parameter val_mpcore__ICDICER1 = 32'h00000000; +parameter mask_mpcore__ICDICER1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER2 = 32'hF8F01188; +parameter val_mpcore__ICDICER2 = 32'h00000000; +parameter mask_mpcore__ICDICER2 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR0 = 32'hF8F01200; +parameter val_mpcore__ICDISPR0 = 32'h00000000; +parameter mask_mpcore__ICDISPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR1 = 32'hF8F01204; +parameter val_mpcore__ICDISPR1 = 32'h00000000; +parameter mask_mpcore__ICDISPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR2 = 32'hF8F01208; +parameter val_mpcore__ICDISPR2 = 32'h00000000; +parameter mask_mpcore__ICDISPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR0 = 32'hF8F01280; +parameter val_mpcore__ICDICPR0 = 32'h00000000; +parameter mask_mpcore__ICDICPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR1 = 32'hF8F01284; +parameter val_mpcore__ICDICPR1 = 32'h00000000; +parameter mask_mpcore__ICDICPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR2 = 32'hF8F01288; +parameter val_mpcore__ICDICPR2 = 32'h00000000; +parameter mask_mpcore__ICDICPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR0 = 32'hF8F01300; +parameter val_mpcore__ICDABR0 = 32'h00000000; +parameter mask_mpcore__ICDABR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR1 = 32'hF8F01304; +parameter val_mpcore__ICDABR1 = 32'h00000000; +parameter mask_mpcore__ICDABR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR2 = 32'hF8F01308; +parameter val_mpcore__ICDABR2 = 32'h00000000; +parameter mask_mpcore__ICDABR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR0 = 32'hF8F01400; +parameter val_mpcore__ICDIPR0 = 32'h00000000; +parameter mask_mpcore__ICDIPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR1 = 32'hF8F01404; +parameter val_mpcore__ICDIPR1 = 32'h00000000; +parameter mask_mpcore__ICDIPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR2 = 32'hF8F01408; +parameter val_mpcore__ICDIPR2 = 32'h00000000; +parameter mask_mpcore__ICDIPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR3 = 32'hF8F0140C; +parameter val_mpcore__ICDIPR3 = 32'h00000000; +parameter mask_mpcore__ICDIPR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR4 = 32'hF8F01410; +parameter val_mpcore__ICDIPR4 = 32'h00000000; +parameter mask_mpcore__ICDIPR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR5 = 32'hF8F01414; +parameter val_mpcore__ICDIPR5 = 32'h00000000; +parameter mask_mpcore__ICDIPR5 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR6 = 32'hF8F01418; +parameter val_mpcore__ICDIPR6 = 32'h00000000; +parameter mask_mpcore__ICDIPR6 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR7 = 32'hF8F0141C; +parameter val_mpcore__ICDIPR7 = 32'h00000000; +parameter mask_mpcore__ICDIPR7 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR8 = 32'hF8F01420; +parameter val_mpcore__ICDIPR8 = 32'h00000000; +parameter mask_mpcore__ICDIPR8 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR9 = 32'hF8F01424; +parameter val_mpcore__ICDIPR9 = 32'h00000000; +parameter mask_mpcore__ICDIPR9 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR10 = 32'hF8F01428; +parameter val_mpcore__ICDIPR10 = 32'h00000000; +parameter mask_mpcore__ICDIPR10 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR11 = 32'hF8F0142C; +parameter val_mpcore__ICDIPR11 = 32'h00000000; +parameter mask_mpcore__ICDIPR11 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR12 = 32'hF8F01430; +parameter val_mpcore__ICDIPR12 = 32'h00000000; +parameter mask_mpcore__ICDIPR12 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR13 = 32'hF8F01434; +parameter val_mpcore__ICDIPR13 = 32'h00000000; +parameter mask_mpcore__ICDIPR13 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR14 = 32'hF8F01438; +parameter val_mpcore__ICDIPR14 = 32'h00000000; +parameter mask_mpcore__ICDIPR14 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR15 = 32'hF8F0143C; +parameter val_mpcore__ICDIPR15 = 32'h00000000; +parameter mask_mpcore__ICDIPR15 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR16 = 32'hF8F01440; +parameter val_mpcore__ICDIPR16 = 32'h00000000; +parameter mask_mpcore__ICDIPR16 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR17 = 32'hF8F01444; +parameter val_mpcore__ICDIPR17 = 32'h00000000; +parameter mask_mpcore__ICDIPR17 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR18 = 32'hF8F01448; +parameter val_mpcore__ICDIPR18 = 32'h00000000; +parameter mask_mpcore__ICDIPR18 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR19 = 32'hF8F0144C; +parameter val_mpcore__ICDIPR19 = 32'h00000000; +parameter mask_mpcore__ICDIPR19 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR20 = 32'hF8F01450; +parameter val_mpcore__ICDIPR20 = 32'h00000000; +parameter mask_mpcore__ICDIPR20 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR21 = 32'hF8F01454; +parameter val_mpcore__ICDIPR21 = 32'h00000000; +parameter mask_mpcore__ICDIPR21 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR22 = 32'hF8F01458; +parameter val_mpcore__ICDIPR22 = 32'h00000000; +parameter mask_mpcore__ICDIPR22 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR23 = 32'hF8F0145C; +parameter val_mpcore__ICDIPR23 = 32'h00000000; +parameter mask_mpcore__ICDIPR23 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR0 = 32'hF8F01800; +parameter val_mpcore__ICDIPTR0 = 32'h01010101; +parameter mask_mpcore__ICDIPTR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR1 = 32'hF8F01804; +parameter val_mpcore__ICDIPTR1 = 32'h01010101; +parameter mask_mpcore__ICDIPTR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR2 = 32'hF8F01808; +parameter val_mpcore__ICDIPTR2 = 32'h01010101; +parameter mask_mpcore__ICDIPTR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR3 = 32'hF8F0180C; +parameter val_mpcore__ICDIPTR3 = 32'h01010101; +parameter mask_mpcore__ICDIPTR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR4 = 32'hF8F01810; +parameter val_mpcore__ICDIPTR4 = 32'h01010101; +parameter mask_mpcore__ICDIPTR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR5 = 32'hF8F01814; +parameter val_mpcore__ICDIPTR5 = 32'h01010101; +parameter mask_mpcore__ICDIPTR5 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR6 = 32'hF8F01818; +parameter val_mpcore__ICDIPTR6 = 32'h01010101; +parameter mask_mpcore__ICDIPTR6 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR7 = 32'hF8F0181C; +parameter val_mpcore__ICDIPTR7 = 32'h01010101; +parameter mask_mpcore__ICDIPTR7 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR8 = 32'hF8F01820; +parameter val_mpcore__ICDIPTR8 = 32'h01010101; +parameter mask_mpcore__ICDIPTR8 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR9 = 32'hF8F01824; +parameter val_mpcore__ICDIPTR9 = 32'h01010101; +parameter mask_mpcore__ICDIPTR9 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR10 = 32'hF8F01828; +parameter val_mpcore__ICDIPTR10 = 32'h01010101; +parameter mask_mpcore__ICDIPTR10 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR11 = 32'hF8F0182C; +parameter val_mpcore__ICDIPTR11 = 32'h01010101; +parameter mask_mpcore__ICDIPTR11 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR12 = 32'hF8F01830; +parameter val_mpcore__ICDIPTR12 = 32'h01010101; +parameter mask_mpcore__ICDIPTR12 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR13 = 32'hF8F01834; +parameter val_mpcore__ICDIPTR13 = 32'h01010101; +parameter mask_mpcore__ICDIPTR13 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR14 = 32'hF8F01838; +parameter val_mpcore__ICDIPTR14 = 32'h01010101; +parameter mask_mpcore__ICDIPTR14 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR15 = 32'hF8F0183C; +parameter val_mpcore__ICDIPTR15 = 32'h01010101; +parameter mask_mpcore__ICDIPTR15 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR16 = 32'hF8F01840; +parameter val_mpcore__ICDIPTR16 = 32'h01010101; +parameter mask_mpcore__ICDIPTR16 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR17 = 32'hF8F01844; +parameter val_mpcore__ICDIPTR17 = 32'h01010101; +parameter mask_mpcore__ICDIPTR17 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR18 = 32'hF8F01848; +parameter val_mpcore__ICDIPTR18 = 32'h01010101; +parameter mask_mpcore__ICDIPTR18 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR19 = 32'hF8F0184C; +parameter val_mpcore__ICDIPTR19 = 32'h01010101; +parameter mask_mpcore__ICDIPTR19 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR20 = 32'hF8F01850; +parameter val_mpcore__ICDIPTR20 = 32'h01010101; +parameter mask_mpcore__ICDIPTR20 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR21 = 32'hF8F01854; +parameter val_mpcore__ICDIPTR21 = 32'h01010101; +parameter mask_mpcore__ICDIPTR21 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR22 = 32'hF8F01858; +parameter val_mpcore__ICDIPTR22 = 32'h01010101; +parameter mask_mpcore__ICDIPTR22 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR23 = 32'hF8F0185C; +parameter val_mpcore__ICDIPTR23 = 32'h01010101; +parameter mask_mpcore__ICDIPTR23 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR0 = 32'hF8F01C00; +parameter val_mpcore__ICDICFR0 = 32'hAAAAAAAA; +parameter mask_mpcore__ICDICFR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR1 = 32'hF8F01C04; +parameter val_mpcore__ICDICFR1 = 32'h7DC00000; +parameter mask_mpcore__ICDICFR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR2 = 32'hF8F01C08; +parameter val_mpcore__ICDICFR2 = 32'h55555555; +parameter mask_mpcore__ICDICFR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR3 = 32'hF8F01C0C; +parameter val_mpcore__ICDICFR3 = 32'h55555555; +parameter mask_mpcore__ICDICFR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR4 = 32'hF8F01C10; +parameter val_mpcore__ICDICFR4 = 32'h55555555; +parameter mask_mpcore__ICDICFR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR5 = 32'hF8F01C14; +parameter val_mpcore__ICDICFR5 = 32'h55555555; +parameter mask_mpcore__ICDICFR5 = 32'hFFFFFFFF; + +parameter mpcore__ppi_status = 32'hF8F01D00; +parameter val_mpcore__ppi_status = 32'h00000000; +parameter mask_mpcore__ppi_status = 32'hFFFFFFFF; + +parameter mpcore__spi_status_0 = 32'hF8F01D04; +parameter val_mpcore__spi_status_0 = 32'h00000000; +parameter mask_mpcore__spi_status_0 = 32'hFFFFFFFF; + +parameter mpcore__spi_status_1 = 32'hF8F01D08; +parameter val_mpcore__spi_status_1 = 32'h00000000; +parameter mask_mpcore__spi_status_1 = 32'hFFFFFFFF; + +parameter mpcore__ICDSGIR = 32'hF8F01F00; +parameter val_mpcore__ICDSGIR = 32'h00000000; +parameter mask_mpcore__ICDSGIR = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR4 = 32'hF8F01FD0; +parameter val_mpcore__ICPIDR4 = 32'h00000004; +parameter mask_mpcore__ICPIDR4 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR5 = 32'hF8F01FD4; +parameter val_mpcore__ICPIDR5 = 32'h00000000; +parameter mask_mpcore__ICPIDR5 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR6 = 32'hF8F01FD8; +parameter val_mpcore__ICPIDR6 = 32'h00000000; +parameter mask_mpcore__ICPIDR6 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR7 = 32'hF8F01FDC; +parameter val_mpcore__ICPIDR7 = 32'h00000000; +parameter mask_mpcore__ICPIDR7 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR0 = 32'hF8F01FE0; +parameter val_mpcore__ICPIDR0 = 32'h00000090; +parameter mask_mpcore__ICPIDR0 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR1 = 32'hF8F01FE4; +parameter val_mpcore__ICPIDR1 = 32'h000000B3; +parameter mask_mpcore__ICPIDR1 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR2 = 32'hF8F01FE8; +parameter val_mpcore__ICPIDR2 = 32'h0000001B; +parameter mask_mpcore__ICPIDR2 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR3 = 32'hF8F01FEC; +parameter val_mpcore__ICPIDR3 = 32'h00000000; +parameter mask_mpcore__ICPIDR3 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR0 = 32'hF8F01FF0; +parameter val_mpcore__ICCIDR0 = 32'h0000000D; +parameter mask_mpcore__ICCIDR0 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR1 = 32'hF8F01FF4; +parameter val_mpcore__ICCIDR1 = 32'h000000F0; +parameter mask_mpcore__ICCIDR1 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR2 = 32'hF8F01FF8; +parameter val_mpcore__ICCIDR2 = 32'h00000005; +parameter mask_mpcore__ICCIDR2 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR3 = 32'hF8F01FFC; +parameter val_mpcore__ICCIDR3 = 32'h000000B1; +parameter mask_mpcore__ICCIDR3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module ocm ocm +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ocm__OCM_PARITY_CTRL = 32'hF800C000; +parameter val_ocm__OCM_PARITY_CTRL = 32'h00000000; +parameter mask_ocm__OCM_PARITY_CTRL = 32'hFFFFFFFF; + +parameter ocm__OCM_PARITY_ERRADDRESS = 32'hF800C004; +parameter val_ocm__OCM_PARITY_ERRADDRESS = 32'h00000000; +parameter mask_ocm__OCM_PARITY_ERRADDRESS = 32'hFFFFFFFF; + +parameter ocm__OCM_IRQ_STS = 32'hF800C008; +parameter val_ocm__OCM_IRQ_STS = 32'h00000000; +parameter mask_ocm__OCM_IRQ_STS = 32'hFFFFFFFF; + +parameter ocm__OCM_CONTROL = 32'hF800C00C; +parameter val_ocm__OCM_CONTROL = 32'h00000000; +parameter mask_ocm__OCM_CONTROL = 32'hFFFFFFFF; + + +// ************************************************************ +// Module qspi qspi +// doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller +// Design Specification document +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter qspi__Config_reg = 32'hE000D000; +parameter val_qspi__Config_reg = 32'h80000000; +parameter mask_qspi__Config_reg = 32'hFFFDFFFF; + +parameter qspi__Intr_status_REG = 32'hE000D004; +parameter val_qspi__Intr_status_REG = 32'h00000004; +parameter mask_qspi__Intr_status_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_en_REG = 32'hE000D008; +parameter val_qspi__Intrpt_en_REG = 32'h00000000; +parameter mask_qspi__Intrpt_en_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_dis_REG = 32'hE000D00C; +parameter val_qspi__Intrpt_dis_REG = 32'h00000000; +parameter mask_qspi__Intrpt_dis_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_mask_REG = 32'hE000D010; +parameter val_qspi__Intrpt_mask_REG = 32'h00000000; +parameter mask_qspi__Intrpt_mask_REG = 32'hFFFFFFFF; + +parameter qspi__En_REG = 32'hE000D014; +parameter val_qspi__En_REG = 32'h00000000; +parameter mask_qspi__En_REG = 32'hFFFFFFFF; + +parameter qspi__Delay_REG = 32'hE000D018; +parameter val_qspi__Delay_REG = 32'h00000000; +parameter mask_qspi__Delay_REG = 32'hFFFFFFFF; + +parameter qspi__TXD0 = 32'hE000D01C; +parameter val_qspi__TXD0 = 32'h00000000; +parameter mask_qspi__TXD0 = 32'hFFFFFFFF; + +parameter qspi__Rx_data_REG = 32'hE000D020; +parameter val_qspi__Rx_data_REG = 32'h00000000; +parameter mask_qspi__Rx_data_REG = 32'hFFFFFFFF; + +parameter qspi__Slave_Idle_count_REG = 32'hE000D024; +parameter val_qspi__Slave_Idle_count_REG = 32'h000000FF; +parameter mask_qspi__Slave_Idle_count_REG = 32'hFFFFFFFF; + +parameter qspi__TX_thres_REG = 32'hE000D028; +parameter val_qspi__TX_thres_REG = 32'h00000001; +parameter mask_qspi__TX_thres_REG = 32'hFFFFFFFF; + +parameter qspi__RX_thres_REG = 32'hE000D02C; +parameter val_qspi__RX_thres_REG = 32'h00000001; +parameter mask_qspi__RX_thres_REG = 32'hFFFFFFFF; + +parameter qspi__GPIO = 32'hE000D030; +parameter val_qspi__GPIO = 32'h00000001; +parameter mask_qspi__GPIO = 32'hFFFFFFFF; + +parameter qspi__LPBK_DLY_ADJ = 32'hE000D038; +parameter val_qspi__LPBK_DLY_ADJ = 32'h00000033; +parameter mask_qspi__LPBK_DLY_ADJ = 32'hFFFFFFFF; + +parameter qspi__TXD1 = 32'hE000D080; +parameter val_qspi__TXD1 = 32'h00000000; +parameter mask_qspi__TXD1 = 32'hFFFFFFFF; + +parameter qspi__TXD2 = 32'hE000D084; +parameter val_qspi__TXD2 = 32'h00000000; +parameter mask_qspi__TXD2 = 32'hFFFFFFFF; + +parameter qspi__TXD3 = 32'hE000D088; +parameter val_qspi__TXD3 = 32'h00000000; +parameter mask_qspi__TXD3 = 32'hFFFFFFFF; + +parameter qspi__LQSPI_CFG = 32'hE000D0A0; +parameter val_qspi__LQSPI_CFG = 32'h03A002EB; +parameter mask_qspi__LQSPI_CFG = 32'hFBFF07FF; + +parameter qspi__LQSPI_STS = 32'hE000D0A4; +parameter val_qspi__LQSPI_STS = 32'h00000000; +parameter mask_qspi__LQSPI_STS = 32'h000001FF; + +parameter qspi__MOD_ID = 32'hE000D0FC; +parameter val_qspi__MOD_ID = 32'h01090101; +parameter mask_qspi__MOD_ID = 32'hFFFFFFFF; + + +// ************************************************************ +// Module sd0 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter sd0__SDMA_system_address_register = 32'hE0100000; +parameter val_sd0__SDMA_system_address_register = 32'h00000000; +parameter mask_sd0__SDMA_system_address_register = 32'hFFFFFFFF; + +parameter sd0__Block_Size_Block_Count = 32'hE0100004; +parameter val_sd0__Block_Size_Block_Count = 32'h00000000; +parameter mask_sd0__Block_Size_Block_Count = 32'hFFFFFFFF; + +parameter sd0__Argument = 32'hE0100008; +parameter val_sd0__Argument = 32'h00000000; +parameter mask_sd0__Argument = 32'hFFFFFFFF; + +parameter sd0__Transfer_Mode_Command = 32'hE010000C; +parameter val_sd0__Transfer_Mode_Command = 32'h00000000; +parameter mask_sd0__Transfer_Mode_Command = 32'h1FFFFFFF; + +parameter sd0__Response0 = 32'hE0100010; +parameter val_sd0__Response0 = 32'h00000000; +parameter mask_sd0__Response0 = 32'hFFFFFFFF; + +parameter sd0__Response1 = 32'hE0100014; +parameter val_sd0__Response1 = 32'h00000000; +parameter mask_sd0__Response1 = 32'hFFFFFFFF; + +parameter sd0__Response2 = 32'hE0100018; +parameter val_sd0__Response2 = 32'h00000000; +parameter mask_sd0__Response2 = 32'hFFFFFFFF; + +parameter sd0__Response3 = 32'hE010001C; +parameter val_sd0__Response3 = 32'h00000000; +parameter mask_sd0__Response3 = 32'hFFFFFFFF; + +parameter sd0__Buffer_Data_Port = 32'hE0100020; +parameter val_sd0__Buffer_Data_Port = 32'h00000000; +parameter mask_sd0__Buffer_Data_Port = 32'hFFFFFFFF; + +parameter sd0__Present_State = 32'hE0100024; +parameter val_sd0__Present_State = 32'h01F20000; +parameter mask_sd0__Present_State = 32'h01FFFFFF; + +parameter sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0100028; +parameter val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000; +parameter mask_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF; + +parameter sd0__Clock_Control_Timeout_control_Software_reset = 32'hE010002C; +parameter val_sd0__Clock_Control_Timeout_control_Software_reset = 32'h00000000; +parameter mask_sd0__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF; + +parameter sd0__Normal_interrupt_status_Error_interrupt_status = 32'hE0100030; +parameter val_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h00000000; +parameter mask_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF; + +parameter sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0100034; +parameter val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000; +parameter mask_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF; + +parameter sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0100038; +parameter val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000; +parameter mask_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF; + +parameter sd0__Auto_CMD12_error_status = 32'hE010003C; +parameter val_sd0__Auto_CMD12_error_status = 32'h00000000; +parameter mask_sd0__Auto_CMD12_error_status = 32'h000000FF; + +parameter sd0__Capabilities = 32'hE0100040; +parameter val_sd0__Capabilities = 32'h69EC0080; +parameter mask_sd0__Capabilities = 32'h7FFFFFFF; + +parameter sd0__Maximum_current_capabilities = 32'hE0100048; +parameter val_sd0__Maximum_current_capabilities = 32'h00000001; +parameter mask_sd0__Maximum_current_capabilities = 32'h00FFFFFF; + +parameter sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0100050; +parameter val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000; +parameter mask_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF; + +parameter sd0__ADMA_error_status = 32'hE0100054; +parameter val_sd0__ADMA_error_status = 32'h00000000; +parameter mask_sd0__ADMA_error_status = 32'h00000007; + +parameter sd0__ADMA_system_address = 32'hE0100058; +parameter val_sd0__ADMA_system_address = 32'h00000000; +parameter mask_sd0__ADMA_system_address = 32'hFFFFFFFF; + +parameter sd0__Boot_Timeout_control = 32'hE0100060; +parameter val_sd0__Boot_Timeout_control = 32'h00000000; +parameter mask_sd0__Boot_Timeout_control = 32'hFFFFFFFF; + +parameter sd0__Debug_Selection = 32'hE0100064; +parameter val_sd0__Debug_Selection = 32'h00000000; +parameter mask_sd0__Debug_Selection = 32'h00000001; + +parameter sd0__SPI_interrupt_support = 32'hE01000F0; +parameter val_sd0__SPI_interrupt_support = 32'h00000000; +parameter mask_sd0__SPI_interrupt_support = 32'h000000FF; + +parameter sd0__Slot_interrupt_status_Host_controller_version = 32'hE01000FC; +parameter val_sd0__Slot_interrupt_status_Host_controller_version = 32'h89010000; +parameter mask_sd0__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF; + + +// ************************************************************ +// Module sd1 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter sd1__SDMA_system_address_register = 32'hE0101000; +parameter val_sd1__SDMA_system_address_register = 32'h00000000; +parameter mask_sd1__SDMA_system_address_register = 32'hFFFFFFFF; + +parameter sd1__Block_Size_Block_Count = 32'hE0101004; +parameter val_sd1__Block_Size_Block_Count = 32'h00000000; +parameter mask_sd1__Block_Size_Block_Count = 32'hFFFFFFFF; + +parameter sd1__Argument = 32'hE0101008; +parameter val_sd1__Argument = 32'h00000000; +parameter mask_sd1__Argument = 32'hFFFFFFFF; + +parameter sd1__Transfer_Mode_Command = 32'hE010100C; +parameter val_sd1__Transfer_Mode_Command = 32'h00000000; +parameter mask_sd1__Transfer_Mode_Command = 32'h1FFFFFFF; + +parameter sd1__Response0 = 32'hE0101010; +parameter val_sd1__Response0 = 32'h00000000; +parameter mask_sd1__Response0 = 32'hFFFFFFFF; + +parameter sd1__Response1 = 32'hE0101014; +parameter val_sd1__Response1 = 32'h00000000; +parameter mask_sd1__Response1 = 32'hFFFFFFFF; + +parameter sd1__Response2 = 32'hE0101018; +parameter val_sd1__Response2 = 32'h00000000; +parameter mask_sd1__Response2 = 32'hFFFFFFFF; + +parameter sd1__Response3 = 32'hE010101C; +parameter val_sd1__Response3 = 32'h00000000; +parameter mask_sd1__Response3 = 32'hFFFFFFFF; + +parameter sd1__Buffer_Data_Port = 32'hE0101020; +parameter val_sd1__Buffer_Data_Port = 32'h00000000; +parameter mask_sd1__Buffer_Data_Port = 32'hFFFFFFFF; + +parameter sd1__Present_State = 32'hE0101024; +parameter val_sd1__Present_State = 32'h01F20000; +parameter mask_sd1__Present_State = 32'h01FFFFFF; + +parameter sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0101028; +parameter val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000; +parameter mask_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF; + +parameter sd1__Clock_Control_Timeout_control_Software_reset = 32'hE010102C; +parameter val_sd1__Clock_Control_Timeout_control_Software_reset = 32'h00000000; +parameter mask_sd1__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF; + +parameter sd1__Normal_interrupt_status_Error_interrupt_status = 32'hE0101030; +parameter val_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h00000000; +parameter mask_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF; + +parameter sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0101034; +parameter val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000; +parameter mask_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF; + +parameter sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0101038; +parameter val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000; +parameter mask_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF; + +parameter sd1__Auto_CMD12_error_status = 32'hE010103C; +parameter val_sd1__Auto_CMD12_error_status = 32'h00000000; +parameter mask_sd1__Auto_CMD12_error_status = 32'h000000FF; + +parameter sd1__Capabilities = 32'hE0101040; +parameter val_sd1__Capabilities = 32'h69EC0080; +parameter mask_sd1__Capabilities = 32'h7FFFFFFF; + +parameter sd1__Maximum_current_capabilities = 32'hE0101048; +parameter val_sd1__Maximum_current_capabilities = 32'h00000001; +parameter mask_sd1__Maximum_current_capabilities = 32'h00FFFFFF; + +parameter sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0101050; +parameter val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000; +parameter mask_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF; + +parameter sd1__ADMA_error_status = 32'hE0101054; +parameter val_sd1__ADMA_error_status = 32'h00000000; +parameter mask_sd1__ADMA_error_status = 32'h00000007; + +parameter sd1__ADMA_system_address = 32'hE0101058; +parameter val_sd1__ADMA_system_address = 32'h00000000; +parameter mask_sd1__ADMA_system_address = 32'hFFFFFFFF; + +parameter sd1__Boot_Timeout_control = 32'hE0101060; +parameter val_sd1__Boot_Timeout_control = 32'h00000000; +parameter mask_sd1__Boot_Timeout_control = 32'hFFFFFFFF; + +parameter sd1__Debug_Selection = 32'hE0101064; +parameter val_sd1__Debug_Selection = 32'h00000000; +parameter mask_sd1__Debug_Selection = 32'h00000001; + +parameter sd1__SPI_interrupt_support = 32'hE01010F0; +parameter val_sd1__SPI_interrupt_support = 32'h00000000; +parameter mask_sd1__SPI_interrupt_support = 32'h000000FF; + +parameter sd1__Slot_interrupt_status_Host_controller_version = 32'hE01010FC; +parameter val_sd1__Slot_interrupt_status_Host_controller_version = 32'h89010000; +parameter mask_sd1__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF; + + +// ************************************************************ +// Module slcr slcr +// doc version: 1.3, based on 11/18/2010 SLCR_spec.doc +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter slcr__SCL = 32'hF8000000; +parameter val_slcr__SCL = 32'h00000000; +parameter mask_slcr__SCL = 32'hFFFFFFFF; + +parameter slcr__SLCR_LOCK = 32'hF8000004; +parameter val_slcr__SLCR_LOCK = 32'h00000000; +parameter mask_slcr__SLCR_LOCK = 32'hFFFFFFFF; + +parameter slcr__SLCR_UNLOCK = 32'hF8000008; +parameter val_slcr__SLCR_UNLOCK = 32'h00000000; +parameter mask_slcr__SLCR_UNLOCK = 32'hFFFFFFFF; + +parameter slcr__SLCR_LOCKSTA = 32'hF800000C; +parameter val_slcr__SLCR_LOCKSTA = 32'h00000001; +parameter mask_slcr__SLCR_LOCKSTA = 32'hFFFFFFFF; + +parameter slcr__ARM_PLL_CTRL = 32'hF8000100; +parameter val_slcr__ARM_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__ARM_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_PLL_CTRL = 32'hF8000104; +parameter val_slcr__DDR_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__DDR_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__IO_PLL_CTRL = 32'hF8000108; +parameter val_slcr__IO_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__IO_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__PLL_STATUS = 32'hF800010C; +parameter val_slcr__PLL_STATUS = 32'h0000003F; +parameter mask_slcr__PLL_STATUS = 32'hFFFFFFFF; + +parameter slcr__ARM_PLL_CFG = 32'hF8000110; +parameter val_slcr__ARM_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__ARM_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__DDR_PLL_CFG = 32'hF8000114; +parameter val_slcr__DDR_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__DDR_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__IO_PLL_CFG = 32'hF8000118; +parameter val_slcr__IO_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__IO_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__PLL_BG_CTRL = 32'hF800011C; +parameter val_slcr__PLL_BG_CTRL = 32'h00000000; +parameter mask_slcr__PLL_BG_CTRL = 32'hFFFFFFFF; + +parameter slcr__ARM_CLK_CTRL = 32'hF8000120; +parameter val_slcr__ARM_CLK_CTRL = 32'h1F000400; +parameter mask_slcr__ARM_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_CLK_CTRL = 32'hF8000124; +parameter val_slcr__DDR_CLK_CTRL = 32'h18400003; +parameter mask_slcr__DDR_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DCI_CLK_CTRL = 32'hF8000128; +parameter val_slcr__DCI_CLK_CTRL = 32'h01E03201; +parameter mask_slcr__DCI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__APER_CLK_CTRL = 32'hF800012C; +parameter val_slcr__APER_CLK_CTRL = 32'h01FFCCCD; +parameter mask_slcr__APER_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB0_CLK_CTRL = 32'hF8000130; +parameter val_slcr__USB0_CLK_CTRL = 32'h00101941; +parameter mask_slcr__USB0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB1_CLK_CTRL = 32'hF8000134; +parameter val_slcr__USB1_CLK_CTRL = 32'h00101941; +parameter mask_slcr__USB1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM0_RCLK_CTRL = 32'hF8000138; +parameter val_slcr__GEM0_RCLK_CTRL = 32'h00000001; +parameter mask_slcr__GEM0_RCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM1_RCLK_CTRL = 32'hF800013C; +parameter val_slcr__GEM1_RCLK_CTRL = 32'h00000001; +parameter mask_slcr__GEM1_RCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM0_CLK_CTRL = 32'hF8000140; +parameter val_slcr__GEM0_CLK_CTRL = 32'h00003C01; +parameter mask_slcr__GEM0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM1_CLK_CTRL = 32'hF8000144; +parameter val_slcr__GEM1_CLK_CTRL = 32'h00003C01; +parameter mask_slcr__GEM1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SMC_CLK_CTRL = 32'hF8000148; +parameter val_slcr__SMC_CLK_CTRL = 32'h00003C21; +parameter mask_slcr__SMC_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__LQSPI_CLK_CTRL = 32'hF800014C; +parameter val_slcr__LQSPI_CLK_CTRL = 32'h00002821; +parameter mask_slcr__LQSPI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SDIO_CLK_CTRL = 32'hF8000150; +parameter val_slcr__SDIO_CLK_CTRL = 32'h00001E03; +parameter mask_slcr__SDIO_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__UART_CLK_CTRL = 32'hF8000154; +parameter val_slcr__UART_CLK_CTRL = 32'h00003F03; +parameter mask_slcr__UART_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SPI_CLK_CTRL = 32'hF8000158; +parameter val_slcr__SPI_CLK_CTRL = 32'h00003F03; +parameter mask_slcr__SPI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_CLK_CTRL = 32'hF800015C; +parameter val_slcr__CAN_CLK_CTRL = 32'h00501903; +parameter mask_slcr__CAN_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_MIOCLK_CTRL = 32'hF8000160; +parameter val_slcr__CAN_MIOCLK_CTRL = 32'h00000000; +parameter mask_slcr__CAN_MIOCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DBG_CLK_CTRL = 32'hF8000164; +parameter val_slcr__DBG_CLK_CTRL = 32'h00000F03; +parameter mask_slcr__DBG_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__PCAP_CLK_CTRL = 32'hF8000168; +parameter val_slcr__PCAP_CLK_CTRL = 32'h00000F01; +parameter mask_slcr__PCAP_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__TOPSW_CLK_CTRL = 32'hF800016C; +parameter val_slcr__TOPSW_CLK_CTRL = 32'h00000000; +parameter mask_slcr__TOPSW_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_CLK_CTRL = 32'hF8000170; +parameter val_slcr__FPGA0_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_CTRL = 32'hF8000174; +parameter val_slcr__FPGA0_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA0_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_CNT = 32'hF8000178; +parameter val_slcr__FPGA0_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA0_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_STA = 32'hF800017C; +parameter val_slcr__FPGA0_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA0_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA1_CLK_CTRL = 32'hF8000180; +parameter val_slcr__FPGA1_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_CTRL = 32'hF8000184; +parameter val_slcr__FPGA1_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA1_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_CNT = 32'hF8000188; +parameter val_slcr__FPGA1_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA1_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_STA = 32'hF800018C; +parameter val_slcr__FPGA1_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA1_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA2_CLK_CTRL = 32'hF8000190; +parameter val_slcr__FPGA2_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA2_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_CTRL = 32'hF8000194; +parameter val_slcr__FPGA2_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA2_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_CNT = 32'hF8000198; +parameter val_slcr__FPGA2_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA2_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_STA = 32'hF800019C; +parameter val_slcr__FPGA2_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA2_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA3_CLK_CTRL = 32'hF80001A0; +parameter val_slcr__FPGA3_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA3_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_CTRL = 32'hF80001A4; +parameter val_slcr__FPGA3_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA3_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_CNT = 32'hF80001A8; +parameter val_slcr__FPGA3_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA3_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_STA = 32'hF80001AC; +parameter val_slcr__FPGA3_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA3_THR_STA = 32'hFFFFFFFF; + +parameter slcr__SRST_UART_CTRL = 32'hF80001B0; +parameter val_slcr__SRST_UART_CTRL = 32'h00000000; +parameter mask_slcr__SRST_UART_CTRL = 32'hFFFFFFFF; + +parameter slcr__BANDGAP_TRIM = 32'hF80001B8; +parameter val_slcr__BANDGAP_TRIM = 32'h0000001F; +parameter mask_slcr__BANDGAP_TRIM = 32'hFFFFFFFF; + +parameter slcr__CC_TEST = 32'hF80001BC; +parameter val_slcr__CC_TEST = 32'h00000000; +parameter mask_slcr__CC_TEST = 32'hFFFFFFFF; + +parameter slcr__PLL_PREDIVISOR = 32'hF80001C0; +parameter val_slcr__PLL_PREDIVISOR = 32'h00000001; +parameter mask_slcr__PLL_PREDIVISOR = 32'hFFFFFFFF; + +parameter slcr__CLK_621_TRUE = 32'hF80001C4; +parameter val_slcr__CLK_621_TRUE = 32'h00000001; +parameter mask_slcr__CLK_621_TRUE = 32'hFFFFFFC1; + +parameter slcr__PICTURE_DBG = 32'hF80001D0; +parameter val_slcr__PICTURE_DBG = 32'h00000000; +parameter mask_slcr__PICTURE_DBG = 32'hFFFFFFFF; + +parameter slcr__PICTURE_DBG_UCNT = 32'hF80001D4; +parameter val_slcr__PICTURE_DBG_UCNT = 32'h00000000; +parameter mask_slcr__PICTURE_DBG_UCNT = 32'hFFFFFFFF; + +parameter slcr__PICTURE_DBG_LCNT = 32'hF80001D8; +parameter val_slcr__PICTURE_DBG_LCNT = 32'h00000000; +parameter mask_slcr__PICTURE_DBG_LCNT = 32'hFFFFFFFF; + +parameter slcr__PSS_RST_CTRL = 32'hF8000200; +parameter val_slcr__PSS_RST_CTRL = 32'h00000000; +parameter mask_slcr__PSS_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_RST_CTRL = 32'hF8000204; +parameter val_slcr__DDR_RST_CTRL = 32'h00000000; +parameter mask_slcr__DDR_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__TOPSW_RST_CTRL = 32'hF8000208; +parameter val_slcr__TOPSW_RST_CTRL = 32'h00000000; +parameter mask_slcr__TOPSW_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DMAC_RST_CTRL = 32'hF800020C; +parameter val_slcr__DMAC_RST_CTRL = 32'h00000000; +parameter mask_slcr__DMAC_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB_RST_CTRL = 32'hF8000210; +parameter val_slcr__USB_RST_CTRL = 32'h00000000; +parameter mask_slcr__USB_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM_RST_CTRL = 32'hF8000214; +parameter val_slcr__GEM_RST_CTRL = 32'h00000000; +parameter mask_slcr__GEM_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SDIO_RST_CTRL = 32'hF8000218; +parameter val_slcr__SDIO_RST_CTRL = 32'h00000000; +parameter mask_slcr__SDIO_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SPI_RST_CTRL = 32'hF800021C; +parameter val_slcr__SPI_RST_CTRL = 32'h00000000; +parameter mask_slcr__SPI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_RST_CTRL = 32'hF8000220; +parameter val_slcr__CAN_RST_CTRL = 32'h00000000; +parameter mask_slcr__CAN_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__I2C_RST_CTRL = 32'hF8000224; +parameter val_slcr__I2C_RST_CTRL = 32'h00000000; +parameter mask_slcr__I2C_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__UART_RST_CTRL = 32'hF8000228; +parameter val_slcr__UART_RST_CTRL = 32'h00000000; +parameter mask_slcr__UART_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__GPIO_RST_CTRL = 32'hF800022C; +parameter val_slcr__GPIO_RST_CTRL = 32'h00000000; +parameter mask_slcr__GPIO_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__LQSPI_RST_CTRL = 32'hF8000230; +parameter val_slcr__LQSPI_RST_CTRL = 32'h00000000; +parameter mask_slcr__LQSPI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SMC_RST_CTRL = 32'hF8000234; +parameter val_slcr__SMC_RST_CTRL = 32'h00000000; +parameter mask_slcr__SMC_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__OCM_RST_CTRL = 32'hF8000238; +parameter val_slcr__OCM_RST_CTRL = 32'h00000000; +parameter mask_slcr__OCM_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DEVCI_RST_CTRL = 32'hF800023C; +parameter val_slcr__DEVCI_RST_CTRL = 32'h00000000; +parameter mask_slcr__DEVCI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA_RST_CTRL = 32'hF8000240; +parameter val_slcr__FPGA_RST_CTRL = 32'h01F33F0F; +parameter mask_slcr__FPGA_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__A9_CPU_RST_CTRL = 32'hF8000244; +parameter val_slcr__A9_CPU_RST_CTRL = 32'h00000000; +parameter mask_slcr__A9_CPU_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__RS_AWDT_CTRL = 32'hF800024C; +parameter val_slcr__RS_AWDT_CTRL = 32'h00000000; +parameter mask_slcr__RS_AWDT_CTRL = 32'hFFFFFFFF; + +parameter slcr__RST_REASON = 32'hF8000250; +parameter val_slcr__RST_REASON = 32'h00000040; +parameter mask_slcr__RST_REASON = 32'hFFFFFFFF; + +parameter slcr__RST_REASON_CLR = 32'hF8000254; +parameter val_slcr__RST_REASON_CLR = 32'h00000000; +parameter mask_slcr__RST_REASON_CLR = 32'hFFFFFFFF; + +parameter slcr__REBOOT_STATUS = 32'hF8000258; +parameter val_slcr__REBOOT_STATUS = 32'h00400000; +parameter mask_slcr__REBOOT_STATUS = 32'hFFFFFFFF; + +parameter slcr__BOOT_MODE = 32'hF800025C; +parameter val_slcr__BOOT_MODE = 32'h00000000; +parameter mask_slcr__BOOT_MODE = 32'hFFFFFFF0; + +parameter slcr__APU_CTRL = 32'hF8000300; +parameter val_slcr__APU_CTRL = 32'h00000000; +parameter mask_slcr__APU_CTRL = 32'hFFFFFFFF; + +parameter slcr__WDT_CLK_SEL = 32'hF8000304; +parameter val_slcr__WDT_CLK_SEL = 32'h00000000; +parameter mask_slcr__WDT_CLK_SEL = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_RAM0 = 32'hF8000400; +parameter val_slcr__TZ_OCM_RAM0 = 32'h00000000; +parameter mask_slcr__TZ_OCM_RAM0 = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_RAM1 = 32'hF8000404; +parameter val_slcr__TZ_OCM_RAM1 = 32'h00000000; +parameter mask_slcr__TZ_OCM_RAM1 = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_ROM = 32'hF8000408; +parameter val_slcr__TZ_OCM_ROM = 32'h00000000; +parameter mask_slcr__TZ_OCM_ROM = 32'hFFFFFFFF; + +parameter slcr__TZ_DDR_RAM = 32'hF8000430; +parameter val_slcr__TZ_DDR_RAM = 32'h00000000; +parameter mask_slcr__TZ_DDR_RAM = 32'h00000001; + +parameter slcr__TZ_DMA_NS = 32'hF8000440; +parameter val_slcr__TZ_DMA_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_DMA_IRQ_NS = 32'hF8000444; +parameter val_slcr__TZ_DMA_IRQ_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_IRQ_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_DMA_PERIPH_NS = 32'hF8000448; +parameter val_slcr__TZ_DMA_PERIPH_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_PERIPH_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_GEM = 32'hF8000450; +parameter val_slcr__TZ_GEM = 32'h00000000; +parameter mask_slcr__TZ_GEM = 32'hFFFFFFFF; + +parameter slcr__TZ_SDIO = 32'hF8000454; +parameter val_slcr__TZ_SDIO = 32'h00000000; +parameter mask_slcr__TZ_SDIO = 32'hFFFFFFFF; + +parameter slcr__TZ_USB = 32'hF8000458; +parameter val_slcr__TZ_USB = 32'h00000000; +parameter mask_slcr__TZ_USB = 32'hFFFFFFFF; + +parameter slcr__TZ_FPGA_M = 32'hF8000484; +parameter val_slcr__TZ_FPGA_M = 32'h00000000; +parameter mask_slcr__TZ_FPGA_M = 32'hFFFFFFFF; + +parameter slcr__TZ_FPGA_AFI = 32'hF8000488; +parameter val_slcr__TZ_FPGA_AFI = 32'h00000000; +parameter mask_slcr__TZ_FPGA_AFI = 32'hFFFFFFFF; + +parameter slcr__DBG_CTRL = 32'hF8000500; +parameter val_slcr__DBG_CTRL = 32'h00000000; +parameter mask_slcr__DBG_CTRL = 32'hFFFFFFFF; + +parameter slcr__PSS_IDCODE = 32'hF8000530; +parameter val_slcr__PSS_IDCODE = 32'h03720093; +parameter mask_slcr__PSS_IDCODE = 32'h0FFE0FFF; + +parameter slcr__DDR_URGENT = 32'hF8000600; +parameter val_slcr__DDR_URGENT = 32'h00000000; +parameter mask_slcr__DDR_URGENT = 32'hFFFFFFFF; + +parameter slcr__DDR_CAL_START = 32'hF800060C; +parameter val_slcr__DDR_CAL_START = 32'h00000000; +parameter mask_slcr__DDR_CAL_START = 32'hFFFFFFFF; + +parameter slcr__DDR_REF_START = 32'hF8000614; +parameter val_slcr__DDR_REF_START = 32'h00000000; +parameter mask_slcr__DDR_REF_START = 32'hFFFFFFFF; + +parameter slcr__DDR_CMD_STA = 32'hF8000618; +parameter val_slcr__DDR_CMD_STA = 32'h00000000; +parameter mask_slcr__DDR_CMD_STA = 32'hFFFFFFFF; + +parameter slcr__DDR_URGENT_SEL = 32'hF800061C; +parameter val_slcr__DDR_URGENT_SEL = 32'h00000000; +parameter mask_slcr__DDR_URGENT_SEL = 32'hFFFFFFFF; + +parameter slcr__DDR_DFI_STATUS = 32'hF8000620; +parameter val_slcr__DDR_DFI_STATUS = 32'h00000000; +parameter mask_slcr__DDR_DFI_STATUS = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_00 = 32'hF8000700; +parameter val_slcr__MIO_PIN_00 = 32'h00001601; +parameter mask_slcr__MIO_PIN_00 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_01 = 32'hF8000704; +parameter val_slcr__MIO_PIN_01 = 32'h00001601; +parameter mask_slcr__MIO_PIN_01 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_02 = 32'hF8000708; +parameter val_slcr__MIO_PIN_02 = 32'h00000601; +parameter mask_slcr__MIO_PIN_02 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_03 = 32'hF800070C; +parameter val_slcr__MIO_PIN_03 = 32'h00000601; +parameter mask_slcr__MIO_PIN_03 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_04 = 32'hF8000710; +parameter val_slcr__MIO_PIN_04 = 32'h00000601; +parameter mask_slcr__MIO_PIN_04 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_05 = 32'hF8000714; +parameter val_slcr__MIO_PIN_05 = 32'h00000601; +parameter mask_slcr__MIO_PIN_05 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_06 = 32'hF8000718; +parameter val_slcr__MIO_PIN_06 = 32'h00000601; +parameter mask_slcr__MIO_PIN_06 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_07 = 32'hF800071C; +parameter val_slcr__MIO_PIN_07 = 32'h00000601; +parameter mask_slcr__MIO_PIN_07 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_08 = 32'hF8000720; +parameter val_slcr__MIO_PIN_08 = 32'h00000601; +parameter mask_slcr__MIO_PIN_08 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_09 = 32'hF8000724; +parameter val_slcr__MIO_PIN_09 = 32'h00001601; +parameter mask_slcr__MIO_PIN_09 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_10 = 32'hF8000728; +parameter val_slcr__MIO_PIN_10 = 32'h00001601; +parameter mask_slcr__MIO_PIN_10 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_11 = 32'hF800072C; +parameter val_slcr__MIO_PIN_11 = 32'h00001601; +parameter mask_slcr__MIO_PIN_11 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_12 = 32'hF8000730; +parameter val_slcr__MIO_PIN_12 = 32'h00001601; +parameter mask_slcr__MIO_PIN_12 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_13 = 32'hF8000734; +parameter val_slcr__MIO_PIN_13 = 32'h00001601; +parameter mask_slcr__MIO_PIN_13 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_14 = 32'hF8000738; +parameter val_slcr__MIO_PIN_14 = 32'h00001601; +parameter mask_slcr__MIO_PIN_14 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_15 = 32'hF800073C; +parameter val_slcr__MIO_PIN_15 = 32'h00001601; +parameter mask_slcr__MIO_PIN_15 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_16 = 32'hF8000740; +parameter val_slcr__MIO_PIN_16 = 32'h00001601; +parameter mask_slcr__MIO_PIN_16 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_17 = 32'hF8000744; +parameter val_slcr__MIO_PIN_17 = 32'h00001601; +parameter mask_slcr__MIO_PIN_17 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_18 = 32'hF8000748; +parameter val_slcr__MIO_PIN_18 = 32'h00001601; +parameter mask_slcr__MIO_PIN_18 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_19 = 32'hF800074C; +parameter val_slcr__MIO_PIN_19 = 32'h00001601; +parameter mask_slcr__MIO_PIN_19 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_20 = 32'hF8000750; +parameter val_slcr__MIO_PIN_20 = 32'h00001601; +parameter mask_slcr__MIO_PIN_20 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_21 = 32'hF8000754; +parameter val_slcr__MIO_PIN_21 = 32'h00001601; +parameter mask_slcr__MIO_PIN_21 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_22 = 32'hF8000758; +parameter val_slcr__MIO_PIN_22 = 32'h00001601; +parameter mask_slcr__MIO_PIN_22 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_23 = 32'hF800075C; +parameter val_slcr__MIO_PIN_23 = 32'h00001601; +parameter mask_slcr__MIO_PIN_23 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_24 = 32'hF8000760; +parameter val_slcr__MIO_PIN_24 = 32'h00001601; +parameter mask_slcr__MIO_PIN_24 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_25 = 32'hF8000764; +parameter val_slcr__MIO_PIN_25 = 32'h00001601; +parameter mask_slcr__MIO_PIN_25 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_26 = 32'hF8000768; +parameter val_slcr__MIO_PIN_26 = 32'h00001601; +parameter mask_slcr__MIO_PIN_26 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_27 = 32'hF800076C; +parameter val_slcr__MIO_PIN_27 = 32'h00001601; +parameter mask_slcr__MIO_PIN_27 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_28 = 32'hF8000770; +parameter val_slcr__MIO_PIN_28 = 32'h00001601; +parameter mask_slcr__MIO_PIN_28 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_29 = 32'hF8000774; +parameter val_slcr__MIO_PIN_29 = 32'h00001601; +parameter mask_slcr__MIO_PIN_29 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_30 = 32'hF8000778; +parameter val_slcr__MIO_PIN_30 = 32'h00001601; +parameter mask_slcr__MIO_PIN_30 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_31 = 32'hF800077C; +parameter val_slcr__MIO_PIN_31 = 32'h00001601; +parameter mask_slcr__MIO_PIN_31 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_32 = 32'hF8000780; +parameter val_slcr__MIO_PIN_32 = 32'h00001601; +parameter mask_slcr__MIO_PIN_32 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_33 = 32'hF8000784; +parameter val_slcr__MIO_PIN_33 = 32'h00001601; +parameter mask_slcr__MIO_PIN_33 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_34 = 32'hF8000788; +parameter val_slcr__MIO_PIN_34 = 32'h00001601; +parameter mask_slcr__MIO_PIN_34 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_35 = 32'hF800078C; +parameter val_slcr__MIO_PIN_35 = 32'h00001601; +parameter mask_slcr__MIO_PIN_35 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_36 = 32'hF8000790; +parameter val_slcr__MIO_PIN_36 = 32'h00001601; +parameter mask_slcr__MIO_PIN_36 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_37 = 32'hF8000794; +parameter val_slcr__MIO_PIN_37 = 32'h00001601; +parameter mask_slcr__MIO_PIN_37 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_38 = 32'hF8000798; +parameter val_slcr__MIO_PIN_38 = 32'h00001601; +parameter mask_slcr__MIO_PIN_38 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_39 = 32'hF800079C; +parameter val_slcr__MIO_PIN_39 = 32'h00001601; +parameter mask_slcr__MIO_PIN_39 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_40 = 32'hF80007A0; +parameter val_slcr__MIO_PIN_40 = 32'h00001601; +parameter mask_slcr__MIO_PIN_40 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_41 = 32'hF80007A4; +parameter val_slcr__MIO_PIN_41 = 32'h00001601; +parameter mask_slcr__MIO_PIN_41 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_42 = 32'hF80007A8; +parameter val_slcr__MIO_PIN_42 = 32'h00001601; +parameter mask_slcr__MIO_PIN_42 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_43 = 32'hF80007AC; +parameter val_slcr__MIO_PIN_43 = 32'h00001601; +parameter mask_slcr__MIO_PIN_43 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_44 = 32'hF80007B0; +parameter val_slcr__MIO_PIN_44 = 32'h00001601; +parameter mask_slcr__MIO_PIN_44 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_45 = 32'hF80007B4; +parameter val_slcr__MIO_PIN_45 = 32'h00001601; +parameter mask_slcr__MIO_PIN_45 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_46 = 32'hF80007B8; +parameter val_slcr__MIO_PIN_46 = 32'h00001601; +parameter mask_slcr__MIO_PIN_46 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_47 = 32'hF80007BC; +parameter val_slcr__MIO_PIN_47 = 32'h00001601; +parameter mask_slcr__MIO_PIN_47 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_48 = 32'hF80007C0; +parameter val_slcr__MIO_PIN_48 = 32'h00001601; +parameter mask_slcr__MIO_PIN_48 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_49 = 32'hF80007C4; +parameter val_slcr__MIO_PIN_49 = 32'h00001601; +parameter mask_slcr__MIO_PIN_49 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_50 = 32'hF80007C8; +parameter val_slcr__MIO_PIN_50 = 32'h00001601; +parameter mask_slcr__MIO_PIN_50 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_51 = 32'hF80007CC; +parameter val_slcr__MIO_PIN_51 = 32'h00001601; +parameter mask_slcr__MIO_PIN_51 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_52 = 32'hF80007D0; +parameter val_slcr__MIO_PIN_52 = 32'h00001601; +parameter mask_slcr__MIO_PIN_52 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_53 = 32'hF80007D4; +parameter val_slcr__MIO_PIN_53 = 32'h00001601; +parameter mask_slcr__MIO_PIN_53 = 32'hFFFFFFFF; + +parameter slcr__MIO_FMIO_GEM_SEL = 32'hF8000800; +parameter val_slcr__MIO_FMIO_GEM_SEL = 32'h00000000; +parameter mask_slcr__MIO_FMIO_GEM_SEL = 32'hFFFFFFFF; + +parameter slcr__MIO_LOOPBACK = 32'hF8000804; +parameter val_slcr__MIO_LOOPBACK = 32'h00000000; +parameter mask_slcr__MIO_LOOPBACK = 32'hFFFFFFFF; + +parameter slcr__MIO_MST_TRI0 = 32'hF800080C; +parameter val_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF; +parameter mask_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF; + +parameter slcr__MIO_MST_TRI1 = 32'hF8000810; +parameter val_slcr__MIO_MST_TRI1 = 32'h003FFFFF; +parameter mask_slcr__MIO_MST_TRI1 = 32'hFFFFFFFF; + +parameter slcr__SD0_WP_CD_SEL = 32'hF8000830; +parameter val_slcr__SD0_WP_CD_SEL = 32'h00000000; +parameter mask_slcr__SD0_WP_CD_SEL = 32'hFFFFFFFF; + +parameter slcr__SD1_WP_CD_SEL = 32'hF8000834; +parameter val_slcr__SD1_WP_CD_SEL = 32'h00000000; +parameter mask_slcr__SD1_WP_CD_SEL = 32'hFFFFFFFF; + +parameter slcr__LVL_SHFTR_EN = 32'hF8000900; +parameter val_slcr__LVL_SHFTR_EN = 32'h00000000; +parameter mask_slcr__LVL_SHFTR_EN = 32'hFFFFFFFF; + +parameter slcr__OCM_CFG = 32'hF8000910; +parameter val_slcr__OCM_CFG = 32'h00000000; +parameter mask_slcr__OCM_CFG = 32'hFFFFFFFF; + +parameter slcr__CPU0_RAM0 = 32'hF8000A00; +parameter val_slcr__CPU0_RAM0 = 32'h00020202; +parameter mask_slcr__CPU0_RAM0 = 32'h00FFFFFF; + +parameter slcr__CPU0_RAM1 = 32'hF8000A04; +parameter val_slcr__CPU0_RAM1 = 32'h00020202; +parameter mask_slcr__CPU0_RAM1 = 32'h00FFFFFF; + +parameter slcr__CPU0_RAM2 = 32'hF8000A08; +parameter val_slcr__CPU0_RAM2 = 32'h02020202; +parameter mask_slcr__CPU0_RAM2 = 32'hFFFFFFFF; + +parameter slcr__CPU1_RAM0 = 32'hF8000A0C; +parameter val_slcr__CPU1_RAM0 = 32'h00020202; +parameter mask_slcr__CPU1_RAM0 = 32'h00FFFFFF; + +parameter slcr__CPU1_RAM1 = 32'hF8000A10; +parameter val_slcr__CPU1_RAM1 = 32'h00020202; +parameter mask_slcr__CPU1_RAM1 = 32'h00FFFFFF; + +parameter slcr__CPU1_RAM2 = 32'hF8000A14; +parameter val_slcr__CPU1_RAM2 = 32'h02020202; +parameter mask_slcr__CPU1_RAM2 = 32'hFFFFFFFF; + +parameter slcr__SCU_RAM = 32'hF8000A18; +parameter val_slcr__SCU_RAM = 32'h00000002; +parameter mask_slcr__SCU_RAM = 32'h000000FF; + +parameter slcr__L2C_RAM = 32'hF8000A1C; +parameter val_slcr__L2C_RAM = 32'h00020202; +parameter mask_slcr__L2C_RAM = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_GEM01 = 32'hF8000A30; +parameter val_slcr__IOU_RAM_GEM01 = 32'h09090909; +parameter mask_slcr__IOU_RAM_GEM01 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_USB01 = 32'hF8000A34; +parameter val_slcr__IOU_RAM_USB01 = 32'h09090909; +parameter mask_slcr__IOU_RAM_USB01 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_SDIO0 = 32'hF8000A38; +parameter val_slcr__IOU_RAM_SDIO0 = 32'h09090909; +parameter mask_slcr__IOU_RAM_SDIO0 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_SDIO1 = 32'hF8000A3C; +parameter val_slcr__IOU_RAM_SDIO1 = 32'h09090909; +parameter mask_slcr__IOU_RAM_SDIO1 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_CAN0 = 32'hF8000A40; +parameter val_slcr__IOU_RAM_CAN0 = 32'h00090909; +parameter mask_slcr__IOU_RAM_CAN0 = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_CAN1 = 32'hF8000A44; +parameter val_slcr__IOU_RAM_CAN1 = 32'h00090909; +parameter mask_slcr__IOU_RAM_CAN1 = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_LQSPI = 32'hF8000A48; +parameter val_slcr__IOU_RAM_LQSPI = 32'h00000909; +parameter mask_slcr__IOU_RAM_LQSPI = 32'h0000FFFF; + +parameter slcr__DMAC_RAM = 32'hF8000A50; +parameter val_slcr__DMAC_RAM = 32'h00000009; +parameter mask_slcr__DMAC_RAM = 32'h000000FF; + +parameter slcr__AFI0_RAM0 = 32'hF8000A60; +parameter val_slcr__AFI0_RAM0 = 32'h09090909; +parameter mask_slcr__AFI0_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI0_RAM1 = 32'hF8000A64; +parameter val_slcr__AFI0_RAM1 = 32'h09090909; +parameter mask_slcr__AFI0_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI0_RAM2 = 32'hF8000A68; +parameter val_slcr__AFI0_RAM2 = 32'h00000909; +parameter mask_slcr__AFI0_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI1_RAM0 = 32'hF8000A6C; +parameter val_slcr__AFI1_RAM0 = 32'h09090909; +parameter mask_slcr__AFI1_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI1_RAM1 = 32'hF8000A70; +parameter val_slcr__AFI1_RAM1 = 32'h09090909; +parameter mask_slcr__AFI1_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI1_RAM2 = 32'hF8000A74; +parameter val_slcr__AFI1_RAM2 = 32'h00000909; +parameter mask_slcr__AFI1_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI2_RAM0 = 32'hF8000A78; +parameter val_slcr__AFI2_RAM0 = 32'h09090909; +parameter mask_slcr__AFI2_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI2_RAM1 = 32'hF8000A7C; +parameter val_slcr__AFI2_RAM1 = 32'h09090909; +parameter mask_slcr__AFI2_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI2_RAM2 = 32'hF8000A80; +parameter val_slcr__AFI2_RAM2 = 32'h00000909; +parameter mask_slcr__AFI2_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI3_RAM0 = 32'hF8000A84; +parameter val_slcr__AFI3_RAM0 = 32'h09090909; +parameter mask_slcr__AFI3_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI3_RAM1 = 32'hF8000A88; +parameter val_slcr__AFI3_RAM1 = 32'h09090909; +parameter mask_slcr__AFI3_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI3_RAM2 = 32'hF8000A8C; +parameter val_slcr__AFI3_RAM2 = 32'h00000909; +parameter mask_slcr__AFI3_RAM2 = 32'h0000FFFF; + +parameter slcr__OCM_RAM = 32'hF8000A90; +parameter val_slcr__OCM_RAM = 32'h01010101; +parameter mask_slcr__OCM_RAM = 32'hFFFFFFFF; + +parameter slcr__OCM_ROM0 = 32'hF8000A94; +parameter val_slcr__OCM_ROM0 = 32'h09090909; +parameter mask_slcr__OCM_ROM0 = 32'hFFFFFFFF; + +parameter slcr__OCM_ROM1 = 32'hF8000A98; +parameter val_slcr__OCM_ROM1 = 32'h09090909; +parameter mask_slcr__OCM_ROM1 = 32'hFFFFFFFF; + +parameter slcr__DEVCI_RAM = 32'hF8000AA0; +parameter val_slcr__DEVCI_RAM = 32'h00000909; +parameter mask_slcr__DEVCI_RAM = 32'h0000FFFF; + +parameter slcr__CSG_RAM = 32'hF8000AB0; +parameter val_slcr__CSG_RAM = 32'h00000001; +parameter mask_slcr__CSG_RAM = 32'h000000FF; + +parameter slcr__GPIOB_CTRL = 32'hF8000B00; +parameter val_slcr__GPIOB_CTRL = 32'h00000000; +parameter mask_slcr__GPIOB_CTRL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS18 = 32'hF8000B04; +parameter val_slcr__GPIOB_CFG_CMOS18 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS18 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS25 = 32'hF8000B08; +parameter val_slcr__GPIOB_CFG_CMOS25 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS25 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS33 = 32'hF8000B0C; +parameter val_slcr__GPIOB_CFG_CMOS33 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS33 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_LVTTL = 32'hF8000B10; +parameter val_slcr__GPIOB_CFG_LVTTL = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_LVTTL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_HSTL = 32'hF8000B14; +parameter val_slcr__GPIOB_CFG_HSTL = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_HSTL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_DRVR_BIAS_CTRL = 32'hF8000B18; +parameter val_slcr__GPIOB_DRVR_BIAS_CTRL = 32'h00000000; +parameter mask_slcr__GPIOB_DRVR_BIAS_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_ADDR0 = 32'hF8000B40; +parameter val_slcr__DDRIOB_ADDR0 = 32'h00000800; +parameter mask_slcr__DDRIOB_ADDR0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_ADDR1 = 32'hF8000B44; +parameter val_slcr__DDRIOB_ADDR1 = 32'h00000800; +parameter mask_slcr__DDRIOB_ADDR1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DATA0 = 32'hF8000B48; +parameter val_slcr__DDRIOB_DATA0 = 32'h00000800; +parameter mask_slcr__DDRIOB_DATA0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DATA1 = 32'hF8000B4C; +parameter val_slcr__DDRIOB_DATA1 = 32'h00000800; +parameter mask_slcr__DDRIOB_DATA1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DIFF0 = 32'hF8000B50; +parameter val_slcr__DDRIOB_DIFF0 = 32'h00000800; +parameter mask_slcr__DDRIOB_DIFF0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DIFF1 = 32'hF8000B54; +parameter val_slcr__DDRIOB_DIFF1 = 32'h00000800; +parameter mask_slcr__DDRIOB_DIFF1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_CLOCK = 32'hF8000B58; +parameter val_slcr__DDRIOB_CLOCK = 32'h00000800; +parameter mask_slcr__DDRIOB_CLOCK = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hF8000B5C; +parameter val_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hF8000B60; +parameter val_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hF8000B64; +parameter val_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hF8000B68; +parameter val_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DDR_CTRL = 32'hF8000B6C; +parameter val_slcr__DDRIOB_DDR_CTRL = 32'h00000000; +parameter mask_slcr__DDRIOB_DDR_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DCI_CTRL = 32'hF8000B70; +parameter val_slcr__DDRIOB_DCI_CTRL = 32'h00000020; +parameter mask_slcr__DDRIOB_DCI_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DCI_STATUS = 32'hF8000B74; +parameter val_slcr__DDRIOB_DCI_STATUS = 32'h00000000; +parameter mask_slcr__DDRIOB_DCI_STATUS = 32'hFFFFFFFF; + + +// ************************************************************ +// Module smcc pl353 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter smcc__memc_status = 32'hE000E000; +parameter val_smcc__memc_status = 32'h00000000; +parameter mask_smcc__memc_status = 32'h00001FFF; + +parameter smcc__memif_cfg = 32'hE000E004; +parameter val_smcc__memif_cfg = 32'h00011205; +parameter mask_smcc__memif_cfg = 32'h0003FFFF; + +parameter smcc__memc_cfg_set = 32'hE000E008; +parameter val_smcc__memc_cfg_set = 32'h00000000; +parameter mask_smcc__memc_cfg_set = 32'h00000000; + +parameter smcc__memc_cfg_clr = 32'hE000E00C; +parameter val_smcc__memc_cfg_clr = 32'h00000000; +parameter mask_smcc__memc_cfg_clr = 32'h00000000; + +parameter smcc__direct_cmd = 32'hE000E010; +parameter val_smcc__direct_cmd = 32'h00000000; +parameter mask_smcc__direct_cmd = 32'h00000000; + +parameter smcc__set_cycles = 32'hE000E014; +parameter val_smcc__set_cycles = 32'h00000000; +parameter mask_smcc__set_cycles = 32'h00000000; + +parameter smcc__set_opmode = 32'hE000E018; +parameter val_smcc__set_opmode = 32'h00000000; +parameter mask_smcc__set_opmode = 32'h00000000; + +parameter smcc__refresh_period_0 = 32'hE000E020; +parameter val_smcc__refresh_period_0 = 32'h00000000; +parameter mask_smcc__refresh_period_0 = 32'h0000000F; + +parameter smcc__refresh_period_1 = 32'hE000E024; +parameter val_smcc__refresh_period_1 = 32'h00000000; +parameter mask_smcc__refresh_period_1 = 32'h0000000F; + +parameter smcc__sram_cycles0_0 = 32'hE000E100; +parameter val_smcc__sram_cycles0_0 = 32'h0002B3CC; +parameter mask_smcc__sram_cycles0_0 = 32'h001FFFFF; + +parameter smcc__opmode0_0 = 32'hE000E104; +parameter val_smcc__opmode0_0 = 32'hE2FE0800; +parameter mask_smcc__opmode0_0 = 32'hFFFFFFFF; + +parameter smcc__sram_cycles0_1 = 32'hE000E120; +parameter val_smcc__sram_cycles0_1 = 32'h0002B3CC; +parameter mask_smcc__sram_cycles0_1 = 32'h001FFFFF; + +parameter smcc__opmode0_1 = 32'hE000E124; +parameter val_smcc__opmode0_1 = 32'hE4FE0800; +parameter mask_smcc__opmode0_1 = 32'hFFFFFFFF; + +parameter smcc__nand_cycles1_0 = 32'hE000E180; +parameter val_smcc__nand_cycles1_0 = 32'h0024ABCC; +parameter mask_smcc__nand_cycles1_0 = 32'h00FFFFFF; + +parameter smcc__opmode1_0 = 32'hE000E184; +parameter val_smcc__opmode1_0 = 32'hE1FF0001; +parameter mask_smcc__opmode1_0 = 32'hFFFFFFFF; + +parameter smcc__user_status = 32'hE000E200; +parameter val_smcc__user_status = 32'h00000000; +parameter mask_smcc__user_status = 32'h000000FF; + +parameter smcc__user_config = 32'hE000E204; +parameter val_smcc__user_config = 32'h00000000; +parameter mask_smcc__user_config = 32'h00000000; + +parameter smcc__ecc_status_0 = 32'hE000E300; +parameter val_smcc__ecc_status_0 = 32'h00000000; +parameter mask_smcc__ecc_status_0 = 32'h3FFFFFFF; + +parameter smcc__ecc_memcfg_0 = 32'hE000E304; +parameter val_smcc__ecc_memcfg_0 = 32'h00000000; +parameter mask_smcc__ecc_memcfg_0 = 32'h00001FFF; + +parameter smcc__ecc_memcommand1_0 = 32'hE000E308; +parameter val_smcc__ecc_memcommand1_0 = 32'h00000000; +parameter mask_smcc__ecc_memcommand1_0 = 32'h01FFFFFF; + +parameter smcc__ecc_memcommand2_0 = 32'hE000E30C; +parameter val_smcc__ecc_memcommand2_0 = 32'h00000000; +parameter mask_smcc__ecc_memcommand2_0 = 32'h01FFFFFF; + +parameter smcc__ecc_addr0_0 = 32'hE000E310; +parameter val_smcc__ecc_addr0_0 = 32'h00000000; +parameter mask_smcc__ecc_addr0_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_addr1_0 = 32'hE000E314; +parameter val_smcc__ecc_addr1_0 = 32'h00000000; +parameter mask_smcc__ecc_addr1_0 = 32'h00FFFFFF; + +parameter smcc__ecc_value0_0 = 32'hE000E318; +parameter val_smcc__ecc_value0_0 = 32'h00000000; +parameter mask_smcc__ecc_value0_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value1_0 = 32'hE000E31C; +parameter val_smcc__ecc_value1_0 = 32'h00000000; +parameter mask_smcc__ecc_value1_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value2_0 = 32'hE000E320; +parameter val_smcc__ecc_value2_0 = 32'h00000000; +parameter mask_smcc__ecc_value2_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value3_0 = 32'hE000E324; +parameter val_smcc__ecc_value3_0 = 32'h00000000; +parameter mask_smcc__ecc_value3_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_status_1 = 32'hE000E400; +parameter val_smcc__ecc_status_1 = 32'h00000000; +parameter mask_smcc__ecc_status_1 = 32'h3FFFFFFF; + +parameter smcc__ecc_memcfg_1 = 32'hE000E404; +parameter val_smcc__ecc_memcfg_1 = 32'h00000043; +parameter mask_smcc__ecc_memcfg_1 = 32'h00001FFF; + +parameter smcc__ecc_memcommand1_1 = 32'hE000E408; +parameter val_smcc__ecc_memcommand1_1 = 32'h01300080; +parameter mask_smcc__ecc_memcommand1_1 = 32'h01FFFFFF; + +parameter smcc__ecc_memcommand2_1 = 32'hE000E40C; +parameter val_smcc__ecc_memcommand2_1 = 32'h01E00585; +parameter mask_smcc__ecc_memcommand2_1 = 32'h01FFFFFF; + +parameter smcc__ecc_addr0_1 = 32'hE000E410; +parameter val_smcc__ecc_addr0_1 = 32'h00000000; +parameter mask_smcc__ecc_addr0_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_addr1_1 = 32'hE000E414; +parameter val_smcc__ecc_addr1_1 = 32'h00000000; +parameter mask_smcc__ecc_addr1_1 = 32'h00FFFFFF; + +parameter smcc__ecc_value0_1 = 32'hE000E418; +parameter val_smcc__ecc_value0_1 = 32'h00000000; +parameter mask_smcc__ecc_value0_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value1_1 = 32'hE000E41C; +parameter val_smcc__ecc_value1_1 = 32'h00000000; +parameter mask_smcc__ecc_value1_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value2_1 = 32'hE000E420; +parameter val_smcc__ecc_value2_1 = 32'h00000000; +parameter mask_smcc__ecc_value2_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value3_1 = 32'hE000E424; +parameter val_smcc__ecc_value3_1 = 32'h00000000; +parameter mask_smcc__ecc_value3_1 = 32'hFFFFFFFF; + +parameter smcc__integration_test = 32'hE000EE00; +parameter val_smcc__integration_test = 32'h00000000; +parameter mask_smcc__integration_test = 32'hFFFFFFFF; + +parameter smcc__periph_id_0 = 32'hE000EFE0; +parameter val_smcc__periph_id_0 = 32'h00000053; +parameter mask_smcc__periph_id_0 = 32'h000000FF; + +parameter smcc__periph_id_1 = 32'hE000EFE4; +parameter val_smcc__periph_id_1 = 32'h00000013; +parameter mask_smcc__periph_id_1 = 32'h000000FF; + +parameter smcc__periph_id_2 = 32'hE000EFE8; +parameter val_smcc__periph_id_2 = 32'h00000054; +parameter mask_smcc__periph_id_2 = 32'h000000FF; + +parameter smcc__periph_id_3 = 32'hE000EFEC; +parameter val_smcc__periph_id_3 = 32'h00000000; +parameter mask_smcc__periph_id_3 = 32'h00000001; + +parameter smcc__pcell_id_0 = 32'hE000EFF0; +parameter val_smcc__pcell_id_0 = 32'h0000000D; +parameter mask_smcc__pcell_id_0 = 32'h000000FF; + +parameter smcc__pcell_id_1 = 32'hE000EFF4; +parameter val_smcc__pcell_id_1 = 32'h000000F0; +parameter mask_smcc__pcell_id_1 = 32'h000000FF; + +parameter smcc__pcell_id_2 = 32'hE000EFF8; +parameter val_smcc__pcell_id_2 = 32'h00000005; +parameter mask_smcc__pcell_id_2 = 32'h000000FF; + +parameter smcc__pcell_id_3 = 32'hE000EFFC; +parameter val_smcc__pcell_id_3 = 32'h000000B1; +parameter mask_smcc__pcell_id_3 = 32'h000000FF; + + +// ************************************************************ +// Module spi0 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter spi0__Config_reg0 = 32'hE0006000; +parameter val_spi0__Config_reg0 = 32'h00020000; +parameter mask_spi0__Config_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intr_status_reg0 = 32'hE0006004; +parameter val_spi0__Intr_status_reg0 = 32'h00000004; +parameter mask_spi0__Intr_status_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_en_reg0 = 32'hE0006008; +parameter val_spi0__Intrpt_en_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_dis_reg0 = 32'hE000600C; +parameter val_spi0__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_mask_reg0 = 32'hE0006010; +parameter val_spi0__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter spi0__En_reg0 = 32'hE0006014; +parameter val_spi0__En_reg0 = 32'h00000000; +parameter mask_spi0__En_reg0 = 32'hFFFFFFFF; + +parameter spi0__Delay_reg0 = 32'hE0006018; +parameter val_spi0__Delay_reg0 = 32'h00000000; +parameter mask_spi0__Delay_reg0 = 32'hFFFFFFFF; + +parameter spi0__Tx_data_reg0 = 32'hE000601C; +parameter val_spi0__Tx_data_reg0 = 32'h00000000; +parameter mask_spi0__Tx_data_reg0 = 32'hFFFFFFFF; + +parameter spi0__Rx_data_reg0 = 32'hE0006020; +parameter val_spi0__Rx_data_reg0 = 32'h00000000; +parameter mask_spi0__Rx_data_reg0 = 32'hFFFFFFFF; + +parameter spi0__Slave_Idle_count_reg0 = 32'hE0006024; +parameter val_spi0__Slave_Idle_count_reg0 = 32'h000000FF; +parameter mask_spi0__Slave_Idle_count_reg0 = 32'hFFFFFFFF; + +parameter spi0__TX_thres_reg0 = 32'hE0006028; +parameter val_spi0__TX_thres_reg0 = 32'h00000001; +parameter mask_spi0__TX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi0__RX_thres_reg0 = 32'hE000602C; +parameter val_spi0__RX_thres_reg0 = 32'h00000001; +parameter mask_spi0__RX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi0__Mod_id_reg0 = 32'hE00060FC; +parameter val_spi0__Mod_id_reg0 = 32'h00090106; +parameter mask_spi0__Mod_id_reg0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module spi1 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter spi1__Config_reg0 = 32'hE0007000; +parameter val_spi1__Config_reg0 = 32'h00020000; +parameter mask_spi1__Config_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intr_status_reg0 = 32'hE0007004; +parameter val_spi1__Intr_status_reg0 = 32'h00000004; +parameter mask_spi1__Intr_status_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_en_reg0 = 32'hE0007008; +parameter val_spi1__Intrpt_en_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_dis_reg0 = 32'hE000700C; +parameter val_spi1__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_mask_reg0 = 32'hE0007010; +parameter val_spi1__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter spi1__En_reg0 = 32'hE0007014; +parameter val_spi1__En_reg0 = 32'h00000000; +parameter mask_spi1__En_reg0 = 32'hFFFFFFFF; + +parameter spi1__Delay_reg0 = 32'hE0007018; +parameter val_spi1__Delay_reg0 = 32'h00000000; +parameter mask_spi1__Delay_reg0 = 32'hFFFFFFFF; + +parameter spi1__Tx_data_reg0 = 32'hE000701C; +parameter val_spi1__Tx_data_reg0 = 32'h00000000; +parameter mask_spi1__Tx_data_reg0 = 32'hFFFFFFFF; + +parameter spi1__Rx_data_reg0 = 32'hE0007020; +parameter val_spi1__Rx_data_reg0 = 32'h00000000; +parameter mask_spi1__Rx_data_reg0 = 32'hFFFFFFFF; + +parameter spi1__Slave_Idle_count_reg0 = 32'hE0007024; +parameter val_spi1__Slave_Idle_count_reg0 = 32'h000000FF; +parameter mask_spi1__Slave_Idle_count_reg0 = 32'hFFFFFFFF; + +parameter spi1__TX_thres_reg0 = 32'hE0007028; +parameter val_spi1__TX_thres_reg0 = 32'h00000001; +parameter mask_spi1__TX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi1__RX_thres_reg0 = 32'hE000702C; +parameter val_spi1__RX_thres_reg0 = 32'h00000001; +parameter mask_spi1__RX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi1__Mod_id_reg0 = 32'hE00070FC; +parameter val_spi1__Mod_id_reg0 = 32'h00090106; +parameter mask_spi1__Mod_id_reg0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module swdt swdt +// doc version: 2.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter swdt__MODE = 32'hF8005000; +parameter val_swdt__MODE = 32'h000001C2; +parameter mask_swdt__MODE = 32'h00FFFFFF; + +parameter swdt__CONTROL = 32'hF8005004; +parameter val_swdt__CONTROL = 32'h03FFC3FC; +parameter mask_swdt__CONTROL = 32'h03FFFFFF; + +parameter swdt__RESTART = 32'hF8005008; +parameter val_swdt__RESTART = 32'h00000000; +parameter mask_swdt__RESTART = 32'h0000FFFF; + +parameter swdt__STATUS = 32'hF800500C; +parameter val_swdt__STATUS = 32'h00000000; +parameter mask_swdt__STATUS = 32'h00000001; + + +// ************************************************************ +// Module ttc0 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ttc0__Clock_Control_1 = 32'hF8001000; +parameter val_ttc0__Clock_Control_1 = 32'h00000000; +parameter mask_ttc0__Clock_Control_1 = 32'h0000007F; + +parameter ttc0__Clock_Control_2 = 32'hF8001004; +parameter val_ttc0__Clock_Control_2 = 32'h00000000; +parameter mask_ttc0__Clock_Control_2 = 32'h0000007F; + +parameter ttc0__Clock_Control_3 = 32'hF8001008; +parameter val_ttc0__Clock_Control_3 = 32'h00000000; +parameter mask_ttc0__Clock_Control_3 = 32'h0000007F; + +parameter ttc0__Counter_Control_1 = 32'hF800100C; +parameter val_ttc0__Counter_Control_1 = 32'h00000021; +parameter mask_ttc0__Counter_Control_1 = 32'h0000007F; + +parameter ttc0__Counter_Control_2 = 32'hF8001010; +parameter val_ttc0__Counter_Control_2 = 32'h00000021; +parameter mask_ttc0__Counter_Control_2 = 32'h0000007F; + +parameter ttc0__Counter_Control_3 = 32'hF8001014; +parameter val_ttc0__Counter_Control_3 = 32'h00000021; +parameter mask_ttc0__Counter_Control_3 = 32'h0000007F; + +parameter ttc0__Counter_Value_1 = 32'hF8001018; +parameter val_ttc0__Counter_Value_1 = 32'h00000000; +parameter mask_ttc0__Counter_Value_1 = 32'h0000FFFF; + +parameter ttc0__Counter_Value_2 = 32'hF800101C; +parameter val_ttc0__Counter_Value_2 = 32'h00000000; +parameter mask_ttc0__Counter_Value_2 = 32'h0000FFFF; + +parameter ttc0__Counter_Value_3 = 32'hF8001020; +parameter val_ttc0__Counter_Value_3 = 32'h00000000; +parameter mask_ttc0__Counter_Value_3 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_1 = 32'hF8001024; +parameter val_ttc0__Interval_Counter_1 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_2 = 32'hF8001028; +parameter val_ttc0__Interval_Counter_2 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_3 = 32'hF800102C; +parameter val_ttc0__Interval_Counter_3 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_1 = 32'hF8001030; +parameter val_ttc0__Match_1_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_2 = 32'hF8001034; +parameter val_ttc0__Match_1_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_3 = 32'hF8001038; +parameter val_ttc0__Match_1_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_1 = 32'hF800103C; +parameter val_ttc0__Match_2_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_2 = 32'hF8001040; +parameter val_ttc0__Match_2_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_3 = 32'hF8001044; +parameter val_ttc0__Match_2_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_1 = 32'hF8001048; +parameter val_ttc0__Match_3_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_2 = 32'hF800104C; +parameter val_ttc0__Match_3_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_3 = 32'hF8001050; +parameter val_ttc0__Match_3_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Interrupt_Register_1 = 32'hF8001054; +parameter val_ttc0__Interrupt_Register_1 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_1 = 32'h0000003F; + +parameter ttc0__Interrupt_Register_2 = 32'hF8001058; +parameter val_ttc0__Interrupt_Register_2 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_2 = 32'h0000003F; + +parameter ttc0__Interrupt_Register_3 = 32'hF800105C; +parameter val_ttc0__Interrupt_Register_3 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_3 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_1 = 32'hF8001060; +parameter val_ttc0__Interrupt_Enable_1 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_1 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_2 = 32'hF8001064; +parameter val_ttc0__Interrupt_Enable_2 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_2 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_3 = 32'hF8001068; +parameter val_ttc0__Interrupt_Enable_3 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_3 = 32'h0000003F; + +parameter ttc0__Event_Control_Timer_1 = 32'hF800106C; +parameter val_ttc0__Event_Control_Timer_1 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_1 = 32'h00000007; + +parameter ttc0__Event_Control_Timer_2 = 32'hF8001070; +parameter val_ttc0__Event_Control_Timer_2 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_2 = 32'h00000007; + +parameter ttc0__Event_Control_Timer_3 = 32'hF8001074; +parameter val_ttc0__Event_Control_Timer_3 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_3 = 32'h00000007; + +parameter ttc0__Event_Register_1 = 32'hF8001078; +parameter val_ttc0__Event_Register_1 = 32'h00000000; +parameter mask_ttc0__Event_Register_1 = 32'h0000FFFF; + +parameter ttc0__Event_Register_2 = 32'hF800107C; +parameter val_ttc0__Event_Register_2 = 32'h00000000; +parameter mask_ttc0__Event_Register_2 = 32'h0000FFFF; + +parameter ttc0__Event_Register_3 = 32'hF8001080; +parameter val_ttc0__Event_Register_3 = 32'h00000000; +parameter mask_ttc0__Event_Register_3 = 32'h0000FFFF; + + +// ************************************************************ +// Module ttc1 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ttc1__Clock_Control_1 = 32'hF8002000; +parameter val_ttc1__Clock_Control_1 = 32'h00000000; +parameter mask_ttc1__Clock_Control_1 = 32'h0000007F; + +parameter ttc1__Clock_Control_2 = 32'hF8002004; +parameter val_ttc1__Clock_Control_2 = 32'h00000000; +parameter mask_ttc1__Clock_Control_2 = 32'h0000007F; + +parameter ttc1__Clock_Control_3 = 32'hF8002008; +parameter val_ttc1__Clock_Control_3 = 32'h00000000; +parameter mask_ttc1__Clock_Control_3 = 32'h0000007F; + +parameter ttc1__Counter_Control_1 = 32'hF800200C; +parameter val_ttc1__Counter_Control_1 = 32'h00000021; +parameter mask_ttc1__Counter_Control_1 = 32'h0000007F; + +parameter ttc1__Counter_Control_2 = 32'hF8002010; +parameter val_ttc1__Counter_Control_2 = 32'h00000021; +parameter mask_ttc1__Counter_Control_2 = 32'h0000007F; + +parameter ttc1__Counter_Control_3 = 32'hF8002014; +parameter val_ttc1__Counter_Control_3 = 32'h00000021; +parameter mask_ttc1__Counter_Control_3 = 32'h0000007F; + +parameter ttc1__Counter_Value_1 = 32'hF8002018; +parameter val_ttc1__Counter_Value_1 = 32'h00000000; +parameter mask_ttc1__Counter_Value_1 = 32'h0000FFFF; + +parameter ttc1__Counter_Value_2 = 32'hF800201C; +parameter val_ttc1__Counter_Value_2 = 32'h00000000; +parameter mask_ttc1__Counter_Value_2 = 32'h0000FFFF; + +parameter ttc1__Counter_Value_3 = 32'hF8002020; +parameter val_ttc1__Counter_Value_3 = 32'h00000000; +parameter mask_ttc1__Counter_Value_3 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_1 = 32'hF8002024; +parameter val_ttc1__Interval_Counter_1 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_2 = 32'hF8002028; +parameter val_ttc1__Interval_Counter_2 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_3 = 32'hF800202C; +parameter val_ttc1__Interval_Counter_3 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_1 = 32'hF8002030; +parameter val_ttc1__Match_1_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_2 = 32'hF8002034; +parameter val_ttc1__Match_1_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_3 = 32'hF8002038; +parameter val_ttc1__Match_1_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_1 = 32'hF800203C; +parameter val_ttc1__Match_2_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_2 = 32'hF8002040; +parameter val_ttc1__Match_2_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_3 = 32'hF8002044; +parameter val_ttc1__Match_2_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_1 = 32'hF8002048; +parameter val_ttc1__Match_3_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_2 = 32'hF800204C; +parameter val_ttc1__Match_3_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_3 = 32'hF8002050; +parameter val_ttc1__Match_3_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Interrupt_Register_1 = 32'hF8002054; +parameter val_ttc1__Interrupt_Register_1 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_1 = 32'h0000003F; + +parameter ttc1__Interrupt_Register_2 = 32'hF8002058; +parameter val_ttc1__Interrupt_Register_2 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_2 = 32'h0000003F; + +parameter ttc1__Interrupt_Register_3 = 32'hF800205C; +parameter val_ttc1__Interrupt_Register_3 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_3 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_1 = 32'hF8002060; +parameter val_ttc1__Interrupt_Enable_1 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_1 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_2 = 32'hF8002064; +parameter val_ttc1__Interrupt_Enable_2 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_2 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_3 = 32'hF8002068; +parameter val_ttc1__Interrupt_Enable_3 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_3 = 32'h0000003F; + +parameter ttc1__Event_Control_Timer_1 = 32'hF800206C; +parameter val_ttc1__Event_Control_Timer_1 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_1 = 32'h00000007; + +parameter ttc1__Event_Control_Timer_2 = 32'hF8002070; +parameter val_ttc1__Event_Control_Timer_2 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_2 = 32'h00000007; + +parameter ttc1__Event_Control_Timer_3 = 32'hF8002074; +parameter val_ttc1__Event_Control_Timer_3 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_3 = 32'h00000007; + +parameter ttc1__Event_Register_1 = 32'hF8002078; +parameter val_ttc1__Event_Register_1 = 32'h00000000; +parameter mask_ttc1__Event_Register_1 = 32'h0000FFFF; + +parameter ttc1__Event_Register_2 = 32'hF800207C; +parameter val_ttc1__Event_Register_2 = 32'h00000000; +parameter mask_ttc1__Event_Register_2 = 32'h0000FFFF; + +parameter ttc1__Event_Register_3 = 32'hF8002080; +parameter val_ttc1__Event_Register_3 = 32'h00000000; +parameter mask_ttc1__Event_Register_3 = 32'h0000FFFF; + + +// ************************************************************ +// Module uart0 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter uart0__Control_reg0 = 32'hE0000000; +parameter val_uart0__Control_reg0 = 32'h00000128; +parameter mask_uart0__Control_reg0 = 32'hFFFFFFFF; + +parameter uart0__mode_reg0 = 32'hE0000004; +parameter val_uart0__mode_reg0 = 32'h00000000; +parameter mask_uart0__mode_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_en_reg0 = 32'hE0000008; +parameter val_uart0__Intrpt_en_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_dis_reg0 = 32'hE000000C; +parameter val_uart0__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_mask_reg0 = 32'hE0000010; +parameter val_uart0__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter uart0__Chnl_int_sts_reg0 = 32'hE0000014; +parameter val_uart0__Chnl_int_sts_reg0 = 32'h00000200; +parameter mask_uart0__Chnl_int_sts_reg0 = 32'hFFFFFFFF; + +parameter uart0__Baud_rate_gen_reg0 = 32'hE0000018; +parameter val_uart0__Baud_rate_gen_reg0 = 32'h0000028B; +parameter mask_uart0__Baud_rate_gen_reg0 = 32'hFFFFFFFF; + +parameter uart0__Rcvr_timeout_reg0 = 32'hE000001C; +parameter val_uart0__Rcvr_timeout_reg0 = 32'h00000000; +parameter mask_uart0__Rcvr_timeout_reg0 = 32'hFFFFFFFF; + +parameter uart0__Rcvr_FIFO_trigger_level0 = 32'hE0000020; +parameter val_uart0__Rcvr_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart0__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF; + +parameter uart0__Modem_ctrl_reg0 = 32'hE0000024; +parameter val_uart0__Modem_ctrl_reg0 = 32'h00000000; +parameter mask_uart0__Modem_ctrl_reg0 = 32'hFFFFFFFF; + +parameter uart0__Modem_sts_reg0 = 32'hE0000028; +parameter val_uart0__Modem_sts_reg0 = 32'h00000000; +parameter mask_uart0__Modem_sts_reg0 = 32'h00000000; + +parameter uart0__Channel_sts_reg0 = 32'hE000002C; +parameter val_uart0__Channel_sts_reg0 = 32'h00000000; +parameter mask_uart0__Channel_sts_reg0 = 32'hFFFFFFFF; + +parameter uart0__TX_RX_FIFO0 = 32'hE0000030; +parameter val_uart0__TX_RX_FIFO0 = 32'h00000000; +parameter mask_uart0__TX_RX_FIFO0 = 32'hFFFFFFFF; + +parameter uart0__Baud_rate_divider_reg0 = 32'hE0000034; +parameter val_uart0__Baud_rate_divider_reg0 = 32'h0000000F; +parameter mask_uart0__Baud_rate_divider_reg0 = 32'hFFFFFFFF; + +parameter uart0__Flow_delay_reg0 = 32'hE0000038; +parameter val_uart0__Flow_delay_reg0 = 32'h00000000; +parameter mask_uart0__Flow_delay_reg0 = 32'hFFFFFFFF; + +parameter uart0__IR_min_rcv_pulse_wdth0 = 32'hE000003C; +parameter val_uart0__IR_min_rcv_pulse_wdth0 = 32'h00000000; +parameter mask_uart0__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF; + +parameter uart0__IR_transmitted_pulse_wdth0 = 32'hE0000040; +parameter val_uart0__IR_transmitted_pulse_wdth0 = 32'h00000000; +parameter mask_uart0__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF; + +parameter uart0__Tx_FIFO_trigger_level0 = 32'hE0000044; +parameter val_uart0__Tx_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart0__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module uart1 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter uart1__Control_reg0 = 32'hE0001000; +parameter val_uart1__Control_reg0 = 32'h00000128; +parameter mask_uart1__Control_reg0 = 32'hFFFFFFFF; + +parameter uart1__mode_reg0 = 32'hE0001004; +parameter val_uart1__mode_reg0 = 32'h00000000; +parameter mask_uart1__mode_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_en_reg0 = 32'hE0001008; +parameter val_uart1__Intrpt_en_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_dis_reg0 = 32'hE000100C; +parameter val_uart1__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_mask_reg0 = 32'hE0001010; +parameter val_uart1__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter uart1__Chnl_int_sts_reg0 = 32'hE0001014; +parameter val_uart1__Chnl_int_sts_reg0 = 32'h00000200; +parameter mask_uart1__Chnl_int_sts_reg0 = 32'hFFFFFFFF; + +parameter uart1__Baud_rate_gen_reg0 = 32'hE0001018; +parameter val_uart1__Baud_rate_gen_reg0 = 32'h0000028B; +parameter mask_uart1__Baud_rate_gen_reg0 = 32'hFFFFFFFF; + +parameter uart1__Rcvr_timeout_reg0 = 32'hE000101C; +parameter val_uart1__Rcvr_timeout_reg0 = 32'h00000000; +parameter mask_uart1__Rcvr_timeout_reg0 = 32'hFFFFFFFF; + +parameter uart1__Rcvr_FIFO_trigger_level0 = 32'hE0001020; +parameter val_uart1__Rcvr_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart1__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF; + +parameter uart1__Modem_ctrl_reg0 = 32'hE0001024; +parameter val_uart1__Modem_ctrl_reg0 = 32'h00000000; +parameter mask_uart1__Modem_ctrl_reg0 = 32'hFFFFFFFF; + +parameter uart1__Modem_sts_reg0 = 32'hE0001028; +parameter val_uart1__Modem_sts_reg0 = 32'h00000000; +parameter mask_uart1__Modem_sts_reg0 = 32'h00000000; + +parameter uart1__Channel_sts_reg0 = 32'hE000102C; +parameter val_uart1__Channel_sts_reg0 = 32'h00000000; +parameter mask_uart1__Channel_sts_reg0 = 32'hFFFFFFFF; + +parameter uart1__TX_RX_FIFO0 = 32'hE0001030; +parameter val_uart1__TX_RX_FIFO0 = 32'h00000000; +parameter mask_uart1__TX_RX_FIFO0 = 32'hFFFFFFFF; + +parameter uart1__Baud_rate_divider_reg0 = 32'hE0001034; +parameter val_uart1__Baud_rate_divider_reg0 = 32'h0000000F; +parameter mask_uart1__Baud_rate_divider_reg0 = 32'hFFFFFFFF; + +parameter uart1__Flow_delay_reg0 = 32'hE0001038; +parameter val_uart1__Flow_delay_reg0 = 32'h00000000; +parameter mask_uart1__Flow_delay_reg0 = 32'hFFFFFFFF; + +parameter uart1__IR_min_rcv_pulse_wdth0 = 32'hE000103C; +parameter val_uart1__IR_min_rcv_pulse_wdth0 = 32'h00000000; +parameter mask_uart1__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF; + +parameter uart1__IR_transmitted_pulse_wdth0 = 32'hE0001040; +parameter val_uart1__IR_transmitted_pulse_wdth0 = 32'h00000000; +parameter mask_uart1__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF; + +parameter uart1__Tx_FIFO_trigger_level0 = 32'hE0001044; +parameter val_uart1__Tx_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart1__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module usb0 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter usb0__ID = 32'hE0002000; +parameter val_usb0__ID = 32'hE441FA05; +parameter mask_usb0__ID = 32'hFFFFFFFF; + +parameter usb0__HWGENERAL = 32'hE0002004; +parameter val_usb0__HWGENERAL = 32'h00000083; +parameter mask_usb0__HWGENERAL = 32'h00000FFF; + +parameter usb0__HWHOST = 32'hE0002008; +parameter val_usb0__HWHOST = 32'h10020001; +parameter mask_usb0__HWHOST = 32'hFFFFFFFF; + +parameter usb0__HWDEVICE = 32'hE000200C; +parameter val_usb0__HWDEVICE = 32'h00000019; +parameter mask_usb0__HWDEVICE = 32'h0000003F; + +parameter usb0__HWTXBUF = 32'hE0002010; +parameter val_usb0__HWTXBUF = 32'h80060A10; +parameter mask_usb0__HWTXBUF = 32'hFFFFFFFF; + +parameter usb0__HWRXBUF = 32'hE0002014; +parameter val_usb0__HWRXBUF = 32'h00000A10; +parameter mask_usb0__HWRXBUF = 32'hFF00FFFF; + +parameter usb0__GPTIMER0LD = 32'hE0002080; +parameter val_usb0__GPTIMER0LD = 32'h00000000; +parameter mask_usb0__GPTIMER0LD = 32'h00FFFFFF; + +parameter usb0__GPTIMER0CTRL = 32'hE0002084; +parameter val_usb0__GPTIMER0CTRL = 32'h00000000; +parameter mask_usb0__GPTIMER0CTRL = 32'hFFFFFFFF; + +parameter usb0__GPTIMER1LD = 32'hE0002088; +parameter val_usb0__GPTIMER1LD = 32'h00000000; +parameter mask_usb0__GPTIMER1LD = 32'h00FFFFFF; + +parameter usb0__GPTIMER1CTRL = 32'hE000208C; +parameter val_usb0__GPTIMER1CTRL = 32'h00000000; +parameter mask_usb0__GPTIMER1CTRL = 32'hFFFFFFFF; + +parameter usb0__SBUSCFG = 32'hE0002090; +parameter val_usb0__SBUSCFG = 32'h00000003; +parameter mask_usb0__SBUSCFG = 32'h00000007; + +parameter usb0__CAPLENGTH_HCIVERSION = 32'hE0002100; +parameter val_usb0__CAPLENGTH_HCIVERSION = 32'h01000040; +parameter mask_usb0__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF; + +parameter usb0__HCSPARAMS = 32'hE0002104; +parameter val_usb0__HCSPARAMS = 32'h00010011; +parameter mask_usb0__HCSPARAMS = 32'h0FFFFFFF; + +parameter usb0__HCCPARAMS = 32'hE0002108; +parameter val_usb0__HCCPARAMS = 32'h00000006; +parameter mask_usb0__HCCPARAMS = 32'h0000FFFF; + +parameter usb0__DCIVERSION = 32'hE0002120; +parameter val_usb0__DCIVERSION = 32'h00000001; +parameter mask_usb0__DCIVERSION = 32'h0000FFFF; + +parameter usb0__DCCPARAMS = 32'hE0002124; +parameter val_usb0__DCCPARAMS = 32'h0000018C; +parameter mask_usb0__DCCPARAMS = 32'h000001FF; + +parameter usb0__USBCMD = 32'hE0002140; +parameter val_usb0__USBCMD = 32'h00000B00; +parameter mask_usb0__USBCMD = 32'h00FFFFFF; + +parameter usb0__USBSTS = 32'hE0002144; +parameter val_usb0__USBSTS = 32'h00000000; +parameter mask_usb0__USBSTS = 32'h03FFFFFF; + +parameter usb0__USBINTR = 32'hE0002148; +parameter val_usb0__USBINTR = 32'h00000000; +parameter mask_usb0__USBINTR = 32'h03FF0FFF; + +parameter usb0__FRINDEX = 32'hE000214C; +parameter val_usb0__FRINDEX = 32'h00000000; +parameter mask_usb0__FRINDEX = 32'h00003FFF; + +parameter usb0__PERIODICLISTBASE_DEVICEADDR = 32'hE0002154; +parameter val_usb0__PERIODICLISTBASE_DEVICEADDR = 32'h00000000; +parameter mask_usb0__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF; + +parameter usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0002158; +parameter val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000; +parameter mask_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF; + +parameter usb0__TTCTRL = 32'hE000215C; +parameter val_usb0__TTCTRL = 32'h00000000; +parameter mask_usb0__TTCTRL = 32'hFFFFFFFF; + +parameter usb0__BURSTSIZE = 32'hE0002160; +parameter val_usb0__BURSTSIZE = 32'h00001010; +parameter mask_usb0__BURSTSIZE = 32'h0001FFFF; + +parameter usb0__TXFILLTUNING = 32'hE0002164; +parameter val_usb0__TXFILLTUNING = 32'h00020000; +parameter mask_usb0__TXFILLTUNING = 32'h003FFFFF; + +parameter usb0__TXTTFILLTUNING = 32'hE0002168; +parameter val_usb0__TXTTFILLTUNING = 32'h00000000; +parameter mask_usb0__TXTTFILLTUNING = 32'h00001FFF; + +parameter usb0__IC_USB = 32'hE000216C; +parameter val_usb0__IC_USB = 32'h00000000; +parameter mask_usb0__IC_USB = 32'hFFFFFFFF; + +parameter usb0__ULPI_VIEWPORT = 32'hE0002170; +parameter val_usb0__ULPI_VIEWPORT = 32'h00000000; +parameter mask_usb0__ULPI_VIEWPORT = 32'hFFFFFFFF; + +parameter usb0__ENDPTNAK = 32'hE0002178; +parameter val_usb0__ENDPTNAK = 32'h00000000; +parameter mask_usb0__ENDPTNAK = 32'hFFFFFFFF; + +parameter usb0__ENDPTNAKEN = 32'hE000217C; +parameter val_usb0__ENDPTNAKEN = 32'h00000000; +parameter mask_usb0__ENDPTNAKEN = 32'hFFFFFFFF; + +parameter usb0__CONFIGFLAG = 32'hE0002180; +parameter val_usb0__CONFIGFLAG = 32'h00000001; +parameter mask_usb0__CONFIGFLAG = 32'hFFFFFFFF; + +parameter usb0__PORTSC1 = 32'hE0002184; +parameter val_usb0__PORTSC1 = 32'h00000000; +parameter mask_usb0__PORTSC1 = 32'hFFFFFFFF; + +parameter usb0__OTGSC = 32'hE00021A4; +parameter val_usb0__OTGSC = 32'h00000020; +parameter mask_usb0__OTGSC = 32'hFFFFFFFF; + +parameter usb0__USBMODE = 32'hE00021A8; +parameter val_usb0__USBMODE = 32'h00000000; +parameter mask_usb0__USBMODE = 32'h0000FFFF; + +parameter usb0__ENDPTSETUPSTAT = 32'hE00021AC; +parameter val_usb0__ENDPTSETUPSTAT = 32'h00000000; +parameter mask_usb0__ENDPTSETUPSTAT = 32'h0000FFFF; + +parameter usb0__ENDPTPRIME = 32'hE00021B0; +parameter val_usb0__ENDPTPRIME = 32'h00000000; +parameter mask_usb0__ENDPTPRIME = 32'hFFFFFFFF; + +parameter usb0__ENDPTFLUSH = 32'hE00021B4; +parameter val_usb0__ENDPTFLUSH = 32'h00000000; +parameter mask_usb0__ENDPTFLUSH = 32'hFFFFFFFF; + +parameter usb0__ENDPTSTAT = 32'hE00021B8; +parameter val_usb0__ENDPTSTAT = 32'h00000000; +parameter mask_usb0__ENDPTSTAT = 32'hFFFFFFFF; + +parameter usb0__ENDPTCOMPLETE = 32'hE00021BC; +parameter val_usb0__ENDPTCOMPLETE = 32'h00000000; +parameter mask_usb0__ENDPTCOMPLETE = 32'hFFFFFFFF; + +parameter usb0__ENDPTCTRL0 = 32'hE00021C0; +parameter val_usb0__ENDPTCTRL0 = 32'h00800080; +parameter mask_usb0__ENDPTCTRL0 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL1 = 32'hE00021C4; +parameter val_usb0__ENDPTCTRL1 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL1 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL2 = 32'hE00021C8; +parameter val_usb0__ENDPTCTRL2 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL2 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL3 = 32'hE00021CC; +parameter val_usb0__ENDPTCTRL3 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL3 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL4 = 32'hE00021D0; +parameter val_usb0__ENDPTCTRL4 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL4 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL5 = 32'hE00021D4; +parameter val_usb0__ENDPTCTRL5 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL5 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL6 = 32'hE00021D8; +parameter val_usb0__ENDPTCTRL6 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL6 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL7 = 32'hE00021DC; +parameter val_usb0__ENDPTCTRL7 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL7 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL8 = 32'hE00021E0; +parameter val_usb0__ENDPTCTRL8 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL8 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL9 = 32'hE00021E4; +parameter val_usb0__ENDPTCTRL9 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL9 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL10 = 32'hE00021E8; +parameter val_usb0__ENDPTCTRL10 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL10 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL11 = 32'hE00021EC; +parameter val_usb0__ENDPTCTRL11 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL11 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL12 = 32'hE00021F0; +parameter val_usb0__ENDPTCTRL12 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL12 = 32'h00FFFFFF; + + +// ************************************************************ +// Module usb1 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter usb1__ID = 32'hE0003000; +parameter val_usb1__ID = 32'hE441FA05; +parameter mask_usb1__ID = 32'hFFFFFFFF; + +parameter usb1__HWGENERAL = 32'hE0003004; +parameter val_usb1__HWGENERAL = 32'h00000083; +parameter mask_usb1__HWGENERAL = 32'h00000FFF; + +parameter usb1__HWHOST = 32'hE0003008; +parameter val_usb1__HWHOST = 32'h10020001; +parameter mask_usb1__HWHOST = 32'hFFFFFFFF; + +parameter usb1__HWDEVICE = 32'hE000300C; +parameter val_usb1__HWDEVICE = 32'h00000019; +parameter mask_usb1__HWDEVICE = 32'h0000003F; + +parameter usb1__HWTXBUF = 32'hE0003010; +parameter val_usb1__HWTXBUF = 32'h80060A10; +parameter mask_usb1__HWTXBUF = 32'hFFFFFFFF; + +parameter usb1__HWRXBUF = 32'hE0003014; +parameter val_usb1__HWRXBUF = 32'h00000A10; +parameter mask_usb1__HWRXBUF = 32'hFF00FFFF; + +parameter usb1__GPTIMER0LD = 32'hE0003080; +parameter val_usb1__GPTIMER0LD = 32'h00000000; +parameter mask_usb1__GPTIMER0LD = 32'h00FFFFFF; + +parameter usb1__GPTIMER0CTRL = 32'hE0003084; +parameter val_usb1__GPTIMER0CTRL = 32'h00000000; +parameter mask_usb1__GPTIMER0CTRL = 32'hFFFFFFFF; + +parameter usb1__GPTIMER1LD = 32'hE0003088; +parameter val_usb1__GPTIMER1LD = 32'h00000000; +parameter mask_usb1__GPTIMER1LD = 32'h00FFFFFF; + +parameter usb1__GPTIMER1CTRL = 32'hE000308C; +parameter val_usb1__GPTIMER1CTRL = 32'h00000000; +parameter mask_usb1__GPTIMER1CTRL = 32'hFFFFFFFF; + +parameter usb1__SBUSCFG = 32'hE0003090; +parameter val_usb1__SBUSCFG = 32'h00000003; +parameter mask_usb1__SBUSCFG = 32'h00000007; + +parameter usb1__CAPLENGTH_HCIVERSION = 32'hE0003100; +parameter val_usb1__CAPLENGTH_HCIVERSION = 32'h01000040; +parameter mask_usb1__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF; + +parameter usb1__HCSPARAMS = 32'hE0003104; +parameter val_usb1__HCSPARAMS = 32'h00010011; +parameter mask_usb1__HCSPARAMS = 32'h0FFFFFFF; + +parameter usb1__HCCPARAMS = 32'hE0003108; +parameter val_usb1__HCCPARAMS = 32'h00000006; +parameter mask_usb1__HCCPARAMS = 32'h0000FFFF; + +parameter usb1__DCIVERSION = 32'hE0003120; +parameter val_usb1__DCIVERSION = 32'h00000001; +parameter mask_usb1__DCIVERSION = 32'h0000FFFF; + +parameter usb1__DCCPARAMS = 32'hE0003124; +parameter val_usb1__DCCPARAMS = 32'h0000018C; +parameter mask_usb1__DCCPARAMS = 32'h000001FF; + +parameter usb1__USBCMD = 32'hE0003140; +parameter val_usb1__USBCMD = 32'h00000B00; +parameter mask_usb1__USBCMD = 32'h00FFFFFF; + +parameter usb1__USBSTS = 32'hE0003144; +parameter val_usb1__USBSTS = 32'h00000000; +parameter mask_usb1__USBSTS = 32'h03FFFFFF; + +parameter usb1__USBINTR = 32'hE0003148; +parameter val_usb1__USBINTR = 32'h00000000; +parameter mask_usb1__USBINTR = 32'h03FF0FFF; + +parameter usb1__FRINDEX = 32'hE000314C; +parameter val_usb1__FRINDEX = 32'h00000000; +parameter mask_usb1__FRINDEX = 32'h00003FFF; + +parameter usb1__PERIODICLISTBASE_DEVICEADDR = 32'hE0003154; +parameter val_usb1__PERIODICLISTBASE_DEVICEADDR = 32'h00000000; +parameter mask_usb1__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF; + +parameter usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0003158; +parameter val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000; +parameter mask_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF; + +parameter usb1__TTCTRL = 32'hE000315C; +parameter val_usb1__TTCTRL = 32'h00000000; +parameter mask_usb1__TTCTRL = 32'hFFFFFFFF; + +parameter usb1__BURSTSIZE = 32'hE0003160; +parameter val_usb1__BURSTSIZE = 32'h00001010; +parameter mask_usb1__BURSTSIZE = 32'h0001FFFF; + +parameter usb1__TXFILLTUNING = 32'hE0003164; +parameter val_usb1__TXFILLTUNING = 32'h00020000; +parameter mask_usb1__TXFILLTUNING = 32'h003FFFFF; + +parameter usb1__TXTTFILLTUNING = 32'hE0003168; +parameter val_usb1__TXTTFILLTUNING = 32'h00000000; +parameter mask_usb1__TXTTFILLTUNING = 32'h00001FFF; + +parameter usb1__IC_USB = 32'hE000316C; +parameter val_usb1__IC_USB = 32'h00000000; +parameter mask_usb1__IC_USB = 32'hFFFFFFFF; + +parameter usb1__ULPI_VIEWPORT = 32'hE0003170; +parameter val_usb1__ULPI_VIEWPORT = 32'h00000000; +parameter mask_usb1__ULPI_VIEWPORT = 32'hFFFFFFFF; + +parameter usb1__ENDPTNAK = 32'hE0003178; +parameter val_usb1__ENDPTNAK = 32'h00000000; +parameter mask_usb1__ENDPTNAK = 32'hFFFFFFFF; + +parameter usb1__ENDPTNAKEN = 32'hE000317C; +parameter val_usb1__ENDPTNAKEN = 32'h00000000; +parameter mask_usb1__ENDPTNAKEN = 32'hFFFFFFFF; + +parameter usb1__CONFIGFLAG = 32'hE0003180; +parameter val_usb1__CONFIGFLAG = 32'h00000001; +parameter mask_usb1__CONFIGFLAG = 32'hFFFFFFFF; + +parameter usb1__PORTSC1 = 32'hE0003184; +parameter val_usb1__PORTSC1 = 32'h00000000; +parameter mask_usb1__PORTSC1 = 32'hFFFFFFFF; + +parameter usb1__OTGSC = 32'hE00031A4; +parameter val_usb1__OTGSC = 32'h00000020; +parameter mask_usb1__OTGSC = 32'hFFFFFFFF; + +parameter usb1__USBMODE = 32'hE00031A8; +parameter val_usb1__USBMODE = 32'h00000000; +parameter mask_usb1__USBMODE = 32'h0000FFFF; + +parameter usb1__ENDPTSETUPSTAT = 32'hE00031AC; +parameter val_usb1__ENDPTSETUPSTAT = 32'h00000000; +parameter mask_usb1__ENDPTSETUPSTAT = 32'h0000FFFF; + +parameter usb1__ENDPTPRIME = 32'hE00031B0; +parameter val_usb1__ENDPTPRIME = 32'h00000000; +parameter mask_usb1__ENDPTPRIME = 32'hFFFFFFFF; + +parameter usb1__ENDPTFLUSH = 32'hE00031B4; +parameter val_usb1__ENDPTFLUSH = 32'h00000000; +parameter mask_usb1__ENDPTFLUSH = 32'hFFFFFFFF; + +parameter usb1__ENDPTSTAT = 32'hE00031B8; +parameter val_usb1__ENDPTSTAT = 32'h00000000; +parameter mask_usb1__ENDPTSTAT = 32'hFFFFFFFF; + +parameter usb1__ENDPTCOMPLETE = 32'hE00031BC; +parameter val_usb1__ENDPTCOMPLETE = 32'h00000000; +parameter mask_usb1__ENDPTCOMPLETE = 32'hFFFFFFFF; + +parameter usb1__ENDPTCTRL0 = 32'hE00031C0; +parameter val_usb1__ENDPTCTRL0 = 32'h00800080; +parameter mask_usb1__ENDPTCTRL0 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL1 = 32'hE00031C4; +parameter val_usb1__ENDPTCTRL1 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL1 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL2 = 32'hE00031C8; +parameter val_usb1__ENDPTCTRL2 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL2 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL3 = 32'hE00031CC; +parameter val_usb1__ENDPTCTRL3 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL3 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL4 = 32'hE00031D0; +parameter val_usb1__ENDPTCTRL4 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL4 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL5 = 32'hE00031D4; +parameter val_usb1__ENDPTCTRL5 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL5 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL6 = 32'hE00031D8; +parameter val_usb1__ENDPTCTRL6 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL6 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL7 = 32'hE00031DC; +parameter val_usb1__ENDPTCTRL7 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL7 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL8 = 32'hE00031E0; +parameter val_usb1__ENDPTCTRL8 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL8 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL9 = 32'hE00031E4; +parameter val_usb1__ENDPTCTRL9 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL9 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL10 = 32'hE00031E8; +parameter val_usb1__ENDPTCTRL10 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL10 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL11 = 32'hE00031EC; +parameter val_usb1__ENDPTCTRL11 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL11 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL12 = 32'hE00031F0; +parameter val_usb1__ENDPTCTRL12 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL12 = 32'h00FFFFFF; diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_regc.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_regc.v new file mode 100644 index 0000000..5cb0341 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_regc.v @@ -0,0 +1,118 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_regc.v + * + * Date : 2012-11 + * + * Description : Controller for Register Map Memory + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_regc( + rstn, + sw_clk, + +/* Goes to port 0 of REG */ + reg_rd_req_port0, + reg_rd_dv_port0, + reg_rd_addr_port0, + reg_rd_data_port0, + reg_rd_bytes_port0, + reg_rd_qos_port0, + + +/* Goes to port 1 of REG */ + reg_rd_req_port1, + reg_rd_dv_port1, + reg_rd_addr_port1, + reg_rd_data_port1, + reg_rd_bytes_port1, + reg_rd_qos_port1 + +); + +input rstn; +input sw_clk; + +input reg_rd_req_port0; +output reg_rd_dv_port0; +input[31:0] reg_rd_addr_port0; +output[1023:0] reg_rd_data_port0; +input[7:0] reg_rd_bytes_port0; +input [3:0] reg_rd_qos_port0; + +input reg_rd_req_port1; +output reg_rd_dv_port1; +input[31:0] reg_rd_addr_port1; +output[1023:0] reg_rd_data_port1; +input[7:0] reg_rd_bytes_port1; +input[3:0] reg_rd_qos_port1; + +wire [3:0] rd_qos; +reg [1023:0] rd_data; +wire [31:0] rd_addr; +wire [7:0] rd_bytes; +reg rd_dv; +wire rd_req; + +processing_system7_bfm_v2_0_arb_rd reg_read_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(reg_rd_qos_port0), + .qos2(reg_rd_qos_port1), + + .prt_req1(reg_rd_req_port0), + .prt_req2(reg_rd_req_port1), + + .prt_data1(reg_rd_data_port0), + .prt_data2(reg_rd_data_port1), + + .prt_addr1(reg_rd_addr_port0), + .prt_addr2(reg_rd_addr_port1), + + .prt_bytes1(reg_rd_bytes_port0), + .prt_bytes2(reg_rd_bytes_port1), + + .prt_dv1(reg_rd_dv_port0), + .prt_dv2(reg_rd_dv_port1), + + .prt_qos(rd_qos), + .prt_req(rd_req), + .prt_data(rd_data), + .prt_addr(rd_addr), + .prt_bytes(rd_bytes), + .prt_dv(rd_dv) + +); + +processing_system7_bfm_v2_0_reg_map regm(); + +reg state; +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + rd_dv <= 0; + state <= 0; +end else begin + case(state) + 0:begin + state <= 0; + rd_dv <= 0; + if(rd_req) begin + regm.read_reg_mem(rd_data,rd_addr, rd_bytes); + rd_dv <= 1; + state <= 1; + end + + end + 1:begin + rd_dv <= 0; + state <= 0; + end + + endcase +end /// if +end// always + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_sparse_mem.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_sparse_mem.v new file mode 100644 index 0000000..b8e954d --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_sparse_mem.v @@ -0,0 +1,317 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_sparse_mem.v + * + * Date : 2012-11 + * + * Description : Sparse Memory Model + * + *****************************************************************************/ + +/*** WA for CR # 695818 ***/ +`ifdef XILINX_SIMULATOR + `define XSIM_ISIM +`endif +`ifdef XILINX_ISIM + `define XSIM_ISIM +`endif + + `timescale 1ns/1ps +module processing_system7_bfm_v2_0_sparse_mem(); + +`include "processing_system7_bfm_v2_0_local_params.v" + +parameter mem_size = 32'h4000_0000; /// 1GB mem size +parameter xsim_mem_size = 32'h1000_0000; ///256 MB mem size (x4 for XSIM/ISIM) + + +`ifdef XSIM_ISIM + reg [data_width-1:0] ddr_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + reg [data_width-1:0] ddr_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + reg [data_width-1:0] ddr_mem2 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + reg [data_width-1:0] ddr_mem3 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem +`else + reg /*sparse*/ [data_width-1:0] ddr_mem [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem +`endif + +event mem_updated; +reg check_we; +reg [addr_width-1:0] check_up_add; +reg [data_width-1:0] updated_data; + +/* preload memory from file */ +task automatic pre_load_mem_from_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; +`ifdef XSIM_ISIM + case(start_addr[31:28]) + 4'd0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits); + 4'd1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits); + 4'd2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits); + 4'd3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits); + endcase +`else + $readmemh(file_name,ddr_mem,start_addr>>shft_addr_bits); +`endif +endtask + +/* preload memory with some random data */ +task automatic pre_load_mem; +input [1:0] data_type; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; +integer i; +reg [addr_width-1:0] addr; +begin +addr = start_addr >> shft_addr_bits; +for (i = 0; i < no_of_bytes; i = i + mem_width) begin + case(data_type) + ALL_RANDOM : set_data(addr , $random); + ALL_ZEROS : set_data(addr , 32'h0000_0000); + ALL_ONES : set_data(addr , 32'hFFFF_FFFF); + default : set_data(addr , $random); + endcase + addr = addr+1; +end +end +endtask + +/* wait for memory update at certain location */ +task automatic wait_mem_update; +input[addr_width-1:0] address; +output[data_width-1:0] dataout; +begin + check_up_add = address >> shft_addr_bits; + check_we = 1; + @(mem_updated); + dataout = updated_data; + check_we = 0; +end +endtask + +/* internal task to write data in memory */ +task automatic set_data; +input [addr_width-1:0] addr; +input [data_width-1:0] data; +begin +if(check_we && (addr === check_up_add)) begin + updated_data = data; + -> mem_updated; +end +`ifdef XSIM_ISIM + case(addr[31:26]) + 6'd0 : ddr_mem0[addr[25:0]] = data; + 6'd1 : ddr_mem1[addr[25:0]] = data; + 6'd2 : ddr_mem2[addr[25:0]] = data; + 6'd3 : ddr_mem3[addr[25:0]] = data; + endcase +`else + ddr_mem[addr] = data; +`endif +end +endtask + +/* internal task to read data from memory */ +task automatic get_data; +input [addr_width-1:0] addr; +output [data_width-1:0] data; +begin +`ifdef XSIM_ISIM + case(addr[31:26]) + 6'd0 : data = ddr_mem0[addr[25:0]]; + 6'd1 : data = ddr_mem1[addr[25:0]]; + 6'd2 : data = ddr_mem2[addr[25:0]]; + 6'd3 : data = ddr_mem3[addr[25:0]]; + endcase +`else + data = ddr_mem[addr]; +`endif +end +endtask + +/* Write memory */ +task write_mem; +input [max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +reg [addr_width-1:0] addr; +reg [max_burst_bits-1 :0] wr_temp_data; +reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data; +integer bytes_left; +integer pre_pad_bytes; +integer post_pad_bytes; +begin +addr = start_addr >> shft_addr_bits; +wr_temp_data = data; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); +`endif + +temp_data = wr_temp_data[data_width-1:0]; +bytes_left = no_of_bytes; +/* when the no. of bytes to be updated is less than mem_width */ +if(bytes_left < mem_width) begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + //temp_data = ddr_mem[addr]; + get_data(addr,temp_data); + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) temp_data = temp_data << 8; + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + wr_temp_data = wr_temp_data >> 8; + end + bytes_left = bytes_left + pre_pad_bytes; + end + /* This is needed for post padding the data ...*/ + post_pad_bytes = mem_width - bytes_left; + //post_pad_data = ddr_mem[addr]; + get_data(addr,post_pad_data); + repeat(post_pad_bytes) temp_data = temp_data << 8; + repeat(bytes_left) post_pad_data = post_pad_data >> 8; + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + post_pad_data = post_pad_data >> 8; + end + //ddr_mem[addr] = temp_data; + set_data(addr,temp_data); +end else begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + //temp_data = ddr_mem[addr]; + get_data(addr,temp_data); + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) temp_data = temp_data << 8; + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + wr_temp_data = wr_temp_data >> 8; + bytes_left = bytes_left -1; + end + end else begin + wr_temp_data = wr_temp_data >> data_width; + bytes_left = bytes_left - mem_width; + end + /* first data word end */ + //ddr_mem[addr] = temp_data; + set_data(addr,temp_data); + addr = addr + 1; + while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes. + //ddr_mem[addr] = wr_temp_data[data_width-1:0]; + set_data(addr,wr_temp_data[data_width-1:0]); + addr = addr+1; + wr_temp_data = wr_temp_data >> data_width; + bytes_left = bytes_left - mem_width; + end + + //post_pad_data = ddr_mem[addr]; + get_data(addr,post_pad_data); + post_pad_bytes = mem_width - bytes_left; + /* This is needed for last transfer in unaliged burst */ + if(bytes_left > 0) begin + temp_data = wr_temp_data[data_width-1:0]; + repeat(post_pad_bytes) temp_data = temp_data << 8; + repeat(bytes_left) post_pad_data = post_pad_data >> 8; + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + post_pad_data = post_pad_data >> 8; + end + //ddr_mem[addr] = temp_data; + set_data(addr,temp_data); + end +end +`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); +`endif +end +endtask + +/* read_memory */ +task read_mem; +output[max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width :0] no_of_bytes; +integer i; +reg [addr_width-1:0] addr; +reg [data_width-1:0] temp_rd_data; +reg [max_burst_bits-1:0] temp_data; +integer pre_bytes; +integer bytes_left; +begin +addr = start_addr >> shft_addr_bits; +pre_bytes = start_addr[shft_addr_bits-1:0]; +bytes_left = no_of_bytes; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); +`endif + +/* Get first data ... if unaligned address */ +//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr]; +get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); + +if(no_of_bytes < mem_width ) begin + temp_data = temp_data >> (pre_bytes * 8); + repeat(max_burst_bytes - mem_width) + temp_data = temp_data >> 8; + +end else begin + bytes_left = bytes_left - (mem_width - pre_bytes); + addr = addr+1; + /* Got first data */ + while (bytes_left > (mem_width-1) ) begin + temp_data = temp_data >> data_width; + //temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr]; + get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); + addr = addr+1; + bytes_left = bytes_left - mem_width; + end + + /* Get last valid data in the burst*/ + //temp_rd_data = ddr_mem[addr]; + get_data(addr,temp_rd_data); + while(bytes_left > 0) begin + temp_data = temp_data >> 8; + temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; + temp_rd_data = temp_rd_data >> 8; + bytes_left = bytes_left - 1; + end + /* align to the brst_byte length */ + repeat(max_burst_bytes - no_of_bytes) + temp_data = temp_data >> 8; +end +data = temp_data; +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); +`endif +end +endtask + +/* backdoor read to memory */ +task peek_mem_to_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; + +integer rd_fd; +integer bytes; +reg [addr_width-1:0] addr; +reg [data_width-1:0] rd_data; +begin +rd_fd = $fopen(file_name,"w"); +bytes = no_of_bytes; + +addr = start_addr >> shft_addr_bits; +while (bytes > 0) begin + get_data(addr,rd_data); + $fdisplayh(rd_fd,rd_data); + bytes = bytes - 4; + addr = addr + 1; +end +end +endtask + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ssw_hp.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ssw_hp.v new file mode 100644 index 0000000..b8b2046 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_ssw_hp.v @@ -0,0 +1,443 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_ssw_hp.v + * + * Date : 2012-11 + * + * Description : SSW switch Model + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_ssw_hp( + sw_clk, + rstn, + w_qos_hp0, + r_qos_hp0, + w_qos_hp1, + r_qos_hp1, + w_qos_hp2, + r_qos_hp2, + w_qos_hp3, + r_qos_hp3, + + wr_ack_ddr_hp0, + wr_data_hp0, + wr_addr_hp0, + wr_bytes_hp0, + wr_dv_ddr_hp0, + rd_req_ddr_hp0, + rd_addr_hp0, + rd_bytes_hp0, + rd_data_ddr_hp0, + rd_dv_ddr_hp0, + + rd_data_ocm_hp0, + wr_ack_ocm_hp0, + wr_dv_ocm_hp0, + rd_req_ocm_hp0, + rd_dv_ocm_hp0, + + wr_ack_ddr_hp1, + wr_data_hp1, + wr_addr_hp1, + wr_bytes_hp1, + wr_dv_ddr_hp1, + rd_req_ddr_hp1, + rd_addr_hp1, + rd_bytes_hp1, + rd_data_ddr_hp1, + rd_data_ocm_hp1, + rd_dv_ddr_hp1, + + wr_ack_ocm_hp1, + wr_dv_ocm_hp1, + rd_req_ocm_hp1, + rd_dv_ocm_hp1, + + wr_ack_ddr_hp2, + wr_data_hp2, + wr_addr_hp2, + wr_bytes_hp2, + wr_dv_ddr_hp2, + rd_req_ddr_hp2, + rd_addr_hp2, + rd_bytes_hp2, + rd_data_ddr_hp2, + rd_data_ocm_hp2, + rd_dv_ddr_hp2, + + wr_ack_ocm_hp2, + wr_dv_ocm_hp2, + rd_req_ocm_hp2, + rd_dv_ocm_hp2, + + wr_ack_ddr_hp3, + wr_data_hp3, + wr_addr_hp3, + wr_bytes_hp3, + wr_dv_ddr_hp3, + rd_req_ddr_hp3, + rd_addr_hp3, + rd_bytes_hp3, + rd_data_ocm_hp3, + rd_data_ddr_hp3, + rd_dv_ddr_hp3, + + wr_ack_ocm_hp3, + wr_dv_ocm_hp3, + rd_req_ocm_hp3, + rd_dv_ocm_hp3, + + ddr_wr_ack0, + ddr_wr_dv0, + ddr_rd_req0, + ddr_rd_dv0, + ddr_rd_qos0, + ddr_wr_qos0, + + ddr_wr_addr0, + ddr_wr_data0, + ddr_wr_bytes0, + ddr_rd_addr0, + ddr_rd_data0, + ddr_rd_bytes0, + + ddr_wr_ack1, + ddr_wr_dv1, + ddr_rd_req1, + ddr_rd_dv1, + ddr_rd_qos1, + ddr_wr_qos1, + ddr_wr_addr1, + ddr_wr_data1, + ddr_wr_bytes1, + ddr_rd_addr1, + ddr_rd_data1, + ddr_rd_bytes1, + + ocm_wr_ack, + ocm_wr_dv, + ocm_rd_req, + ocm_rd_dv, + + ocm_wr_qos, + ocm_rd_qos, + ocm_wr_addr, + ocm_wr_data, + ocm_wr_bytes, + ocm_rd_addr, + ocm_rd_data, + ocm_rd_bytes + + + +); + +input sw_clk; +input rstn; +input [3:0] w_qos_hp0; +input [3:0] r_qos_hp0; +input [3:0] w_qos_hp1; +input [3:0] r_qos_hp1; +input [3:0] w_qos_hp2; +input [3:0] r_qos_hp2; +input [3:0] w_qos_hp3; +input [3:0] r_qos_hp3; + +output [3:0] ddr_rd_qos0; +output [3:0] ddr_wr_qos0; +output [3:0] ddr_rd_qos1; +output [3:0] ddr_wr_qos1; +output [3:0] ocm_wr_qos; +output [3:0] ocm_rd_qos; + +output wr_ack_ddr_hp0; +input [1023:0] wr_data_hp0; +input [31:0] wr_addr_hp0; +input [7:0] wr_bytes_hp0; +output wr_dv_ddr_hp0; + +input rd_req_ddr_hp0; +input [31:0] rd_addr_hp0; +input [7:0] rd_bytes_hp0; +output [1023:0] rd_data_ddr_hp0; +output rd_dv_ddr_hp0; + +output wr_ack_ddr_hp1; +input [1023:0] wr_data_hp1; +input [31:0] wr_addr_hp1; +input [7:0] wr_bytes_hp1; +output wr_dv_ddr_hp1; + +input rd_req_ddr_hp1; +input [31:0] rd_addr_hp1; +input [7:0] rd_bytes_hp1; +output [1023:0] rd_data_ddr_hp1; +output rd_dv_ddr_hp1; + +output wr_ack_ddr_hp2; +input [1023:0] wr_data_hp2; +input [31:0] wr_addr_hp2; +input [7:0] wr_bytes_hp2; +output wr_dv_ddr_hp2; + +input rd_req_ddr_hp2; +input [31:0] rd_addr_hp2; +input [7:0] rd_bytes_hp2; +output [1023:0] rd_data_ddr_hp2; +output rd_dv_ddr_hp2; + +output wr_ack_ddr_hp3; +input [1023:0] wr_data_hp3; +input [31:0] wr_addr_hp3; +input [7:0] wr_bytes_hp3; +output wr_dv_ddr_hp3; + +input rd_req_ddr_hp3; +input [31:0] rd_addr_hp3; +input [7:0] rd_bytes_hp3; +output [1023:0] rd_data_ddr_hp3; +output rd_dv_ddr_hp3; + +input ddr_wr_ack0; +output ddr_wr_dv0; +output [31:0]ddr_wr_addr0; +output [1023:0]ddr_wr_data0; +output [7:0]ddr_wr_bytes0; + +input ddr_rd_dv0; +input [1023:0] ddr_rd_data0; +output ddr_rd_req0; +output [31:0] ddr_rd_addr0; +output [7:0] ddr_rd_bytes0; + +input ddr_wr_ack1; +output ddr_wr_dv1; +output [31:0]ddr_wr_addr1; +output [1023:0]ddr_wr_data1; +output [7:0]ddr_wr_bytes1; + +input ddr_rd_dv1; +input [1023:0] ddr_rd_data1; +output ddr_rd_req1; +output [31:0] ddr_rd_addr1; +output [7:0] ddr_rd_bytes1; + +output wr_ack_ocm_hp0; +input wr_dv_ocm_hp0; +input rd_req_ocm_hp0; +output rd_dv_ocm_hp0; +output [1023:0] rd_data_ocm_hp0; + +output wr_ack_ocm_hp1; +input wr_dv_ocm_hp1; +input rd_req_ocm_hp1; +output rd_dv_ocm_hp1; +output [1023:0] rd_data_ocm_hp1; + +output wr_ack_ocm_hp2; +input wr_dv_ocm_hp2; +input rd_req_ocm_hp2; +output rd_dv_ocm_hp2; +output [1023:0] rd_data_ocm_hp2; + +output wr_ack_ocm_hp3; +input wr_dv_ocm_hp3; +input rd_req_ocm_hp3; +output rd_dv_ocm_hp3; +output [1023:0] rd_data_ocm_hp3; + +input ocm_wr_ack; +output ocm_wr_dv; +output [31:0]ocm_wr_addr; +output [1023:0]ocm_wr_data; +output [7:0]ocm_wr_bytes; + +input ocm_rd_dv; +input [1023:0] ocm_rd_data; +output ocm_rd_req; +output [31:0] ocm_rd_addr; +output [7:0] ocm_rd_bytes; + +/* FOR DDR */ +processing_system7_bfm_v2_0_arb_hp0_1 ddr_hp01 ( + .sw_clk(sw_clk), + .rstn(rstn), + .w_qos_hp0(w_qos_hp0), + .r_qos_hp0(r_qos_hp0), + .w_qos_hp1(w_qos_hp1), + .r_qos_hp1(r_qos_hp1), + + .wr_ack_ddr_hp0(wr_ack_ddr_hp0), + .wr_data_hp0(wr_data_hp0), + .wr_addr_hp0(wr_addr_hp0), + .wr_bytes_hp0(wr_bytes_hp0), + .wr_dv_ddr_hp0(wr_dv_ddr_hp0), + .rd_req_ddr_hp0(rd_req_ddr_hp0), + .rd_addr_hp0(rd_addr_hp0), + .rd_bytes_hp0(rd_bytes_hp0), + .rd_data_ddr_hp0(rd_data_ddr_hp0), + .rd_dv_ddr_hp0(rd_dv_ddr_hp0), + + .wr_ack_ddr_hp1(wr_ack_ddr_hp1), + .wr_data_hp1(wr_data_hp1), + .wr_addr_hp1(wr_addr_hp1), + .wr_bytes_hp1(wr_bytes_hp1), + .wr_dv_ddr_hp1(wr_dv_ddr_hp1), + .rd_req_ddr_hp1(rd_req_ddr_hp1), + .rd_addr_hp1(rd_addr_hp1), + .rd_bytes_hp1(rd_bytes_hp1), + .rd_data_ddr_hp1(rd_data_ddr_hp1), + .rd_dv_ddr_hp1(rd_dv_ddr_hp1), + + .ddr_wr_ack(ddr_wr_ack0), + .ddr_wr_dv(ddr_wr_dv0), + .ddr_rd_req(ddr_rd_req0), + .ddr_rd_dv(ddr_rd_dv0), + .ddr_rd_qos(ddr_rd_qos0), + .ddr_wr_qos(ddr_wr_qos0), + .ddr_wr_addr(ddr_wr_addr0), + .ddr_wr_data(ddr_wr_data0), + .ddr_wr_bytes(ddr_wr_bytes0), + .ddr_rd_addr(ddr_rd_addr0), + .ddr_rd_data(ddr_rd_data0), + .ddr_rd_bytes(ddr_rd_bytes0) +); + +/* FOR DDR */ +processing_system7_bfm_v2_0_arb_hp2_3 ddr_hp23 ( + .sw_clk(sw_clk), + .rstn(rstn), + .w_qos_hp2(w_qos_hp2), + .r_qos_hp2(r_qos_hp2), + .w_qos_hp3(w_qos_hp3), + .r_qos_hp3(r_qos_hp3), + + .wr_ack_ddr_hp2(wr_ack_ddr_hp2), + .wr_data_hp2(wr_data_hp2), + .wr_addr_hp2(wr_addr_hp2), + .wr_bytes_hp2(wr_bytes_hp2), + .wr_dv_ddr_hp2(wr_dv_ddr_hp2), + .rd_req_ddr_hp2(rd_req_ddr_hp2), + .rd_addr_hp2(rd_addr_hp2), + .rd_bytes_hp2(rd_bytes_hp2), + .rd_data_ddr_hp2(rd_data_ddr_hp2), + .rd_dv_ddr_hp2(rd_dv_ddr_hp2), + + .wr_ack_ddr_hp3(wr_ack_ddr_hp3), + .wr_data_hp3(wr_data_hp3), + .wr_addr_hp3(wr_addr_hp3), + .wr_bytes_hp3(wr_bytes_hp3), + .wr_dv_ddr_hp3(wr_dv_ddr_hp3), + .rd_req_ddr_hp3(rd_req_ddr_hp3), + .rd_addr_hp3(rd_addr_hp3), + .rd_bytes_hp3(rd_bytes_hp3), + .rd_data_ddr_hp3(rd_data_ddr_hp3), + .rd_dv_ddr_hp3(rd_dv_ddr_hp3), + + .ddr_wr_ack(ddr_wr_ack1), + .ddr_wr_dv(ddr_wr_dv1), + .ddr_rd_req(ddr_rd_req1), + .ddr_rd_dv(ddr_rd_dv1), + .ddr_rd_qos(ddr_rd_qos1), + .ddr_wr_qos(ddr_wr_qos1), + + .ddr_wr_addr(ddr_wr_addr1), + .ddr_wr_data(ddr_wr_data1), + .ddr_wr_bytes(ddr_wr_bytes1), + .ddr_rd_addr(ddr_rd_addr1), + .ddr_rd_data(ddr_rd_data1), + .ddr_rd_bytes(ddr_rd_bytes1) +); + + +/* FOR OCM_WR */ +processing_system7_bfm_v2_0_arb_wr_4 ocm_wr_hp( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(w_qos_hp0), + .qos2(w_qos_hp1), + .qos3(w_qos_hp2), + .qos4(w_qos_hp3), + + .prt_dv1(wr_dv_ocm_hp0), + .prt_dv2(wr_dv_ocm_hp1), + .prt_dv3(wr_dv_ocm_hp2), + .prt_dv4(wr_dv_ocm_hp3), + + .prt_data1(wr_data_hp0), + .prt_data2(wr_data_hp1), + .prt_data3(wr_data_hp2), + .prt_data4(wr_data_hp3), + + .prt_addr1(wr_addr_hp0), + .prt_addr2(wr_addr_hp1), + .prt_addr3(wr_addr_hp2), + .prt_addr4(wr_addr_hp3), + + .prt_bytes1(wr_bytes_hp0), + .prt_bytes2(wr_bytes_hp1), + .prt_bytes3(wr_bytes_hp2), + .prt_bytes4(wr_bytes_hp3), + + .prt_ack1(wr_ack_ocm_hp0), + .prt_ack2(wr_ack_ocm_hp1), + .prt_ack3(wr_ack_ocm_hp2), + .prt_ack4(wr_ack_ocm_hp3), + + .prt_qos(ocm_wr_qos), + .prt_req(ocm_wr_dv), + .prt_data(ocm_wr_data), + .prt_addr(ocm_wr_addr), + .prt_bytes(ocm_wr_bytes), + .prt_ack(ocm_wr_ack) + +); + +/* FOR OCM_RD */ +processing_system7_bfm_v2_0_arb_rd_4 ocm_rd_hp( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(r_qos_hp0), + .qos2(r_qos_hp1), + .qos3(r_qos_hp2), + .qos4(r_qos_hp3), + + .prt_req1(rd_req_ocm_hp0), + .prt_req2(rd_req_ocm_hp1), + .prt_req3(rd_req_ocm_hp2), + .prt_req4(rd_req_ocm_hp3), + + .prt_data1(rd_data_ocm_hp0), + .prt_data2(rd_data_ocm_hp1), + .prt_data3(rd_data_ocm_hp2), + .prt_data4(rd_data_ocm_hp3), + + .prt_addr1(rd_addr_hp0), + .prt_addr2(rd_addr_hp1), + .prt_addr3(rd_addr_hp2), + .prt_addr4(rd_addr_hp3), + + .prt_bytes1(rd_bytes_hp0), + .prt_bytes2(rd_bytes_hp1), + .prt_bytes3(rd_bytes_hp2), + .prt_bytes4(rd_bytes_hp3), + + .prt_dv1(rd_dv_ocm_hp0), + .prt_dv2(rd_dv_ocm_hp1), + .prt_dv3(rd_dv_ocm_hp2), + .prt_dv4(rd_dv_ocm_hp3), + + .prt_qos(ocm_rd_qos), + .prt_req(ocm_rd_req), + .prt_data(ocm_rd_data), + .prt_addr(ocm_rd_addr), + .prt_bytes(ocm_rd_bytes), + .prt_dv(ocm_rd_dv) + +); + + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_unused_ports.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_unused_ports.v new file mode 100644 index 0000000..9b096f9 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_unused_ports.v @@ -0,0 +1,433 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_unused_ports.v + * + * Date : 2012-11 + * + * Description : Semantic checks for unused ports. + * + *****************************************************************************/ + +/* CAN */ +assign CAN0_PHY_TX = 0; +assign CAN1_PHY_TX = 0; +always @(CAN0_PHY_RX or CAN1_PHY_RX) +begin + if(CAN0_PHY_RX | CAN1_PHY_RX) + $display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* ETHERNET */ +/* ------------------------------------------- */ + +assign ENET0_GMII_TX_EN = 0; +assign ENET0_GMII_TX_ER = 0; +assign ENET0_MDIO_MDC = 0; +assign ENET0_MDIO_O = 0; /// confirm +assign ENET0_MDIO_T = 0; +assign ENET0_PTP_DELAY_REQ_RX = 0; +assign ENET0_PTP_DELAY_REQ_TX = 0; +assign ENET0_PTP_PDELAY_REQ_RX = 0; +assign ENET0_PTP_PDELAY_REQ_TX = 0; +assign ENET0_PTP_PDELAY_RESP_RX = 0; +assign ENET0_PTP_PDELAY_RESP_TX = 0; +assign ENET0_PTP_SYNC_FRAME_RX = 0; +assign ENET0_PTP_SYNC_FRAME_TX = 0; +assign ENET0_SOF_RX = 0; +assign ENET0_SOF_TX = 0; +assign ENET0_GMII_TXD = 0; +always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or + ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or + ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD) +begin + if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN | + ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER | + ENET0_GMII_TX_CLK | ENET0_MDIO_I ) + $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR); +end + +assign ENET1_GMII_TX_EN = 0; +assign ENET1_GMII_TX_ER = 0; +assign ENET1_MDIO_MDC = 0; +assign ENET1_MDIO_O = 0;/// confirm +assign ENET1_MDIO_T = 0; +assign ENET1_PTP_DELAY_REQ_RX = 0; +assign ENET1_PTP_DELAY_REQ_TX = 0; +assign ENET1_PTP_PDELAY_REQ_RX = 0; +assign ENET1_PTP_PDELAY_REQ_TX = 0; +assign ENET1_PTP_PDELAY_RESP_RX = 0; +assign ENET1_PTP_PDELAY_RESP_TX = 0; +assign ENET1_PTP_SYNC_FRAME_RX = 0; +assign ENET1_PTP_SYNC_FRAME_TX = 0; +assign ENET1_SOF_RX = 0; +assign ENET1_SOF_TX = 0; +assign ENET1_GMII_TXD = 0; +always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or + ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or + ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD) +begin + if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN | + ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER | + ENET1_GMII_TX_CLK | ENET1_MDIO_I ) + $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* GPIO */ +/* ------------------------------------------- */ + +assign GPIO_O = 0; +assign GPIO_T = 0; +always@(GPIO_I) +begin +if(GPIO_I !== 0) + $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* I2C */ +/* ------------------------------------------- */ + +assign I2C0_SDA_O = 0; +assign I2C0_SDA_T = 0; +assign I2C0_SCL_O = 0; +assign I2C0_SCL_T = 0; +assign I2C1_SDA_O = 0; +assign I2C1_SDA_T = 0; +assign I2C1_SCL_O = 0; +assign I2C1_SCL_T = 0; +always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I ) +begin + if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I) + $display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* JTAG */ +/* ------------------------------------------- */ + +assign PJTAG_TD_T = 0; +assign PJTAG_TD_O = 0; +always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I) +begin + if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I) + $display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* SDIO */ +/* ------------------------------------------- */ + +assign SDIO0_CLK = 0; +assign SDIO0_CMD_O = 0; +assign SDIO0_CMD_T = 0; +assign SDIO0_DATA_O = 0; +assign SDIO0_DATA_T = 0; +assign SDIO0_LED = 0; +assign SDIO0_BUSPOW = 0; +assign SDIO0_BUSVOLT = 0; +always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP ) +begin + if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP ) + $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR); +end + +assign SDIO1_CLK = 0; +assign SDIO1_CMD_O = 0; +assign SDIO1_CMD_T = 0; +assign SDIO1_DATA_O = 0; +assign SDIO1_DATA_T = 0; +assign SDIO1_LED = 0; +assign SDIO1_BUSPOW = 0; +assign SDIO1_BUSVOLT = 0; +always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP ) +begin + if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP ) + $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* SPI */ +/* ------------------------------------------- */ + +assign SPI0_SCLK_O = 0; +assign SPI0_SCLK_T = 0; +assign SPI0_MOSI_O = 0; +assign SPI0_MOSI_T = 0; +assign SPI0_MISO_O = 0; +assign SPI0_MISO_T = 0; +assign SPI0_SS_O = 0; /// confirm +assign SPI0_SS1_O = 0;/// confirm +assign SPI0_SS2_O = 0;/// confirm +assign SPI0_SS_T = 0; +always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I) +begin + if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I) + $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR); +end + +assign SPI1_SCLK_O = 0; +assign SPI1_SCLK_T = 0; +assign SPI1_MOSI_O = 0; +assign SPI1_MOSI_T = 0; +assign SPI1_MISO_O = 0; +assign SPI1_MISO_T = 0; +assign SPI1_SS_O = 0; +assign SPI1_SS1_O = 0; +assign SPI1_SS2_O = 0; +assign SPI1_SS_T = 0; +always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I) +begin + if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I) + $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* UART */ +/* ------------------------------------------- */ +/// confirm +assign UART0_DTRN = 0; +assign UART0_RTSN = 0; +assign UART0_TX = 0; +always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX) +begin + if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX) + $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR); +end + +assign UART1_DTRN = 0; +assign UART1_RTSN = 0; +assign UART1_TX = 0; +always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX) +begin + if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX) + $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* TTC */ +/* ------------------------------------------- */ + +assign TTC0_WAVE0_OUT = 0; +assign TTC0_WAVE1_OUT = 0; +assign TTC0_WAVE2_OUT = 0; +always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN) +begin + if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN) + $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR); +end + +assign TTC1_WAVE0_OUT = 0; +assign TTC1_WAVE1_OUT = 0; +assign TTC1_WAVE2_OUT = 0; +always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN) +begin + if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN) + $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* WDT */ +/* ------------------------------------------- */ + +assign WDT_RST_OUT = 0; +always@(WDT_CLK_IN) +begin + if(WDT_CLK_IN) + $display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* TRACE */ +/* ------------------------------------------- */ + +assign TRACE_CTL = 0; +assign TRACE_DATA = 0; +always@(TRACE_CLK) +begin + if(TRACE_CLK) + $display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* USB */ +/* ------------------------------------------- */ +assign USB0_PORT_INDCTL = 0; +assign USB0_VBUS_PWRSELECT = 0; +always@(USB0_VBUS_PWRFAULT) +begin + if(USB0_VBUS_PWRFAULT) + $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR); +end + +assign USB1_PORT_INDCTL = 0; +assign USB1_VBUS_PWRSELECT = 0; +always@(USB1_VBUS_PWRFAULT) +begin + if(USB1_VBUS_PWRFAULT) + $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR); +end + +always@(SRAM_INTIN) +begin + if(SRAM_INTIN) + $display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* DMA */ +/* ------------------------------------------- */ + +assign DMA0_DATYPE = 0; +assign DMA0_DAVALID = 0; +assign DMA0_DRREADY = 0; +assign DMA0_RSTN = 0; +always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE) +begin + if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +assign DMA1_DATYPE = 0; +assign DMA1_DAVALID = 0; +assign DMA1_DRREADY = 0; +assign DMA1_RSTN = 0; +always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE) +begin + if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +assign DMA2_DATYPE = 0; +assign DMA2_DAVALID = 0; +assign DMA2_DRREADY = 0; +assign DMA2_RSTN = 0; +always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE) +begin + if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +assign DMA3_DATYPE = 0; +assign DMA3_DAVALID = 0; +assign DMA3_DRREADY = 0; +assign DMA3_RSTN = 0; +always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE) +begin + if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* FTM */ +/* ------------------------------------------- */ + +assign FTMT_F2P_TRIGACK = 0; +assign FTMT_P2F_TRIG = 0; +assign FTMT_P2F_DEBUG = 0; +always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or + FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK) +begin + if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK) + $display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* EVENT */ +/* ------------------------------------------- */ + +assign EVENT_EVENTO = 0; +assign EVENT_STANDBYWFE = 0; +assign EVENT_STANDBYWFI = 0; +always@(EVENT_EVENTI) +begin + if(EVENT_EVENTI) + $display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* MIO */ +/* ------------------------------------------- */ + +always@(MIO) +begin + if(MIO !== 0) + $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* FCLK_TRIG */ +/* ------------------------------------------- */ + +always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N ) +begin + if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N ) + $display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* MISC */ +/* ------------------------------------------- */ + +always@(FPGA_IDLE_N) +begin + if(FPGA_IDLE_N) + $display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR); +end + +always@(DDR_ARB) +begin + if(DDR_ARB !== 0) + $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR); +end + +always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ ) +begin + if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ) + $display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* DDR */ +/* ------------------------------------------- */ + +assign DDR_WEB = 0; +always@(DDR_Clk or DDR_CS_n) +begin +if(!DDR_CS_n) + $display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* IRQ_P2F */ +/* ------------------------------------------- */ + +assign IRQ_P2F_DMAC_ABORT = 0; +assign IRQ_P2F_DMAC0 = 0; +assign IRQ_P2F_DMAC1 = 0; +assign IRQ_P2F_DMAC2 = 0; +assign IRQ_P2F_DMAC3 = 0; +assign IRQ_P2F_DMAC4 = 0; +assign IRQ_P2F_DMAC5 = 0; +assign IRQ_P2F_DMAC6 = 0; +assign IRQ_P2F_DMAC7 = 0; +assign IRQ_P2F_SMC = 0; +assign IRQ_P2F_QSPI = 0; +assign IRQ_P2F_CTI = 0; +assign IRQ_P2F_GPIO = 0; +assign IRQ_P2F_USB0 = 0; +assign IRQ_P2F_ENET0 = 0; +assign IRQ_P2F_ENET_WAKE0 = 0; +assign IRQ_P2F_SDIO0 = 0; +assign IRQ_P2F_I2C0 = 0; +assign IRQ_P2F_SPI0 = 0; +assign IRQ_P2F_UART0 = 0; +assign IRQ_P2F_CAN0 = 0; +assign IRQ_P2F_USB1 = 0; +assign IRQ_P2F_ENET1 = 0; +assign IRQ_P2F_ENET_WAKE1 = 0; +assign IRQ_P2F_SDIO1 = 0; +assign IRQ_P2F_I2C1 = 0; +assign IRQ_P2F_SPI1 = 0; +assign IRQ_P2F_UART1 = 0; +assign IRQ_P2F_CAN1 = 0; diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/fixedio.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/fixedio.xml new file mode 100644 index 0000000..565966e --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/fixedio.xml @@ -0,0 +1,10 @@ + + + xilinx.com + display_processing_system7 + fixedio + 1.0 + false + false + Zynq fixed IO interface consisting of ports with fixed locations + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/fixedio_rtl.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/fixedio_rtl.xml new file mode 100644 index 0000000..a390c88 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/fixedio_rtl.xml @@ -0,0 +1,106 @@ + + + xilinx.com + display_processing_system7 + fixedio_rtl + 1.0 + + + + MIO + Multiplexed IO + + + optional + 54 + inout + + + optional + 54 + inout + + + + + PS_SRSTB + Debug system reset + + + optional + 1 + inout + + + optional + 1 + inout + + + + + PS_CLK + System reference clock + + + optional + 1 + inout + + + optional + 1 + inout + + + + + PS_PORB + Power on reset + + + optional + 1 + inout + + + optional + 1 + inout + + + + + DDR_VRN + DCI voltage reference. Connect DDR_VRN to a resister to VCC_DDR + + + optional + 1 + inout + + + optional + 1 + inout + + + + + DDR_VRP + DCI voltage reference. Connect DDR_VRP to a resistor to GND + + + optional + 1 + inout + + + optional + 1 + inout + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_atc.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_atc.v new file mode 100644 index 0000000..98caca1 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_atc.v @@ -0,0 +1,409 @@ +//----------------------------------------------------------------------------- +//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved. +//-- +//-- This file contains confidential and proprietary information +//-- of Xilinx, Inc. and is protected under U.S. and +//-- international copyright and other intellectual property +//-- laws. +//-- +//-- DISCLAIMER +//-- This disclaimer is not a license and does not grant any +//-- rights to the materials distributed herewith. Except as +//-- otherwise provided in a valid license issued to you by +//-- Xilinx, and to the maximum extent permitted by applicable +//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +//-- (2) Xilinx shall not be liable (whether in contract or tort, +//-- including negligence, or under any other theory of +//-- liability) for any loss or damage of any kind or nature +//-- related to, arising under or in connection with these +//-- materials, including for any direct, or any indirect, +//-- special, incidental, or consequential loss or damage +//-- (including loss of data, profits, goodwill, or any type of +//-- loss or damage suffered as a result of any action brought +//-- by a third party) even if such damage or loss was +//-- reasonably foreseeable or Xilinx had been advised of the +//-- possibility of the same. +//-- +//-- CRITICAL APPLICATIONS +//-- Xilinx products are not designed or intended to be fail- +//-- safe, or for use in any application requiring fail-safe +//-- performance, such as life-support or safety devices or +//-- systems, Class III medical devices, nuclear facilities, +//-- applications related to the deployment of airbags, or any +//-- other applications that could lead to death, personal +//-- injury, or severe property or environmental damage +//-- (individually and collectively, "Critical +//-- Applications"). Customer assumes the sole risk and +//-- liability of any use of Xilinx products in Critical +//-- Applications, subject only to applicable laws and +//-- regulations governing limitations on product liability. +//-- +//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +//-- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: ACP Transaction Checker +// +// Check for optimized ACP transactions and flag if they are broken. +// +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// atc +// aw_atc +// w_atc +// b_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps +`default_nettype none + +module processing_system7_v5_5_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_ADDR_WIDTH = 32, + // Width of all ADDR signals on SI and MI side of checker. + // Range: 32. + parameter integer C_AXI_DATA_WIDTH = 64, + // Width of all DATA signals on SI and MI side of checker. + // Range: 64. + parameter integer C_AXI_AWUSER_WIDTH = 1, + // Width of AWUSER signals. + // Range: >= 1. + parameter integer C_AXI_ARUSER_WIDTH = 1, + // Width of ARUSER signals. + // Range: >= 1. + parameter integer C_AXI_WUSER_WIDTH = 1, + // Width of WUSER signals. + // Range: >= 1. + parameter integer C_AXI_RUSER_WIDTH = 1, + // Width of RUSER signals. + // Range: >= 1. + parameter integer C_AXI_BUSER_WIDTH = 1 + // Width of BUSER signals. + // Range: >= 1. + ) + ( + // Global Signals + input wire ACLK, + input wire ARESETN, + + // Slave Interface Write Address Ports + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, + input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, + input wire [4-1:0] S_AXI_AWLEN, + input wire [3-1:0] S_AXI_AWSIZE, + input wire [2-1:0] S_AXI_AWBURST, + input wire [2-1:0] S_AXI_AWLOCK, + input wire [4-1:0] S_AXI_AWCACHE, + input wire [3-1:0] S_AXI_AWPROT, + input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, + input wire S_AXI_AWVALID, + output wire S_AXI_AWREADY, + // Slave Interface Write Data Ports + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID, + input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, + input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, + input wire S_AXI_WLAST, + input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, + input wire S_AXI_WVALID, + output wire S_AXI_WREADY, + // Slave Interface Write Response Ports + output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, + output wire [2-1:0] S_AXI_BRESP, + output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, + output wire S_AXI_BVALID, + input wire S_AXI_BREADY, + // Slave Interface Read Address Ports + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, + input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, + input wire [4-1:0] S_AXI_ARLEN, + input wire [3-1:0] S_AXI_ARSIZE, + input wire [2-1:0] S_AXI_ARBURST, + input wire [2-1:0] S_AXI_ARLOCK, + input wire [4-1:0] S_AXI_ARCACHE, + input wire [3-1:0] S_AXI_ARPROT, + input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, + input wire S_AXI_ARVALID, + output wire S_AXI_ARREADY, + // Slave Interface Read Data Ports + output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID, + output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, + output wire [2-1:0] S_AXI_RRESP, + output wire S_AXI_RLAST, + output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, + output wire S_AXI_RVALID, + input wire S_AXI_RREADY, + + // Master Interface Write Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, + output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, + output wire [4-1:0] M_AXI_AWLEN, + output wire [3-1:0] M_AXI_AWSIZE, + output wire [2-1:0] M_AXI_AWBURST, + output wire [2-1:0] M_AXI_AWLOCK, + output wire [4-1:0] M_AXI_AWCACHE, + output wire [3-1:0] M_AXI_AWPROT, + output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, + output wire M_AXI_AWVALID, + input wire M_AXI_AWREADY, + // Master Interface Write Data Ports + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, + output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, + output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, + output wire M_AXI_WLAST, + output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, + output wire M_AXI_WVALID, + input wire M_AXI_WREADY, + // Master Interface Write Response Ports + input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, + input wire [2-1:0] M_AXI_BRESP, + input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, + input wire M_AXI_BVALID, + output wire M_AXI_BREADY, + // Master Interface Read Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID, + output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, + output wire [4-1:0] M_AXI_ARLEN, + output wire [3-1:0] M_AXI_ARSIZE, + output wire [2-1:0] M_AXI_ARBURST, + output wire [2-1:0] M_AXI_ARLOCK, + output wire [4-1:0] M_AXI_ARCACHE, + output wire [3-1:0] M_AXI_ARPROT, + output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, + output wire M_AXI_ARVALID, + input wire M_AXI_ARREADY, + // Master Interface Read Data Ports + input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID, + input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, + input wire [2-1:0] M_AXI_RRESP, + input wire M_AXI_RLAST, + input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, + input wire M_AXI_RVALID, + output wire M_AXI_RREADY, + + output wire ERROR_TRIGGER, + output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + localparam C_FIFO_DEPTH_LOG = 4; + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Internal reset. + reg ARESET; + + // AW->W command queue signals. + wire cmd_w_valid; + wire cmd_w_check; + wire [C_AXI_ID_WIDTH-1:0] cmd_w_id; + wire cmd_w_ready; + + // W->B command queue signals. + wire cmd_b_push; + wire cmd_b_error; + wire [C_AXI_ID_WIDTH-1:0] cmd_b_id; + wire cmd_b_full; + wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr; + wire cmd_b_ready; + + + ///////////////////////////////////////////////////////////////////////////// + // Handle Internal Reset + ///////////////////////////////////////////////////////////////////////////// + always @ (posedge ACLK) begin + ARESET <= !ARESETN; + end + + + ///////////////////////////////////////////////////////////////////////////// + // Handle Write Channels (AW/W/B) + ///////////////////////////////////////////////////////////////////////////// + + // Write Address Channel. + processing_system7_v5_5_aw_atc # + ( + .C_FAMILY (C_FAMILY), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), + .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), + .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG) + ) write_addr_inst + ( + // Global Signals + .ARESET (ARESET), + .ACLK (ACLK), + + // Command Interface (Out) + .cmd_w_valid (cmd_w_valid), + .cmd_w_check (cmd_w_check), + .cmd_w_id (cmd_w_id), + .cmd_w_ready (cmd_w_ready), + .cmd_b_addr (cmd_b_addr), + .cmd_b_ready (cmd_b_ready), + + // Slave Interface Write Address Ports + .S_AXI_AWID (S_AXI_AWID), + .S_AXI_AWADDR (S_AXI_AWADDR), + .S_AXI_AWLEN (S_AXI_AWLEN), + .S_AXI_AWSIZE (S_AXI_AWSIZE), + .S_AXI_AWBURST (S_AXI_AWBURST), + .S_AXI_AWLOCK (S_AXI_AWLOCK), + .S_AXI_AWCACHE (S_AXI_AWCACHE), + .S_AXI_AWPROT (S_AXI_AWPROT), + .S_AXI_AWUSER (S_AXI_AWUSER), + .S_AXI_AWVALID (S_AXI_AWVALID), + .S_AXI_AWREADY (S_AXI_AWREADY), + + // Master Interface Write Address Port + .M_AXI_AWID (M_AXI_AWID), + .M_AXI_AWADDR (M_AXI_AWADDR), + .M_AXI_AWLEN (M_AXI_AWLEN), + .M_AXI_AWSIZE (M_AXI_AWSIZE), + .M_AXI_AWBURST (M_AXI_AWBURST), + .M_AXI_AWLOCK (M_AXI_AWLOCK), + .M_AXI_AWCACHE (M_AXI_AWCACHE), + .M_AXI_AWPROT (M_AXI_AWPROT), + .M_AXI_AWUSER (M_AXI_AWUSER), + .M_AXI_AWVALID (M_AXI_AWVALID), + .M_AXI_AWREADY (M_AXI_AWREADY) + ); + + // Write Data channel. + processing_system7_v5_5_w_atc # + ( + .C_FAMILY (C_FAMILY), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), + .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH) + ) write_data_inst + ( + // Global Signals + .ARESET (ARESET), + .ACLK (ACLK), + + // Command Interface (In) + .cmd_w_valid (cmd_w_valid), + .cmd_w_check (cmd_w_check), + .cmd_w_id (cmd_w_id), + .cmd_w_ready (cmd_w_ready), + + // Command Interface (Out) + .cmd_b_push (cmd_b_push), + .cmd_b_error (cmd_b_error), + .cmd_b_id (cmd_b_id), + .cmd_b_full (cmd_b_full), + + // Slave Interface Write Data Ports + .S_AXI_WID (S_AXI_WID), + .S_AXI_WDATA (S_AXI_WDATA), + .S_AXI_WSTRB (S_AXI_WSTRB), + .S_AXI_WLAST (S_AXI_WLAST), + .S_AXI_WUSER (S_AXI_WUSER), + .S_AXI_WVALID (S_AXI_WVALID), + .S_AXI_WREADY (S_AXI_WREADY), + + // Master Interface Write Data Ports + .M_AXI_WID (M_AXI_WID), + .M_AXI_WDATA (M_AXI_WDATA), + .M_AXI_WSTRB (M_AXI_WSTRB), + .M_AXI_WLAST (M_AXI_WLAST), + .M_AXI_WUSER (M_AXI_WUSER), + .M_AXI_WVALID (M_AXI_WVALID), + .M_AXI_WREADY (M_AXI_WREADY) + ); + + // Write Response channel. + processing_system7_v5_5_b_atc # + ( + .C_FAMILY (C_FAMILY), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), + .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG) + ) write_response_inst + ( + // Global Signals + .ARESET (ARESET), + .ACLK (ACLK), + + // Command Interface (In) + .cmd_b_push (cmd_b_push), + .cmd_b_error (cmd_b_error), + .cmd_b_id (cmd_b_id), + .cmd_b_full (cmd_b_full), + .cmd_b_addr (cmd_b_addr), + .cmd_b_ready (cmd_b_ready), + + // Slave Interface Write Response Ports + .S_AXI_BID (S_AXI_BID), + .S_AXI_BRESP (S_AXI_BRESP), + .S_AXI_BUSER (S_AXI_BUSER), + .S_AXI_BVALID (S_AXI_BVALID), + .S_AXI_BREADY (S_AXI_BREADY), + + // Master Interface Write Response Ports + .M_AXI_BID (M_AXI_BID), + .M_AXI_BRESP (M_AXI_BRESP), + .M_AXI_BUSER (M_AXI_BUSER), + .M_AXI_BVALID (M_AXI_BVALID), + .M_AXI_BREADY (M_AXI_BREADY), + + // Trigger detection + .ERROR_TRIGGER (ERROR_TRIGGER), + .ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID) + ); + + + + ///////////////////////////////////////////////////////////////////////////// + // Handle Read Channels (AR/R) + ///////////////////////////////////////////////////////////////////////////// + // Read Address Port + assign M_AXI_ARID = S_AXI_ARID; + assign M_AXI_ARADDR = S_AXI_ARADDR; + assign M_AXI_ARLEN = S_AXI_ARLEN; + assign M_AXI_ARSIZE = S_AXI_ARSIZE; + assign M_AXI_ARBURST = S_AXI_ARBURST; + assign M_AXI_ARLOCK = S_AXI_ARLOCK; + assign M_AXI_ARCACHE = S_AXI_ARCACHE; + assign M_AXI_ARPROT = S_AXI_ARPROT; + assign M_AXI_ARUSER = S_AXI_ARUSER; + assign M_AXI_ARVALID = S_AXI_ARVALID; + assign S_AXI_ARREADY = M_AXI_ARREADY; + + // Read Data Port + assign S_AXI_RID = M_AXI_RID; + assign S_AXI_RDATA = M_AXI_RDATA; + assign S_AXI_RRESP = M_AXI_RRESP; + assign S_AXI_RLAST = M_AXI_RLAST; + assign S_AXI_RUSER = M_AXI_RUSER; + assign S_AXI_RVALID = M_AXI_RVALID; + assign M_AXI_RREADY = S_AXI_RREADY; + + +endmodule +`default_nettype wire diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_aw_atc.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_aw_atc.v new file mode 100644 index 0000000..25bbc9d --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_aw_atc.v @@ -0,0 +1,298 @@ +// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: Address Write Channel for ATC +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// aw_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps + + +module processing_system7_v5_5_aw_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_ADDR_WIDTH = 32, + // Width of all ADDR signals on SI and MI side of checker. + // Range: 32. + parameter integer C_AXI_AWUSER_WIDTH = 1, + // Width of AWUSER signals. + // Range: >= 1. + parameter integer C_FIFO_DEPTH_LOG = 4 + ) + ( + // Global Signals + input wire ARESET, + input wire ACLK, + + // Command Interface + output reg cmd_w_valid, + output wire cmd_w_check, + output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, + input wire cmd_w_ready, + input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, + input wire cmd_b_ready, + + // Slave Interface Write Address Port + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, + input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, + input wire [4-1:0] S_AXI_AWLEN, + input wire [3-1:0] S_AXI_AWSIZE, + input wire [2-1:0] S_AXI_AWBURST, + input wire [2-1:0] S_AXI_AWLOCK, + input wire [4-1:0] S_AXI_AWCACHE, + input wire [3-1:0] S_AXI_AWPROT, + input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, + input wire S_AXI_AWVALID, + output wire S_AXI_AWREADY, + + // Master Interface Write Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, + output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, + output wire [4-1:0] M_AXI_AWLEN, + output wire [3-1:0] M_AXI_AWSIZE, + output wire [2-1:0] M_AXI_AWBURST, + output wire [2-1:0] M_AXI_AWLOCK, + output wire [4-1:0] M_AXI_AWCACHE, + output wire [3-1:0] M_AXI_AWPROT, + output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, + output wire M_AXI_AWVALID, + input wire M_AXI_AWREADY + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + // Constants for burst types. + localparam [2-1:0] C_FIX_BURST = 2'b00; + localparam [2-1:0] C_INCR_BURST = 2'b01; + localparam [2-1:0] C_WRAP_BURST = 2'b10; + + // Constants for size. + localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011; + + // Constants for length. + localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011; + + // Constants for cacheline address. + localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0; + + // Command FIFO settings + localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; + localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; + + + ///////////////////////////////////////////////////////////////////////////// + // Variables for generating parameter controlled instances. + ///////////////////////////////////////////////////////////////////////////// + + integer index; + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Transaction properties. + wire access_is_incr; + wire access_is_wrap; + wire access_is_coherent; + wire access_optimized_size; + wire incr_addr_boundary; + wire incr_is_optimized; + wire wrap_is_optimized; + wire access_is_optimized; + + // Command FIFO. + wire cmd_w_push; + reg cmd_full; + reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; + wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr; + reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Decode: + // + // Detect if transaction is of correct typ, size and length to qualify as + // an optimized transaction that has to be checked for errors. + // + ///////////////////////////////////////////////////////////////////////////// + + // Transaction burst type. + assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST ); + assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST ); + + // Transaction has to be Coherent. + assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) & + ( S_AXI_AWCACHE[1] == 1'b1 ); + + // Transaction cacheline boundary address. + assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET ); + + // Transaction length & size. + assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & + ( S_AXI_AWLEN == C_OPTIMIZED_LEN ); + + // Transaction is optimized. + assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary; + assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size; + assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized ); + + + ///////////////////////////////////////////////////////////////////////////// + // Command FIFO: + // + // Since supported write interleaving is only 1, it is safe to use only a + // simple SRL based FIFO as a command queue. + // + ///////////////////////////////////////////////////////////////////////////// + + // Determine when transaction infromation is pushed to the FIFO. + assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full; + + // SRL FIFO Pointer. + always @ (posedge ACLK) begin + if (ARESET) begin + addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; + end else begin + if ( cmd_w_push & ~cmd_w_ready ) begin + addr_ptr <= addr_ptr + 1; + end else if ( ~cmd_w_push & cmd_w_ready ) begin + addr_ptr <= addr_ptr - 1; + end + end + end + + // Total number of buffered commands. + assign all_addr_ptr = addr_ptr + cmd_b_addr + 2; + + // FIFO Flags. + always @ (posedge ACLK) begin + if (ARESET) begin + cmd_full <= 1'b0; + cmd_w_valid <= 1'b0; + end else begin + if ( cmd_w_push & ~cmd_w_ready ) begin + cmd_w_valid <= 1'b1; + end else if ( ~cmd_w_push & cmd_w_ready ) begin + cmd_w_valid <= ( addr_ptr != 0 ); + end + if ( cmd_w_push & ~cmd_b_ready ) begin + // Going to full. + cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 ); + end else if ( ~cmd_w_push & cmd_b_ready ) begin + // Pop in middle of queue doesn't affect full status. + cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 ); + end + end + end + + // Infere SRL for storage. + always @ (posedge ACLK) begin + if ( cmd_w_push ) begin + for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin + data_srl[index+1] <= data_srl[index]; + end + data_srl[0] <= {access_is_optimized, S_AXI_AWID}; + end + end + + // Get current transaction info. + assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr]; + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Throttling: + // + // Stall commands if FIFO is full. + // + ///////////////////////////////////////////////////////////////////////////// + + // Propagate masked valid. + assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full; + + // Return ready with push back. + assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full; + + + ///////////////////////////////////////////////////////////////////////////// + // Address Write propagation: + // + // All information is simply forwarded on from the SI- to MI-Side untouched. + // + ///////////////////////////////////////////////////////////////////////////// + + // 1:1 mapping. + assign M_AXI_AWID = S_AXI_AWID; + assign M_AXI_AWADDR = S_AXI_AWADDR; + assign M_AXI_AWLEN = S_AXI_AWLEN; + assign M_AXI_AWSIZE = S_AXI_AWSIZE; + assign M_AXI_AWBURST = S_AXI_AWBURST; + assign M_AXI_AWLOCK = S_AXI_AWLOCK; + assign M_AXI_AWCACHE = S_AXI_AWCACHE; + assign M_AXI_AWPROT = S_AXI_AWPROT; + assign M_AXI_AWUSER = S_AXI_AWUSER; + + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_b_atc.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_b_atc.v new file mode 100644 index 0000000..36f280f --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_b_atc.v @@ -0,0 +1,413 @@ +// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: Write Response Channel for ATC +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// b_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps + + +module processing_system7_v5_5_b_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_BUSER_WIDTH = 1, + // Width of AWUSER signals. + // Range: >= 1. + parameter integer C_FIFO_DEPTH_LOG = 4 + ) + ( + // Global Signals + input wire ARESET, + input wire ACLK, + + // Command Interface + input wire cmd_b_push, + input wire cmd_b_error, + input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id, + output wire cmd_b_ready, + output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, + output reg cmd_b_full, + + // Slave Interface Write Response Ports + output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, + output reg [2-1:0] S_AXI_BRESP, + output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, + output wire S_AXI_BVALID, + input wire S_AXI_BREADY, + + // Master Interface Write Response Ports + input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, + input wire [2-1:0] M_AXI_BRESP, + input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, + input wire M_AXI_BVALID, + output wire M_AXI_BREADY, + + // Trigger detection + output reg ERROR_TRIGGER, + output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + // Constants for packing levels. + localparam [2-1:0] C_RESP_OKAY = 2'b00; + localparam [2-1:0] C_RESP_EXOKAY = 2'b01; + localparam [2-1:0] C_RESP_SLVERROR = 2'b10; + localparam [2-1:0] C_RESP_DECERR = 2'b11; + + // Command FIFO settings + localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; + localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; + + + ///////////////////////////////////////////////////////////////////////////// + // Variables for generating parameter controlled instances. + ///////////////////////////////////////////////////////////////////////////// + + integer index; + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Command Queue. + reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; + reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; + reg cmd_b_valid; + wire cmd_b_ready_i; + wire inject_error; + wire [C_AXI_ID_WIDTH-1:0] current_id; + + // Search command. + wire found_match; + wire use_match; + wire matching_id; + + // Manage valid command. + wire write_valid_cmd; + reg [C_FIFO_DEPTH-2:0] valid_cmd; + reg [C_FIFO_DEPTH-2:0] updated_valid_cmd; + reg [C_FIFO_DEPTH-2:0] next_valid_cmd; + reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr; + reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr; + + // Pipelined data + reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I; + reg [2-1:0] M_AXI_BRESP_I; + reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I; + reg M_AXI_BVALID_I; + wire M_AXI_BREADY_I; + + + ///////////////////////////////////////////////////////////////////////////// + // Command Queue: + // + // Keep track of depth of Queue to generate full flag. + // + // Also generate valid to mark pressence of commands in Queue. + // + // Maintain Queue and extract data from currently searched entry. + // + ///////////////////////////////////////////////////////////////////////////// + + // SRL FIFO Pointer. + always @ (posedge ACLK) begin + if (ARESET) begin + addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; + end else begin + if ( cmd_b_push & ~cmd_b_ready_i ) begin + // Pushing data increase length/addr. + addr_ptr <= addr_ptr + 1; + end else if ( cmd_b_ready_i ) begin + // Collapse addr when data is popped. + addr_ptr <= collapsed_addr_ptr; + end + end + end + + // FIFO Flags. + always @ (posedge ACLK) begin + if (ARESET) begin + cmd_b_full <= 1'b0; + cmd_b_valid <= 1'b0; + end else begin + if ( cmd_b_push & ~cmd_b_ready_i ) begin + cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 ); + cmd_b_valid <= 1'b1; + end else if ( ~cmd_b_push & cmd_b_ready_i ) begin + cmd_b_full <= 1'b0; + cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 ); + end + end + end + + // Infere SRL for storage. + always @ (posedge ACLK) begin + if ( cmd_b_push ) begin + for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin + data_srl[index+1] <= data_srl[index]; + end + data_srl[0] <= {cmd_b_error, cmd_b_id}; + end + end + + // Get current transaction info. + assign {inject_error, current_id} = data_srl[search_addr_ptr]; + + // Assign outputs. + assign cmd_b_addr = collapsed_addr_ptr; + + + ///////////////////////////////////////////////////////////////////////////// + // Search Command Queue: + // + // Search for matching valid command in queue. + // + // A command is found when an valid entry with correct ID is found. The queue + // is search from the oldest entry, i.e. from a high value. + // When new commands are pushed the search address has to be updated to always + // start the search from the oldest available. + // + ///////////////////////////////////////////////////////////////////////////// + + // Handle search addr. + always @ (posedge ACLK) begin + if (ARESET) begin + search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; + end else begin + if ( cmd_b_ready_i ) begin + // Collapse addr when data is popped. + search_addr_ptr <= collapsed_addr_ptr; + + end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin + // Skip non valid command. + search_addr_ptr <= search_addr_ptr - 1; + + end else if ( cmd_b_push ) begin + search_addr_ptr <= search_addr_ptr + 1; + + end + end + end + + // Check if searched command is valid and match ID (for existing response on MI side). + assign matching_id = ( M_AXI_BID_I == current_id ); + assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I; + assign use_match = found_match & S_AXI_BREADY; + + + ///////////////////////////////////////////////////////////////////////////// + // Track Used Commands: + // + // Actions that affect Valid Command: + // * When a new command is pushed + // => Shift valid vector one step + // * When a command is used + // => Clear corresponding valid bit + // + ///////////////////////////////////////////////////////////////////////////// + + // Valid command status is updated when a command is used or a new one is pushed. + assign write_valid_cmd = cmd_b_push | cmd_b_ready_i; + + // Update the used command valid bit. + always @ * + begin + updated_valid_cmd = valid_cmd; + updated_valid_cmd[search_addr_ptr] = ~use_match; + end + + // Shift valid vector when command is pushed. + always @ * + begin + if ( cmd_b_push ) begin + next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1}; + end else begin + next_valid_cmd = updated_valid_cmd; + end + end + + // Valid signals for next cycle. + always @ (posedge ACLK) begin + if (ARESET) begin + valid_cmd <= {C_FIFO_WIDTH{1'b0}}; + end else if ( write_valid_cmd ) begin + valid_cmd <= next_valid_cmd; + end + end + + // Detect oldest available command in Queue. + always @ * + begin + // Default to empty. + collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}}; + + for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin + if ( next_valid_cmd[index] ) begin + collapsed_addr_ptr = index; + end + end + end + + + ///////////////////////////////////////////////////////////////////////////// + // Pipe incoming data: + // + // The B channel is piped to improve timing and avoid impact in search + // mechanism due to late arriving signals. + // + ///////////////////////////////////////////////////////////////////////////// + + // Clock data. + always @ (posedge ACLK) begin + if (ARESET) begin + M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}}; + M_AXI_BRESP_I <= 2'b00; + M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}}; + M_AXI_BVALID_I <= 1'b0; + end else begin + if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin + M_AXI_BVALID_I <= 1'b0; + end + if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin + M_AXI_BID_I <= M_AXI_BID; + M_AXI_BRESP_I <= M_AXI_BRESP; + M_AXI_BUSER_I <= M_AXI_BUSER; + M_AXI_BVALID_I <= 1'b1; + end + end + end + + // Generate ready to get new transaction. + assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I; + + + ///////////////////////////////////////////////////////////////////////////// + // Inject Error: + // + // BRESP is modified according to command information. + // + ///////////////////////////////////////////////////////////////////////////// + + // Inject error in response. + always @ * + begin + if ( inject_error ) begin + S_AXI_BRESP = C_RESP_SLVERROR; + end else begin + S_AXI_BRESP = M_AXI_BRESP_I; + end + end + + // Handle interrupt generation. + always @ (posedge ACLK) begin + if (ARESET) begin + ERROR_TRIGGER <= 1'b0; + ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}}; + end else begin + if ( inject_error & cmd_b_ready_i ) begin + ERROR_TRIGGER <= 1'b1; + ERROR_TRANSACTION_ID <= M_AXI_BID_I; + end else begin + ERROR_TRIGGER <= 1'b0; + end + end + end + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Throttling: + // + // Response is passed forward when a matching entry has been found in queue. + // Both ready and valid are set when the command is completed. + // + ///////////////////////////////////////////////////////////////////////////// + + // Propagate masked valid. + assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match; + + // Return ready with push back. + assign M_AXI_BREADY_I = cmd_b_valid & use_match; + + // Command has been handled. + assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match; + assign cmd_b_ready = cmd_b_ready_i; + + + ///////////////////////////////////////////////////////////////////////////// + // Write Response Propagation: + // + // All information is simply forwarded on from MI- to SI-Side untouched. + // + ///////////////////////////////////////////////////////////////////////////// + + // 1:1 mapping. + assign S_AXI_BID = M_AXI_BID_I; + assign S_AXI_BUSER = M_AXI_BUSER_I; + + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_trace_buffer.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_trace_buffer.v new file mode 100644 index 0000000..0c776b3 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_trace_buffer.v @@ -0,0 +1,310 @@ +// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// Filename: trace_buffer.v +// Description: Trace port buffer +//----------------------------------------------------------------------------- +// Structure: This section shows the hierarchical structure of +// pss_wrapper. +// +// --processing_system7 +// | +// --trace_buffer +//----------------------------------------------------------------------------- + + +module processing_system7_v5_5_trace_buffer # + ( + parameter integer FIFO_SIZE = 128, + parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0, + parameter integer C_DELAY_CLKS = 12 + ) + ( + input wire TRACE_CLK, + input wire RST, + input wire TRACE_VALID_IN, + input wire [3:0] TRACE_ATID_IN, + input wire [31:0] TRACE_DATA_IN, + output wire TRACE_VALID_OUT, + output wire [3:0] TRACE_ATID_OUT, + output wire [31:0] TRACE_DATA_OUT + ); + +//------------------------------------------------------------ +// Architecture section +//------------------------------------------------------------ + +// function called clogb2 that returns an integer which has the +// value of the ceiling of the log base 2. + +function integer clogb2 (input integer bit_depth); + integer i; + integer temp_log; + begin + temp_log = 0; + for(i=bit_depth; i > 0; i = i>>1) + clogb2 = temp_log; + temp_log=temp_log+1; + end +endfunction + +localparam DEPTH = clogb2(FIFO_SIZE-1); + +wire [31:0] reset_zeros; +reg [31:0] trace_pedge; // write enable for FIFO +reg [31:0] ti; +reg [31:0] tom; + +reg [3:0] atid; + +reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory + +reg [4:0] dly_ctr; +reg [DEPTH-1:0] fifo_wp; +reg [DEPTH-1:0] fifo_rp; + +reg fifo_re; +wire fifo_empty; +wire fifo_full; +reg fifo_full_reg; + +assign reset_zeros = 32'h0; + + +// Pipeline Stage for Traceport ATID ports + always @(posedge TRACE_CLK) begin + // process pedge_ti + // rising clock edge + if((RST == 1'b1)) begin + atid <= reset_zeros; + end + else begin + atid <= TRACE_ATID_IN; + end + end + + assign TRACE_ATID_OUT = atid; + + ///////////////////////////////////////////// + // Generate FIFO data based on TRACE_VALID_IN + ///////////////////////////////////////////// + generate + if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector + ///////////////////////////////////////////// + + // memory update process + // Update memory when positive edge detected and FIFO not full + always @(posedge TRACE_CLK) begin + if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin + trace_fifo[fifo_wp] <= TRACE_DATA_IN; + end + end + + // fifo write pointer + always @(posedge TRACE_CLK) begin + // process + if(RST == 1'b1) begin + fifo_wp <= {DEPTH{1'b0}}; + end + else if(TRACE_VALID_IN ) begin + if(fifo_wp == (FIFO_SIZE - 1)) begin + if (fifo_empty) begin + fifo_wp <= {DEPTH{1'b0}}; + end + end + else begin + fifo_wp <= fifo_wp + 1; + end + end + end + + + ///////////////////////////////////////////// + // Generate FIFO data based on data edge + ///////////////////////////////////////////// + end else begin : gen_data_edge_detector + ///////////////////////////////////////////// + + + // purpose: check for pos edge on any trace input + always @(posedge TRACE_CLK) begin + // process pedge_ti + // rising clock edge + if((RST == 1'b1)) begin + ti <= reset_zeros; + trace_pedge <= reset_zeros; + end + else begin + ti <= TRACE_DATA_IN; + trace_pedge <= (~ti & TRACE_DATA_IN); + //trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti; + // posedge only + end + end + + // memory update process + // Update memory when positive edge detected and FIFO not full + always @(posedge TRACE_CLK) begin + if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin + trace_fifo[fifo_wp] <= trace_pedge; + end + end + + // fifo write pointer + always @(posedge TRACE_CLK) begin + // process + if(RST == 1'b1) begin + fifo_wp <= {DEPTH{1'b0}}; + end + else if(|(trace_pedge) == 1'b1) begin + if(fifo_wp == (FIFO_SIZE - 1)) begin + if (fifo_empty) begin + fifo_wp <= {DEPTH{1'b0}}; + end + end + else begin + fifo_wp <= fifo_wp + 1; + end + end + end + + + end + endgenerate + + + always @(posedge TRACE_CLK) begin + tom <= trace_fifo[fifo_rp] ; + end + + +// // fifo write pointer +// always @(posedge TRACE_CLK) begin +// // process +// if(RST == 1'b1) begin +// fifo_wp <= {DEPTH{1'b0}}; +// end +// else if(|(trace_pedge) == 1'b1) begin +// if(fifo_wp == (FIFO_SIZE - 1)) begin +// fifo_wp <= {DEPTH{1'b0}}; +// end +// else begin +// fifo_wp <= fifo_wp + 1; +// end +// end +// end + + + // fifo read pointer update + always @(posedge TRACE_CLK) begin + if(RST == 1'b1) begin + fifo_rp <= {DEPTH{1'b0}}; + fifo_re <= 1'b0; + end + else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin + fifo_re <= 1'b1; + if(fifo_rp == (FIFO_SIZE - 1)) begin + fifo_rp <= {DEPTH{1'b0}}; + end + else begin + fifo_rp <= fifo_rp + 1; + end + end + else begin + fifo_re <= 1'b0; + end + end + + // delay counter update + always @(posedge TRACE_CLK) begin + if(RST == 1'b1) begin + dly_ctr <= 5'h0; + end + else if (fifo_re == 1'b1) begin + dly_ctr <= C_DELAY_CLKS-1; + end + else if(dly_ctr != 5'h0) begin + dly_ctr <= dly_ctr - 1; + end + end + + // fifo empty update + assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0; + + // fifo full update + assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0; + + always @(posedge TRACE_CLK) begin + if(RST == 1'b1) begin + fifo_full_reg <= 1'b0; + end + else if (fifo_empty) begin + fifo_full_reg <= 1'b0; + end else begin + fifo_full_reg <= fifo_full; + end + end + +// always @(posedge TRACE_CLK) begin +// if(RST == 1'b1) begin +// fifo_full_reg <= 1'b0; +// end +// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin +// fifo_full_reg <= 1'b1; +// end +// else begin +// fifo_full_reg <= 1'b0; +// end +// end +// + assign TRACE_DATA_OUT = tom; + + assign TRACE_VALID_OUT = fifo_re; + + + + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_w_atc.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_w_atc.v new file mode 100644 index 0000000..8b19a70 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hdl/verilog/processing_system7_v5_5_w_atc.v @@ -0,0 +1,244 @@ +// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: Write Channel for ATC +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// w_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps + + +module processing_system7_v5_5_w_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_DATA_WIDTH = 64, + // Width of all DATA signals on SI and MI side of checker. + // Range: 64. + parameter integer C_AXI_WUSER_WIDTH = 1 + // Width of AWUSER signals. + // Range: >= 1. + ) + ( + // Global Signals + input wire ARESET, + input wire ACLK, + + // Command Interface (In) + input wire cmd_w_valid, + input wire cmd_w_check, + input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, + output wire cmd_w_ready, + + // Command Interface (Out) + output wire cmd_b_push, + output wire cmd_b_error, + output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id, + input wire cmd_b_full, + + // Slave Interface Write Port + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID, + input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, + input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, + input wire S_AXI_WLAST, + input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, + input wire S_AXI_WVALID, + output wire S_AXI_WREADY, + + // Master Interface Write Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, + output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, + output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, + output wire M_AXI_WLAST, + output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, + output wire M_AXI_WVALID, + input wire M_AXI_WREADY + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Variables for generating parameter controlled instances. + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Detecttion. + wire any_strb_deasserted; + wire incoming_strb_issue; + reg first_word; + reg strb_issue; + + // Data flow. + wire data_pop; + wire cmd_b_push_blocked; + reg cmd_b_push_i; + + + ///////////////////////////////////////////////////////////////////////////// + // Detect error: + // + // Detect and accumulate error when a transaction shall be scanned for + // potential issues. + // Accumulation of error is restarted for each ne transaction. + // + ///////////////////////////////////////////////////////////////////////////// + + // Check stobe information + assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} ); + assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted; + + // Keep track of first word in a transaction. + always @ (posedge ACLK) begin + if (ARESET) begin + first_word <= 1'b1; + end else if ( data_pop ) begin + first_word <= S_AXI_WLAST; + end + end + + // Keep track of error status. + always @ (posedge ACLK) begin + if (ARESET) begin + strb_issue <= 1'b0; + cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}}; + end else if ( data_pop ) begin + if ( first_word ) begin + strb_issue <= incoming_strb_issue; + end else begin + strb_issue <= incoming_strb_issue | strb_issue; + end + cmd_b_id <= cmd_w_id; + end + end + + assign cmd_b_error = strb_issue; + + + ///////////////////////////////////////////////////////////////////////////// + // Control command queue to B: + // + // Push command to B queue when all data for the transaction has flowed + // through. + // Delay pipelined command until there is room in the Queue. + // + ///////////////////////////////////////////////////////////////////////////// + + // Detect when data is popped. + assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; + + // Push command when last word in transfered (pipelined). + always @ (posedge ACLK) begin + if (ARESET) begin + cmd_b_push_i <= 1'b0; + end else begin + cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked; + end + end + + // Detect if pipelined push is blocked. + assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full; + + // Assign output. + assign cmd_b_push = cmd_b_push_i & ~cmd_b_full; + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Throttling: + // + // Stall commands if FIFO is full or there is no valid command information + // from AW. + // + ///////////////////////////////////////////////////////////////////////////// + + // Propagate masked valid. + assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; + + // Return ready with push back. + assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; + + // End of burst. + assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST; + + + ///////////////////////////////////////////////////////////////////////////// + // Write propagation: + // + // All information is simply forwarded on from the SI- to MI-Side untouched. + // + ///////////////////////////////////////////////////////////////////////////// + + // 1:1 mapping. + assign M_AXI_WID = S_AXI_WID; + assign M_AXI_WDATA = S_AXI_WDATA; + assign M_AXI_WSTRB = S_AXI_WSTRB; + assign M_AXI_WLAST = S_AXI_WLAST; + assign M_AXI_WUSER = S_AXI_WUSER; + + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hpstatusctrl.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hpstatusctrl.xml new file mode 100644 index 0000000..16ca7bc --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hpstatusctrl.xml @@ -0,0 +1,10 @@ + + + xilinx.com + display_processing_system7 + hpstatusctrl + 1.0 + false + false + Zynq HP status ctrl interface consists of FIFO occupancy and Interconnect Issuance Throttling signals for High performance axi interface + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hpstatusctrl_rtl.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hpstatusctrl_rtl.xml new file mode 100644 index 0000000..ddf2cbd --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hpstatusctrl_rtl.xml @@ -0,0 +1,106 @@ + + + xilinx.com + display_processing_system7 + hpstatusctrl_rtl + 1.0 + + + + RCOUNT + Fill level of the RdData Channel FIFO + + + optional + 8 + out + + + optional + 8 + in + + + + + WCOUNT + Fill level of the WrData Channel FIFO + + + optional + 8 + out + + + optional + 8 + in + + + + + RACOUNT + Fill level of the RdAddr Channel FIFO + + + optional + 3 + out + + + optional + 3 + in + + + + + WACOUNT + Fill level of the WrAddr Channel FIFO + + + optional + 6 + out + + + optional + 6 + in + + + + + RDISSUECAPEN + Enables Maximum Outstanding Read Commands Capability + + + optional + 1 + in + + + optional + 1 + out + + + + + WRISSUECAPEN + Enables Maximum Outstanding Write Commands Capability + + + optional + 1 + in + + + optional + 1 + out + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/jtag.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/jtag.xml new file mode 100644 index 0000000..8cbced8 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/jtag.xml @@ -0,0 +1,12 @@ + + + xilinx.com + interface + jtag + 2.0 + true + false + 1 + 1 + Provides debug access via a standard JTAG debug interface + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/jtag_rtl.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/jtag_rtl.xml new file mode 100644 index 0000000..2cb2f4d --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/jtag_rtl.xml @@ -0,0 +1,79 @@ + + + xilinx.com + interface + jtag_rtl + 2.0 + + + + TCK + + + true + + + required + 1 + out + + + required + 1 + in + + + + + TMS + + + required + 1 + out + + + required + 1 + in + + + + + TDI + + + true + + + required + 1 + out + + + required + 1 + in + + + + + TDO + + + true + + + required + 1 + in + + + required + 1 + out + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/usbctrl.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/usbctrl.xml new file mode 100644 index 0000000..987fa44 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/usbctrl.xml @@ -0,0 +1,10 @@ + + + xilinx.com + display_processing_system7 + usbctrl + 1.0 + false + false + The usbctrl interface consists of Port indicator and power signals + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/usbctrl_rtl.xml b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/usbctrl_rtl.xml new file mode 100644 index 0000000..b0af643 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/usbctrl_rtl.xml @@ -0,0 +1,58 @@ + + + xilinx.com + display_processing_system7 + usbctrl_rtl + 1.0 + + + + PORT_INDCTL + Port Indicator + + + optional + 2 + out + + + optional + 2 + in + + + + + VBUS_PWRSELECT + Power Select + + + optional + 1 + out + + + optional + 1 + in + + + + + VBUS_PWRFAULT + Power Fault + + + optional + 1 + in + + + optional + 1 + out + + + + + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/util_vector_logic_v2_0/5ac42227/hdl/util_vector_logic.vhd b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/util_vector_logic_v2_0/5ac42227/hdl/util_vector_logic.vhd new file mode 100644 index 0000000..cb7fa3f --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/util_vector_logic_v2_0/5ac42227/hdl/util_vector_logic.vhd @@ -0,0 +1,140 @@ +------------------------------------------------------------------------------- +-- $Id: util_vector_logic.vhd,v 2.0 2014/10/03 04:52:57 abq_ip Exp $ +------------------------------------------------------------------------------- +-- util_vector_logic.vhd - Entity and architecture +-- +-- *************************************************************************** +-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. ** +-- ** ** +-- ** This text contains proprietary, confidential ** +-- ** information of Xilinx, Inc. , is distributed by ** +-- ** under license from Xilinx, Inc., and may be used, ** +-- ** copied and/or disclosed only pursuant to the terms ** +-- ** of a valid license agreement with Xilinx, Inc. ** +-- ** ** +-- ** Unmodified source code is guaranteed to place and route, ** +-- ** function and run at speed according to the datasheet ** +-- ** specification. Source code is provided "as-is", with no ** +-- ** obligation on the part of Xilinx to provide support. ** +-- ** ** +-- ** Xilinx Hotline support of source code IP shall only include ** +-- ** standard level Xilinx Hotline support, and will only address ** +-- ** issues and questions related to the standard released Netlist ** +-- ** version of the core (and thus indirectly, the original core source). ** +-- ** ** +-- ** The Xilinx Support Hotline does not have access to source ** +-- ** code and therefore cannot answer specific questions related ** +-- ** to source HDL. The Xilinx Support Hotline will only be able ** +-- ** to confirm the problem in the Netlist version of the core. ** +-- ** ** +-- ** This copyright and support notice must be retained as part ** +-- ** of this text at all times. ** +-- *************************************************************************** +-- +------------------------------------------------------------------------------- +-- Filename: util_vector_logic.vhd +-- +-- Description: +-- +-- VHDL-Standard: VHDL'93 +------------------------------------------------------------------------------- +-- Structure: +-- util_vector_logic.vhd +-- +------------------------------------------------------------------------------- +-- Author: goran +-- Revision: $Revision: 1.1 $ +-- Date: $Date: 2003/10/03 04:52:57 $ +-- +-- History: +-- goran 2003-06-06 First Version +-- +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity util_vector_logic is + generic ( + C_OPERATION : string := "and"; + C_SIZE : integer := 8 + ); + port ( + Op1 : in std_logic_vector(C_SIZE-1 downto 0); + Op2 : in std_logic_vector(C_SIZE-1 downto 0); + Res : out std_logic_vector(C_SIZE-1 downto 0) + ); +end util_vector_logic; + +architecture IMP of util_vector_logic is + + function LowerCase_Char(char : character) return character is + begin + -- If char is not an upper case letter then return char + if char < 'A' or char > 'Z' then + return char; + end if; + -- Otherwise map char to its corresponding lower case character and + -- return that + case char is + when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd'; + when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h'; + when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l'; + when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p'; + when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't'; + when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x'; + when 'Y' => return 'y'; when 'Z' => return 'z'; + when others => return char; + end case; + end LowerCase_Char; + + function LowerCase_String (s : string) return string is + variable res : string(s'range); + begin -- function LoweerCase_String + for I in s'range loop + res(I) := LowerCase_Char(s(I)); + end loop; -- I + return res; + end function LowerCase_String; + + constant C_Oper : string := LowerCase_String(C_OPERATION); + +begin + + Use_AND: if (C_Oper = "and") generate + res <= Op1 and Op2; + end generate Use_AND; + + Use_OR: if (C_Oper = "or") generate + res <= Op1 or Op2; + end generate Use_OR; + + Use_XOR: if (C_Oper = "xor") generate + res <= Op1 xor Op2; + end generate Use_XOR; + + Use_NOT: if (C_Oper = "not") generate + res <= NOT Op1; + end generate Use_NOT; + +end IMP; + diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.v b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.v new file mode 100644 index 0000000..04b9d03 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.v @@ -0,0 +1,276 @@ +//------------------------------------------------------------------------ +//-- +//-- Filename : xlconcat.v +//-- +//-- Date : 06/05/12 +//- +//- Description : Verilog description of a concat block. This +//- block does not use a core. +//- +//----------------------------------------------------------------------- + +`timescale 1ps/1ps + +module xlconcat (In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, In10, In11, In12, In13, In14, In15, In16, In17, In18, In19, In20, In21, In22, In23, In24, In25, In26, In27, In28, In29, In30, In31, dout); +parameter IN0_WIDTH = 1; +input [IN0_WIDTH -1:0] In0; +parameter IN1_WIDTH = 1; +input [IN1_WIDTH -1:0] In1; +parameter IN2_WIDTH = 1; +input [IN2_WIDTH -1:0] In2; +parameter IN3_WIDTH = 1; +input [IN3_WIDTH -1:0] In3; +parameter IN4_WIDTH = 1; +input [IN4_WIDTH -1:0] In4; +parameter IN5_WIDTH = 1; +input [IN5_WIDTH -1:0] In5; +parameter IN6_WIDTH = 1; +input [IN6_WIDTH -1:0] In6; +parameter IN7_WIDTH = 1; +input [IN7_WIDTH -1:0] In7; +parameter IN8_WIDTH = 1; +input [IN8_WIDTH -1:0] In8; +parameter IN9_WIDTH = 1; +input [IN9_WIDTH -1:0] In9; +parameter IN10_WIDTH = 1; +input [IN10_WIDTH -1:0] In10; +parameter IN11_WIDTH = 1; +input [IN11_WIDTH -1:0] In11; +parameter IN12_WIDTH = 1; +input [IN12_WIDTH -1:0] In12; +parameter IN13_WIDTH = 1; +input [IN13_WIDTH -1:0] In13; +parameter IN14_WIDTH = 1; +input [IN14_WIDTH -1:0] In14; +parameter IN15_WIDTH = 1; +input [IN15_WIDTH -1:0] In15; +parameter IN16_WIDTH = 1; +input [IN16_WIDTH -1:0] In16; +parameter IN17_WIDTH = 1; +input [IN17_WIDTH -1:0] In17; +parameter IN18_WIDTH = 1; +input [IN18_WIDTH -1:0] In18; +parameter IN19_WIDTH = 1; +input [IN19_WIDTH -1:0] In19; +parameter IN20_WIDTH = 1; +input [IN20_WIDTH -1:0] In20; +parameter IN21_WIDTH = 1; +input [IN21_WIDTH -1:0] In21; +parameter IN22_WIDTH = 1; +input [IN22_WIDTH -1:0] In22; +parameter IN23_WIDTH = 1; +input [IN23_WIDTH -1:0] In23; +parameter IN24_WIDTH = 1; +input [IN24_WIDTH -1:0] In24; +parameter IN25_WIDTH = 1; +input [IN25_WIDTH -1:0] In25; +parameter IN26_WIDTH = 1; +input [IN26_WIDTH -1:0] In26; +parameter IN27_WIDTH = 1; +input [IN27_WIDTH -1:0] In27; +parameter IN28_WIDTH = 1; +input [IN28_WIDTH -1:0] In28; +parameter IN29_WIDTH = 1; +input [IN29_WIDTH -1:0] In29; +parameter IN30_WIDTH = 1; +input [IN30_WIDTH -1:0] In30; +parameter IN31_WIDTH = 1; +input [IN31_WIDTH -1:0] In31; +parameter dout_width = 2; +output [dout_width-1:0] dout; +parameter NUM_PORTS =2; + + +generate if (NUM_PORTS == 1) +begin : C_NUM_1 + assign dout = In0; +end +endgenerate + +generate if (NUM_PORTS == 2) +begin : C_NUM_2 + assign dout = {In1,In0}; +end +endgenerate + +generate if (NUM_PORTS == 3) +begin:C_NUM_3 + assign dout = {In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 4) +begin:C_NUM_4 + assign dout = {In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 5) +begin:C_NUM_5 + assign dout = {In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 6) +begin:C_NUM_6 + assign dout = {In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 7) +begin:C_NUM_7 + assign dout = {In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 8) +begin:C_NUM_8 + assign dout = {In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 9) +begin:C_NUM_9 + assign dout = {In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 10) +begin:C_NUM_10 + assign dout = {In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 11) +begin:C_NUM_11 + assign dout = {In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 12) +begin:C_NUM_12 + assign dout = {In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 13) +begin:C_NUM_13 + assign dout = {In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 14) +begin:C_NUM_14 + assign dout = {In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 15) +begin:C_NUM_15 + assign dout = {In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 16) +begin:C_NUM_16 + assign dout = {In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 17) +begin:C_NUM_17 + assign dout = {In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 18) +begin:C_NUM_18 + assign dout = {In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 19) +begin:C_NUM_19 + assign dout = {In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 20) +begin:C_NUM_20 + assign dout = {In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 21) +begin:C_NUM_21 + assign dout = {In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 22) +begin:C_NUM_22 + assign dout = {In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 23) +begin:C_NUM_23 + assign dout = {In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 24) +begin:C_NUM_24 + assign dout = {In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 25) +begin:C_NUM_25 + assign dout = {In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 26) +begin:C_NUM_26 + assign dout = {In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 27) +begin:C_NUM_27 + assign dout = {In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 28) +begin:C_NUM_28 + assign dout = {In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 29) +begin:C_NUM_29 + assign dout = {In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 30) +begin:C_NUM_30 + assign dout = {In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 31) +begin:C_NUM_31 + assign dout = {In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +generate if (NUM_PORTS == 32) +begin:C_NUM_32 + assign dout = {In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; +end +endgenerate + +endmodule diff --git a/sdsoc-platform/zturn-7z020/vivado/z_turn20.xpr b/sdsoc-platform/zturn-7z020/vivado/z_turn20.xpr new file mode 100644 index 0000000..e41d149 --- /dev/null +++ b/sdsoc-platform/zturn-7z020/vivado/z_turn20.xpr @@ -0,0 +1,155 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/z_turn20_hw.pfm b/sdsoc-platform/zturn-7z020/z_turn20_hw.pfm new file mode 100644 index 0000000..372689b --- /dev/null +++ b/sdsoc-platform/zturn-7z020/z_turn20_hw.pfm @@ -0,0 +1,77 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sdsoc-platform/zturn-7z020/z_turn20_sw.pfm b/sdsoc-platform/zturn-7z020/z_turn20_sw.pfm new file mode 100644 index 0000000..9fe85bd --- /dev/null +++ b/sdsoc-platform/zturn-7z020/z_turn20_sw.pfm @@ -0,0 +1,27 @@ + + + + Basic platform targeting the Z-turn Board, which includes 1 GB of DDR3, 128 Mb QSPI Flash and a MicroSD card interface. More information at http://www.myir-tech.com/product/z-turn_board.htm + + + + + + + + +