fixed several smaller details in new version of the board defintion files (schema version 2.1 for Vivado 2015.x)
This commit is contained in:
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9ed7c22604
commit
f56ddd4d19
10 changed files with 235 additions and 205 deletions
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@ -1,60 +1,32 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><!--
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################################################################################
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#
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# MYiR ZTurn Zynq 7010 Board Definition File
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# MYiR Z-turn Board Definition File
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#
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# Sergiusz 'q3k' Bazański <q3k@q3k.org>
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# Steffen 'stv0g' Vogel <stv0g@0l.de>
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#
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################################################################################-->
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<board schema_version="2.0"
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vendor="myir.com"
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name="mys-7z010"
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display_name="Z-turn (MYS-7Z010-C)"
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url="http://www.myirtech.com/list.asp?id=502"
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preset_file="preset.xml">
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<board name="mys-7z010" schema_version="2.1" vendor="myir.com" display_name="Z-turn Board (MYS-7Z010-C)" url="http://www.myirtech.com/list.asp?id=502" preset_file="preset.xml">
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<images>
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<image name="zturn.jpg" display_name="Z-turn Board" sub_type="board">
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<image name="zturn_board.jpg" display_name="Z-turn Board" sub_type="board">
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<description>Z-turn Board top image</description>
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</image>
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</images>
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<description>The Z-turn board is a cheap Zynq 7010 evalation from the Chinese company MYiR.</description>
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<file_version>2.0</file_version>
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<description>The Z-turn board is a cheap Zynq evaluation board from the Chinese company MYiR Technologies.</description>
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<file_version>2.1</file_version>
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<compatible_board_revisions>
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<revision id="0">4</revision>
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</compatible_board_revisions>
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<jumpers>
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<jumper name="JP1">
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<description>Selects the boot mode of the PS:
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If JP1 is set and JP2 is set: QSPI.
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If JP1 is set and JP2 is not set: JTAG.
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If JP1 is not set and JP2 is set: SD card.
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If JP1 is not set and JP2 is not set: NAND flash.</description>
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</jumper>
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<jumper name="JP2">
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<description>Selects the boot mode of the PS. See JP1.</description>
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</jumper>
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</jumpers>
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<components>
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<component name="part0" display_name="Z-turn Zynq Board"
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type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml"
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vendor="xilinx" spec_url="http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/">
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<description>Zynq SoC on the board</description>
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<component name="part0" display_name="Z-turn Board" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.myirtech.com/list.asp?id=502">
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<description>FPGA part on the board</description>
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<interfaces>
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<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"></interface>
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<interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="rgb_led_preset">
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<interface name="ps7_fixedio" mode="master" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset" />
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<interface name="rgb_led" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="rgb_led_preset">
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0" />
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<preferred_ip name="axi_gpio" vendor="xilinx.com" library="ip" order="0" />
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</preferred_ips>
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<port_maps>
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<port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0">
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@ -66,10 +38,9 @@
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</port_map>
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</port_maps>
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</interface>
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<interface mode="master" name="buzzer" type="xilinx.com:interface:gpio_rtl:1.0" of_component="buzzer" preset_proc="buzzer_preset">
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<interface name="buzzer" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="buzzer" preset_proc="buzzer_preset">
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0" />
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<preferred_ip name="axi_gpio" vendor="xilinx.com" library="ip" order="0" />
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</preferred_ips>
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<port_maps>
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<port_map logical_port="TRI_O" physical_port="buzzer_tri_o" dir="out">
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@ -79,8 +50,7 @@
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</port_map>
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</port_maps>
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</interface>
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<interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="sws_4bits_preset">
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<interface name="sws_4bits" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="sws_4bits_preset">
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0" />
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</preferred_ips>
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@ -95,68 +65,77 @@
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</port_map>
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</port_maps>
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</interface>
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<!-- TODO
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<interface mode="master" name="i2c0" type="xilinx.com:interface:iic_rtl:1.0">
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<interface mode="master" name="i2c0" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c0">
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<description>I2C Interface for onboard G-rate and temperature sensors</description>
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</interface>-->
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0" />
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</preferred_ips>
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<port_maps>
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<port_map logical_port="SDA_I" physical_port="i2c0_sda_i" dir="in">
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<pin_maps>
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<pin_map port_index="0" component_pin="i2c0_sda_i" />
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</pin_maps>
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</port_map>
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<port_map logical_port="SDA_O" physical_port="i2c0_sda_o" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="i2c0_sda_i" />
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</pin_maps>
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</port_map>
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<port_map logical_port="SDA_T" physical_port="i2c0_sda_t" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="i2c0_sda_i" />
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</pin_maps>
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</port_map>
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<port_map logical_port="SCL_I" physical_port="i2c0_scl_i" dir="in">
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<pin_maps>
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<pin_map port_index="0" component_pin="i2c0_scl_i" />
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</pin_maps>
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</port_map>
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<port_map logical_port="SCL_O" physical_port="i2c0_scl_o" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="i2c0_scl_i" />
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</pin_maps>
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</port_map>
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<port_map logical_port="SCL_T" physical_port="i2c0_scl_t" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="i2c0_scl_i" />
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</pin_maps>
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</port_map>
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</port_maps>
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</interface>
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</interfaces>
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</component>
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<component name="ps7_fixedio" display_name="PS7 fixed IO" type="chip" sub_type="fixed_io" major_group="" />
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<component name="buzzer" display_name="Piezo Buzzer" type="chip" sub_type="led" major_group="General Purpose Input or Output">
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<description>Piezo Buzzer on Board (Schematic: M1)</description>
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</component>
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<component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="General Purpose Input or Output">
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<description>RGB LED, 2 to 0, Active Low (Schematic: D34)</description>
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</component>
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<component name="sws_4bits" display_name="DIP switches" type="chip" sub_type="switch" major_group="General Purpose Input or Output">
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<description>DIP Switches, 3 to 0 (Schematic: U20)</description>
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</component>
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<!-- TODO
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<component name="adxl345" display_name="ADXL345 Digital MEMS Accelerometer" type="chip" sub_type="sensor">
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<description>Slave on I2C0 bus. Address: @0x53</description>
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<component name="i2c0" display_name="IIC" type="chip" sub_type="mux" major_group="Miscellaneous">
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<description>I2C Bus 0 wired to PL</description>
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</component>
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<component name="stlm75" display_name="STLM75 Digital temperature sensor and thermal watchdog" type="chip" sub_type="sensor">
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<description>Slave on I2C0 bus. Address: @0x49</description>
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</component>-->
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<!-- Those components are hardwired to the PS. Therefore are not really needed here..
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<component name="sii9022a" display_name="Silicon Image HDMI Transmitter SiI9022A" type="chip" major_group="Video Transmitter" />
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<component name="ddr3_sdram" display_name="DDR3 SDRAM"
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type="chip" sub_type="ddr3"
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major_group="External Memory" part_name="MT41K256M16HA-125:E" vendor="Micron"
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spec_url="www.micron.com/memory">
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<description>1GB DDR3 SDRAM (2x 512 MB), 32bit Data line (Schematic: U4 + U5)</description>
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</component>
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<component name="spi_flash" display_name="SPI Flash"
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type="chip" sub_type="flash"
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major_group="External Memory" part_name="W25Q128BVFIG" vendor="Winbond"
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spec_url="www.micron.com/memory">
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<description>16MB SPI Flash (Schematic: U6)</description>
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</component>-->
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</components>
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<jtag_chains>
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<jtag_chain name="chain1">
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<position name="0" component="part0" />
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</jtag_chain>
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</jtag_chains>
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<connections>
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<connection name="part0_rgb_led" component1="part0" component2="rgb_led">
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<connection_map name="part0_rgb_led_1" c1_st_index="4" c1_end_index="6" c2_st_index="0" c2_end_index="2" />
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</connection>
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<connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
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<connection_map name="part0_sws_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3" />
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</connection>
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<connection name="part0_buzzer" component1="part0" component2="buzzer">
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<connection_map name="part0_buzzer_1" c1_st_index="7" c1_end_index="7" c2_st_index="0" c2_end_index="0" />
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</connection>
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<connection name="part0_i2c0" component1="part0" component2="i2c0">
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<connection_map name="part0_i2c0_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1" />
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</connection>
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</connections>
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</board>
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</board>
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<?xml version="1.0" encoding="UTF-8" standalone="no"?><!--
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################################################################################
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#
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# MYiR ZTurn Zynq 7010 Pin Definition File
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# MYiR Z-turn FPGA Pin Definition File
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#
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# Sergiusz 'q3k' Bazański <q3k@q3k.org>
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# Steffen 'stv0g' Vogel <stv0g@0l.de>
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<pin index="5" name="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="Y16" /><!-- IO_B34_LP7 -->
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<pin index="6" name="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="Y17" /><!-- IO_B34_LN7 -->
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<pin index="7" name="buzzer_tri_o_0" iostandard="LVCMOS33" loc="P18" /><!-- BP -->
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<pin index="8" name="i2c0_sda" iostandard="LVCMOS33" loc="P15" /><!-- I2C0_SDA -->
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<pin index="9" name="i2c0_scl" iostandard="LVCMOS33" loc="P16" /><!-- I2C0_SCL -->
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<pin index="10" name="mems_intn" iostandard="LVCMOS33" loc="P18" /><!-- MEMS_INTn -->
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<pin index="8" name ="i2c0_scl_i" iostandard="LVCMOS33" loc="P16" /><!-- I2C0_SCL -->
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<pin index="9" name ="i2c0_sda_i" iostandard="LVCMOS33" loc="P15" /><!-- I2C0_SDA -->
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<pin index="10" name="mems_temp_intn" iostandard="LVCMOS33" loc="N17" /><!-- MEMS_INTn (wired-or for LM75 and Sil902x)-->
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<pin index="11" name="hdmi_int" iostandard="LVCMOS33" loc="W19" /><!-- HDMI_INT -->
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</pins>
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</part_info>
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><!--
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################################################################################
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#
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# MYiR ZTurn Zynq 7010 Board Definition File
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# MYiR Z-turn Board IP Presets
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#
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# Sergiusz 'q3k' Bazański <q3k@q3k.org>
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# Steffen 'stv0g' Vogel <stv0g@0l.de>
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################################################################################-->
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<ip_presets schema="1.0">
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<ip_preset preset_proc_name="ps7_preset">
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<ip_preset preset_proc_name="ps7_preset">
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<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
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<user_parameters>
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<!--########################################################################
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</user_parameters>
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</ip>
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</ip_preset>
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<!-- <ip_preset preset_proc_name="rgb_led_preset">
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<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
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<user_parameters>
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<user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
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<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
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</user_parameters>
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</ip>
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<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
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<user_parameters>
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<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
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<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
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<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
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</user_parameters>
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</ip>
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</ip_preset> -->
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<ip_preset preset_proc_name="rgb_led_preset">
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<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
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<user_parameters>
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<user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
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<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
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<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
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</user_parameters>
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</ip>
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<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
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<user_parameters>
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<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
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<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
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<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
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<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
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</user_parameters>
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</ip>
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</ip_preset>
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<ip_preset preset_proc_name="buzzer_preset">
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<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
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<user_parameters>
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<user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
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<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
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<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
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</user_parameters>
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</ip>
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<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
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<user_parameters>
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<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
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<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
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<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
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<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
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</user_parameters>
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</ip>
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</ip_preset>
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<ip_preset preset_proc_name="sws_4bits_preset">
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<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
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<user_parameters>
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<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
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<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
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<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
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</user_parameters>
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</ip>
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<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
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<user_parameters>
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<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
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<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
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<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
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<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
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</user_parameters>
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</ip>
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</ip_preset>
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</ip_presets>
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Binary file not shown.
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Before Width: | Height: | Size: 210 KiB |
Binary file not shown.
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After Width: | Height: | Size: 219 KiB |
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@ -1,60 +1,32 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><!--
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################################################################################
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#
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# MYiR ZTurn Zynq 7010 Board Definition File
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# MYiR Z-turn Board Definition File
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#
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# Sergiusz 'q3k' Bazański <q3k@q3k.org>
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||||
# Steffen 'stv0g' Vogel <stv0g@0l.de>
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#
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################################################################################-->
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<board schema_version="2.0"
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vendor="myir.com"
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name="mys-7z020"
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display_name="Z-turn (MYS-7Z020-C)"
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url="http://www.myirtech.com/list.asp?id=502"
|
||||
preset_file="preset.xml">
|
||||
|
||||
<board name="mys-7z020" schema_version="2.1" vendor="myir.com" display_name="Z-turn Board (MYS-7Z020-C)" url="http://www.myirtech.com/list.asp?id=502" preset_file="preset.xml">
|
||||
<images>
|
||||
<image name="zturn.jpg" display_name="Z-turn Board" sub_type="board">
|
||||
<image name="zturn_board.jpg" display_name="Z-turn Board" sub_type="board">
|
||||
<description>Z-turn Board top image</description>
|
||||
</image>
|
||||
</images>
|
||||
|
||||
<description>The Z-turn board is a cheap Zynq 7020 evaluation board from the Chinese company MYiR.</description>
|
||||
|
||||
<file_version>2.0</file_version>
|
||||
|
||||
<description>The Z-turn board is a cheap Zynq evaluation board from the Chinese company MYiR Technologies.</description>
|
||||
<file_version>2.1</file_version>
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">4</revision>
|
||||
</compatible_board_revisions>
|
||||
|
||||
<jumpers>
|
||||
<jumper name="JP1">
|
||||
<description>Selects the boot mode of the PS:
|
||||
If JP1 is set and JP2 is set: QSPI.
|
||||
If JP1 is set and JP2 is not set: JTAG.
|
||||
If JP1 is not set and JP2 is set: SD card.
|
||||
If JP1 is not set and JP2 is not set: NAND flash.</description>
|
||||
</jumper>
|
||||
<jumper name="JP2">
|
||||
<description>Selects the boot mode of the PS. See JP1.</description>
|
||||
</jumper>
|
||||
</jumpers>
|
||||
|
||||
<components>
|
||||
<component name="part0" display_name="Z-turn Zynq Board"
|
||||
type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml"
|
||||
vendor="xilinx" spec_url="http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/">
|
||||
|
||||
<description>Zynq SoC on the board</description>
|
||||
|
||||
<component name="part0" display_name="Z-turn Board" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.myirtech.com/list.asp?id=502">
|
||||
<description>FPGA part on the board</description>
|
||||
<interfaces>
|
||||
<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"></interface>
|
||||
|
||||
<interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="rgb_led_preset">
|
||||
<interface name="ps7_fixedio" mode="master" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset" />
|
||||
<interface name="rgb_led" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="rgb_led_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0" />
|
||||
<preferred_ip name="axi_gpio" vendor="xilinx.com" library="ip" order="0" />
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0">
|
||||
|
|
@ -66,10 +38,9 @@
|
|||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
|
||||
<interface mode="master" name="buzzer" type="xilinx.com:interface:gpio_rtl:1.0" of_component="buzzer" preset_proc="buzzer_preset">
|
||||
<interface name="buzzer" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="buzzer" preset_proc="buzzer_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0" />
|
||||
<preferred_ip name="axi_gpio" vendor="xilinx.com" library="ip" order="0" />
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="buzzer_tri_o" dir="out">
|
||||
|
|
@ -79,8 +50,7 @@
|
|||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
|
||||
<interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="sws_4bits_preset">
|
||||
<interface name="sws_4bits" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="sws_4bits_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0" />
|
||||
</preferred_ips>
|
||||
|
|
@ -95,68 +65,77 @@
|
|||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
|
||||
<!-- TODO
|
||||
<interface mode="master" name="i2c0" type="xilinx.com:interface:iic_rtl:1.0">
|
||||
<interface mode="master" name="i2c0" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c0">
|
||||
<description>I2C Interface for onboard G-rate and temperature sensors</description>
|
||||
</interface>-->
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0" />
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="SDA_I" physical_port="i2c0_sda_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c0_sda_i" />
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SDA_O" physical_port="i2c0_sda_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c0_sda_i" />
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SDA_T" physical_port="i2c0_sda_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c0_sda_i" />
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_I" physical_port="i2c0_scl_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c0_scl_i" />
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_O" physical_port="i2c0_scl_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c0_scl_i" />
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_T" physical_port="i2c0_scl_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c0_scl_i" />
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
|
||||
<component name="ps7_fixedio" display_name="PS7 fixed IO" type="chip" sub_type="fixed_io" major_group="" />
|
||||
|
||||
<component name="buzzer" display_name="Piezo Buzzer" type="chip" sub_type="led" major_group="General Purpose Input or Output">
|
||||
<description>Piezo Buzzer on Board (Schematic: M1)</description>
|
||||
</component>
|
||||
|
||||
<component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="General Purpose Input or Output">
|
||||
<description>RGB LED, 2 to 0, Active Low (Schematic: D34)</description>
|
||||
</component>
|
||||
|
||||
<component name="sws_4bits" display_name="DIP switches" type="chip" sub_type="switch" major_group="General Purpose Input or Output">
|
||||
<description>DIP Switches, 3 to 0 (Schematic: U20)</description>
|
||||
</component>
|
||||
|
||||
<!-- TODO
|
||||
<component name="adxl345" display_name="ADXL345 Digital MEMS Accelerometer" type="chip" sub_type="sensor">
|
||||
<description>Slave on I2C0 bus. Address: @0x53</description>
|
||||
<component name="i2c0" display_name="IIC" type="chip" sub_type="mux" major_group="Miscellaneous">
|
||||
<description>I2C Bus 0 wired to PL</description>
|
||||
</component>
|
||||
|
||||
<component name="stlm75" display_name="STLM75 Digital temperature sensor and thermal watchdog" type="chip" sub_type="sensor">
|
||||
<description>Slave on I2C0 bus. Address: @0x49</description>
|
||||
</component>-->
|
||||
|
||||
<!-- Those components are hardwired to the PS. Therefore are not really needed here..
|
||||
<component name="sii9022a" display_name="Silicon Image HDMI Transmitter SiI9022A" type="chip" major_group="Video Transmitter" />
|
||||
|
||||
<component name="ddr3_sdram" display_name="DDR3 SDRAM"
|
||||
type="chip" sub_type="ddr3"
|
||||
major_group="External Memory" part_name="MT41K256M16HA-125:E" vendor="Micron"
|
||||
spec_url="www.micron.com/memory">
|
||||
<description>1GB DDR3 SDRAM (2x 512 MB), 32bit Data line (Schematic: U4 + U5)</description>
|
||||
</component>
|
||||
|
||||
<component name="spi_flash" display_name="SPI Flash"
|
||||
type="chip" sub_type="flash"
|
||||
major_group="External Memory" part_name="W25Q128BVFIG" vendor="Winbond"
|
||||
spec_url="www.micron.com/memory">
|
||||
<description>16MB SPI Flash (Schematic: U6)</description>
|
||||
</component>-->
|
||||
</components>
|
||||
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0" />
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
|
||||
<connections>
|
||||
<connection name="part0_rgb_led" component1="part0" component2="rgb_led">
|
||||
<connection_map name="part0_rgb_led_1" c1_st_index="4" c1_end_index="6" c2_st_index="0" c2_end_index="2" />
|
||||
</connection>
|
||||
|
||||
<connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
|
||||
<connection_map name="part0_sws_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3" />
|
||||
</connection>
|
||||
<connection name="part0_buzzer" component1="part0" component2="buzzer">
|
||||
<connection_map name="part0_buzzer_1" c1_st_index="7" c1_end_index="7" c2_st_index="0" c2_end_index="0" />
|
||||
</connection>
|
||||
<connection name="part0_i2c0" component1="part0" component2="i2c0">
|
||||
<connection_map name="part0_i2c0_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1" />
|
||||
</connection>
|
||||
</connections>
|
||||
</board>
|
||||
</board>
|
||||
|
|
@ -1,14 +1,14 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?><!--
|
||||
################################################################################
|
||||
#
|
||||
# MYiR ZTurn Zynq 7010 Pin Definition File
|
||||
# MYiR Z-turn FPGA Pin Definition File
|
||||
#
|
||||
# Sergiusz 'q3k' Bazański <q3k@q3k.org>
|
||||
# Steffen 'stv0g' Vogel <stv0g@0l.de>
|
||||
#
|
||||
################################################################################-->
|
||||
|
||||
<part_info part_name="xc7z010clg400-1">
|
||||
<part_info part_name="xc7z020clg400-1">
|
||||
<pins>
|
||||
<pin index="0" name="sws_4bits_tri_i_0" iostandard="LVCMOS33" loc="R19" /><!-- IO_B34_0 -->
|
||||
<pin index="1" name="sws_4bits_tri_i_1" iostandard="LVCMOS33" loc="T19" /><!-- IO_B34_25 -->
|
||||
|
|
@ -18,8 +18,9 @@
|
|||
<pin index="5" name="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="Y16" /><!-- IO_B34_LP7 -->
|
||||
<pin index="6" name="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="Y17" /><!-- IO_B34_LN7 -->
|
||||
<pin index="7" name="buzzer_tri_o_0" iostandard="LVCMOS33" loc="P18" /><!-- BP -->
|
||||
<pin index="8" name="i2c0_sda" iostandard="LVCMOS33" loc="P15" /><!-- I2C0_SDA -->
|
||||
<pin index="9" name="i2c0_scl" iostandard="LVCMOS33" loc="P16" /><!-- I2C0_SCL -->
|
||||
<pin index="10" name="mems_intn" iostandard="LVCMOS33" loc="P18" /><!-- MEMS_INTn -->
|
||||
<pin index="8" name ="i2c0_scl_i" iostandard="LVCMOS33" loc="P16" /><!-- I2C0_SCL -->
|
||||
<pin index="9" name ="i2c0_sda_i" iostandard="LVCMOS33" loc="P15" /><!-- I2C0_SDA -->
|
||||
<pin index="10" name="mems_temp_intn" iostandard="LVCMOS33" loc="N17" /><!-- MEMS_INTn (wired-or for LM75 and Sil902x)-->
|
||||
<pin index="11" name="hdmi_int" iostandard="LVCMOS33" loc="W19" /><!-- HDMI_INT -->
|
||||
</pins>
|
||||
</part_info>
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><!--
|
||||
################################################################################
|
||||
#
|
||||
# MYiR ZTurn Zynq 7010 Board Definition File
|
||||
# MYiR Z-turn Board IP Presets
|
||||
#
|
||||
# Sergiusz 'q3k' Bazański <q3k@q3k.org>
|
||||
# Steffen 'stv0g' Vogel <stv0g@0l.de>
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
################################################################################-->
|
||||
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ps7_preset">
|
||||
<ip_preset preset_proc_name="ps7_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
|
||||
<user_parameters>
|
||||
<!--########################################################################
|
||||
|
|
@ -270,20 +270,55 @@
|
|||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<!-- <ip_preset preset_proc_name="rgb_led_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset> -->
|
||||
<ip_preset preset_proc_name="rgb_led_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="buzzer_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="sws_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
</ip_presets>
|
||||
|
|
|
|||
Binary file not shown.
|
Before Width: | Height: | Size: 210 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 219 KiB |
Loading…
Add table
Reference in a new issue