155 lines
9.4 KiB
XML
155 lines
9.4 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2015.2 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="5" Path="E:/temp/platforms/z_turn20/vivado/z_turn20.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="67a56dd1476d4ff392569b01f18dbedc"/>
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<Option Name="Part" Val="xc7z020clg400-1"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="BoardPart" Val=""/>
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<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../../Vivado/tmp/ip"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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<Option Name="EnableCoreContainerForIPI" Val="FALSE"/>
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</Configuration>
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/z_turn.bd">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../z_turn/vivado/z_turn/z_turn.srcs/sources_1/bd/z_turn/z_turn.bd"/>
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<Attr Name="ImportTime" Val="1436341728"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="hw_handoff/z_turn.hwh"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="hdl/z_turn.hwdef"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="hw_handoff/z_turn_bd.tcl"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_proc_sys_reset_1_0/z_turn_proc_sys_reset_1_0.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="hdl/z_turn.v"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="ip/z_turn_proc_sys_reset_3_0/z_turn_proc_sys_reset_3_0.xci"/>
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<CompFileExtendedInfo CompFileName="z_turn.bd" FileRelPathName="z_turn_ooc.xdc"/>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/hdl/z_turn_wrapper.v">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../z_turn/vivado/z_turn/z_turn.srcs/sources_1/bd/z_turn/hdl/z_turn_wrapper.v"/>
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<Attr Name="ImportTime" Val="1436341727"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_1_0/z_turn_proc_sys_reset_1_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_3_0/z_turn_proc_sys_reset_3_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.upgrade_log"/>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="z_turn_wrapper"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<Filter Type="Constrs"/>
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<File Path="$PSRCDIR/constrs_1/new/system.xdc">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../../Vivado/z7010-1-clg400/myir_custom/system/system.srcs/constrs_1/new/system.xdc"/>
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<Attr Name="ImportTime" Val="1402970942"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/system.xdc"/>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
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<Filter Type="Srcs"/>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="design_1_wrapper"/>
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<Option Name="TopLib" Val="work"/>
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<Option Name="TopRTLFile" Val="$PPRDIR/../../../Vivado/z7010-1-clg400/mys_xc7z010/mys-xc7z010-arm-hmmi-xylon/mys-xc7z010-arm-hmmi-xylon.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="SimMode" Val="post-implementation"/>
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<Option Name="SrcSet" Val="sources_1"/>
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</Config>
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</FileSet>
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</FileSets>
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<Simulators>
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<Simulator Name="XSim">
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<Option Name="Description" Val="Vivado Simulator"/>
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<Option Name="CompiledLib" Val="0"/>
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</Simulator>
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<Simulator Name="ModelSim">
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<Option Name="Description" Val="ModelSim Simulator"/>
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</Simulator>
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<Simulator Name="Questa">
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<Option Name="Description" Val="Questa Advanced Simulator"/>
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</Simulator>
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<Simulator Name="IES">
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<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
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</Simulator>
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<Simulator Name="VCS">
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<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
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</Simulator>
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<Simulator Name="Riviera">
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<Option Name="Description" Val="Riviera-PRO Simulator"/>
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</Simulator>
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<Simulator Name="ActiveHDL">
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<Option Name="Description" Val="Active-HDL Simulator"/>
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</Simulator>
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</Simulators>
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<Runs Version="1" Minor="9">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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</Run>
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</Runs>
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</Project>
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