Go to file
Steffen Vogel 272a3fac36 Fix include order
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-14 10:09:52 +01:00
.devcontainer decvontainer: Fix formatting 2024-02-13 16:23:02 +01:00
.reuse Make project REUSE compliant 2023-09-07 11:16:04 +02:00
LICENSES Make project REUSE compliant 2023-09-07 11:16:04 +02:00
clients Apply clang-format changes 2023-09-08 11:37:42 +02:00
cmake Make project REUSE compliant 2023-09-07 11:16:04 +02:00
common@3a66d8ff65 update common and fpga submodules 2024-02-08 11:19:51 +01:00
doc hook-digest: Add hook for computing digests 2023-09-19 19:07:22 +02:00
etc rework fpga node type 2024-02-08 11:19:51 +01:00
fpga@d0c1fbb192 update fpga subrepo 2024-02-08 11:19:51 +01:00
include/villas Fix formatting using clang-format 2024-02-14 10:09:52 +01:00
lib Fix include order 2024-02-14 10:09:52 +01:00
lua/hooks Add NEW_FRAME to SampleFlags 2023-09-19 19:07:22 +02:00
packaging deps: Do now show Git warning about detached HEAD state 2024-02-13 16:23:02 +01:00
plugins Apply clang-format changes 2023-09-08 11:37:42 +02:00
python python: Pin dependencies 2024-02-13 16:23:02 +01:00
src src: Suppress cppcheck false positive 2023-09-26 17:59:39 +02:00
tests hook-digest: Add integration test 2023-09-19 19:07:22 +02:00
tools Add script to format all files in repository 2023-09-08 11:37:42 +02:00
web Make project REUSE compliant 2023-09-07 11:16:04 +02:00
.clang-format Add missing REUSE headers 2023-09-08 11:37:42 +02:00
.clangd Add missing REUSE headers 2023-09-08 11:37:42 +02:00
.dockerignore Make project REUSE compliant 2023-09-07 11:16:04 +02:00
.editorconfig editorconfig: Cover more files. 2023-09-21 14:46:54 +02:00
.envrc Make project REUSE compliant 2023-09-07 11:16:04 +02:00
.git-blame-ignore-revs Add missing REUSE headers 2023-09-08 11:37:42 +02:00
.gitignore Add clangd configuration file 2023-09-08 11:37:42 +02:00
.gitlab-ci.yml add docker tag to reuse step 2024-02-08 11:19:51 +01:00
.gitmodules Make project REUSE compliant 2023-09-07 11:16:04 +02:00
.mailmap Add missing REUSE headers 2023-09-08 11:37:42 +02:00
CMakeLists.txt packaging-nix: Update inputs 2023-09-26 17:59:39 +02:00
CODEOWNERS Make project REUSE compliant 2023-09-07 11:16:04 +02:00
CONTRIBUTING.md Update contribution guide 2023-09-08 11:37:42 +02:00
LICENSE Make project REUSE compliant 2023-09-07 11:16:04 +02:00
README.md Fix typo in README 2024-02-13 16:23:02 +01:00

README.md

VILLASnode

build status

This is VILLASnode, a gateway for processing and forwardning simulation data between real-time simulators. VILLASnode is a client/server application to connect simulation equipment and software such as:

  • OPAL-RT RT-LAB,
  • RTDS GTFPGA cards,
  • RTDS GTWIF cards,
  • Simulink,
  • LabView,
  • and FPGA models

by using protocols such as:

  • IEEE 802.2 Ethernet / IP / UDP,
  • ZeroMQ & nanomsg,
  • MQTT & AMQP
  • WebSockets
  • Shared Memory
  • Files
  • IEC 61850 Sampled Values / GOOSE
  • Analog/Digital IO via Comedi drivers
  • Infiniband (ibverbs)

It's designed with a focus on very low latency to achieve real-time exchange of simulation data. VILLASnode is used in distributed- and co-simulation scenarios and developed for the field of power grid simulation at the EON Energy Research Center in Aachen, Germany.

Documentation

User documentation is available here: https://villas.fein-aachen.org/docs/

License

This project is released under the terms of the Apache 2.0 license.

We kindly ask all academic publications employing components of VILLASframework to cite one of the following papers:

For other licensing options please consult Prof. Antonello Monti.

  • SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
  • SPDX-FileCopyrightText: 2023 OPAL-RT Germany GmbH
  • SPDX-License-Identifier: Apache-2.0

Contact

EONERC ACS Logo

Institute for Automation of Complex Power Systems (ACS)
EON Energy Research Center (EONERC)
RWTH University Aachen, Germany