mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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72 lines
2.2 KiB
C
72 lines
2.2 KiB
C
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/** Static server configuration
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*
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* This file contains some compiled-in settings.
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* This settings are not part of the configuration file.
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*
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* @file
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Institute for Automation of Complex Power Systems, EONERC
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#pragma once
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#ifndef V
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#define V 2
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#endif
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/* Paths */
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#define PLUGIN_PATH PREFIX "/share/villas/node/plugins"
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#define WEB_PATH PREFIX "/share/villas/node/web"
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#define SYSFS_PATH "/sys"
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#define PROCFS_PATH "/proc"
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/** Default number of values in a sample */
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#define DEFAULT_SAMPLELEN 64
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#define DEFAULT_QUEUELEN 1024
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/** Number of hugepages which are requested from the the kernel.
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* @see https://www.kernel.org/doc/Documentation/vm/hugetlbpage.txt */
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#define DEFAULT_NR_HUGEPAGES 100
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/** Width of log output in characters */
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#define LOG_WIDTH 80
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#define LOG_HEIGHT 25
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/** Socket priority */
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#define SOCKET_PRIO 7
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/* Protocol numbers */
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#define IPPROTO_VILLAS 137
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#define ETH_P_VILLAS 0xBABE
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#define USER_AGENT "VILLASfpga (" BUILDID ")"
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/* Required kernel version */
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#define KERNEL_VERSION_MAJ 3
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#define KERNEL_VERSION_MIN 6
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/** PCIe BAR number of VILLASfpga registers */
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#define FPGA_PCI_BAR 0
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#define FPGA_PCI_VID_XILINX 0x10ee
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#define FPGA_PCI_PID_VFPGA 0x7022
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/** AXI Bus frequency for all components
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* except RTDS AXI Stream bridge which runs at RTDS_HZ (100 Mhz) */
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#define FPGA_AXI_HZ 125000000 // 125 MHz
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