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hwdef-parse: parse PCI and AXI BARs

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This commit is contained in:
Daniel Krebs 2018-05-15 15:08:30 +02:00
parent 5b8f573337
commit 01803abade
1 changed files with 23 additions and 0 deletions
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23
fpga/scripts/hwdef-parse.py
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@ -255,4 +255,27 @@ for bram in brams:
if instance in ips:
ips[instance]['size'] = int(size)
pcies = root.xpath('.//MODULE[@MODTYPE="axi_pcie"]')
for pcie in pcies:
instance = pcie.get('INSTANCE')
axi_bars = ips[instance].setdefault('axi_bars', {})
pcie_bars = ips[instance].setdefault('pcie_bars', {})
for from_bar, to_bar, from_bars in (('AXIBAR', 'PCIEBAR', axi_bars), ('PCIEBAR', 'AXIBAR', pcie_bars)):
from_bar_num = int(pcie.find('.//PARAMETER[@NAME="C_{}_NUM"]'.format(from_bar)).get('VALUE'))
for i in range(0, from_bar_num):
from_bar_to_bar_offset = int(pcie.find('.//PARAMETER[@NAME="C_{}2{}_{}"]'.format(from_bar, to_bar, i)).get('VALUE'), 16)
from_bars['BAR{}'.format(i)] = { 'translation': from_bar_to_bar_offset }
if from_bar == 'AXIBAR':
axi_bar_lo = int(pcie.find('.//PARAMETER[@NAME="C_{}_{}"]'.format(from_bar, i)).get('VALUE'), 16)
axi_bar_hi = int(pcie.find('.//PARAMETER[@NAME="C_{}_HIGHADDR_{}"]'.format(from_bar, i)).get('VALUE'), 16)
axi_bar_size = axi_bar_hi - axi_bar_lo + 1
axi_bar = from_bars['BAR{}'.format(i)]
axi_bar['baseaddr'] = axi_bar_lo
axi_bar['highaddr'] = axi_bar_hi
axi_bar['size'] = axi_bar_size
print(json.dumps(ips, indent=2))