mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
Reformat Python code with black
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
This commit is contained in:
parent
ab5a3004bf
commit
0382475e47
3 changed files with 296 additions and 272 deletions
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@ -5,52 +5,53 @@
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import villas_pb2
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import time, socket, errno, sys, os, signal
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layer = sys.argv[1] if len(sys.argv) == 2 else 'udp'
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layer = sys.argv[1] if len(sys.argv) == 2 else "udp"
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if layer not in ['udp', 'unix']:
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raise Exception('Unsupported socket type')
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if layer not in ["udp", "unix"]:
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raise Exception("Unsupported socket type")
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if layer == 'unix':
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local = '/var/run/villas-node.client.sock'
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remote = '/var/run/villas-node.server.sock'
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if layer == "unix":
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local = "/var/run/villas-node.client.sock"
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remote = "/var/run/villas-node.server.sock"
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skt = socket.socket(socket.AF_UNIX, socket.SOCK_DGRAM)
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skt = socket.socket(socket.AF_UNIX, socket.SOCK_DGRAM)
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# Delete stale sockets
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if os.path.exists(local):
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os.unlink(local)
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elif layer == 'udp':
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local = ('0.0.0.0', 12001)
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remote = ('127.0.0.1', 12000)
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# Delete stale sockets
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if os.path.exists(local):
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os.unlink(local)
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elif layer == "udp":
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local = ("0.0.0.0", 12001)
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remote = ("127.0.0.1", 12000)
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skt = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
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skt = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
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print('Start client...')
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print("Start client...")
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skt.bind(local)
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# Try to connect in case Unix domain socket does not exist yet..
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connected = False
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while not connected:
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try:
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skt.connect(remote)
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except socket.error as serr:
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if serr.errno not in [ errno.ECONNREFUSED, errno.ENOENT ]:
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raise serr
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print('Not connected. Retrying in 1 sec')
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time.sleep(1)
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else:
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connected = True
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try:
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skt.connect(remote)
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except socket.error as serr:
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if serr.errno not in [errno.ECONNREFUSED, errno.ENOENT]:
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raise serr
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print('Ready. Ctrl-C to quit.')
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print("Not connected. Retrying in 1 sec")
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time.sleep(1)
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else:
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connected = True
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print("Ready. Ctrl-C to quit.")
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msg = villas_pb2.Message()
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# Gracefully shutdown
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def sighandler(signum, frame):
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running = False
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running = False
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signal.signal(signal.SIGINT, sighandler)
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signal.signal(signal.SIGTERM, sighandler)
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@ -58,15 +59,15 @@ signal.signal(signal.SIGTERM, sighandler)
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running = True
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while running:
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dgram = skt.recv(1024)
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if not dgram:
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break
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else:
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msg.ParseFromString(dgram)
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print(msg)
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skt.send(msg.SerializeToString())
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dgram = skt.recv(1024)
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if not dgram:
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break
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else:
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msg.ParseFromString(dgram)
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print(msg)
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skt.send(msg.SerializeToString())
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skt.close()
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print('Bye.')
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print("Bye.")
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@ -1,5 +1,5 @@
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#!/bin/env python3
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''' Example Python config
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""" Example Python config
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This example demonstrates how you can use Python to generate complex
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configuration files.
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@ -11,7 +11,7 @@
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Author: Steffen Vogel <post@steffenvogel.de>
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SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
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SPDX-License-Identifier: Apache-2.0
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'''
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"""
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import json
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import sys
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@ -19,59 +19,38 @@ import sys
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N = 10
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nodes = {
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'raspberry': {
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'type': 'socket',
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'layer': 'udp',
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'format': 'protobuf',
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'in': {
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'address': '*:12000',
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"raspberry": {
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"type": "socket",
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"layer": "udp",
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"format": "protobuf",
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"in": {
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"address": "*:12000",
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},
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'out': {
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'address': '1.2.3.4:12000'
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}
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"out": {"address": "1.2.3.4:12000"},
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}
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}
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for i in range(N):
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name = f'agent{i}'
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name = f"agent{i}"
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port = 12000 + i
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nodes[name] = {
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'type': 'socket',
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'layer': 'udp',
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'format': 'protobuf',
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'in': {
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'address': '*:12000',
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'signals': [
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{
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'name': 'in',
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'type': 'float'
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}
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]
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},
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'out': {
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'address': f'5.6.7.8:{port}'
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}
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"type": "socket",
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"layer": "udp",
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"format": "protobuf",
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"in": {"address": "*:12000", "signals": [{"name": "in", "type": "float"}]},
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"out": {"address": f"5.6.7.8:{port}"},
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}
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paths = [
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{
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'in': [f'agent{i}' for i in range(N)],
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'out': 'raspberry',
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'mode': 'any',
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'hooks': [
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{
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'type': 'print'
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}
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]
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"in": [f"agent{i}" for i in range(N)],
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"out": "raspberry",
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"mode": "any",
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"hooks": [{"type": "print"}],
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},
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]
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config = {
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'nodes': nodes,
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'paths': paths
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}
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config = {"nodes": nodes, "paths": paths}
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json.dump(config, sys.stdout, indent=2)
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@ -34,291 +34,335 @@ import re
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import json
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whitelist = [
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[ 'xilinx.com', 'ip', 'zynq_ultra_ps_e' ],
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[ 'xilinx.com', 'ip', 'axi_timer' ],
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[ 'xilinx.com', 'ip', 'axis_switch' ],
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[ 'xilinx.com', 'ip', 'axi_fifo_mm_s' ],
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[ 'xilinx.com', 'ip', 'axi_dma' ],
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[ 'xilinx.com', 'ip', 'aurora_8b10b' ],
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[ 'xilinx.com', 'ip', 'axi_gpio' ],
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[ 'xilinx.com', 'ip', 'axi_bram_ctrl' ],
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[ 'xilinx.com', 'ip', 'axi_pcie' ],
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[ 'xilinx.com', 'ip', 'axi_iic' ],
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[ 'xilinx.com', 'module_ref', 'dinoif_fast' ],
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[ 'xilinx.com', 'module_ref', 'dinoif_dac' ],
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[ 'xilinx.com', 'module_ref', 'axi_pcie_intc' ],
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[ 'xilinx.com', 'module_ref', 'registerif' ],
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[ 'xilinx.com', 'hls', 'rtds2gpu' ],
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[ 'xilinx.com', 'hls', 'mem' ],
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[ 'acs.eonerc.rwth-aachen.de', 'user', 'axi_pcie_intc' ],
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[ 'acs.eonerc.rwth-aachen.de', 'user', 'rtds_axis' ],
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[ 'acs.eonerc.rwth-aachen.de', 'user', 'aurora_axis' ],
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[ 'acs.eonerc.rwth-aachen.de', 'hls' ],
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[ 'acs.eonerc.rwth-aachen.de', 'sysgen' ]
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["xilinx.com", "ip", "zynq_ultra_ps_e"],
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["xilinx.com", "ip", "axi_timer"],
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["xilinx.com", "ip", "axis_switch"],
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["xilinx.com", "ip", "axi_fifo_mm_s"],
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["xilinx.com", "ip", "axi_dma"],
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["xilinx.com", "ip", "aurora_8b10b"],
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["xilinx.com", "ip", "axi_gpio"],
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["xilinx.com", "ip", "axi_bram_ctrl"],
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["xilinx.com", "ip", "axi_pcie"],
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["xilinx.com", "ip", "axi_iic"],
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["xilinx.com", "module_ref", "dinoif_fast"],
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["xilinx.com", "module_ref", "dinoif_dac"],
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["xilinx.com", "module_ref", "axi_pcie_intc"],
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["xilinx.com", "module_ref", "registerif"],
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["xilinx.com", "hls", "rtds2gpu"],
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["xilinx.com", "hls", "mem"],
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["acs.eonerc.rwth-aachen.de", "user", "axi_pcie_intc"],
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["acs.eonerc.rwth-aachen.de", "user", "rtds_axis"],
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["acs.eonerc.rwth-aachen.de", "user", "aurora_axis"],
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["acs.eonerc.rwth-aachen.de", "hls"],
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["acs.eonerc.rwth-aachen.de", "sysgen"],
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]
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# List of VLNI ids of AXI4-Stream infrastructure IP cores which do not alter data
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# see PG085 (AXI4-Stream Infrastructure IP Suite v2.2)
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axi_converter_whitelist = [
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[ 'xilinx.com', 'ip', 'axis_subset_converter' ],
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[ 'xilinx.com', 'ip', 'axis_clock_converter' ],
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[ 'xilinx.com', 'ip', 'axis_register_slice' ],
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[ 'xilinx.com', 'ip', 'axis_dwidth_converter' ],
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[ 'xilinx.com', 'ip', 'axis_register_slice' ],
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[ 'xilinx.com', 'ip', 'axis_data_fifo' ],
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[ 'xilinx.com', 'ip', 'floating_point' ]
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["xilinx.com", "ip", "axis_subset_converter"],
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["xilinx.com", "ip", "axis_clock_converter"],
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["xilinx.com", "ip", "axis_register_slice"],
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["xilinx.com", "ip", "axis_dwidth_converter"],
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["xilinx.com", "ip", "axis_register_slice"],
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["xilinx.com", "ip", "axis_data_fifo"],
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["xilinx.com", "ip", "floating_point"],
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]
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opponent = {
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'MASTER' : ('SLAVE', 'TARGET'),
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'SLAVE' : ('MASTER', 'INITIATOR'),
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'INITIATOR' : ('TARGET', 'SLAVE'),
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'TARGET' : ('INITIATOR', 'MASTER')
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"MASTER": ("SLAVE", "TARGET"),
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"SLAVE": ("MASTER", "INITIATOR"),
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"INITIATOR": ("TARGET", "SLAVE"),
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"TARGET": ("INITIATOR", "MASTER"),
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}
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def bus_trace(root, busname, type, whitelist):
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module = root.xpath('.//MODULE[.//BUSINTERFACE[@BUSNAME="{}" and (@TYPE="{}" or @TYPE="{}")]]'.format(busname, type[0], type[1]))
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module = root.xpath(
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'.//MODULE[.//BUSINTERFACE[@BUSNAME="{}" and (@TYPE="{}" or @TYPE="{}")]]'.format(
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busname, type[0], type[1]
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)
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)
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vlnv = module[0].get('VLNV')
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instance = module[0].get('INSTANCE')
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vlnv = module[0].get("VLNV")
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instance = module[0].get("INSTANCE")
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if vlnv_match(vlnv, whitelist):
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return instance, busname
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elif vlnv_match(vlnv, axi_converter_whitelist):
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next_bus = module[0].xpath('.//BUSINTERFACE[@TYPE="{}" or @TYPE="{}"]'.format(opponent[type[0]][0], opponent[type[0]][1]))
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next_busname = next_bus[0].get('BUSNAME')
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if vlnv_match(vlnv, whitelist):
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return instance, busname
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elif vlnv_match(vlnv, axi_converter_whitelist):
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next_bus = module[0].xpath(
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'.//BUSINTERFACE[@TYPE="{}" or @TYPE="{}"]'.format(
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opponent[type[0]][0], opponent[type[0]][1]
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)
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)
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next_busname = next_bus[0].get("BUSNAME")
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return bus_trace(root, next_busname, type, whitelist)
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else:
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raise TypeError("Unsupported AXI4-Stream IP core: %s (%s)" % (instance, vlnv))
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return bus_trace(root, next_busname, type, whitelist)
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else:
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raise TypeError('Unsupported AXI4-Stream IP core: %s (%s)' % (instance, vlnv))
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def vlnv_match(vlnv, whitelist):
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c = vlnv.split(':')
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c = vlnv.split(":")
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for w in whitelist:
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if c[:len(w)] == w:
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return True
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for w in whitelist:
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if c[: len(w)] == w:
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return True
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return False
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return False
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def remove_prefix(text, prefix):
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return text[text.startswith(prefix) and len(prefix):]
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return text[text.startswith(prefix) and len(prefix) :]
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def sanitize_name(name):
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name = remove_prefix(name, 'S_')
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name = remove_prefix(name, 'M_')
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name = remove_prefix(name, 'AXI_')
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name = remove_prefix(name, 'AXIS_')
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name = remove_prefix(name, "S_")
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name = remove_prefix(name, "M_")
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name = remove_prefix(name, "AXI_")
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name = remove_prefix(name, "AXIS_")
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return name
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return name
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if len(sys.argv) < 2:
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print('Usage: {} path/to/*.hwdef'.format(sys.argv[0]))
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print(' {} path/to/*.hwh'.format(sys.argv[0]))
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sys.exit(1)
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print("Usage: {} path/to/*.hwdef".format(sys.argv[0]))
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print(" {} path/to/*.hwh".format(sys.argv[0]))
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sys.exit(1)
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try:
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# read .hwdef which is actually a zip-file
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zip = zipfile.ZipFile(sys.argv[1], 'r')
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hwh = zip.read('top.hwh')
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# read .hwdef which is actually a zip-file
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zip = zipfile.ZipFile(sys.argv[1], "r")
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hwh = zip.read("top.hwh")
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except:
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f = open(sys.argv[1], 'r')
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hwh = f.read()
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f = open(sys.argv[1], "r")
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hwh = f.read()
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# parse .hwh file which is actually XML
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try:
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root = etree.XML(hwh)
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root = etree.XML(hwh)
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except:
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print('Bad format of "{}"! Did you choose the right file?'.format(sys.argv[1]))
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sys.exit(1)
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print('Bad format of "{}"! Did you choose the right file?'.format(sys.argv[1]))
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sys.exit(1)
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ips = {}
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# find all whitelisted modules
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modules = root.find('.//MODULES')
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modules = root.find(".//MODULES")
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for module in modules:
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instance = module.get('INSTANCE')
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vlnv = module.get('VLNV')
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instance = module.get("INSTANCE")
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vlnv = module.get("VLNV")
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# Ignroing unkown
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if not vlnv_match(vlnv, whitelist):
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continue
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# Ignroing unkown
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if not vlnv_match(vlnv, whitelist):
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continue
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ips[instance] = {
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'vlnv' : vlnv
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}
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ips[instance] = {"vlnv": vlnv}
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# populate parameters
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params = module.find('.//PARAMETERS')
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if params is not None and instance != "zynq_ultra_ps_e_0": #! Parameters of "zynq" ignored
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p = ips[instance].setdefault('parameters', {})
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# populate parameters
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params = module.find(".//PARAMETERS")
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if (
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params is not None and instance != "zynq_ultra_ps_e_0"
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): #! Parameters of "zynq" ignored
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p = ips[instance].setdefault("parameters", {})
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for param in params:
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name = param.get('NAME').lower()
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value = param.get('VALUE')
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for param in params:
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name = param.get("NAME").lower()
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value = param.get("VALUE")
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try:
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value = int(value, 0)
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except ValueError:
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pass
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try:
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value = int(value, 0)
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except ValueError:
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pass
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p[name] = value
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p[name] = value
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# populate memory view
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mmap = module.find('.//MEMORYMAP')
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if mmap is None:
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continue
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# populate memory view
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mmap = module.find(".//MEMORYMAP")
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if mmap is None:
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continue
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mem = ips[instance].setdefault('memory-view', {})
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for mrange in mmap:
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mem_interface = mrange.get('MASTERBUSINTERFACE')
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mem_instance = mrange.get('INSTANCE')
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mem_block = mrange.get('ADDRESSBLOCK')
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mem = ips[instance].setdefault("memory-view", {})
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for mrange in mmap:
|
||||
mem_interface = mrange.get("MASTERBUSINTERFACE")
|
||||
mem_instance = mrange.get("INSTANCE")
|
||||
mem_block = mrange.get("ADDRESSBLOCK")
|
||||
|
||||
_interface = mem.setdefault(mem_interface, {})
|
||||
_instance = _interface.setdefault(mem_instance, {})
|
||||
_block = _instance.setdefault(mem_block, {})
|
||||
_interface = mem.setdefault(mem_interface, {})
|
||||
_instance = _interface.setdefault(mem_instance, {})
|
||||
_block = _instance.setdefault(mem_block, {})
|
||||
|
||||
_block['baseaddr'] = int(mrange.get('BASEVALUE'), 16)
|
||||
_block['highaddr'] = int(mrange.get('HIGHVALUE'), 16)
|
||||
_block['size'] = _block['highaddr'] - _block['baseaddr'] + 1
|
||||
_block["baseaddr"] = int(mrange.get("BASEVALUE"), 16)
|
||||
_block["highaddr"] = int(mrange.get("HIGHVALUE"), 16)
|
||||
_block["size"] = _block["highaddr"] - _block["baseaddr"] + 1
|
||||
|
||||
|
||||
# find AXI-Stream switch port mapping
|
||||
switch = root.find('.//MODULE[@MODTYPE="axis_switch"]')
|
||||
busifs = switch.find('.//BUSINTERFACES')
|
||||
busifs = switch.find(".//BUSINTERFACES")
|
||||
switch_ports = 0
|
||||
for busif in busifs:
|
||||
if busif.get('VLNV') != 'xilinx.com:interface:axis:1.0':
|
||||
continue
|
||||
if busif.get("VLNV") != "xilinx.com:interface:axis:1.0":
|
||||
continue
|
||||
|
||||
switch_ports += 1
|
||||
switch_ports += 1
|
||||
|
||||
busname = busif.get('BUSNAME')
|
||||
name = busif.get('NAME')
|
||||
type = busif.get('TYPE')
|
||||
busname = busif.get("BUSNAME")
|
||||
name = busif.get("NAME")
|
||||
type = busif.get("TYPE")
|
||||
|
||||
r = re.compile('(M|S)([0-9]+)_AXIS')
|
||||
m = r.search(name)
|
||||
r = re.compile("(M|S)([0-9]+)_AXIS")
|
||||
m = r.search(name)
|
||||
|
||||
port = int(m.group(2))
|
||||
port = int(m.group(2))
|
||||
|
||||
switch_ip_ports = ips[switch.get('INSTANCE')].setdefault('ports', [])
|
||||
switch_ip_ports = ips[switch.get("INSTANCE")].setdefault("ports", [])
|
||||
|
||||
ep, busname_ep = bus_trace(root, busname, opponent[type], whitelist)
|
||||
if ep in ips:
|
||||
ep, busname_ep = bus_trace(root, busname, opponent[type], whitelist)
|
||||
if ep in ips:
|
||||
ports = ips[ep].setdefault("ports", [])
|
||||
ports.append(
|
||||
{
|
||||
"role": opponent[type][0].lower(),
|
||||
"target": "{}:{}".format(switch.get("INSTANCE"), name),
|
||||
}
|
||||
)
|
||||
|
||||
ports = ips[ep].setdefault('ports', [])
|
||||
ports.append({
|
||||
'role': opponent[type][0].lower(),
|
||||
'target': '{}:{}'.format(switch.get('INSTANCE'), name)
|
||||
})
|
||||
module_ep = root.find('.//MODULE[@INSTANCE="{}"]'.format(ep))
|
||||
busif_ep = module_ep.find('.//BUSINTERFACE[@BUSNAME="{}"]'.format(busname_ep))
|
||||
if busif_ep is None:
|
||||
print("cannot find businterface: {}".format(busname_ep))
|
||||
sys.exit(1)
|
||||
|
||||
module_ep = root.find('.//MODULE[@INSTANCE="{}"]'.format(ep))
|
||||
busif_ep = module_ep.find('.//BUSINTERFACE[@BUSNAME="{}"]'.format(busname_ep))
|
||||
if busif_ep is None:
|
||||
print("cannot find businterface: {}".format(busname_ep))
|
||||
sys.exit(1)
|
||||
busif_name = ports[-1]["name"] = sanitize_name(busif_ep.get("NAME"))
|
||||
ports[-1]["name"] = busif_name
|
||||
|
||||
busif_name = ports[-1]['name'] = sanitize_name(busif_ep.get('NAME'))
|
||||
ports[-1]['name'] = busif_name
|
||||
|
||||
switch_ip_ports.append({
|
||||
'role': type.lower(),
|
||||
'target': '{}:{}'.format(ep, busif_name),
|
||||
'name': name
|
||||
})
|
||||
switch_ip_ports.append(
|
||||
{
|
||||
"role": type.lower(),
|
||||
"target": "{}:{}".format(ep, busif_name),
|
||||
"name": name,
|
||||
}
|
||||
)
|
||||
|
||||
# set number of master/slave port pairs for switch
|
||||
ips[switch.get('INSTANCE')]['num_ports'] = int(switch_ports / 2)
|
||||
ips[switch.get("INSTANCE")]["num_ports"] = int(switch_ports / 2)
|
||||
|
||||
# find interrupt assignments
|
||||
intc = root.find('.//MODULE[@MODTYPE="axi_pcie_intc"]')
|
||||
if intc is not None:
|
||||
intr = intc.xpath('.//PORT[@NAME="intr" and @DIR="I"]')[0]
|
||||
concat = root.xpath('.//MODULE[@MODTYPE="xlconcat" and .//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(intr.get('SIGNAME')))[0]
|
||||
ports = concat.xpath('.//PORT[@DIR="I"]')
|
||||
intr = intc.xpath('.//PORT[@NAME="intr" and @DIR="I"]')[0]
|
||||
concat = root.xpath(
|
||||
'.//MODULE[@MODTYPE="xlconcat" and .//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(
|
||||
intr.get("SIGNAME")
|
||||
)
|
||||
)[0]
|
||||
ports = concat.xpath('.//PORT[@DIR="I"]')
|
||||
|
||||
for port in ports:
|
||||
name = port.get('NAME')
|
||||
signame = port.get('SIGNAME')
|
||||
for port in ports:
|
||||
name = port.get("NAME")
|
||||
signame = port.get("SIGNAME")
|
||||
|
||||
# Skip unconnected IRQs
|
||||
if not signame:
|
||||
continue
|
||||
# Skip unconnected IRQs
|
||||
if not signame:
|
||||
continue
|
||||
|
||||
r = re.compile('In([0-9+])')
|
||||
m = r.search(name)
|
||||
r = re.compile("In([0-9+])")
|
||||
m = r.search(name)
|
||||
|
||||
irq = int(m.group(1))
|
||||
ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0]
|
||||
irq = int(m.group(1))
|
||||
ip = root.xpath(
|
||||
'.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame)
|
||||
)[0]
|
||||
|
||||
instance = ip.get('INSTANCE')
|
||||
vlnv = ip.get('VLNV')
|
||||
modtype = ip.get('MODTYPE')
|
||||
instance = ip.get("INSTANCE")
|
||||
vlnv = ip.get("VLNV")
|
||||
modtype = ip.get("MODTYPE")
|
||||
|
||||
originators = []
|
||||
originators = []
|
||||
|
||||
# follow one level of OR gates merging interrupts (may be generalized later)
|
||||
if modtype == 'util_vector_logic':
|
||||
logic_op = ip.xpath('.//PARAMETER[@NAME="C_OPERATION"]')[0]
|
||||
if logic_op.get('VALUE') == 'or':
|
||||
# hardware interrupts sharing the same IRQ at the controller
|
||||
ports = ip.xpath('.//PORT[@DIR="I"]')
|
||||
for port in ports:
|
||||
signame = port.get('SIGNAME')
|
||||
ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0]
|
||||
instance = ip.get('INSTANCE')
|
||||
originators.append((instance, signame))
|
||||
else:
|
||||
# consider this instance as originator
|
||||
originators.append((instance, signame))
|
||||
# follow one level of OR gates merging interrupts (may be generalized later)
|
||||
if modtype == "util_vector_logic":
|
||||
logic_op = ip.xpath('.//PARAMETER[@NAME="C_OPERATION"]')[0]
|
||||
if logic_op.get("VALUE") == "or":
|
||||
# hardware interrupts sharing the same IRQ at the controller
|
||||
ports = ip.xpath('.//PORT[@DIR="I"]')
|
||||
for port in ports:
|
||||
signame = port.get("SIGNAME")
|
||||
ip = root.xpath(
|
||||
'.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame)
|
||||
)[0]
|
||||
instance = ip.get("INSTANCE")
|
||||
originators.append((instance, signame))
|
||||
else:
|
||||
# consider this instance as originator
|
||||
originators.append((instance, signame))
|
||||
|
||||
for instance, signame in originators:
|
||||
ip = root.xpath(
|
||||
'.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame)
|
||||
)[0]
|
||||
port = ip.xpath('.//PORT[@SIGNAME="{}" and @DIR="O"]'.format(signame))[0]
|
||||
irqname = port.get("NAME")
|
||||
|
||||
for instance, signame in originators:
|
||||
ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0]
|
||||
port = ip.xpath('.//PORT[@SIGNAME="{}" and @DIR="O"]'.format(signame))[0]
|
||||
irqname = port.get('NAME')
|
||||
|
||||
if instance in ips:
|
||||
irqs = ips[instance].setdefault('irqs', {})
|
||||
irqs[irqname] = '{}:{}'.format(intc.get('INSTANCE'), irq)
|
||||
if instance in ips:
|
||||
irqs = ips[instance].setdefault("irqs", {})
|
||||
irqs[irqname] = "{}:{}".format(intc.get("INSTANCE"), irq)
|
||||
|
||||
# Find BRAM storage depths (size)
|
||||
brams = root.xpath('.//MODULE[@MODTYPE="axi_bram_ctrl"]')
|
||||
for bram in brams:
|
||||
instance = bram.get('INSTANCE')
|
||||
instance = bram.get("INSTANCE")
|
||||
|
||||
width = bram.find('.//PARAMETER[@NAME="DATA_WIDTH"]').get('VALUE')
|
||||
depth = bram.find('.//PARAMETER[@NAME="MEM_DEPTH"]').get('VALUE')
|
||||
width = bram.find('.//PARAMETER[@NAME="DATA_WIDTH"]').get("VALUE")
|
||||
depth = bram.find('.//PARAMETER[@NAME="MEM_DEPTH"]').get("VALUE")
|
||||
|
||||
size = int(width) * int(depth) / 8
|
||||
size = int(width) * int(depth) / 8
|
||||
|
||||
if instance in ips:
|
||||
ips[instance]['size'] = int(size)
|
||||
if instance in ips:
|
||||
ips[instance]["size"] = int(size)
|
||||
|
||||
pcies = root.xpath('.//MODULE[@MODTYPE="axi_pcie"]')
|
||||
for pcie in pcies:
|
||||
instance = pcie.get('INSTANCE')
|
||||
axi_bars = ips[instance].setdefault('axi_bars', {})
|
||||
pcie_bars = ips[instance].setdefault('pcie_bars', {})
|
||||
instance = pcie.get("INSTANCE")
|
||||
axi_bars = ips[instance].setdefault("axi_bars", {})
|
||||
pcie_bars = ips[instance].setdefault("pcie_bars", {})
|
||||
|
||||
for from_bar, to_bar, from_bars in (('AXIBAR', 'PCIEBAR', axi_bars), ('PCIEBAR', 'AXIBAR', pcie_bars)):
|
||||
from_bar_num = int(pcie.find('.//PARAMETER[@NAME="C_{}_NUM"]'.format(from_bar)).get('VALUE'))
|
||||
for from_bar, to_bar, from_bars in (
|
||||
("AXIBAR", "PCIEBAR", axi_bars),
|
||||
("PCIEBAR", "AXIBAR", pcie_bars),
|
||||
):
|
||||
from_bar_num = int(
|
||||
pcie.find('.//PARAMETER[@NAME="C_{}_NUM"]'.format(from_bar)).get("VALUE")
|
||||
)
|
||||
|
||||
for i in range(0, from_bar_num):
|
||||
from_bar_to_bar_offset = int(pcie.find('.//PARAMETER[@NAME="C_{}2{}_{}"]'.format(from_bar, to_bar, i)).get('VALUE'), 16)
|
||||
from_bars['BAR{}'.format(i)] = { 'translation': from_bar_to_bar_offset }
|
||||
for i in range(0, from_bar_num):
|
||||
from_bar_to_bar_offset = int(
|
||||
pcie.find(
|
||||
'.//PARAMETER[@NAME="C_{}2{}_{}"]'.format(from_bar, to_bar, i)
|
||||
).get("VALUE"),
|
||||
16,
|
||||
)
|
||||
from_bars["BAR{}".format(i)] = {"translation": from_bar_to_bar_offset}
|
||||
|
||||
if from_bar == 'AXIBAR':
|
||||
axi_bar_lo = int(pcie.find('.//PARAMETER[@NAME="C_{}_{}"]'.format(from_bar, i)).get('VALUE'), 16)
|
||||
axi_bar_hi = int(pcie.find('.//PARAMETER[@NAME="C_{}_HIGHADDR_{}"]'.format(from_bar, i)).get('VALUE'), 16)
|
||||
axi_bar_size = axi_bar_hi - axi_bar_lo + 1
|
||||
if from_bar == "AXIBAR":
|
||||
axi_bar_lo = int(
|
||||
pcie.find('.//PARAMETER[@NAME="C_{}_{}"]'.format(from_bar, i)).get(
|
||||
"VALUE"
|
||||
),
|
||||
16,
|
||||
)
|
||||
axi_bar_hi = int(
|
||||
pcie.find(
|
||||
'.//PARAMETER[@NAME="C_{}_HIGHADDR_{}"]'.format(from_bar, i)
|
||||
).get("VALUE"),
|
||||
16,
|
||||
)
|
||||
axi_bar_size = axi_bar_hi - axi_bar_lo + 1
|
||||
|
||||
axi_bar = from_bars['BAR{}'.format(i)]
|
||||
axi_bar['baseaddr'] = axi_bar_lo
|
||||
axi_bar['highaddr'] = axi_bar_hi
|
||||
axi_bar['size'] = axi_bar_size
|
||||
axi_bar = from_bars["BAR{}".format(i)]
|
||||
axi_bar["baseaddr"] = axi_bar_lo
|
||||
axi_bar["highaddr"] = axi_bar_hi
|
||||
axi_bar["size"] = axi_bar_size
|
||||
|
||||
print(json.dumps(ips, indent=2))
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue