refactor Core::configure() to Core::parse()

Signed-off-by: Steffen Vogel <post@steffenvogel.de>

fpga/include/villas/fpga/core.hpp

@@ -305,7 +305,7 @@ protected:
 
 	// Configure IP instance from JSON config
 	virtual
-	void configure(Core &, json_t *)
+	void parse(Core &, json_t *)
 	{ }
 
 private:

fpga/include/villas/fpga/ips/bram.hpp

@@ -57,7 +57,7 @@ private:
 class BramFactory : public CoreFactory {
 public:
 
-	void configure(Core &ip, json_t *cfg);
+	void parse(Core &ip, json_t *cfg);
 
 	Core* create()
 	{

fpga/include/villas/fpga/ips/dma.hpp

@@ -175,7 +175,7 @@ public:
 	}
 
 	virtual
-	void configure(Core& ip, json_t* json) override;
+	void parse(Core& ip, json_t* json) override;
 
 	virtual void
 	configurePollingMode(Core& ip, PollingMode mode) override

fpga/include/villas/fpga/ips/pcie.hpp

@@ -67,7 +67,7 @@ public:
 		return "xilinx.com:ip:axi_pcie:";
 	}
 
-	void configure(Core &ip, json_t *cfg);
+	void parse(Core &ip, json_t *cfg);
 
 	Core* create()
 	{

fpga/include/villas/fpga/ips/switch.hpp

@@ -79,7 +79,7 @@ public:
 		return "xilinx.com:ip:axis_switch:";
 	}
 
-	void configure(Core &ip, json_t *cfg);
+	void parse(Core &ip, json_t *cfg);
 
 	Core* create()
 	{

fpga/include/villas/fpga/node.hpp

@@ -167,7 +167,7 @@ public:
 	using CoreFactory::CoreFactory;
 
 	virtual
-	void configure(Core &ip, json_t *cfg);
+	void parse(Core &ip, json_t *cfg);
 };
 
 } /* namespace ip */

fpga/lib/core.cpp

@@ -245,7 +245,7 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
 		}
 
 		// IP-specific setup via JSON config
-		CoreFactory->configure(*ip, json_ip);
+		CoreFactory->parse(*ip, json_ip);
 
 		// Set polling mode
 		CoreFactory->configurePollingMode(*ip, (card->polling ? PollingMode::POLL : PollingMode::IRQ));

fpga/lib/ips/bram.cpp

@@ -27,9 +27,9 @@ using namespace villas::fpga::ip;
 
 static BramFactory factory;
 
-void BramFactory::configure(Core &ip, json_t* cfg)
+void BramFactory::parse(Core &ip, json_t* cfg)
 {
-	CoreFactory::configure(ip, cfg);
+	CoreFactory::parse(ip, cfg);
 
 	auto &bram = dynamic_cast<Bram&>(ip);
 

fpga/lib/ips/dma.cpp

@@ -618,9 +618,9 @@ void Dma::dump()
 	logger->info("MM2S_DMASR:  {:x}", XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_TX_OFFSET + XAXIDMA_SR_OFFSET));
 }
 
-void DmaFactory::configure(Core &ip, json_t *cfg)
+void DmaFactory::parse(Core &ip, json_t *cfg)
 {
-	NodeFactory::configure(ip, cfg);
+	NodeFactory::parse(ip, cfg);
 
 	auto &dma = dynamic_cast<Dma&>(ip);
 

fpga/lib/ips/pcie.cpp

@@ -113,9 +113,9 @@ AxiPciExpressBridge::init()
 }
 
 void
-AxiPciExpressBridgeFactory::configure(Core &ip, json_t *cfg)
+AxiPciExpressBridgeFactory::parse(Core &ip, json_t *cfg)
 {
-	CoreFactory::configure(ip, cfg);
+	CoreFactory::parse(ip, cfg);
 
 	auto logger = getLogger();
 	auto &pcie = dynamic_cast<AxiPciExpressBridge&>(ip);

fpga/lib/ips/switch.cpp

@@ -128,9 +128,9 @@ int AxiStreamSwitch::portNameToNum(const std::string &portName)
 	return std::stoi(number);
 }
 
-void AxiStreamSwitchFactory::configure(Core &ip, json_t *cfg)
+void AxiStreamSwitchFactory::parse(Core &ip, json_t *cfg)
 {
-	NodeFactory::configure(ip, cfg);
+	NodeFactory::parse(ip, cfg);
 
 	auto logger = getLogger();
 

fpga/lib/node.cpp

@@ -36,9 +36,9 @@ using namespace villas::fpga::ip;
 StreamGraph
 Node::streamGraph;
 
-void NodeFactory::configure(Core &ip, json_t *cfg)
+void NodeFactory::parse(Core &ip, json_t *cfg)
 {
-	CoreFactory::configure(ip, cfg);
+	CoreFactory::parse(ip, cfg);
 
 	auto &Node = dynamic_cast<ip::Node&>(ip);
 	auto logger = getLogger();