mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
dma: added second version of scatter-gather support
This commit is contained in:
parent
2f7107753a
commit
0dfffb94c4
2 changed files with 240 additions and 181 deletions
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@ -47,12 +47,12 @@ public:
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size_t writeComplete()
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{
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return hasScatterGather() ? writeCompleteSG() : writeCompleteSimple();
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return hasScatterGather() ? writeCompleteScatterGather() : writeCompleteSimple();
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}
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size_t readComplete()
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{
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return hasScatterGather() ? readCompleteSG() : readCompleteSimple();
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return hasScatterGather() ? readCompleteScatterGather() : readCompleteSimple();
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}
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bool memcpy(const MemoryBlock &src, const MemoryBlock &dst, size_t len);
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@ -79,18 +79,21 @@ public:
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}
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private:
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bool writeSG(const void* buf, size_t len);
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bool readSG(void* buf, size_t len);
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size_t writeCompleteSG();
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size_t readCompleteSG();
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bool writeScatterGather(const void* buf, size_t len);
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bool readScatterGather(void* buf, size_t len);
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size_t writeCompleteScatterGather();
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size_t readCompleteScatterGather();
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bool writeSimple(const void* buf, size_t len);
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bool readSimple(void* buf, size_t len);
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size_t writeCompleteSimple();
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size_t readCompleteSimple();
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void setupRingRx();
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void setupRingTx();
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void setupScatterGather();
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void setupScatterGatherRingRx();
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void setupScatterGatherRingTx();
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static constexpr size_t ringSize = sizeof(uint16_t) * XAXIDMA_BD_NUM_WORDS * 1024;
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public:
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static constexpr const char* s2mmPort = "S2MM";
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@ -122,7 +125,11 @@ private:
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XAxiDma xDma;
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bool hasSG;
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MemoryBlock sgRings;
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int delay;
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int coalesce;
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MemoryBlock::UniquePtr sgRingTx;
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MemoryBlock::UniquePtr sgRingRx;
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};
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class DmaFactory : public NodeFactory {
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@ -148,9 +155,7 @@ public:
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virtual Vlnv
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getCompatibleVlnv() const
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{
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return {
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"xilinx.com:ip:axi_dma:"
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};
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return Vlnv("xilinx.com:ip:axi_dma:");
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}
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};
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@ -43,6 +43,9 @@ static DmaFactory factory;
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bool
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Dma::init()
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{
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coalesce = 1;
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delay = 0;
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// If there is a scatter-gather interface, then this instance has it
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hasSG = busMasterInterfaces.count(sgInterface) == 1;
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logger->info("Scatter-Gather support: {}", hasScatterGather());
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@ -64,6 +67,7 @@ Dma::init()
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xdma_cfg.S2MmBurstSize = 16;
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xdma_cfg.MicroDmaMode = 0;
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xdma_cfg.AddrWidth = 32;
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xdma_cfg.SgLengthWidth = 14;
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if (XAxiDma_CfgInitialize(&xDma, &xdma_cfg) != XST_SUCCESS) {
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logger->error("Cannot initialize Xilinx DMA driver");
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@ -79,15 +83,7 @@ Dma::init()
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// Map buffer descriptors
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if (hasScatterGather()) {
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auto &alloc = villas::HostRam::getAllocator();
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auto mem = alloc.allocate<uint8_t>(0x2000);
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sgRings = mem.getMemoryBlock();
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makeAccesibleFromVA(sgRings);
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setupRingRx();
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setupRingTx();
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setupScatterGather();
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}
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// Enable completion interrupts for both channels
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@ -100,138 +96,105 @@ Dma::init()
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return true;
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}
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void Dma::setupRingRx()
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void Dma::setupScatterGather()
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{
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XAxiDma_BdRing *RxRingPtr;
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int Delay = 0;
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int Coalesce = 1;
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int Status;
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XAxiDma_Bd BdTemplate;
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XAxiDma_Bd *BdPtr;
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XAxiDma_Bd *BdCurPtr;
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u32 BdCount;
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u32 FreeBdCount;
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UINTPTR RxBufferPtr;
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int Index;
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RxRingPtr = XAxiDma_GetRxRing(&xDma);
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/* Disable all RX interrupts before RxBD space setup */
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XAxiDma_BdRingIntDisable(RxRingPtr, XAXIDMA_IRQ_ALL_MASK);
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/* Set delay and coalescing */
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XAxiDma_BdRingSetCoalesce(RxRingPtr, Coalesce, Delay);
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/* Setup Rx BD space */
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BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, 0x1000);
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Status = XAxiDma_BdRingCreate(RxRingPtr, sgRings., RX_BD_SPACE_BASE, XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);
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if (Status != XST_SUCCESS)
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throw RuntimeError("RX create BD ring failed {}", Status);
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/*
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* Setup an all-zero BD as the template for the Rx channel.
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*/
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XAxiDma_BdClear(&BdTemplate);
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Status = XAxiDma_BdRingClone(RxRingPtr, &BdTemplate);
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if (Status != XST_SUCCESS)
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throw RuntimeError("RX clone BD failed {}", Status);
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/* Attach buffers to RxBD ring so we are ready to receive packets */
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FreeBdCount = XAxiDma_BdRingGetFreeCnt(RxRingPtr);
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Status = XAxiDma_BdRingAlloc(RxRingPtr, FreeBdCount, &BdPtr);
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if (Status != XST_SUCCESS)
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throw RuntimeError("RX alloc BD failed {}", Status);
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BdCurPtr = BdPtr;
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RxBufferPtr = RX_BUFFER_BASE;
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for (Index = 0; Index < FreeBdCount; Index++) {
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Status = XAxiDma_BdSetBufAddr(BdCurPtr, RxBufferPtr);
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if (Status != XST_SUCCESS)
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throw RuntimeError("Set buffer addr {} on BD {} failed {}", (unsigned int)RxBufferPtr, (UINTPTR)BdCurPtr, Status);
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Status = XAxiDma_BdSetLength(BdCurPtr, MAX_PKT_LEN, RxRingPtr->MaxTransferLen);
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if (Status != XST_SUCCESS)
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throw RuntimeError("Rx set length {} on BD {} failed {}", MAX_PKT_LEN, (UINTPTR)BdCurPtr, Status);
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/* Receive BDs do not need to set anything for the control
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* The hardware will set the SOF/EOF bits per stream status
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*/
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XAxiDma_BdSetCtrl(BdCurPtr, 0);
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XAxiDma_BdSetId(BdCurPtr, RxBufferPtr);
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RxBufferPtr += MAX_PKT_LEN;
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BdCurPtr = (XAxiDma_Bd *)XAxiDma_BdRingNext(RxRingPtr, BdCurPtr);
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}
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/* Clear the receive buffer, so we can verify data
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*/
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memset((void *)RX_BUFFER_BASE, 0, MAX_PKT_LEN);
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Status = XAxiDma_BdRingToHw(RxRingPtr, FreeBdCount, BdPtr);
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if (Status != XST_SUCCESS)
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throw RuntimeError("RX submit hw failed {}", Status);
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/* Start RX DMA channel */
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Status = XAxiDma_BdRingStart(RxRingPtr);
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if (Status != XST_SUCCESS)
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throw RuntimeError("RX start hw failed {}", Status);
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setupScatterGatherRingRx();
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setupScatterGatherRingTx();
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}
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void Dma::setupRingTx()
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void Dma::setupScatterGatherRingRx()
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{
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XAxiDma_BdRing *TxRingPtr;
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int ret;
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auto *rxRingPtr = XAxiDma_GetRxRing(&xDma);
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// Disable all RX interrupts before RxBD space setup
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XAxiDma_BdRingIntDisable(rxRingPtr, XAXIDMA_IRQ_ALL_MASK);
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// Set delay and coalescing
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XAxiDma_BdRingSetCoalesce(rxRingPtr, coalesce, delay);
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// Allocate and map space for BD ring in host RAM
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auto &alloc = villas::HostRam::getAllocator();
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sgRingRx = alloc.allocateBlock(ringSize);
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if (not card->mapMemoryBlock(*sgRingRx))
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throw RuntimeError("Memory not accessible by DMA");
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auto &mm = MemoryManager::get();
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auto trans = mm.getTranslation(busMasterInterfaces[sgInterface], sgRingRx->getAddrSpaceId());
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auto physAddr = reinterpret_cast<uintptr_t>(trans.getLocalAddr(0));
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auto virtAddr = reinterpret_cast<uintptr_t>(mm.getTranslationFromProcess(sgRingRx->getAddrSpaceId()).getLocalAddr(0));
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// Setup Rx BD space
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auto bdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, sgRingRx->getSize());
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ret = XAxiDma_BdRingCreate(rxRingPtr, physAddr, virtAddr, XAXIDMA_BD_MINIMUM_ALIGNMENT, bdCount);
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if (ret != XST_SUCCESS)
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throw RuntimeError("Failed to create RX ring: {}", ret);
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// Setup an all-zero BD as the template for the Rx channel.
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XAxiDma_Bd bdTemplate;
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XAxiDma_BdClear(&bdTemplate);
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ret = XAxiDma_BdRingClone(rxRingPtr, &bdTemplate);
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if (ret != XST_SUCCESS)
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throw RuntimeError("Failed to clone BD template: {}", ret);
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// Start the RX channel
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ret = XAxiDma_BdRingStart(rxRingPtr);
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if (ret != XST_SUCCESS)
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throw RuntimeError("Failed to start TX ring: {}", ret);
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}
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void Dma::setupScatterGatherRingTx()
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{
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int ret;
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auto *txRingPtr = XAxiDma_GetTxRing(&xDma);
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// Disable all TX interrupts before TxBD space setup
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XAxiDma_BdRingIntDisable(txRingPtr, XAXIDMA_IRQ_ALL_MASK);
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// Set TX delay and coalesce
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XAxiDma_BdRingSetCoalesce(txRingPtr, coalesce, delay);
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// Allocate and map space for BD ring in host RAM
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auto &alloc = villas::HostRam::getAllocator();
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sgRingTx = alloc.allocateBlock(ringSize);
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if (not card->mapMemoryBlock(*sgRingTx))
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throw RuntimeError("Memory not accessible by DMA");
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auto &mm = MemoryManager::get();
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auto trans = mm.getTranslation(busMasterInterfaces[sgInterface], sgRingTx->getAddrSpaceId());
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auto physAddr = reinterpret_cast<uintptr_t>(trans.getLocalAddr(0));
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auto virtAddr = reinterpret_cast<uintptr_t>(mm.getTranslationFromProcess(sgRingTx->getAddrSpaceId()).getLocalAddr(0));
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// Setup TxBD space
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auto bdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, sgRingTx->getSize());
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ret = XAxiDma_BdRingCreate(txRingPtr, physAddr, virtAddr, XAXIDMA_BD_MINIMUM_ALIGNMENT, bdCount);
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if (ret != XST_SUCCESS)
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throw RuntimeError("Failed to create TX BD ring: {}", ret);
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// We create an all-zero BD as the template.
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XAxiDma_Bd BdTemplate;
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int Delay = 0;
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int Coalesce = 1;
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int Status;
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u32 BdCount;
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TxRingPtr = XAxiDma_GetTxRing(&xDma);
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/* Disable all TX interrupts before TxBD space setup */
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XAxiDma_BdRingIntDisable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);
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/* Set TX delay and coalesce */
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XAxiDma_BdRingSetCoalesce(TxRingPtr, Coalesce, Delay);
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/* Setup TxBD space */
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BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, TX_BD_SPACE_HIGH - TX_BD_SPACE_BASE + 1);
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Status = XAxiDma_BdRingCreate(TxRingPtr, TX_BD_SPACE_BASE, TX_BD_SPACE_BASE, XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);
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if (Status != XST_SUCCESS)
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throw RuntimeError("failed create BD ring in txsetup");
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/*
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* We create an all-zero BD as the template.
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*/
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XAxiDma_BdClear(&BdTemplate);
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Status = XAxiDma_BdRingClone(TxRingPtr, &BdTemplate);
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if (Status != XST_SUCCESS)
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throw RuntimeError("failed bdring clone in txsetup {}", Status);
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ret = XAxiDma_BdRingClone(txRingPtr, &BdTemplate);
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if (ret != XST_SUCCESS)
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throw RuntimeError("Failed to clone TX ring BD: {}", ret);
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/* Start the TX channel */
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Status = XAxiDma_BdRingStart(TxRingPtr);
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if (Status != XST_SUCCESS)
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throw RuntimeError("failed start bdring txsetup {}", Status);
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// Start the TX channel
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ret = XAxiDma_BdRingStart(txRingPtr);
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if (ret != XST_SUCCESS)
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throw RuntimeError("Failed to start TX ring: {}", ret);
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}
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bool
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Dma::reset()
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{
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logger->info("DMA resetted");
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XAxiDma_Reset(&xDma);
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// Value taken from libxil implementation
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@ -244,6 +207,8 @@ Dma::reset()
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timeout--;
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}
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logger->info("DMA resetted");
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return false;
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}
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@ -274,63 +239,159 @@ Dma::memcpy(const MemoryBlock &src, const MemoryBlock &dst, size_t len)
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bool
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Dma::write(const MemoryBlock &mem, size_t len)
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{
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if (len == 0)
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return true;
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if (len > FPGA_DMA_BOUNDARY)
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return false;
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auto &mm = MemoryManager::get();
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// User has to make sure that memory is accessible, otherwise this will throw
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auto translation = mm.getTranslation(busMasterInterfaces[mm2sInterface],
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mem.getAddrSpaceId());
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const void* buf = reinterpret_cast<void*>(translation.getLocalAddr(0));
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auto trans = mm.getTranslation(busMasterInterfaces[mm2sInterface], mem.getAddrSpaceId());
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const void *buf = reinterpret_cast<void*>(trans.getLocalAddr(0));
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if (buf == nullptr)
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throw RuntimeError("Buffer was null");
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logger->debug("Write to stream from address {:p}", buf);
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return hasScatterGather() ? writeSG(buf, len) : writeSimple(buf, len);
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return hasScatterGather() ? writeScatterGather(buf, len) : writeSimple(buf, len);
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}
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bool
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Dma::read(const MemoryBlock &mem, size_t len)
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{
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if (len == 0)
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return true;
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if (len > FPGA_DMA_BOUNDARY)
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return false;
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auto &mm = MemoryManager::get();
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// User has to make sure that memory is accessible, otherwise this will throw
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auto translation = mm.getTranslation(busMasterInterfaces[s2mmInterface],
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mem.getAddrSpaceId());
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void* buf = reinterpret_cast<void*>(translation.getLocalAddr(0));
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auto trans = mm.getTranslation(busMasterInterfaces[s2mmInterface], mem.getAddrSpaceId());
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void *buf = reinterpret_cast<void*>(trans.getLocalAddr(0));
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if (buf == nullptr)
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throw RuntimeError("Buffer was null");
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logger->debug("Read from stream and write to address {:p}", buf);
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return hasScatterGather() ? readSG(buf, len) : readSimple(buf, len);
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return hasScatterGather() ? readScatterGather(buf, len) : readSimple(buf, len);
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}
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bool
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Dma::writeSG(const void* buf, size_t len)
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Dma::writeScatterGather(const void* buf, size_t len)
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{
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(void) buf;
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(void) len;
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logger->error("DMA Scatter Gather write not implemented");
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// buf is address from view of DMA controller
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return false;
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int ret = XST_FAILURE;
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auto *txRing = XAxiDma_GetTxRing(&xDma);
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if (txRing == nullptr)
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throw RuntimeError("TxRing was null.");
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XAxiDma_Bd *bd;
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ret = XAxiDma_BdRingAlloc(txRing, 1, &bd);
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if (ret != XST_SUCCESS)
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throw RuntimeError("BdRingAlloc returned {}.", ret);
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ret = XAxiDma_BdSetBufAddr(bd, (uintptr_t) buf);
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if (ret != XST_SUCCESS)
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throw RuntimeError("Setting BdBufAddr to {} returned {}.", buf, ret);
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ret = XAxiDma_BdSetLength(bd, len, txRing->MaxTransferLen);
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if (ret != XST_SUCCESS)
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throw RuntimeError("Setting BdBufLength to {} returned {}.", len, ret);
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// We have a single descriptor so it is both start and end of the list
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XAxiDma_BdSetCtrl(bd, XAXIDMA_BD_CTRL_TXEOF_MASK | XAXIDMA_BD_CTRL_TXSOF_MASK);
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// TODO: Check if we really need this
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XAxiDma_BdSetId(bd, (uintptr_t) buf);
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// Give control of BD to HW. We should not access it until transfer is finished.
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// Failure could also indicate that EOF is not set on last Bd
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ret = XAxiDma_BdRingToHw(txRing, 1, bd);
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if (ret != XST_SUCCESS)
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throw RuntimeError("Enqueuing Bd and giving control to HW failed {}", ret);
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return true;
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}
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bool
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Dma::readSG(void* buf, size_t len)
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Dma::readScatterGather(void* buf, size_t len)
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{
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(void) buf;
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(void) len;
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logger->error("DMA Scatter Gather read not implemented");
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int ret = XST_FAILURE;
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return false;
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auto *rxRing = XAxiDma_GetRxRing(&xDma);
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if (rxRing == nullptr)
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throw RuntimeError("RxRing was null.");
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XAxiDma_Bd *bd;
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ret = XAxiDma_BdRingAlloc(rxRing, 1, &bd);
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||||
if (ret != XST_SUCCESS)
|
||||
throw RuntimeError("Failed to alloc BD in RX ring: {}", ret);
|
||||
|
||||
ret = XAxiDma_BdSetBufAddr(bd, (uintptr_t) buf);
|
||||
if (ret != XST_SUCCESS)
|
||||
throw RuntimeError("Failed to set buffer address {:x} on BD {:x}: {}", (uintptr_t) buf, (uintptr_t) bd, ret);
|
||||
|
||||
ret = XAxiDma_BdSetLength(bd, len, rxRing->MaxTransferLen);
|
||||
if (ret != XST_SUCCESS)
|
||||
throw RuntimeError("Rx set length {} on BD {:x} failed {}", len, (uintptr_t) bd, ret);
|
||||
|
||||
// Receive BDs do not need to set anything for the control
|
||||
// The hardware will set the SOF/EOF bits per stream status
|
||||
XAxiDma_BdSetCtrl(bd, 0);
|
||||
|
||||
ret = XAxiDma_BdRingToHw(rxRing, 1, bd);
|
||||
if (ret != XST_SUCCESS)
|
||||
throw RuntimeError("Failed to submit BD to RX ring: {}", ret);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
size_t
|
||||
Dma::writeCompleteSG()
|
||||
Dma::writeCompleteScatterGather()
|
||||
{
|
||||
logger->error("DMA Scatter Gather write not implemented");
|
||||
XAxiDma_Bd *bd;
|
||||
size_t processedBds = 0;
|
||||
auto txRing = XAxiDma_GetTxRing(&xDma);
|
||||
int ret = XST_FAILURE;
|
||||
|
||||
return 0;
|
||||
// Poll until the one BD TX transaction is done.
|
||||
while ((processedBds = XAxiDma_BdRingFromHw(txRing, XAXIDMA_ALL_BDS, &bd)) == 0) {}
|
||||
|
||||
if (bd == nullptr)
|
||||
throw RuntimeError("BD was null");
|
||||
|
||||
// Free all processed TX BDs for future transmission.
|
||||
ret = XAxiDma_BdRingFree(txRing, processedBds, bd);
|
||||
if (ret != XST_SUCCESS)
|
||||
throw RuntimeError("Failed to free {} TX BDs {}", processedBds, ret);
|
||||
|
||||
return processedBds;
|
||||
}
|
||||
|
||||
size_t
|
||||
Dma::readCompleteSG()
|
||||
Dma::readCompleteScatterGather()
|
||||
{
|
||||
logger->error("DMA Scatter Gather read not implemented");
|
||||
XAxiDma_Bd *bd;
|
||||
size_t processedBds = 0;
|
||||
auto rxRing = XAxiDma_GetRxRing(&xDma);
|
||||
int ret = XST_FAILURE;
|
||||
|
||||
// Wait until the data has been received by the Rx channel.
|
||||
while ((processedBds = XAxiDma_BdRingFromHw(rxRing, XAXIDMA_ALL_BDS, &bd)) == 0) { }
|
||||
|
||||
if (bd == nullptr)
|
||||
throw RuntimeError("BdPtr was null.");
|
||||
|
||||
// Free all processed RX BDs for future transmission.
|
||||
ret = XAxiDma_BdRingFree(rxRing, processedBds, bd);
|
||||
if (ret != XST_SUCCESS)
|
||||
throw RuntimeError("Failed to free {} TX BDs {}.", processedBds, ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -340,17 +401,13 @@ Dma::writeSimple(const void *buf, size_t len)
|
|||
{
|
||||
XAxiDma_BdRing *ring = XAxiDma_GetTxRing(&xDma);
|
||||
|
||||
if ((len == 0) || (len > FPGA_DMA_BOUNDARY))
|
||||
return false;
|
||||
|
||||
if (not ring->HasDRE) {
|
||||
const uint32_t mask = xDma.MicroDmaMode
|
||||
? XAXIDMA_MICROMODE_MIN_BUF_ALIGN
|
||||
: ring->DataWidth - 1;
|
||||
|
||||
if (reinterpret_cast<uintptr_t>(buf) & mask) {
|
||||
if (reinterpret_cast<uintptr_t>(buf) & mask)
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
const bool dmaChannelHalted =
|
||||
|
|
@ -359,19 +416,17 @@ Dma::writeSimple(const void *buf, size_t len)
|
|||
const bool dmaToDeviceBusy = XAxiDma_Busy(&xDma, XAXIDMA_DMA_TO_DEVICE);
|
||||
|
||||
// If the engine is doing a transfer, cannot submit
|
||||
if (not dmaChannelHalted and dmaToDeviceBusy) {
|
||||
if (not dmaChannelHalted and dmaToDeviceBusy)
|
||||
return false;
|
||||
}
|
||||
|
||||
// Set lower 32 bit of source address
|
||||
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_SRCADDR_OFFSET,
|
||||
LOWER_32_BITS(reinterpret_cast<uintptr_t>(buf)));
|
||||
|
||||
// If neccessary, set upper 32 bit of source address
|
||||
if (xDma.AddrWidth > 32) {
|
||||
if (xDma.AddrWidth > 32)
|
||||
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_SRCADDR_MSB_OFFSET,
|
||||
UPPER_32_BITS(reinterpret_cast<uintptr_t>(buf)));
|
||||
}
|
||||
|
||||
// Start DMA channel
|
||||
auto channelControl = XAxiDma_ReadReg(ring->ChanBase, XAXIDMA_CR_OFFSET);
|
||||
|
|
@ -389,17 +444,13 @@ Dma::readSimple(void *buf, size_t len)
|
|||
{
|
||||
XAxiDma_BdRing *ring = XAxiDma_GetRxRing(&xDma);
|
||||
|
||||
if ((len == 0) || (len > FPGA_DMA_BOUNDARY))
|
||||
return false;
|
||||
|
||||
if (not ring->HasDRE) {
|
||||
const uint32_t mask = xDma.MicroDmaMode
|
||||
? XAXIDMA_MICROMODE_MIN_BUF_ALIGN
|
||||
: ring->DataWidth - 1;
|
||||
|
||||
if (reinterpret_cast<uintptr_t>(buf) & mask) {
|
||||
if (reinterpret_cast<uintptr_t>(buf) & mask)
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
const bool dmaChannelHalted =
|
||||
|
|
@ -408,9 +459,8 @@ Dma::readSimple(void *buf, size_t len)
|
|||
const bool deviceToDmaBusy = XAxiDma_Busy(&xDma, XAXIDMA_DEVICE_TO_DMA);
|
||||
|
||||
// If the engine is doing a transfer, cannot submit
|
||||
if (not dmaChannelHalted and deviceToDmaBusy) {
|
||||
if (not dmaChannelHalted and deviceToDmaBusy)
|
||||
return false;
|
||||
}
|
||||
|
||||
// Set lower 32 bit of destination address
|
||||
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_DESTADDR_OFFSET,
|
||||
|
|
@ -499,6 +549,10 @@ Dma::dump()
|
|||
|
||||
logger->info("S2MM_DMACR: {:x}", XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_RX_OFFSET + XAXIDMA_CR_OFFSET));
|
||||
logger->info("S2MM_DMASR: {:x}", XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_RX_OFFSET + XAXIDMA_SR_OFFSET));
|
||||
logger->info("S2MM_LENGTH: {:x}", XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_RX_OFFSET + XAXIDMA_BUFFLEN_OFFSET));
|
||||
}
|
||||
|
||||
if (!hasScatterGather())
|
||||
logger->info("S2MM_LENGTH: {:x}", XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_RX_OFFSET + XAXIDMA_BUFFLEN_OFFSET));
|
||||
|
||||
logger->info("MM2S_DMACR: {:x}", XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_TX_OFFSET + XAXIDMA_CR_OFFSET));
|
||||
logger->info("MM2S_DMASR: {:x}", XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_TX_OFFSET + XAXIDMA_SR_OFFSET));
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue