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Code Issues Releases Wiki Activity

fix coding style

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This commit is contained in:
Steffen Vogel 2022-10-28 02:19:16 -04:00
parent 7ccb23d8b4
commit 0e0197a3be
40 changed files with 551 additions and 409 deletions
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50
fpga/include/villas/fpga/card.hpp
View file

@ -24,10 +24,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <list>
@ -58,7 +54,6 @@ public:
using List = std::list<Ptr>;
friend PCIeCardFactory;
};
class PCIeCard : public Card {
@ -67,10 +62,24 @@ public:
~PCIeCard();
bool init();
bool stop() { return true; }
bool check() { return true; }
bool reset() { return true; }
void dump() { }
bool stop()
{
return true;
}
bool check()
{
return true;
}
bool reset()
{
return true;
}
void dump()
{ }
ip::Core::Ptr
lookupIp(const std::string &name) const;
@ -81,7 +90,6 @@ public:
ip::Core::Ptr
lookupIp(const ip::IpIdentifier &id) const;
bool
mapMemoryBlock(const MemoryBlock &block);
@ -115,7 +123,9 @@ public: // TODO: make this private
protected:
Logger
getLogger() const
{ return villas::logging.get(name); }
{
return villas::logging.get(name);
}
Logger logger;
};
@ -128,19 +138,27 @@ public:
static PCIeCard*
create()
{ return new PCIeCard(); }
{
return new PCIeCard();
}
static Logger
getStaticLogger()
{ return villas::logging.get("pcie:card:factory"); }
{
return villas::logging.get("pcie:card:factory");
}
virtual std::string
getName() const
{ return "pcie"; }
{
return "pcie";
}
virtual std::string
getDescription() const
{ return "Xilinx PCIe FPGA cards"; }
{
return "Xilinx PCIe FPGA cards";
}
virtual
std::string getType() const
@ -151,5 +169,3 @@ public:
} /* namespace fpga */
} /* namespace villas */
/** @} */

134
fpga/include/villas/fpga/core.hpp
View file

@ -24,10 +24,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <map>
@ -59,22 +55,32 @@ class IpIdentifier {
public:
IpIdentifier(Vlnv vlnv = Vlnv::getWildcard(), std::string name = "") :
vlnv(vlnv), name(name) {}
vlnv(vlnv),
name(name)
{ }
IpIdentifier(std::string vlnvString, std::string name = "") :
vlnv(vlnvString), name(name) {}
vlnv(vlnvString),
name(name)
{ }
const std::string&
getName() const
{ return name; }
{
return name;
}
const Vlnv&
getVlnv() const
{ return vlnv; }
{
return vlnv;
}
friend std::ostream&
operator<< (std::ostream &stream, const IpIdentifier &id)
{ return stream << id.name << " vlnv=" << id.vlnv; }
{
return stream << id.name << " vlnv=" << id.vlnv;
}
bool
operator==(const IpIdentifier &otherId) const {
@ -89,19 +95,23 @@ public:
bool
operator!=(const IpIdentifier &otherId) const
{ return !(*this == otherId); }
{
return !(*this == otherId);
}
private:
Vlnv vlnv;
std::string name;
};
class Core {
friend CoreFactory;
public:
Core() : card(nullptr) {}
Core() :
card(nullptr)
{ }
virtual ~Core() = default;
using Ptr = std::shared_ptr<Core>;
@ -112,16 +122,27 @@ public:
// Runtime setup of IP, should access and initialize hardware
virtual bool init()
{ return true; }
{
return true;
}
// Runtime check of IP, should verify basic functionality
virtual bool check() { return true; }
virtual bool check()
{
return true;
}
// Generic disabling of IP, meaning may depend on IP
virtual bool stop() { return true; }
virtual bool stop()
{
return true;
}
// Reset the IP, it should behave like freshly initialized afterwards
virtual bool reset() { return true; }
virtual bool reset()
{
return true;
}
// Print some debug information about the IP
virtual void dump();
@ -133,77 +154,109 @@ protected:
// Each IP can declare via this function which memory blocks it requires
virtual std::list<MemoryBlockName>
getMemoryBlocks() const
{ return {}; }
{
return {};
}
public:
const std::string&
getInstanceName() const
{ return id.getName(); }
{
return id.getName();
}
// Operators
bool
operator==(const Vlnv &otherVlnv) const
{ return id.getVlnv() == otherVlnv; }
{
return id.getVlnv() == otherVlnv;
}
bool
operator!=(const Vlnv &otherVlnv) const
{ return id.getVlnv() != otherVlnv; }
{
return id.getVlnv() != otherVlnv;
}
bool
operator==(const IpIdentifier &otherId) const
{ return this->id == otherId; }
{
return this->id == otherId;
}
bool
operator!=(const IpIdentifier &otherId) const
{ return this->id != otherId; }
{
return this->id != otherId;
}
bool
operator==(const std::string &otherName) const
{ return getInstanceName() == otherName; }
{
return getInstanceName() == otherName;
}
bool
operator!=(const std::string &otherName) const
{ return getInstanceName() != otherName; }
{
return getInstanceName() != otherName;
}
bool
operator==(const Core &otherIp) const
{ return this->id == otherIp.id; }
{
return this->id == otherIp.id;
}
bool
operator!=(const Core &otherIp) const
{ return this->id != otherIp.id; }
{
return this->id != otherIp.id;
}
friend std::ostream&
operator<< (std::ostream &stream, const Core &ip)
{ return stream << ip.id; }
{
return stream << ip.id;
}
protected:
uintptr_t
getBaseAddr(const MemoryBlockName &block) const
{ return getLocalAddr(block, 0); }
{
return getLocalAddr(block, 0);
}
uintptr_t
getLocalAddr(const MemoryBlockName &block, uintptr_t address) const;
MemoryManager::AddressSpaceId
getAddressSpaceId(const MemoryBlockName &block) const
{ return slaveAddressSpaces.at(block); }
{
return slaveAddressSpaces.at(block);
}
InterruptController*
getInterruptController(const std::string &interruptName) const;
MemoryManager::AddressSpaceId
getMasterAddrSpaceByInterface(const std::string &masterInterfaceName) const
{ return busMasterInterfaces.at(masterInterfaceName); }
{
return busMasterInterfaces.at(masterInterfaceName);
}
template<typename T>
T readMemory(const std::string &block, uintptr_t address) const
{ return *(reinterpret_cast<T*>(getLocalAddr(block, address))); }
{
return *(reinterpret_cast<T*>(getLocalAddr(block, address)));
}
template<typename T>
void writeMemory(const std::string &block, uintptr_t address, T value)
{ T* ptr = reinterpret_cast<T*>(getLocalAddr(block, address)); *ptr = value; }
{
T* ptr = reinterpret_cast<T*>(getLocalAddr(block, address)); *ptr = value;
}
protected:
struct IrqPort {
@ -234,8 +287,6 @@ protected:
std::map<std::string, MemoryManager::AddressSpaceId> busMasterInterfaces;
};
class CoreFactory : public plugin::Plugin {
public:
using plugin::Plugin::Plugin;
@ -253,7 +304,9 @@ public:
protected:
Logger
getLogger() const
{ return villas::logging.get(getName()); }
{
return villas::logging.get(getName());
}
private:
// Create a concrete IP instance
@ -261,21 +314,24 @@ private:
// Configure IP instance from JSON config
virtual bool configureJson(Core& /* ip */, json_t* /* json */)
{ return true; }
{
return true;
}
virtual Vlnv getCompatibleVlnv() const = 0;
protected:
static Logger
getStaticLogger() { return villas::logging.get("core:factory"); }
getStaticLogger()
{
return villas::logging.get("core:factory");
}
private:
static CoreFactory*
lookup(const Vlnv &vlnv);
};
/** @} */
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */

38
fpga/include/villas/fpga/ips/aurora.hpp
View file

@ -21,10 +21,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <villas/fpga/node.hpp>
@ -41,15 +37,23 @@ public:
void dump();
std::list<std::string> getMemoryBlocks() const
{ return { registerMemory }; }
{
return {
registerMemory
};
}
const StreamVertex&
getDefaultSlavePort() const
{ return getSlavePort(slavePort); }
{
return getSlavePort(slavePort);
}
const StreamVertex&
getDefaultMasterPort() const
{ return getMasterPort(masterPort); }
{
return getMasterPort(masterPort);
}
void
setLoopback(bool state);
@ -61,29 +65,33 @@ private:
static constexpr const char registerMemory[] = "reg0";
};
class AuroraFactory : public NodeFactory {
public:
Core* create()
{ return new Aurora; }
{
return new Aurora;
}
virtual std::string
getName() const
{ return "Aurora"; }
{
return "Aurora";
}
virtual std::string
getDescription() const
{ return "Aurora 8B/10B and additional support modules, like an AXI4-Lite register interface."; }
{
return "Aurora 8B/10B and additional support modules, like an AXI4-Lite register interface.";
}
virtual Vlnv
getCompatibleVlnv() const
{ return {"acs.eonerc.rwth-aachen.de:user:aurora_axis:"}; }
{
return Vlnv("acs.eonerc.rwth-aachen.de:user:aurora_axis:");
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

32
fpga/include/villas/fpga/ips/aurora_xilinx.hpp
View file

@ -20,10 +20,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <villas/fpga/node.hpp>
@ -39,36 +35,44 @@ public:
const StreamVertex&
getDefaultSlavePort() const
{ return getSlavePort(slavePort); }
{
return getSlavePort(slavePort);
}
const StreamVertex&
getDefaultMasterPort() const
{ return getMasterPort(masterPort); }
{
return getMasterPort(masterPort);
}
};
class AuroraXilinxFactory : public NodeFactory {
public:
Core* create()
{ return new AuroraXilinx; }
{
return new AuroraXilinx;
}
virtual std::string
getName() const
{ return "Aurora"; }
{
return "Aurora";
}
virtual std::string
getDescription() const
{ return "Xilinx Aurora 8B/10B."; }
{
return "Xilinx Aurora 8B/10B.";
}
virtual Vlnv
getCompatibleVlnv() const
{ return {"xilinx.com:ip:aurora_8b10b:"}; }
{
return Vlnv("xilinx.com:ip:aurora_8b10b:");
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

38
fpga/include/villas/fpga/ips/bram.hpp
View file

@ -20,10 +20,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <villas/memory.hpp>
@ -33,9 +29,7 @@ namespace villas {
namespace fpga {
namespace ip {
class Bram : public Core
{
class Bram : public Core {
friend class BramFactory;
public:
@ -43,42 +37,52 @@ public:
LinearAllocator&
getAllocator()
{ return *allocator; }
{
return *allocator;
}
private:
static constexpr const char* memoryBlock = "Mem0";
std::list<MemoryBlockName> getMemoryBlocks() const
{ return { memoryBlock }; }
{
return {
memoryBlock
};
}
size_t size;
std::unique_ptr<LinearAllocator> allocator;
};
class BramFactory : public CoreFactory {
public:
bool configureJson(Core &ip, json_t *json_ip);
Core* create()
{ return new Bram; }
{
return new Bram;
}
virtual std::string
getName() const
{ return "Bram"; }
{
return "Bram";
}
virtual std::string
getDescription() const
{ return "Block RAM"; }
{
return "Block RAM";
}
virtual Vlnv
getCompatibleVlnv() const
{ return {"xilinx.com:ip:axi_bram_ctrl:"}; }
{
return Vlnv("xilinx.com:ip:axi_bram_ctrl:");
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

52
fpga/include/villas/fpga/ips/dma.hpp
View file

@ -20,10 +20,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
******************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <xilinx/xaxidma.h>
@ -50,10 +46,14 @@ public:
bool read(const MemoryBlock &mem, size_t len);
size_t writeComplete()
{ return hasScatterGather() ? writeCompleteSG() : writeCompleteSimple(); }
{
return hasScatterGather() ? writeCompleteSG() : writeCompleteSimple();
}
size_t readComplete()
{ return hasScatterGather() ? readCompleteSG() : readCompleteSimple(); }
{
return hasScatterGather() ? readCompleteSG() : readCompleteSimple();
}
bool memcpy(const MemoryBlock &src, const MemoryBlock &dst, size_t len);
@ -62,15 +62,21 @@ public:
inline bool
hasScatterGather() const
{ return hasSG; }
{
return hasSG;
}
const StreamVertex&
getDefaultSlavePort() const
{ return getSlavePort(s2mmPort); }
{
return getSlavePort(s2mmPort);
}
const StreamVertex&
getDefaultMasterPort() const
{ return getMasterPort(mm2sPort); }
{
return getMasterPort(mm2sPort);
}
private:
bool writeSG(const void* buf, size_t len);
@ -107,7 +113,11 @@ private:
static constexpr char sgInterface[] = "M_AXI_SG";
std::list<MemoryBlockName> getMemoryBlocks() const
{ return { registerMemory }; }
{
return {
registerMemory
};
}
XAxiDma xDma;
bool hasSG;
@ -115,29 +125,35 @@ private:
MemoryBlock sgRings;
};
class DmaFactory : public NodeFactory {
public:
Core* create()
{ return new Dma; }
{
return new Dma;
}
virtual std::string
getName() const
{ return "Dma"; }
{
return "Dma";
}
virtual std::string
getDescription() const
{ return "Xilinx's AXI4 Direct Memory Access Controller"; }
{
return "Xilinx's AXI4 Direct Memory Access Controller";
}
virtual Vlnv
getCompatibleVlnv() const
{ return {"xilinx.com:ip:axi_dma:"}; }
{
return {
"xilinx.com:ip:axi_dma:"
};
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

36
fpga/include/villas/fpga/ips/emc.hpp
View file

@ -21,10 +21,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <xilinx/xilflash.h>
@ -35,9 +31,7 @@ namespace villas {
namespace fpga {
namespace ip {
class EMC : public Core
{
class EMC : public Core {
public:
bool init();
@ -54,34 +48,40 @@ private:
static constexpr char registerMemory[] = "Reg";
std::list<MemoryBlockName> getMemoryBlocks() const
{ return { registerMemory }; }
{
return {
registerMemory
};
}
};
class EMCFactory : public CoreFactory {
public:
static constexpr const char*
getCompatibleVlnvString()
{ return "xilinx.com:ip:axi_emc:"; }
Core* create()
{ return new EMC; }
{
return new EMC;
}
virtual std::string
getName() const
{ return "ExternalMemoryController"; }
{
return "ExternalMemoryController";
}
virtual std::string
getDescription() const
{ return "Xilinx's AXI External Memory Controller (EMC) "; }
{
return "Xilinx's AXI External Memory Controller (EMC) ";
}
virtual Vlnv
getCompatibleVlnv() const
{ return Vlnv(getCompatibleVlnvString()); }
{
return Vlnv("xilinx.com:ip:axi_emc:");
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

55
fpga/include/villas/fpga/ips/fifo.hpp
View file

@ -23,9 +23,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
@ -33,14 +30,11 @@
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Fifo : public Node
{
class Fifo : public Node {
public:
friend class FifoFactory;
@ -56,58 +50,75 @@ private:
static constexpr char irqName[] = "interrupt";
std::list<MemoryBlockName> getMemoryBlocks() const
{ return { registerMemory, axi4Memory }; }
{
return {
registerMemory,
axi4Memory
};
}
XLlFifo xFifo;
};
class FifoFactory : public NodeFactory {
public:
Core* create()
{ return new Fifo; }
{
return new Fifo;
}
std::string
getName() const
{ return "Fifo"; }
{
return "Fifo";
}
std::string
getDescription() const
{ return "Xilinx's AXI4 FIFO data mover"; }
{
return "Xilinx's AXI4 FIFO data mover";
}
Vlnv getCompatibleVlnv() const
{ return {"xilinx.com:ip:axi_fifo_mm_s:"}; }
{
return Vlnv("xilinx.com:ip:axi_fifo_mm_s:");
}
};
class FifoData : public Node {
friend class FifoDataFactory;
};
class FifoDataFactory : public NodeFactory {
public:
Core* create()
{ return new FifoData; }
{
return new FifoData;
}
virtual std::string
getName() const
{ return "FifoData"; }
{
return "FifoData";
}
virtual std::string
getDescription() const
{ return "Xilinx's AXI4 data stream FIFO"; }
{
return "Xilinx's AXI4 data stream FIFO";
}
virtual Vlnv
getCompatibleVlnv() const
{ return {"xilinx.com:ip:axis_data_fifo:"}; }
{
return {
"xilinx.com:ip:axis_data_fifo:"
};
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

36
fpga/include/villas/fpga/ips/gpio.hpp
View file

@ -22,10 +22,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <villas/fpga/core.hpp>
@ -34,9 +30,7 @@ namespace villas {
namespace fpga {
namespace ip {
class GeneralPurposeIO : public Core
{
class GeneralPurposeIO : public Core {
public:
bool init();
@ -46,34 +40,40 @@ private:
static constexpr char registerMemory[] = "Reg";
std::list<MemoryBlockName> getMemoryBlocks() const
{ return { registerMemory }; }
{
return {
registerMemory
};
}
};
class GeneralPurposeIOFactory : public CoreFactory {
public:
static constexpr const char*
getCompatibleVlnvString()
{ return "xilinx.com:ip:axi_gpio:"; }
Core* create()
{ return new GeneralPurposeIO; }
{
return new GeneralPurposeIO;
}
virtual std::string
getName() const
{ return "GeneralPurposeIO"; }
{
return "GeneralPurposeIO";
}
virtual std::string
getDescription() const
{ return "Xilinx's AXI4 general purpose IO"; }
{
return "Xilinx's AXI4 general purpose IO";
}
virtual Vlnv
getCompatibleVlnv() const
{ return Vlnv(getCompatibleVlnvString()); }
{
return Vlnv("xilinx.com:ip:axi_gpio:");
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

26
fpga/include/villas/fpga/ips/gpu2rtds.hpp
View file

@ -11,7 +11,6 @@ namespace villas {
namespace fpga {
namespace ip {
class Gpu2Rtds : public Node, public Hls
{
public:
@ -26,11 +25,15 @@ public:
const StreamVertex&
getDefaultMasterPort() const
{ return getMasterPort(rtdsOutputStreamPort); }
{
return getMasterPort(rtdsOutputStreamPort);
}
MemoryBlock
getRegisterMemory() const
{ return MemoryBlock(0, 1 << 10, getAddressSpaceId(registerMemory)); }
{
return MemoryBlock(0, 1 << 10, getAddressSpaceId(registerMemory));
}
private:
bool updateStatus();
@ -62,24 +65,31 @@ public:
bool started;
};
class Gpu2RtdsFactory : public NodeFactory {
public:
Core* create()
{ return new Gpu2Rtds; }
{
return new Gpu2Rtds;
}
virtual std::string
getName() const
{ return "Gpu2Rtds"; }
{
return "Gpu2Rtds";
}
virtual std::string
getDescription() const
{ return "HLS Gpu2Rtds IP"; }
{
return "HLS Gpu2Rtds IP";
}
virtual Vlnv
getCompatibleVlnv() const
{ return {"acs.eonerc.rwth-aachen.de:hls:gpu2rtds:"}; }
{
return Vlnv("acs.eonerc.rwth-aachen.de:hls:gpu2rtds:");
}
};
} /* namespace ip */

77
fpga/include/villas/fpga/ips/hls.hpp
View file

@ -7,7 +7,6 @@ namespace villas {
namespace fpga {
namespace ip {
class Hls : public virtual Core
{
public:
@ -35,46 +34,61 @@ public:
}
virtual bool isFinished()
{ updateRunningStatus(); return !running; }
{
updateRunningStatus();
return !running;
}
bool isRunning()
{ updateRunningStatus(); return running; }
{
updateRunningStatus();
return running;
}
void setAutoRestart(bool enabled) const
{ controlRegister->auto_restart = enabled; }
{
controlRegister->auto_restart = enabled;
}
void setGlobalInterrupt(bool enabled) const
{ globalIntRegister->globalInterruptEnable = enabled; }
{
globalIntRegister->globalInterruptEnable = enabled;
}
void setReadyInterrupt(bool enabled) const
{ ipIntEnableRegister->ap_ready = enabled; }
{
ipIntEnableRegister->ap_ready = enabled;
}
void setDoneInterrupt(bool enabled) const
{ ipIntEnableRegister->ap_done = enabled; }
{
ipIntEnableRegister->ap_done = enabled;
}
bool isIdleBit() const
{ return controlRegister->ap_idle; }
{
return controlRegister->ap_idle;
}
bool isReadyBit() const
{ return controlRegister->ap_ready; }
{
return controlRegister->ap_ready;
}
// Warning: the corresponding bit is cleared on read of the register, so if
// not used correctly, this function may never return true. Only use this
// function if you really know what you are doing!
bool isDoneBit() const
{ return controlRegister->ap_done; }
{
return controlRegister->ap_done;
}
bool isAutoRestartBit() const
{ return controlRegister->auto_restart; }
{
return controlRegister->auto_restart;
}
private:
void updateRunningStatus()
@ -89,8 +103,11 @@ protected:
static constexpr const char* registerMemory = "Reg";
virtual std::list<MemoryBlockName> getMemoryBlocks() const
{ return { registerMemory }; }
{
return {
registerMemory
};
}
public:
// Register definitions
@ -135,24 +152,28 @@ protected:
class HlsFactory : public CoreFactory {
public:
static constexpr const char*
getCompatibleVlnvString()
{ return "acs.eonerc.rwth-aachen.de:hls:"; }
Core* create()
{ return new Hls; }
{
return new Hls;
}
virtual std::string
getName() const
{ return "HighLevelSynthesis"; }
{
return "HighLevelSynthesis";
}
virtual std::string
getDescription() const
{ return "Xilinx's HLS IP Cores"; }
{
return "Xilinx's HLS IP Cores";
}
virtual Vlnv
getCompatibleVlnv() const
{ return Vlnv(getCompatibleVlnvString()); }
{
return Vlnv("acs.eonerc.rwth-aachen.de:hls:");
}
};
} /* namespace ip */

51
fpga/include/villas/fpga/ips/intc.hpp
View file

@ -22,10 +22,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <xilinx/xintc.h>
@ -36,9 +32,7 @@ namespace villas {
namespace fpga {
namespace ip {
class InterruptController : public Core
{
class InterruptController : public Core {
public:
using IrqMaskType = uint32_t;
static constexpr int maxIrqs = 32;
@ -49,23 +43,32 @@ public:
bool enableInterrupt(IrqMaskType mask, bool polling);
bool enableInterrupt(IrqPort irq, bool polling)
{ return enableInterrupt(1 << irq.num, polling); }
{
return enableInterrupt(1 << irq.num, polling);
}
bool disableInterrupt(IrqMaskType mask);
bool disableInterrupt(IrqPort irq)
{ return disableInterrupt(1 << irq.num); }
{
return disableInterrupt(1 << irq.num);
}
int waitForInterrupt(int irq);
int waitForInterrupt(IrqPort irq)
{ return waitForInterrupt(irq.num); }
{
return waitForInterrupt(irq.num);
}
private:
static constexpr char registerMemory[] = "reg0";
std::list<MemoryBlockName> getMemoryBlocks() const
{ return { registerMemory }; }
{
return {
registerMemory
};
}
struct Interrupt {
int eventFd; // Event file descriptor
@ -79,33 +82,39 @@ private:
bool polling[maxIrqs];
};
class InterruptControllerFactory : public CoreFactory {
public:
static constexpr const char*
getCompatibleVlnvString()
{ return "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:"; }
{
return "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:";
}
Core* create()
{ return new InterruptController; }
{
return new InterruptController;
}
virtual std::string
getName() const
{ return "InterruptController"; }
{
return "InterruptController";
}
virtual std::string
getDescription() const
{ return "Xilinx's programmable interrupt controller"; }
{
return "Xilinx's programmable interrupt controller";
}
virtual Vlnv
getCompatibleVlnv() const
{ return Vlnv(getCompatibleVlnvString()); }
{
return Vlnv(getCompatibleVlnvString());
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

27
fpga/include/villas/fpga/ips/pcie.hpp
View file

@ -24,10 +24,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <xilinx/xaxis_switch.h>
@ -62,34 +58,41 @@ private:
std::map<std::string, PciBar> pcieToAxiTranslations;
};
class AxiPciExpressBridgeFactory : public CoreFactory {
public:
static constexpr const char*
getCompatibleVlnvString()
{ return "xilinx.com:ip:axi_pcie:"; }
{
return "xilinx.com:ip:axi_pcie:";
}
bool configureJson(Core &ip, json_t *json_ip);
Core* create()
{ return new AxiPciExpressBridge; }
{
return new AxiPciExpressBridge;
}
virtual std::string
getName() const
{ return "AxiPciExpressBridge"; }
{
return "AxiPciExpressBridge";
}
virtual std::string
getDescription() const
{ return "Xilinx's AXI-PCIe Bridge"; }
{
return "Xilinx's AXI-PCIe Bridge";
}
virtual Vlnv
getCompatibleVlnv() const
{ return Vlnv(getCompatibleVlnvString()); }
{
return Vlnv(getCompatibleVlnvString());
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

37
fpga/include/villas/fpga/ips/rtds.hpp
View file

@ -21,10 +21,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <villas/fpga/node.hpp>
@ -42,15 +38,23 @@ public:
double getDt();
std::list<std::string> getMemoryBlocks() const
{ return { registerMemory }; }
{
return {
registerMemory
};
}
const StreamVertex&
getDefaultSlavePort() const
{ return getSlavePort(slavePort); }
{
return getSlavePort(slavePort);
}
const StreamVertex&
getDefaultMasterPort() const
{ return getMasterPort(masterPort); }
{
return getMasterPort(masterPort);
}
private:
static constexpr const char registerMemory[] = "reg0";
@ -59,27 +63,32 @@ private:
static constexpr const char* irqCase = "irq_case";
};
class RtdsFactory : public NodeFactory {
public:
Core* create()
{ return new Rtds; }
{
return new Rtds;
}
virtual std::string
getName() const
{ return "rtds"; }
{
return "rtds";
}
virtual std::string
getDescription() const
{ return "RTDS's AXI4-Stream - GTFPGA interface"; }
{
return "RTDS's AXI4-Stream - GTFPGA interface";
}
virtual Vlnv
getCompatibleVlnv() const
{ return {"acs.eonerc.rwth-aachen.de:user:rtds_axis:"}; }
{
return Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:");
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

37
fpga/include/villas/fpga/ips/rtds2gpu.hpp
View file

@ -24,7 +24,6 @@ union ControlRegister {
};
};
class Rtds2Gpu : public Node, public Hls
{
public:
@ -41,20 +40,29 @@ public:
void dumpDoorbell(uint32_t doorbellRegister) const;
bool doorbellIsValid(const uint32_t &doorbellRegister) const
{ return reinterpret_cast<const reg_doorbell_t&>(doorbellRegister).is_valid; }
{
return reinterpret_cast<const reg_doorbell_t&>(doorbellRegister).is_valid;
}
void doorbellReset(uint32_t &doorbellRegister) const
{ doorbellRegister = 0; }
{
doorbellRegister = 0;
}
static constexpr const char* registerMemory = "Reg";
std::list<MemoryBlockName> getMemoryBlocks() const
{ return { registerMemory }; }
{
return {
registerMemory
};
}
const StreamVertex&
getDefaultSlavePort() const
{ return getSlavePort(rtdsInputStreamPort); }
{
return getSlavePort(rtdsInputStreamPort);
}
private:
bool updateStatus();
@ -71,24 +79,31 @@ private:
bool started;
};
class Rtds2GpuFactory : public NodeFactory {
public:
Core* create()
{ return new Rtds2Gpu; }
{
return new Rtds2Gpu;
}
virtual std::string
getName() const
{ return "Rtds2Gpu"; }
{
return "Rtds2Gpu";
}
virtual std::string
getDescription() const
{ return "HLS RTDS2GPU IP"; }
{
return "HLS RTDS2GPU IP";
}
virtual Vlnv
getCompatibleVlnv() const
{ return {"acs.eonerc.rwth-aachen.de:hls:rtds2gpu:"}; }
{
return Vlnv("acs.eonerc.rwth-aachen.de:hls:rtds2gpu:");
}
};
} /* namespace ip */

33
fpga/include/villas/fpga/ips/switch.hpp
View file

@ -24,10 +24,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <map>
@ -57,7 +53,11 @@ private:
static constexpr char registerMemory[] = "Reg";
std::list<MemoryBlockName> getMemoryBlocks() const
{ return { registerMemory }; }
{
return {
registerMemory
};
}
struct Path {
Core* masterOut;
@ -69,34 +69,41 @@ private:
std::map<std::string, std::string> portMapping;
};
class AxiStreamSwitchFactory : public NodeFactory {
public:
static constexpr const char*
getCompatibleVlnvString()
{ return "xilinx.com:ip:axis_switch:"; }
{
return "xilinx.com:ip:axis_switch:";
}
bool configureJson(Core &ip, json_t *json_ip);
Core* create()
{ return new AxiStreamSwitch; }
{
return new AxiStreamSwitch;
}
virtual std::string
getName() const
{ return "AxiStreamSwitch"; }
{
return "AxiStreamSwitch";
}
virtual std::string
getDescription() const
{ return "Xilinx's AXI4-Stream switch"; }
{
return "Xilinx's AXI4-Stream switch";
}
virtual Vlnv
getCompatibleVlnv() const
{ return Vlnv(getCompatibleVlnvString()); }
{
return Vlnv(getCompatibleVlnvString());
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

46
fpga/include/villas/fpga/ips/timer.hpp
View file

@ -23,10 +23,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <cstdint>
@ -39,9 +35,7 @@ namespace villas {
namespace fpga {
namespace ip {
class Timer : public Core
{
class Timer : public Core {
friend class TimerFactory;
public:
bool init();
@ -51,19 +45,29 @@ public:
uint32_t remaining();
inline bool isRunning()
{ return remaining() != 0; }
{
return remaining() != 0;
}
inline bool isFinished()
{ return remaining() == 0; }
{
return remaining() == 0;
}
static constexpr uint32_t
getFrequency()
{ return FPGA_AXI_HZ; }
{
return FPGA_AXI_HZ;
}
private:
std::list<MemoryBlockName> getMemoryBlocks() const
{ return { registerMemory }; }
{
return {
registerMemory
};
}
static constexpr char irqName[] = "generateout0";
static constexpr char registerMemory[] = "Reg";
@ -71,29 +75,33 @@ private:
XTmrCtr xTmr;
};
class TimerFactory : public CoreFactory {
public:
Core* create()
{ return new Timer; }
{
return new Timer;
}
virtual std::string
getName() const
{ return "Timer"; }
{
return "Timer";
}
virtual std::string
getDescription() const
{ return "Xilinx's programmable timer / counter"; }
{
return "Xilinx's programmable timer / counter";
}
virtual Vlnv
getCompatibleVlnv() const
{ return {"xilinx.com:ip:axi_timer:"}; }
{
return Vlnv("xilinx.com:ip:axi_timer:");
}
};
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */
/** @} */

41
fpga/include/villas/fpga/node.hpp
View file

@ -24,10 +24,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <map>
@ -45,14 +41,21 @@ namespace ip {
class StreamVertex : public graph::Vertex {
public:
StreamVertex(const std::string &node, const std::string &port, bool isMaster) :
nodeName(node), portName(port), isMaster(isMaster) {}
nodeName(node),
portName(port),
isMaster(isMaster)
{ }
std::string getName() const
{ return nodeName + "/" + portName + "(" + (isMaster ? "M" : "S") + ")"; }
{
return nodeName + "/" + portName + "(" + (isMaster ? "M" : "S") + ")";
}
friend std::ostream&
operator<< (std::ostream &stream, const StreamVertex &vertex)
{ return stream << vertex.getIdentifier() << ": " << vertex.getName(); }
{
return stream << vertex.getIdentifier() << ": " << vertex.getName();
}
public:
std::string nodeName;
@ -60,10 +63,11 @@ public:
bool isMaster;
};
class StreamGraph : public graph::DirectedGraph<StreamVertex> {
public:
StreamGraph() : graph::DirectedGraph<StreamVertex>("stream:graph") {}
StreamGraph() :
graph::DirectedGraph<StreamVertex>("stream:graph")
{ }
std::shared_ptr<StreamVertex>
getOrCreateStreamVertex(const std::string &node,
@ -84,7 +88,6 @@ public:
}
};
class Node : public virtual Core {
public:
@ -99,11 +102,15 @@ public:
const StreamVertex&
getMasterPort(const std::string &name) const
{ return *portsMaster.at(name); }
{
return *portsMaster.at(name);
}
const StreamVertex&
getSlavePort(const std::string &name) const
{ return *portsSlave.at(name); }
{
return *portsSlave.at(name);
}
bool connect(const StreamVertex &from, const StreamVertex &to);
bool connect(const StreamVertex &from, const StreamVertex &to, bool reverse)
@ -121,7 +128,9 @@ public:
// Easy-usage assuming that the slave IP to connect to only has one slave
// port and implements the getDefaultSlavePort() function
bool connect(const Node &slaveNode, bool reverse = false)
{ return this->connect(this->getDefaultMasterPort(), slaveNode.getDefaultSlavePort(), reverse); }
{
return this->connect(this->getDefaultMasterPort(), slaveNode.getDefaultSlavePort(), reverse);
}
// Used by easy-usage connect, will throw if not implemented by derived node
virtual const StreamVertex&
@ -133,7 +142,9 @@ public:
static const StreamGraph&
getGraph()
{ return streamGraph; }
{
return streamGraph;
}
bool loopbackPossible() const;
bool connectLoopback();
@ -160,8 +171,6 @@ public:
virtual bool configureJson(Core &ip, json_t *json_ip);
};
/** @} */
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */

25
fpga/include/villas/fpga/vlnv.hpp
View file

@ -21,10 +21,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
/** @addtogroup fpga VILLASfpga
* @{
*/
#pragma once
#include <string>
@ -39,15 +35,22 @@ public:
static constexpr char delimiter = ':';
Vlnv() :
vendor(""), library(""), name(""), version("") {}
vendor(""),
library(""),
name(""),
version("")
{ }
Vlnv(std::string s) {
Vlnv(std::string s)
{
parseFromString(s);
}
static Vlnv
getWildcard()
{ return Vlnv(); }
{
return Vlnv();
}
std::string
toString() const;
@ -57,7 +60,9 @@ public:
bool
operator!=(const Vlnv &other) const
{ return !(*this == other); }
{
return !(*this == other);
}
friend std::ostream&
operator<< (std::ostream &stream, const Vlnv &vlnv)
@ -65,7 +70,7 @@ public:
return stream
<< (vlnv.vendor.empty() ? "*" : vlnv.vendor) << ":"
<< (vlnv.library.empty() ? "*" : vlnv.library) << ":"
<< (vlnv.name.empty() ? "*" : vlnv.name) << ":"
<< (vlnv.name.empty() ? "*" : vlnv.name) << ":"
<< (vlnv.version.empty() ? "*" : vlnv.version);
}
@ -81,5 +86,3 @@ private:
} /* namespace fpga */
} /* namespace villas */
/** _FPGA_VLNV_HPP_ @} */

2
fpga/lib/CMakeLists.txt
View file

@ -87,5 +87,3 @@ install(TARGETS villas-fpga
)
install(DIRECTORY ../include/villas DESTINATION include)

4
fpga/lib/card.cpp
View file

@ -139,7 +139,6 @@ PCIeCard::~PCIeCard()
}
}
ip::Core::Ptr
PCIeCard::lookupIp(const std::string &name) const
{
@ -152,7 +151,6 @@ PCIeCard::lookupIp(const std::string &name) const
return nullptr;
}
ip::Core::Ptr
PCIeCard::lookupIp(const Vlnv &vlnv) const
{
@ -177,7 +175,6 @@ PCIeCard::lookupIp(const ip::IpIdentifier &id) const
return nullptr;
}
bool
PCIeCard::mapMemoryBlock(const MemoryBlock &block)
{
@ -218,7 +215,6 @@ PCIeCard::mapMemoryBlock(const MemoryBlock &block)
return true;
}
bool
PCIeCard::init()
{

8
fpga/lib/core.cpp
View file

@ -49,7 +49,6 @@ vlnvInitializationOrder = {
Vlnv(AxiStreamSwitchFactory::getCompatibleVlnvString()),
};
Core::List
CoreFactory::make(PCIeCard* card, json_t *json_ips)
{
@ -62,7 +61,6 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
Core::List configuredIps; // Successfully configured IPs
Core::List initializedIps; // Initialized, i.e. ready-to-use IPs
// Parse all IP instance names and their VLNV into list `allIps`
const char* ipName;
json_t* json_ip;
@ -151,7 +149,6 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
json_object_foreach(json_irqs, irqName, json_irq) {
const char* irqEntry = json_string_value(json_irq);
auto tokens = utils::tokenize(irqEntry, ":");
if (tokens.size() != 2) {
logger->warn("Cannot parse IRQ '{}' of " CLR_BLD("{}"),
@ -300,7 +297,6 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
initializedIps.push_back(std::move(ip));
}
loggerStatic->debug("Initialized IPs:");
for (auto &ip : initializedIps) {
loggerStatic->debug(" {}", *ip);
@ -309,7 +305,6 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
return initializedIps;
}
void
Core::dump()
{
@ -324,7 +319,6 @@ Core::dump()
}
}
CoreFactory*
CoreFactory::lookup(const Vlnv &vlnv)
{
@ -336,7 +330,6 @@ CoreFactory::lookup(const Vlnv &vlnv)
return nullptr;
}
uintptr_t
Core::getLocalAddr(const MemoryBlockName &block, uintptr_t address) const
{
@ -346,7 +339,6 @@ Core::getLocalAddr(const MemoryBlockName &block, uintptr_t address) const
return translation.getLocalAddr(address);
}
InterruptController*
Core::getInterruptController(const std::string &interruptName) const
{

1
fpga/lib/ips/aurora.cpp
View file

@ -64,7 +64,6 @@
* handled by Aurora IP, otherwise this bit is ignored.*/
#define AURORA_AXIS_CR_SEQ_ECHO (1 << 4)
using namespace villas::fpga::ip;
static AuroraFactory auroraFactoryInstance;

20
fpga/lib/ips/dma.cpp
View file

@ -35,7 +35,6 @@
// Max. size of a DMA transfer in simple mode
#define FPGA_DMA_BOUNDARY 0x1000
using namespace villas::fpga::ip;
// Instantiate factory to make available to plugin infrastructure
@ -101,7 +100,6 @@ Dma::init()
return true;
}
void Dma::setupRingRx()
{
XAxiDma_BdRing *RxRingPtr;
@ -188,7 +186,6 @@ void Dma::setupRingRx()
throw RuntimeError("RX start hw failed {}", Status);
}
void Dma::setupRingTx()
{
XAxiDma_BdRing *TxRingPtr;
@ -250,7 +247,6 @@ Dma::reset()
return false;
}
bool
Dma::memcpy(const MemoryBlock &src, const MemoryBlock &dst, size_t len)
{
@ -275,7 +271,6 @@ Dma::memcpy(const MemoryBlock &src, const MemoryBlock &dst, size_t len)
return true;
}
bool
Dma::write(const MemoryBlock &mem, size_t len)
{
@ -290,7 +285,6 @@ Dma::write(const MemoryBlock &mem, size_t len)
return hasScatterGather() ? writeSG(buf, len) : writeSimple(buf, len);
}
bool
Dma::read(const MemoryBlock &mem, size_t len)
{
@ -305,7 +299,6 @@ Dma::read(const MemoryBlock &mem, size_t len)
return hasScatterGather() ? readSG(buf, len) : readSimple(buf, len);
}
bool
Dma::writeSG(const void* buf, size_t len)
{
@ -316,7 +309,6 @@ Dma::writeSG(const void* buf, size_t len)
return false;
}
bool
Dma::readSG(void* buf, size_t len)
{
@ -327,7 +319,6 @@ Dma::readSG(void* buf, size_t len)
return false;
}
size_t
Dma::writeCompleteSG()
{
@ -336,7 +327,6 @@ Dma::writeCompleteSG()
return 0;
}
size_t
Dma::readCompleteSG()
{
@ -345,7 +335,6 @@ Dma::readCompleteSG()
return 0;
}
bool
Dma::writeSimple(const void *buf, size_t len)
{
@ -392,11 +381,9 @@ Dma::writeSimple(const void *buf, size_t len)
// Set tail descriptor pointer
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_BUFFLEN_OFFSET, len);
return true;
}
bool
Dma::readSimple(void *buf, size_t len)
{
@ -445,7 +432,6 @@ Dma::readSimple(void *buf, size_t len)
return true;
}
size_t
Dma::writeCompleteSimple()
{
@ -460,7 +446,6 @@ Dma::writeCompleteSimple()
return bytesWritten;
}
size_t
Dma::readCompleteSimple()
{
@ -475,15 +460,13 @@ Dma::readCompleteSimple()
return bytesRead;
}
bool
Dma::makeAccesibleFromVA(const MemoryBlock &mem)
{
// Only symmetric mapping supported currently
if (isMemoryBlockAccesible(mem, s2mmInterface) and
isMemoryBlockAccesible(mem, mm2sInterface)) {
isMemoryBlockAccesible(mem, mm2sInterface))
return true;
}
// Try mapping via FPGA-card (VFIO)
if (not card->mapMemoryBlock(mem)) {
@ -501,7 +484,6 @@ Dma::makeAccesibleFromVA(const MemoryBlock &mem)
return true;
}
bool
Dma::isMemoryBlockAccesible(const MemoryBlock &mem, const std::string &interface)
{

2
fpga/lib/ips/fifo.cpp
View file

@ -31,14 +31,12 @@
#include <villas/fpga/ips/fifo.hpp>
#include <villas/fpga/ips/intc.hpp>
using namespace villas::fpga::ip;
// Instantiate factory to make available to plugin infrastructure
static FifoFactory factory;
static FifoDataFactory factoryData;
bool Fifo::init()
{
XLlFifo_Config fifo_cfg;

1
fpga/lib/ips/gpio.cpp
View file

@ -26,7 +26,6 @@
using namespace villas::fpga::ip;
// Instantiate factory to make available to plugin infrastructure
static GeneralPurposeIOFactory factory;

1
fpga/lib/ips/intc.cpp
View file

@ -85,7 +85,6 @@ InterruptController::init()
logger->debug("enabled interrupts");
return true;
}

6
fpga/lib/ips/pcie.cpp
View file

@ -28,7 +28,6 @@
#include <villas/fpga/card.hpp>
#include <villas/fpga/ips/pcie.hpp>
using namespace villas::fpga::ip;
static AxiPciExpressBridgeFactory factory;
@ -118,7 +117,10 @@ AxiPciExpressBridgeFactory::configureJson(Core &ip, json_t* json_ip)
auto logger = getLogger();
auto &pcie = dynamic_cast<AxiPciExpressBridge&>(ip);
for (auto barType : std::list<std::string>{"axi_bars", "pcie_bars"}) {
for (auto barType : std::list<std::string>{
"axi_bars",
"pcie_bars"
}) {
json_t* json_bars = json_object_get(json_ip, barType.c_str());
if (not json_is_object(json_bars)) {
return false;

2
fpga/lib/ips/rtds.cpp
View file

@ -27,7 +27,6 @@
#include <villas/fpga/card.hpp>
#include <villas/fpga/ips/rtds.hpp>
#define RTDS_HZ 100000000 // 100 MHz
#define RTDS_AXIS_MAX_TX 64 // The amount of values which is supported by the vfpga card
@ -57,7 +56,6 @@ using namespace villas::fpga::ip;
static RtdsFactory rtdsFactoryInstance;
void Rtds::dump()
{
// Check RTDS_Axis registers

4
fpga/lib/ips/rtds2gpu/gpu2rtds.cpp
View file

@ -83,10 +83,6 @@ void Gpu2Rtds::dump(spdlog::level::level_enum logLevel)
// return start();
//}
//bool
//Gpu2Rtds::updateStatus()
//{

1
fpga/lib/ips/switch.cpp
View file

@ -153,7 +153,6 @@ AxiStreamSwitchFactory::configureJson(Core &ip, json_t* json_ip)
return true;
}
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */

1
fpga/lib/ips/timer.cpp
View file

@ -32,7 +32,6 @@
using namespace villas::fpga::ip;
// Instantiate factory to make available to plugin infrastructure
static TimerFactory factory;

1
fpga/lib/memory.cpp
View file

@ -33,7 +33,6 @@ HostRam::free(void* addr, size_t length)
return munmap(addr, length) == 0;
}
void*
HostRam::allocate(size_t length, int flags)
{

5
fpga/lib/node.cpp
View file

@ -84,14 +84,13 @@ NodeFactory::configureJson(Core &ip, json_t* json_ip)
tokens[1],
not isMaster);
if (isMaster) {
Node::streamGraph.addDefaultEdge(thisVertex->getIdentifier(),
connectedVertex->getIdentifier());
Node.portsMaster[name_raw] = thisVertex;
} else { // Slave
Node.portsSlave[name_raw] = thisVertex;
}
else // Slave
Node.portsSlave[name_raw] = thisVertex;
}
return true;

2
fpga/src/README.pcimem.md
View file

@ -23,7 +23,6 @@ bash# ./pcimem /sys/devices/pci0001\:00/0001\:00\:07.0/resource0 0 w
PCI Memory mapped to address 0x4801f000.
Value at offset 0x0 (0x4801f000): 0xC0BE0100
== Why do this at all ? ==
When I start working on a new PCI device driver I generally go through a
@ -34,7 +33,6 @@ to target, load module, unload module, dmesg.
Urk! There has to be a better way - sysfs and mmap() to the rescue.
== Sysfs ==
Let's start at with the PCI files under sysfs:

4
fpga/src/villas-fpga-pipe.cpp
View file

@ -62,7 +62,9 @@ void setupColorHandling()
sigaction(SIGINT, &sigIntHandler, nullptr);
// Reset color if exiting not by signal
std::atexit([](){std::cout << rang::style::reset;});
std::atexit([](){
std::cout << rang::style::reset;
});
}
std::shared_ptr<fpga::PCIeCard>

3
fpga/tests/unit/gpu.cpp
View file

@ -96,7 +96,6 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests")
gpu->makeAccessibleToPCIeAndVA(gpuMem0.getMemoryBlock());
gpu->makeAccessibleToPCIeAndVA(gpuMem1.getMemoryBlock());
// auto &src = bram0;
// auto &dst = bram1;
@ -109,7 +108,6 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests")
// auto &src = gpuMem0;
auto &dst = gpuMem1;
std::list<std::pair<std::string, std::function<void()>>> memcpyFuncs = {
{"cudaMemcpy", [&]() {gpu->memcpySync(src.getMemoryBlock(), dst.getMemoryBlock(), len);}},
{"CUDA kernel", [&]() {gpu->memcpyKernel(src.getMemoryBlock(), dst.getMemoryBlock(), len);}},
@ -147,6 +145,5 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests")
MemoryManager::getGraph().dump();
}
cr_assert(count > 0, "No BRAM found");
}

3
fpga/tests/unit/gpu_kernels.cu
View file

@ -7,8 +7,6 @@
#include <villas/gpu.hpp>
#include <villas/fpga/ips/rtds2gpu.hpp>
__global__ void
gpu_rtds_rtt_kernel(volatile uint32_t* dataIn, volatile reg_doorbell_t* doorbellIn,
volatile uint32_t* dataOut, volatile villas::fpga::ip::ControlRegister* controlRegister,
@ -62,7 +60,6 @@ void gpu_rtds_rtt_start(volatile uint32_t* dataIn, volatile reg_doorbell_t* door
}
printf("run: %p\n", run);
*run = 1;
gpu_rtds_rtt_kernel<<<1, 1>>>(dataIn, doorbellIn, dataOut, controlRegister, run);
printf("[cpu] kernel launched\n");

1
fpga/tests/unit/rtds.cpp
View file

@ -85,7 +85,6 @@ Test(fpga, rtds, .description = "RTDS")
auto mem = villas::HostRam::getAllocator().allocate<int32_t>(0x100 / sizeof(int32_t));
// auto start = std::chrono::high_resolution_clock::now();
for (int i = 1; i < 5; i++) {

17
fpga/tests/unit/rtds2gpu.cpp
View file

@ -40,7 +40,6 @@
using namespace villas;
static constexpr size_t SAMPLE_SIZE = 4;
static constexpr size_t SAMPLE_COUNT = 1;
static constexpr size_t FRAME_SIZE = SAMPLE_COUNT * SAMPLE_SIZE;
@ -79,7 +78,6 @@ Test(fpga, rtds2gpu_loopback_dma, .description = "Rtds2Gpu")
logger->info("Testing {}", *ip);
// Collect neccessary IPs
auto rtds2gpu = std::dynamic_pointer_cast<fpga::ip::Rtds2Gpu>(ip);
@ -95,7 +93,6 @@ Test(fpga, rtds2gpu_loopback_dma, .description = "Rtds2Gpu")
auto rtds = std::dynamic_pointer_cast<fpga::ip::Rtds>(
state.cards.front()->lookupIp(fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")));
cr_assert_not_null(axiSwitch, "No AXI switch IP found");
cr_assert_not_null(dma, "No DMA IP found");
cr_assert_not_null(gpu2rtds, "No Gpu2Rtds IP found");
@ -104,7 +101,6 @@ Test(fpga, rtds2gpu_loopback_dma, .description = "Rtds2Gpu")
rtds2gpu.dump(spdlog::level::debug);
gpu2rtds->dump(spdlog::level::debug);
// Allocate and prepare memory
// Allocate space for all samples and doorbell register
@ -112,7 +108,6 @@ Test(fpga, rtds2gpu_loopback_dma, .description = "Rtds2Gpu")
auto dmaMemDst = HostDmaRam::getAllocator(0).allocate<uint32_t>(SAMPLE_COUNT + 1);
auto dmaMemDst2 = HostDmaRam::getAllocator(0).allocate<uint32_t>(SAMPLE_COUNT + 1);
memset(&dmaMemSrc, 0x11, dmaMemSrc.getMemoryBlock().getSize());
memset(&dmaMemDst, 0x55, dmaMemDst.getMemoryBlock().getSize());
memset(&dmaMemDst2, 0x77, dmaMemDst2.getMemoryBlock().getSize());
@ -125,7 +120,6 @@ Test(fpga, rtds2gpu_loopback_dma, .description = "Rtds2Gpu")
dumpMem(dataDst, dmaMemDst.getMemoryBlock().getSize());
dumpMem(dataDst2, dmaMemDst2.getMemoryBlock().getSize());
// Connect AXI Stream from DMA to Rtds2Gpu IP
cr_assert(dma->connect(rtds2gpu));
@ -146,11 +140,8 @@ Test(fpga, rtds2gpu_loopback_dma, .description = "Rtds2Gpu")
cr_assert(memcmp(dataSrc, dataDst, FRAME_SIZE) == 0, "Memory not equal");
for (size_t i = 0; i < SAMPLE_COUNT; i++) {
for (size_t i = 0; i < SAMPLE_COUNT; i++)
gpu2rtds->registerFrames[i] = dmaMemDst[i];
}
// Connect AXI Stream from Gpu2Rtds IP to DMA
cr_assert(gpu2rtds->connect(*dma));
@ -210,7 +201,6 @@ Test(fpga, rtds2gpu_rtt_cpu, .description = "Rtds2Gpu RTT via CPU")
cr_assert(rtds.connect(*rtds2gpu));
cr_assert(gpu2rtds->connect(rtds));
for (size_t i = 1; i <= 10000; ) {
rtds2gpu->doorbellReset(*doorbell);
rtds2gpu->startOnce(dmaRam.getMemoryBlock(), SAMPLE_COUNT, DATA_OFFSET * 4, DOORBELL_OFFSET * 4);
@ -221,7 +211,6 @@ Test(fpga, rtds2gpu_rtt_cpu, .description = "Rtds2Gpu RTT via CPU")
// Wait by polling (local) doorbell register (= just memory)
while (not rtds2gpu->doorbellIsValid(*doorbell));
// Copy samples to gpu2rtds IP
for (size_t i = 0; i < SAMPLE_COUNT; i++) {
gpu2rtds->registerFrames[i] = data[i];
@ -283,7 +272,6 @@ Test(fpga, rtds2gpu_rtt_gpu, .description = "Rtds2Gpu RTT via GPU")
auto dataIn = reinterpret_cast<uint32_t*>(tr.getLocalAddr(DATA_OFFSET * sizeof(uint32_t)));
auto doorbellIn = reinterpret_cast<reg_doorbell_t*>(tr.getLocalAddr(DOORBELL_OFFSET * sizeof(uint32_t)));
auto gpu2rtdsRegisters = gpu->translate(gpu2rtds->getRegisterMemory());
auto frameRegister = reinterpret_cast<uint32_t*>(gpu2rtdsRegisters.getLocalAddr(gpu2rtds->registerFrameOffset));
@ -298,7 +286,6 @@ Test(fpga, rtds2gpu_rtt_gpu, .description = "Rtds2Gpu RTT via GPU")
auto &rtds = dynamic_cast<fpga::ip::Rtds&>(*ip);
logger->info("Testing {}", rtds);
// TEST: rtds loopback via switch, this should always work and have RTT=1
//cr_assert(rtds.connect(rtds));
//logger->info("loopback");
@ -340,8 +327,6 @@ Test(fpga, rtds2gpu_rtt_gpu, .description = "Rtds2Gpu RTT via GPU")
gpu_rtds_rtt_stop();
logger->info(CLR_GRN("Passed"));
}
}