mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
lib/ip-node: add IpNode class, IpCore which has streaming ports
This commit is contained in:
daniel-k
parent
f3f0f4d630
commit
12024d53e5
6 changed files with 229 additions and 17 deletions
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@ -26,7 +26,6 @@
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"slot": "03:00.0",
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"do_reset": true,
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"ips": {
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"axi_reset_0": {
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"vlnv": "xilinx.com:ip:axi_gpio:2.0",
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"baseaddr": 28672
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@ -39,7 +38,6 @@
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"dma_0": {
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"vlnv": "xilinx.com:ip:axi_dma:7.1",
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"baseaddr": 12288,
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"port": "switch_0:1",
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"irq": "axi_pcie_intc_0:3"
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},
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"axi_pcie_intc_0": {
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@ -49,26 +47,38 @@
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"dma_1": {
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"vlnv": "xilinx.com:ip:axi_dma:7.1",
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"baseaddr": 8192,
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"port": "switch_0:6",
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"ports": {
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"master": [ { "num": 0, "other": "switch_0:6" } ],
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"slave": [ { "num": 0, "other": "switch_0:6" } ]
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},
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"irq": "axi_pcie_intc_0:3"
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},
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"fifo_mm_s_0": {
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"vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.1",
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"baseaddr": 24576,
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"baseaddr_axi4": 49152,
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"port": "switch_0:2",
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"ports": {
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"master": [ { "num": 0, "other": "switch_0:2" } ],
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"slave": [ { "num": 0, "other": "switch_0:2" } ]
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},
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"irq": "axi_pcie_intc_0:2"
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},
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"rtds_axis_0": {
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"vlnv": "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0",
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"baseaddr": 32768,
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"port": "switch_0:0",
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"ports": {
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"master": [ { "num": 0, "other": "switch_0:0" } ],
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"slave": [ { "num": 0, "other": "switch_0:0" } ]
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},
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"irq": "axi_pcie_intc_0:5"
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},
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"hls_dft_0": {
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"vlnv": "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0",
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"baseaddr": 36864,
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"port": "switch_0:5",
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"ports": {
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"master": [ { "num": 0, "other": "switch_0:5" } ],
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"slave": [ { "num": 0, "other": "switch_0:5" } ]
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},
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"irq": "axi_pcie_intc_0:1",
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"period": 400,
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"harmonics": [
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@ -82,23 +92,47 @@
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},
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"axis_data_fifo_0": {
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"vlnv": "xilinx.com:ip:axis_data_fifo:1.1",
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"port": "switch_0:3"
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"ports": {
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"master": [ { "num": 0, "other": "switch_0:3" } ],
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"slave": [ { "num": 0, "other": "switch_0:3" } ]
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}
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},
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"switch_0": {
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"vlnv": "xilinx.com:ip:axis_interconnect:2.1",
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"baseaddr": 20480,
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"num_ports": 10,
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"paths": [
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{
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"in": "rtds_axis_0",
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"out": "dma_1",
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"reverse": true
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}
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]
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"ports": {
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"master": [
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{ "num": 0 },
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{ "num": 1 },
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{ "num": 2 },
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{ "num": 3 },
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{ "num": 4 },
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{ "num": 5 },
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{ "num": 6 },
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{ "num": 7 },
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{ "num": 8 },
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{ "num": 9 }
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],
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"slave": [
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{ "num": 0 },
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{ "num": 1 },
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{ "num": 2 },
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{ "num": 3 },
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{ "num": 4 },
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{ "num": 5 },
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{ "num": 6 },
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{ "num": 7 },
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{ "num": 8 },
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{ "num": 9 }
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]
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}
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},
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"axis_data_fifo_1": {
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"vlnv": "xilinx.com:ip:axis_data_fifo:1.1",
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"port": "switch_0:6"
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"ports": {
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"master": [ { "num": 0, "other": "switch_0:6" } ],
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"slave": [ { "num": 0, "other": "switch_0:6" } ]
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}
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}
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}
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}
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@ -122,7 +122,7 @@ using IpCoreList = std::list<std::unique_ptr<IpCore>>;
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class IpCoreFactory : public Plugin {
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public:
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IpCoreFactory(std::string concreteName) :
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Plugin(std::string("FPGA IpCore Factory: ") + concreteName)
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Plugin(std::string("IpCore - ") + concreteName)
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{ pluginType = Plugin::Type::FpgaIp; }
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/// Returns a running and checked FPGA IP
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81
fpga/include/villas/fpga/ip_node.hpp
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81
fpga/include/villas/fpga/ip_node.hpp
Normal file
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@ -0,0 +1,81 @@
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/** Interlectual Property component.
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*
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* This class represents a module within the FPGA.
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*
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* @file
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @author Daniel Krebs <github@daniel-krebs.net>
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* @copyright 2017, Institute for Automation of Complex Power Systems, EONERC
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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/** @addtogroup fpga VILLASfpga
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* @{
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*/
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#ifndef VILLAS_IP_NODE_HPP
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#define VILLAS_IP_NODE_HPP
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#include <map>
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#include <string>
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#include <jansson.h>
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#include "ip.hpp"
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#include "log.hpp"
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namespace villas {
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namespace fpga {
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namespace ip {
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// TODO: reflect on interface that an IpNode exposes and how to design it to
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// blend in with VILLASnode software nodes
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class IpNode : public IpCore {
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public:
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friend class IpNodeFactory;
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struct OtherIpNode {
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int otherPortNum;
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std::string otherName;
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};
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bool connectTo(int port, const OtherIpNode& other);
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bool disconnect(int port);
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protected:
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std::map<int, OtherIpNode> portsMaster;
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std::map<int, OtherIpNode> portsSlave;
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};
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class IpNodeFactory : public IpCoreFactory {
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public:
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IpNodeFactory(std::string name) : IpCoreFactory("Ip Node - " + name) {}
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virtual bool configureJson(IpCore& ip, json_t *json_ip);
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private:
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bool populatePorts(std::map<int, IpNode::OtherIpNode>& portMap, json_t* json);
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};
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/** @} */
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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#endif // VILLAS_IP_NODE_HPP
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@ -31,6 +31,8 @@
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#include "fpga/ip.hpp"
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#include <xilinx/xintc.h>
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#include "fpga/ip_node.hpp"
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namespace villas {
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namespace fpga {
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namespace ip {
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@ -1,6 +1,7 @@
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set(SOURCES
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ip.cpp
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ip.c
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ip_node.cpp
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vlnv.cpp
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vlnv.c
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card.c
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94
fpga/lib/ip_node.cpp
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94
fpga/lib/ip_node.cpp
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@ -0,0 +1,94 @@
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#include <map>
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#include <stdexcept>
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#include <jansson.h>
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#include "utils.hpp"
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#include "fpga/ip_node.hpp"
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namespace villas {
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namespace fpga {
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namespace ip {
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bool
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IpNodeFactory::configureJson(IpCore& ip, json_t* json_ip)
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{
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auto ipNode = reinterpret_cast<IpNode&>(ip);
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json_t* json_ports = json_object_get(json_ip, "ports");
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if(json_ports == nullptr) {
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cpp_error << "IpNode " << ip << " has no ports property";
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return false;
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}
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json_t* json_master = json_object_get(json_ports, "master");
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json_t* json_slave = json_object_get(json_ports, "slave");
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const bool hasMasterPorts = json_is_array(json_master);
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const bool hasSlavePorts = json_is_array(json_slave);
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if( (not hasMasterPorts) and (not hasSlavePorts)) {
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cpp_error << "IpNode " << ip << " has not ports";
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return false;
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}
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// intentionally use short-circuit evaluation to only call populatePorts
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// if the property exists
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bool masterPortsSuccess =
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(hasMasterPorts and populatePorts(ipNode.portsMaster, json_master))
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or (not hasMasterPorts);
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bool slavePortsSuccess =
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(hasSlavePorts and populatePorts(ipNode.portsSlave, json_slave))
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or (not hasSlavePorts);
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return (masterPortsSuccess and slavePortsSuccess);
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}
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bool
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IpNodeFactory::populatePorts(std::map<int, IpNode::OtherIpNode>& portMap, json_t* json)
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{
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size_t index;
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json_t* json_port;
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json_array_foreach(json, index, json_port) {
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int myPortNum;
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const char* other = nullptr;
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int ret = json_unpack(json_port, "{ s : i, s? : s}",
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"num", &myPortNum,
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"other", &other);
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if(ret != 0) {
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cpp_error << "Port definition required field 'num'";
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return false;
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}
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if(other == nullptr) {
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cpp_warn << "Nothing connected to port " << myPortNum;
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portMap[myPortNum] = {};
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continue;
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}
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const auto tokens = utils::tokenize(other, ":");
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if(tokens.size() != 2) {
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cpp_error << "Too many tokens in property 'other'";
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return false;
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}
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int otherPortNum;
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try {
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otherPortNum = std::stoi(tokens[1]);
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} catch(const std::invalid_argument&) {
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cpp_error << "Other port number is not an integral number";
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return false;
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}
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cpp_debug << "Adding port mapping: " << myPortNum << ":" << other;
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portMap[myPortNum] = { otherPortNum, tokens[0] };
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}
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return true;
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}
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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