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https://git.rwth-aachen.de/acs/public/villas/node/
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fpga: move register config for dino to DinoAdc
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
This commit is contained in:
parent
4911c96d8d
commit
12af65b2b4
4 changed files with 40 additions and 17 deletions
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@ -10,6 +10,7 @@
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#pragma once
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#include <villas/fpga/ips/i2c.hpp>
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#include <villas/fpga/ips/register.hpp>
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#include <villas/fpga/node.hpp>
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namespace villas {
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@ -63,11 +64,11 @@ public:
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static constexpr const char *masterPort = "M00_AXIS";
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static constexpr const char *slavePort = "S00_AXIS";
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const StreamVertex &getDefaultSlavePort() const {
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const StreamVertex &getDefaultSlavePort() const override {
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return getSlavePort(slavePort);
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}
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const StreamVertex &getDefaultMasterPort() const {
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const StreamVertex &getDefaultMasterPort() const override {
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return getMasterPort(masterPort);
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}
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@ -90,6 +91,19 @@ public:
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DinoAdc();
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virtual ~DinoAdc();
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virtual void configureHardware() override;
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/** Set the configuration of the ADC registers
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*
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* @param reg Register to set
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* @param sampleRate Sample rate in Hz. The default is 100 Hz.
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*/
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static void setRegisterConfig(std::shared_ptr<Register> reg,
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double sampleRate = (1 / 10e-3));
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static void setRegisterConfigTimestep(std::shared_ptr<Register> reg,
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double timestep = 10e-3) {
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setRegisterConfig(reg, 1 / timestep);
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}
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};
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class DinoDac : public Dino {
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@ -103,7 +117,9 @@ public:
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class DinoFactory : NodeFactory {
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public:
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virtual std::string getDescription() const { return "Dino Analog I/O"; }
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virtual std::string getDescription() const override {
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return "Dino Analog I/O";
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}
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protected:
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virtual void parse(Core &ip, json_t *json) override;
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@ -30,7 +30,7 @@ protected:
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const size_t registerNum = 8;
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const size_t registerSize = 32;
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static constexpr char registerMemory[] = "reg0";
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std::list<MemoryBlockName> getMemoryBlocks() const {
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std::list<MemoryBlockName> getMemoryBlocks() const override {
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return {registerMemory};
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}
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};
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@ -137,6 +137,26 @@ void DinoAdc::configureHardware() {
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logger->debug("ADC Ioext: Output register configured to {}", readback);
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}
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void DinoAdc::setRegisterConfig(std::shared_ptr<Register> reg,
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double sampleRate) {
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// This is Dino specific for now - we should possibly move this to Dino in the future
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constexpr double dinoClk = 25e6; // Dino is clocked with 25 Mhz
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uint32_t dinoTimerVal = static_cast<uint32_t>(dinoClk / sampleRate);
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double rateError = dinoClk / dinoTimerVal - sampleRate;
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reg->setRegister(
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0,
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dinoTimerVal); // Timer value for generating ADC trigger signal
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reg->setRegister(1, -0.001615254F); // Scale factor for ADC value
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reg->setRegister(2, 10.8061F); // Offset for ADC value
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uint32_t rate = reg->getRegister(0);
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float scale = reg->getRegisterFloat(1);
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float offset = reg->getRegisterFloat(2);
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logging.get("Dino")->info("Check: Register configuration: Rate: {}, Scale: "
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"{}, Offset: {}, Rate-Error: {} Hz",
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rate, scale, offset, rateError);
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}
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DinoDac::DinoDac() : Dino() {}
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DinoDac::~DinoDac() {}
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@ -42,19 +42,6 @@ bool Register::check() {
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logger->debug("Register {}: 0x{:08x}", i, getRegister(i));
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}
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// This is Dino specific for now - we should possibly move this to Dino in the future
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constexpr double dinoClk = 25e9; // Dino is clocked with 25 Mhz
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constexpr double sampleRate = 20e6; // We want to achieve a timestep of 50us
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constexpr uint32_t dinoTimerVal = static_cast<uint32_t>(dinoClk / sampleRate);
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setRegister(0, dinoTimerVal); // Timer value for generating ADC trigger signal
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setRegister(1, -0.001615254F); // Scale factor for ADC value
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setRegister(2, 10.8061F); // Offset for ADC value
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uint32_t rate = getRegister(0);
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float scale = getRegisterFloat(1);
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float offset = getRegisterFloat(2);
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logger->info("Check: Register configuration: Rate: {}, Scale: {}, Offset: {}",
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rate, scale, offset);
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return true;
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}
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