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fpga: move register config for dino to DinoAdc

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
This commit is contained in:
Niklas Eiling 2024-05-27 14:40:07 +02:00 committed by Niklas Eiling
parent 4911c96d8d
commit 12af65b2b4
4 changed files with 40 additions and 17 deletions

View file

@ -10,6 +10,7 @@
#pragma once
#include <villas/fpga/ips/i2c.hpp>
#include <villas/fpga/ips/register.hpp>
#include <villas/fpga/node.hpp>
namespace villas {
@ -63,11 +64,11 @@ public:
static constexpr const char *masterPort = "M00_AXIS";
static constexpr const char *slavePort = "S00_AXIS";
const StreamVertex &getDefaultSlavePort() const {
const StreamVertex &getDefaultSlavePort() const override {
return getSlavePort(slavePort);
}
const StreamVertex &getDefaultMasterPort() const {
const StreamVertex &getDefaultMasterPort() const override {
return getMasterPort(masterPort);
}
@ -90,6 +91,19 @@ public:
DinoAdc();
virtual ~DinoAdc();
virtual void configureHardware() override;
/** Set the configuration of the ADC registers
*
* @param reg Register to set
* @param sampleRate Sample rate in Hz. The default is 100 Hz.
*/
static void setRegisterConfig(std::shared_ptr<Register> reg,
double sampleRate = (1 / 10e-3));
static void setRegisterConfigTimestep(std::shared_ptr<Register> reg,
double timestep = 10e-3) {
setRegisterConfig(reg, 1 / timestep);
}
};
class DinoDac : public Dino {
@ -103,7 +117,9 @@ public:
class DinoFactory : NodeFactory {
public:
virtual std::string getDescription() const { return "Dino Analog I/O"; }
virtual std::string getDescription() const override {
return "Dino Analog I/O";
}
protected:
virtual void parse(Core &ip, json_t *json) override;

View file

@ -30,7 +30,7 @@ protected:
const size_t registerNum = 8;
const size_t registerSize = 32;
static constexpr char registerMemory[] = "reg0";
std::list<MemoryBlockName> getMemoryBlocks() const {
std::list<MemoryBlockName> getMemoryBlocks() const override {
return {registerMemory};
}
};

View file

@ -137,6 +137,26 @@ void DinoAdc::configureHardware() {
logger->debug("ADC Ioext: Output register configured to {}", readback);
}
void DinoAdc::setRegisterConfig(std::shared_ptr<Register> reg,
double sampleRate) {
// This is Dino specific for now - we should possibly move this to Dino in the future
constexpr double dinoClk = 25e6; // Dino is clocked with 25 Mhz
uint32_t dinoTimerVal = static_cast<uint32_t>(dinoClk / sampleRate);
double rateError = dinoClk / dinoTimerVal - sampleRate;
reg->setRegister(
0,
dinoTimerVal); // Timer value for generating ADC trigger signal
reg->setRegister(1, -0.001615254F); // Scale factor for ADC value
reg->setRegister(2, 10.8061F); // Offset for ADC value
uint32_t rate = reg->getRegister(0);
float scale = reg->getRegisterFloat(1);
float offset = reg->getRegisterFloat(2);
logging.get("Dino")->info("Check: Register configuration: Rate: {}, Scale: "
"{}, Offset: {}, Rate-Error: {} Hz",
rate, scale, offset, rateError);
}
DinoDac::DinoDac() : Dino() {}
DinoDac::~DinoDac() {}

View file

@ -42,19 +42,6 @@ bool Register::check() {
logger->debug("Register {}: 0x{:08x}", i, getRegister(i));
}
// This is Dino specific for now - we should possibly move this to Dino in the future
constexpr double dinoClk = 25e9; // Dino is clocked with 25 Mhz
constexpr double sampleRate = 20e6; // We want to achieve a timestep of 50us
constexpr uint32_t dinoTimerVal = static_cast<uint32_t>(dinoClk / sampleRate);
setRegister(0, dinoTimerVal); // Timer value for generating ADC trigger signal
setRegister(1, -0.001615254F); // Scale factor for ADC value
setRegister(2, 10.8061F); // Offset for ADC value
uint32_t rate = getRegister(0);
float scale = getRegisterFloat(1);
float offset = getRegisterFloat(2);
logger->info("Check: Register configuration: Rate: {}, Scale: {}, Offset: {}",
rate, scale, offset);
return true;
}