add connect to vfio

fpga/include/villas/fpga/card.hpp

@@ -10,8 +10,6 @@
 
 #pragma once
 
-#include <set>
-
 #include <villas/fpga/core.hpp>
 #include <villas/kernel/vfio_container.hpp>
 
@@ -21,8 +19,9 @@ namespace fpga {
 class Card {
 public:
   bool polling;
-
-  std::string name; // The name of the FPGA card
+  bool doReset;					// Reset VILLASfpga during startup?
+	int affinity;					// Affinity for MSI interrupts
+	std::string name;			// The name of the FPGA card
   std::shared_ptr<kernel::vfio::Container> vfioContainer;
   std::shared_ptr<kernel::vfio::Device> vfioDevice;
 
@@ -39,6 +38,9 @@ public:
 
   virtual ~Card();
 
+  virtual void
+  connectVFIOtoIps(std::list<std::shared_ptr<ip::Core>> configuredIps) = 0;
+
   virtual bool mapMemoryBlock(const std::shared_ptr<MemoryBlock> block);
   virtual bool unmapMemoryBlock(const MemoryBlock &block);
 

fpga/include/villas/fpga/pcie_card.hpp

@@ -37,6 +37,9 @@ class PCIeCard : public Card {
 public:
   ~PCIeCard();
 
+  void
+  connectVFIOtoIps(std::list<std::shared_ptr<ip::Core>> configuredIps) override;
+
   bool init();
 
   bool stop() { return true; }

fpga/lib/core.cpp

@@ -30,6 +30,7 @@ using namespace villas::fpga::ip;
 // same order as they appear in this list, i.e. first here will be initialized
 // first.
 static std::list<Vlnv> vlnvInitializationOrder = {
+    Vlnv("xilinx.com:ip:zynq_ultra_ps_e:"),
     Vlnv("xilinx.com:ip:axi_pcie:"),
     Vlnv("xilinx.com:ip:xdma:"),
     Vlnv("xilinx.com:module_ref:axi_pcie_intc:"),
@@ -320,6 +321,8 @@ std::list<std::shared_ptr<Core>> CoreFactory::make(Card *card,
   std::list<std::shared_ptr<Core>> configuredIps =
       configureIps(orderedIps, json_ips, card); // Successfully configured IPs
 
+  card->connectVFIOtoIps(configuredIps);
+
   initIps(configuredIps, card);
 
   return card->ips;