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https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
re-add old interrupt controller to make project compile again
This commit is contained in:
daniel-k
parent
e735c7e248
commit
151abd2fd5
2 changed files with 181 additions and 0 deletions
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@ -12,6 +12,7 @@ set(SOURCES
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ips/fifo.c
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ips/dma.c
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ips/intc.cpp
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ips/intc.c
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ips/gpio.c
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ips/rtds_axis.c
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180
fpga/lib/ips/intc.c
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180
fpga/lib/ips/intc.c
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@ -0,0 +1,180 @@
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/** AXI-PCIe Interrupt controller
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <unistd.h>
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#include "config.h"
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#include "log.h"
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#include "plugin.h"
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#include "kernel/vfio.h"
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#include "kernel/kernel.h"
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#include "fpga/ip.h"
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#include "fpga/card.h"
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#include "fpga/ips/intc.h"
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int intc_start(struct fpga_ip *c)
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{
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int ret;
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struct fpga_card *f = c->card;
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struct intc *intc = (struct intc *) c->_vd;
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uintptr_t base = (uintptr_t) f->map + c->baseaddr;
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if (c != f->intc)
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error("There can be only one interrupt controller per FPGA");
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intc->num_irqs = vfio_pci_msi_init(&f->vfio_device, intc->efds);
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if (intc->num_irqs < 0)
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return -1;
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ret = vfio_pci_msi_find(&f->vfio_device, intc->nos);
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if (ret)
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return -2;
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/* For each IRQ */
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for (int i = 0; i < intc->num_irqs; i++) {
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/* Pin to core */
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ret = kernel_irq_setaffinity(intc->nos[i], f->affinity, NULL);
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if (ret)
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serror("Failed to change affinity of VFIO-MSI interrupt");
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/* Setup vector */
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XIntc_Out32(base + XIN_IVAR_OFFSET + i * 4, i);
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}
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XIntc_Out32(base + XIN_IMR_OFFSET, 0); /* Use manual acknowlegement for all IRQs */
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XIntc_Out32(base + XIN_IAR_OFFSET, 0xFFFFFFFF); /* Acknowlege all pending IRQs manually */
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XIntc_Out32(base + XIN_IMR_OFFSET, 0xFFFFFFFF); /* Use fast acknowlegement for all IRQs */
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XIntc_Out32(base + XIN_IER_OFFSET, 0x00000000); /* Disable all IRQs by default */
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XIntc_Out32(base + XIN_MER_OFFSET, XIN_INT_HARDWARE_ENABLE_MASK | XIN_INT_MASTER_ENABLE_MASK);
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debug(4, "FPGA: enabled interrupts");
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return 0;
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}
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int intc_destroy(struct fpga_ip *c)
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{
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struct fpga_card *f = c->card;
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struct intc *intc = (struct intc *) c->_vd;
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vfio_pci_msi_deinit(&f->vfio_device, intc->efds);
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return 0;
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}
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int intc_enable(struct fpga_ip *c, uint32_t mask, int flags)
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{
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struct fpga_card *f = c->card;
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struct intc *intc = (struct intc *) c->_vd;
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uint32_t ier, imr;
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uintptr_t base = (uintptr_t) f->map + c->baseaddr;
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/* Current state of INTC */
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ier = XIntc_In32(base + XIN_IER_OFFSET);
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imr = XIntc_In32(base + XIN_IMR_OFFSET);
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/* Clear pending IRQs */
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XIntc_Out32(base + XIN_IAR_OFFSET, mask);
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for (int i = 0; i < intc->num_irqs; i++) {
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if (mask & (1 << i))
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intc->flags[i] = flags;
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}
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if (flags & INTC_POLLING) {
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XIntc_Out32(base + XIN_IMR_OFFSET, imr & ~mask);
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XIntc_Out32(base + XIN_IER_OFFSET, ier & ~mask);
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}
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else {
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XIntc_Out32(base + XIN_IER_OFFSET, ier | mask);
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XIntc_Out32(base + XIN_IMR_OFFSET, imr | mask);
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}
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debug(3, "New ier = %#x", XIntc_In32(base + XIN_IER_OFFSET));
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debug(3, "New imr = %#x", XIntc_In32(base + XIN_IMR_OFFSET));
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debug(3, "New isr = %#x", XIntc_In32(base + XIN_ISR_OFFSET));
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debug(8, "FPGA: Interupt enabled: mask=%#x flags=%#x", mask, flags);
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return 0;
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}
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int intc_disable(struct fpga_ip *c, uint32_t mask)
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{
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struct fpga_card *f = c->card;
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uintptr_t base = (uintptr_t) f->map + c->baseaddr;
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uint32_t ier = XIntc_In32(base + XIN_IER_OFFSET);
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XIntc_Out32(base + XIN_IER_OFFSET, ier & ~mask);
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return 0;
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}
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uint64_t intc_wait(struct fpga_ip *c, int irq)
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{
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struct fpga_card *f = c->card;
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struct intc *intc = (struct intc *) c->_vd;
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uintptr_t base = (uintptr_t) f->map + c->baseaddr;
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if (intc->flags[irq] & INTC_POLLING) {
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uint32_t isr, mask = 1 << irq;
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do {
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isr = XIntc_In32(base + XIN_ISR_OFFSET);
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pthread_testcancel();
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} while ((isr & mask) != mask);
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XIntc_Out32(base + XIN_IAR_OFFSET, mask);
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return 1;
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}
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else {
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uint64_t cnt;
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ssize_t ret = read(intc->efds[irq], &cnt, sizeof(cnt));
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if (ret != sizeof(cnt))
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return 0;
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return cnt;
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}
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}
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static struct plugin p = {
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.name = "Xilinx's programmable interrupt controller",
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.description = "",
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.type = PLUGIN_TYPE_FPGA_IP,
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.ip = {
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.vlnv = { "acs.eonerc.rwth-aachen.de", "user", "axi_pcie_intc", NULL },
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.type = FPGA_IP_TYPE_MISC,
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.start = intc_start,
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.destroy = intc_destroy,
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.size = sizeof(struct intc)
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}
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};
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REGISTER_PLUGIN(&p)
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