fpga: make compatible to new bitstream iteration

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>

fpga/include/villas/fpga/core.hpp

@@ -111,6 +111,7 @@ protected:
 public:
   size_t getBaseaddr() const { return baseaddr; }
   const std::string &getInstanceName() const { return id.getName(); }
+  const std::string getAddressSpaceName() const {return getInstanceName() + "/" + getMemoryBlocks().front();}
 
   // Operators
 

fpga/include/villas/fpga/ips/dino.hpp

@@ -131,7 +131,7 @@ public:
 
 private:
   virtual Vlnv getCompatibleVlnv() const {
-    return Vlnv("xilinx.com:module_ref:dinoif_fast:");
+    return Vlnv("xilinx.com:module_ref:dinoif_adc:");
   }
   Core *make() const { return new DinoAdc; };
 };

fpga/lib/platform_card.cpp

@@ -131,11 +131,7 @@ void PlatformCard::connect(std::string device_name,
 
   size_t srcVertexId = mm.getOrCreateAddressSpace(device_name);
 
-  // TODO: This is really bad!
+  size_t targetVertexId = mm.getOrCreateAddressSpace(ip->getAddressSpaceName());
-  std::string taget_address_space_name =
-      ip->getInstanceName() + "/Reg"; //? TODO: Reg neded?
-  size_t targetVertexId;
-  targetVertexId = mm.getOrCreateAddressSpace(taget_address_space_name);
 
   mm.createMapping(0, 0, ip_mem_size, "vfio to ip", srcVertexId,
                    targetVertexId);