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https://git.rwth-aachen.de/acs/public/villas/node/
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ips/rtds: add C++ version of RTDS IP
This commit is contained in:
Daniel Krebs
parent
a93278b74e
commit
28143e7188
5 changed files with 133 additions and 90 deletions
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@ -196,6 +196,10 @@ protected:
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getMasterAddrSpaceByInterface(const std::string& masterInterfaceName) const
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{ return busMasterInterfaces.at(masterInterfaceName); }
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template<typename T>
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T readMemory(const std::string& block, uintptr_t address) const
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{ return *(reinterpret_cast<T*>(getLocalAddr(block, address))); }
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protected:
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struct IrqPort {
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int num;
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78
fpga/include/villas/fpga/ips/rtds.hpp
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78
fpga/include/villas/fpga/ips/rtds.hpp
Normal file
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@ -0,0 +1,78 @@
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/** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
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*
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* @file
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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/** @addtogroup fpga VILLASfpga
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* @{
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*/
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#pragma once
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#include <villas/fpga/ip_node.hpp>
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namespace villas {
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namespace fpga {
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namespace ip {
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class Rtds : public IpNode {
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public:
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static constexpr const char* masterPort = "m_axis";
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static constexpr const char* slavePort = "s_axis";
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void dump();
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double getDt();
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std::list<std::string> getMemoryBlocks() const
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{ return { registerMemory }; }
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private:
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static constexpr const char registerMemory[] = "reg0";
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static constexpr const char* irqTs = "irq_ts";
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static constexpr const char* irqOverflow = "irq_overflow";
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static constexpr const char* irqCase = "irq_case";
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};
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class RtdsFactory : public IpNodeFactory {
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public:
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RtdsFactory();
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IpCore* create()
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{ return new Rtds; }
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std::string
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getName() const
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{ return "Rtds"; }
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std::string
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getDescription() const
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{ return "RTDS's AXI4-Stream - GTFPGA interface"; }
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Vlnv getCompatibleVlnv() const
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{ return {"acs.eonerc.rwth-aachen.de:user:rtds_axis:"}; }
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};
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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/** @} */
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@ -13,6 +13,7 @@ set(SOURCES
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ips/pcie.cpp
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ips/dma.cpp
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ips/bram.cpp
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ips/rtds.cpp
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kernel/kernel.c
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kernel/pci.c
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@ -1,6 +1,5 @@
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/** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
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*
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* @file
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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* @license GNU General Public License (version 3)
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@ -21,14 +20,13 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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/** @addtogroup fpga VILLASfpga
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* @{
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*/
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#include <cstdint>
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#pragma once
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#include <villas/utils.h>
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#include <villas/fpga/card.hpp>
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#include <villas/fpga/ips/rtds.hpp>
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/* Forward declarations */
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struct ip;
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#define RTDS_HZ 100000000 // 100 MHz
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@ -55,8 +53,50 @@ struct ip;
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/* Control register bits */
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#define RTDS_AXIS_CR_DISABLE_LINK 0 /**< Disable SFP TX when set */
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void rtds_axis_dump(struct fpga_ip *c);
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namespace villas {
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namespace fpga {
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namespace ip {
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double rtds_axis_dt(struct fpga_ip *c);
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static RtdsFactory rtdsFactoryInstance;
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/** @} */
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void Rtds::dump()
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{
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/* Check RTDS_Axis registers */
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const uint32_t sr = readMemory<uint32_t>(registerMemory, RTDS_AXIS_SR_OFFSET);
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logger->info("RTDS AXI Stream interface details:");
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logger->info("RTDS status: {:#x}", sr);
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logger->info(" Card detected: {}", sr & RTDS_AXIS_SR_CARDDETECTED ? CLR_GRN("yes") : CLR_RED("no"));
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logger->info(" Link up: {}", sr & RTDS_AXIS_SR_LINKUP ? CLR_GRN("yes") : CLR_RED("no"));
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logger->info(" TX queue full: {}", sr & RTDS_AXIS_SR_TX_FULL ? CLR_RED("yes") : CLR_GRN("no"));
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logger->info(" TX in progress: {}", sr & RTDS_AXIS_SR_TX_INPROGRESS ? CLR_YEL("yes") : "no");
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logger->info(" Case running: {}", sr & RTDS_AXIS_SR_CASE_RUNNING ? CLR_GRN("yes") : CLR_RED("no"));
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logger->info("RTDS control: {:#x}", readMemory<uint32_t>(registerMemory, RTDS_AXIS_CR_OFFSET));
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logger->info("RTDS IRQ coalesc: {}", readMemory<uint32_t>(registerMemory, RTDS_AXIS_COALESC_OFFSET));
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logger->info("RTDS IRQ version: {:#x}", readMemory<uint32_t>(registerMemory, RTDS_AXIS_VERSION_OFFSET));
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logger->info("RTDS IRQ multi-rate: {}", readMemory<uint32_t>(registerMemory, RTDS_AXIS_MRATE));
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const uint64_t timestepLow = readMemory<uint32_t>(registerMemory, RTDS_AXIS_TSCNT_LOW_OFFSET);
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const uint64_t timestepHigh = readMemory<uint32_t>(registerMemory, RTDS_AXIS_TSCNT_HIGH_OFFSET);
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const uint64_t timestep = (timestepHigh << 32) | timestepLow;
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logger->info("RTDS timestep counter: {}", timestep);
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logger->info("RTDS timestep period: {:.3f} us", getDt() * 1e6);
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}
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double Rtds::getDt()
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{
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const auto dt = readMemory<uint16_t>(registerMemory, RTDS_AXIS_TS_PERIOD_OFFSET);
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return (dt == 0xFFFF) ? 0.0 : (double) dt / RTDS_HZ;
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}
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RtdsFactory::RtdsFactory() :
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IpNodeFactory(getName())
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{
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}
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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@ -1,80 +0,0 @@
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/** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <stdint.h>
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#include "log.h"
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#include "utils.h"
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#include "plugin.h"
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#include "fpga/ip.h"
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#include "fpga/card.h"
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#include "fpga/ips/rtds_axis.h"
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void rtds_axis_dump(struct fpga_ip *c)
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{
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/* Check RTDS_Axis registers */
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uint32_t *regs = (uint32_t *) (c->card->map + c->baseaddr);
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uint32_t sr = regs[RTDS_AXIS_SR_OFFSET/4];
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info("RTDS AXI Stream interface details");
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{ INDENT
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info("RTDS status: %#08x", sr);
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{ INDENT
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info("Card detected: %s", sr & RTDS_AXIS_SR_CARDDETECTED ? CLR_GRN("yes") : CLR_RED("no"));
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info("Link up: %s", sr & RTDS_AXIS_SR_LINKUP ? CLR_GRN("yes") : CLR_RED("no"));
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info("TX queue full: %s", sr & RTDS_AXIS_SR_TX_FULL ? CLR_RED("yes") : CLR_GRN("no"));
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info("TX in progress: %s", sr & RTDS_AXIS_SR_TX_INPROGRESS ? CLR_YEL("yes") : "no");
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info("Case running: %s", sr & RTDS_AXIS_SR_CASE_RUNNING ? CLR_GRN("yes") : CLR_RED("no"));
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}
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info("RTDS control: %#08x", regs[RTDS_AXIS_CR_OFFSET/4]);
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info("RTDS IRQ coalesc: %u", regs[RTDS_AXIS_COALESC_OFFSET/4]);
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info("RTDS IRQ version: %#06x", regs[RTDS_AXIS_VERSION_OFFSET/4]);
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info("RTDS IRQ multi-rate: %u", regs[RTDS_AXIS_MRATE/4]);
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info("RTDS timestep counter: %lu", (uint64_t) regs[RTDS_AXIS_TSCNT_LOW_OFFSET/4] | (uint64_t) regs[RTDS_AXIS_TSCNT_HIGH_OFFSET/4] << 32);
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info("RTDS timestep period: %.3f uS", rtds_axis_dt(c) * 1e6);
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}
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}
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double rtds_axis_dt(struct fpga_ip *c)
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{
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uint32_t *regs = (uint32_t *) (c->card->map + c->baseaddr);
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uint16_t dt = regs[RTDS_AXIS_TS_PERIOD_OFFSET/4];
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return (dt == 0xFFFF) ? -1.0 : (double) dt / RTDS_HZ;
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}
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static struct plugin p = {
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.name = "RTDS's AXI4-Stream - GTFPGA interface",
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.description = "",
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.type = PLUGIN_TYPE_FPGA_IP,
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.ip = {
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.vlnv = { "acs.eonerc.rwth-aachen.de", "user", "rtds_axis", NULL },
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.type = FPGA_IP_TYPE_INTERFACE,
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.dump = rtds_axis_dump,
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.size = 0
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}
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};
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REGISTER_PLUGIN(&p)
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