mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
update rtds2gpu HLS IP to v1.1
- better tested IP (testbenches) - detect invalid frame sizes - more status reporting
This commit is contained in:
Daniel Krebs
parent
bf286568dd
commit
28458fdf8a
8 changed files with 207 additions and 102 deletions
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@ -4,6 +4,7 @@
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#include <villas/fpga/ip_node.hpp>
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#include "rtds2gpu/xrtds2gpu.h"
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#include "rtds2gpu/register_types.hpp"
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namespace villas {
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namespace fpga {
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@ -17,11 +18,22 @@ public:
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bool init();
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void dump();
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bool start();
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bool startOnce(const MemoryBlock& mem, size_t frameSize);
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void dump(spdlog::level::level_enum logLevel = spdlog::level::info);
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bool isDone();
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bool startOnce(const MemoryBlock& mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset);
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bool isFinished();
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bool isReady();
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size_t getMaxFrameSize();
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void dumpDoorbell(uint32_t doorbellRegister) const;
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private:
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bool updateStatus();
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private:
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static constexpr const char* registerMemory = "Reg";
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@ -32,6 +44,11 @@ private:
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{ return { registerMemory }; }
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XRtds2gpu xInstance;
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axilite_reg_status_t status;
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size_t maxFrameSize;
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bool started;
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};
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30
fpga/include/villas/fpga/ips/rtds2gpu/register_types.hpp
Normal file
30
fpga/include/villas/fpga/ips/rtds2gpu/register_types.hpp
Normal file
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@ -0,0 +1,30 @@
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#ifndef REGISTER_TYPES_H
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#define REGISTER_TYPES_H
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#include <stdint.h>
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union axilite_reg_status_t {
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uint32_t value;
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struct {
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uint32_t
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last_seq_nr : 16,
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last_count : 6,
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max_frame_size : 6,
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invalid_frame_size : 1,
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frame_too_short : 1,
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frame_too_long : 1,
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is_running : 1;
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};
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};
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union reg_doorbell_t {
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uint32_t value;
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struct {
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uint32_t
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seq_nr : 16,
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count : 6,
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is_valid : 1;
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};
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};
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#endif // REGISTER_TYPES_H
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@ -93,11 +93,10 @@ void XRtds2gpu_Set_data_offset(XRtds2gpu *InstancePtr, u32 Data);
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u32 XRtds2gpu_Get_data_offset(XRtds2gpu *InstancePtr);
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void XRtds2gpu_Set_doorbell_offset(XRtds2gpu *InstancePtr, u32 Data);
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u32 XRtds2gpu_Get_doorbell_offset(XRtds2gpu *InstancePtr);
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void XRtds2gpu_Set_status_i(XRtds2gpu *InstancePtr, u32 Data);
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u32 XRtds2gpu_Get_status_i(XRtds2gpu *InstancePtr);
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u32 XRtds2gpu_Get_status_o(XRtds2gpu *InstancePtr);
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void XRtds2gpu_Set_frame_size(XRtds2gpu *InstancePtr, u32 Data);
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u32 XRtds2gpu_Get_frame_size(XRtds2gpu *InstancePtr);
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u32 XRtds2gpu_Get_status(XRtds2gpu *InstancePtr);
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u32 XRtds2gpu_Get_status_vld(XRtds2gpu *InstancePtr);
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void XRtds2gpu_InterruptGlobalEnable(XRtds2gpu *InstancePtr);
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void XRtds2gpu_InterruptGlobalDisable(XRtds2gpu *InstancePtr);
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@ -33,15 +33,14 @@
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// 0x20 : Data signal of doorbell_offset
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// bit 31~0 - doorbell_offset[31:0] (Read/Write)
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// 0x24 : reserved
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// 0x28 : Data signal of status_i
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// bit 31~0 - status_i[31:0] (Read/Write)
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// 0x2c : reserved
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// 0x30 : Data signal of status_o
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// bit 31~0 - status_o[31:0] (Read)
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// 0x34 : reserved
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// 0x38 : Data signal of frame_size
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// 0x28 : Data signal of frame_size
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// bit 31~0 - frame_size[31:0] (Read/Write)
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// 0x3c : reserved
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// 0x2c : reserved
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// 0x30 : Data signal of status
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// bit 31~0 - status[31:0] (Read)
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// 0x34 : Control signal of status
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// bit 0 - status_ap_vld (Read/COR)
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// others - reserved
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// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
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#define XRTDS2GPU_CTRL_ADDR_AP_CTRL 0x00
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@ -54,10 +53,9 @@
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#define XRTDS2GPU_CTRL_BITS_DATA_OFFSET_DATA 32
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#define XRTDS2GPU_CTRL_ADDR_DOORBELL_OFFSET_DATA 0x20
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#define XRTDS2GPU_CTRL_BITS_DOORBELL_OFFSET_DATA 32
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#define XRTDS2GPU_CTRL_ADDR_STATUS_I_DATA 0x28
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#define XRTDS2GPU_CTRL_BITS_STATUS_I_DATA 32
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#define XRTDS2GPU_CTRL_ADDR_STATUS_O_DATA 0x30
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#define XRTDS2GPU_CTRL_BITS_STATUS_O_DATA 32
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#define XRTDS2GPU_CTRL_ADDR_FRAME_SIZE_DATA 0x38
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#define XRTDS2GPU_CTRL_ADDR_FRAME_SIZE_DATA 0x28
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#define XRTDS2GPU_CTRL_BITS_FRAME_SIZE_DATA 32
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#define XRTDS2GPU_CTRL_ADDR_STATUS_DATA 0x30
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#define XRTDS2GPU_CTRL_BITS_STATUS_DATA 32
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#define XRTDS2GPU_CTRL_ADDR_STATUS_CTRL 0x34
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@ -29,6 +29,10 @@ set(SOURCES
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log_helper.c
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)
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# we don't have much influence on drivers generated by Xilinx, so ignore warnings
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set_source_files_properties(ips/rtds2gpu/xrtds2gpu.c
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PROPERTIES COMPILE_FLAGS -Wno-int-to-pointer-cast)
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include(FindPkgConfig)
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pkg_check_modules(JANSSON jansson)
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@ -20,44 +20,64 @@ bool Rtds2Gpu::init()
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// make sure IP is stopped for now
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XRtds2gpu_DisableAutoRestart(&xInstance);
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dump();
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status.value = 0;
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started = false;
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maxFrameSize = getMaxFrameSize();
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logger->info("Max. frame size supported: {}", maxFrameSize);
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return true;
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}
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void Rtds2Gpu::dump()
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bool Rtds2Gpu::start()
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{
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XRtds2gpu_Start(&xInstance);
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started = true;
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return true;
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}
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void Rtds2Gpu::dump(spdlog::level::level_enum logLevel)
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{
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const auto baseaddr = XRtds2gpu_Get_baseaddr(&xInstance);
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const auto data_offset = XRtds2gpu_Get_data_offset(&xInstance);
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const auto doorbell_offset = XRtds2gpu_Get_doorbell_offset(&xInstance);
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const auto frame_size = XRtds2gpu_Get_frame_size(&xInstance);
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const auto status = XRtds2gpu_Get_status_o(&xInstance);
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logger->debug("Rtds2Gpu registers (IP base {:#x}):", xInstance.Ctrl_BaseAddress);
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logger->debug(" Base address (bytes): {:#x}", baseaddr);
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logger->debug(" Doorbell offset (bytes): {:#x}", doorbell_offset);
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logger->debug(" Data offset (bytes): {:#x}", data_offset);
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logger->debug(" Frame size (words): {:#x}", frame_size);
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logger->debug(" Status: {:#x}", status);
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logger->log(logLevel, "Rtds2Gpu registers (IP base {:#x}):", xInstance.Ctrl_BaseAddress);
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logger->log(logLevel, " Base address (bytes): {:#x}", baseaddr);
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logger->log(logLevel, " Doorbell offset (bytes): {:#x}", doorbell_offset);
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logger->log(logLevel, " Data offset (bytes): {:#x}", data_offset);
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logger->log(logLevel, " Frame size (words): {:#x}", frame_size);
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logger->log(logLevel, " Status: {:#x}", status.value);
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logger->log(logLevel, " Running: {}", (status.is_running ? "yes" : "no"));
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logger->log(logLevel, " Frame too short: {}", (status.frame_too_short ? "yes" : "no"));
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logger->log(logLevel, " Frame too long: {}", (status.frame_too_long ? "yes" : "no"));
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logger->log(logLevel, " Frame size invalid: {}", (status.invalid_frame_size ? "yes" : "no"));
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logger->log(logLevel, " Last count: {}", status.last_count);
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logger->log(logLevel, " Last seq. number: {}", status.last_seq_nr);
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logger->log(logLevel, " Max. frame size: {}", status.max_frame_size);
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}
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bool Rtds2Gpu::startOnce(const MemoryBlock& mem, size_t frameSize)
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bool Rtds2Gpu::startOnce(const MemoryBlock& mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset)
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{
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auto& mm = MemoryManager::get();
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if(frameSize > maxFrameSize) {
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logger->error("Requested frame size of {} exceeds max. frame size of {}",
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frameSize, maxFrameSize);
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return false;
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}
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auto translationFromIp = mm.getTranslation(
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getMasterAddrSpaceByInterface(axiInterface),
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mem.getAddrSpaceId());
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// make sure IP is stopped for now
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XRtds2gpu_DisableAutoRestart(&xInstance);
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// while(not XRtds2gpu_IsIdle(&xInstance) and not XRtds2gpu_IsDone(&xInstance));
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// set address of memory block in HLS IP
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XRtds2gpu_Set_baseaddr(&xInstance, translationFromIp.getLocalAddr(0));
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XRtds2gpu_Set_doorbell_offset(&xInstance, 0);
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XRtds2gpu_Set_data_offset(&xInstance, 4);
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XRtds2gpu_Set_doorbell_offset(&xInstance, doorbellOffset);
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XRtds2gpu_Set_data_offset(&xInstance, dataOffset);
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XRtds2gpu_Set_frame_size(&xInstance, frameSize);
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// prepare memory with all zeroes
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@ -66,15 +86,61 @@ bool Rtds2Gpu::startOnce(const MemoryBlock& mem, size_t frameSize)
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memset(memory, 0, mem.getSize());
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// start IP
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// XRtds2gpu_EnableAutoRestart(&xInstance);
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XRtds2gpu_Start(&xInstance);
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return start();
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}
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bool Rtds2Gpu::isFinished()
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{
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if(started and isReady()) {
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started = false;
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if(not updateStatus()) {
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throw "IP is finished but status register invalid";
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}
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}
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return !started;
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}
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bool
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Rtds2Gpu::isReady()
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{
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// use the idle bit to indicate readiness, we don't care about the difference
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// here
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return XRtds2gpu_IsIdle(&xInstance);
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}
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bool
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Rtds2Gpu::updateStatus()
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{
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if(not XRtds2gpu_Get_status_vld(&xInstance))
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return false;
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status.value = XRtds2gpu_Get_status(&xInstance);
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return true;
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}
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bool Rtds2Gpu::isDone()
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size_t
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Rtds2Gpu::getMaxFrameSize()
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{
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return XRtds2gpu_IsDone(&xInstance);
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XRtds2gpu_Set_frame_size(&xInstance, 0);
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start();
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while(not isFinished());
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return status.max_frame_size;
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}
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void
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Rtds2Gpu::dumpDoorbell(uint32_t doorbellRegister) const
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{
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auto& doorbell = reinterpret_cast<reg_doorbell_t&>(doorbellRegister);
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logger->info("Doorbell register: {:#08x}", doorbell.value);
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logger->info(" Valid: {}", (doorbell.is_valid ? "yes" : "no"));
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logger->info(" Count: {}", doorbell.count);
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logger->info(" Seq. number: {}", doorbell.seq_nr);
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}
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Rtds2GpuFactory::Rtds2GpuFactory() :
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@ -127,33 +127,6 @@ u32 XRtds2gpu_Get_doorbell_offset(XRtds2gpu *InstancePtr) {
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return Data;
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}
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void XRtds2gpu_Set_status_i(XRtds2gpu *InstancePtr, u32 Data) {
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_STATUS_I_DATA, Data);
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}
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u32 XRtds2gpu_Get_status_i(XRtds2gpu *InstancePtr) {
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u32 Data;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_STATUS_I_DATA);
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return Data;
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}
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u32 XRtds2gpu_Get_status_o(XRtds2gpu *InstancePtr) {
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u32 Data;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_STATUS_O_DATA);
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return Data;
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}
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void XRtds2gpu_Set_frame_size(XRtds2gpu *InstancePtr, u32 Data) {
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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@ -171,6 +144,26 @@ u32 XRtds2gpu_Get_frame_size(XRtds2gpu *InstancePtr) {
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return Data;
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}
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u32 XRtds2gpu_Get_status(XRtds2gpu *InstancePtr) {
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u32 Data;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_STATUS_DATA);
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return Data;
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}
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u32 XRtds2gpu_Get_status_vld(XRtds2gpu *InstancePtr) {
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u32 Data;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_STATUS_CTRL);
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return Data & 0x1;
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}
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void XRtds2gpu_InterruptGlobalEnable(XRtds2gpu *InstancePtr) {
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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@ -35,9 +35,12 @@
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static constexpr size_t SAMPLE_SIZE = 4;
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static constexpr size_t SAMPLE_COUNT = 8;
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static constexpr size_t SAMPLE_COUNT = 16;
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static constexpr size_t FRAME_SIZE = SAMPLE_COUNT * SAMPLE_SIZE;
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static constexpr size_t DOORBELL_OFFSET = SAMPLE_COUNT;
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static constexpr size_t DATA_OFFSET = 0;
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Test(fpga, rtds2gpu, .description = "Rtds2Gpu")
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{
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@ -49,60 +52,55 @@ Test(fpga, rtds2gpu, .description = "Rtds2Gpu")
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logger->info("Testing {}", *ip);
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/* Collect neccessary IPs */
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auto rtds2gpu = reinterpret_cast<villas::fpga::ip::Rtds2Gpu&>(*ip);
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auto dmaMem0 = villas::HostDmaRam::getAllocator(0).allocate<char>(FRAME_SIZE + 4);
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auto dmaMem1 = villas::HostDmaRam::getAllocator(0).allocate<char>(FRAME_SIZE + 4);
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// continue;
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auto axiSwitch = reinterpret_cast<villas::fpga::ip::AxiStreamSwitch*>(
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state.cards.front()->lookupIp(villas::fpga::Vlnv("xilinx.com:ip:axis_switch:")));
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cr_assert_not_null(axiSwitch);
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auto dma = reinterpret_cast<villas::fpga::ip::Dma*>(
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state.cards.front()->lookupIp(villas::fpga::Vlnv("xilinx.com:ip:axi_dma:")));
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cr_assert_not_null(dma);
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memset(&dmaMem0, 0x55, dmaMem0.getMemoryBlock().getSize());
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memset(&dmaMem1, 0x11, dmaMem1.getMemoryBlock().getSize());
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rtds2gpu.dump(spdlog::level::debug);
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puts("Before:");
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for(size_t i = 0; i < dmaMem0.getMemoryBlock().getSize(); i++) {
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printf("0x%02x ", dmaMem0[i]);
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}
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puts("");
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cr_assert_not_null(axiSwitch, "No AXI switch IP found");
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cr_assert_not_null(dma, "No DMA IP found");
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rtds2gpu.dump();
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cr_assert(axiSwitch->connect(7, 6));
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/* Allocate and prepare memory */
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// allocate space for all samples and doorbell register
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auto dmaMemSrc = villas::HostDmaRam::getAllocator(0).allocate<uint32_t>(SAMPLE_COUNT + 1);
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auto dmaMemDst = villas::HostDmaRam::getAllocator(0).allocate<uint32_t>(SAMPLE_COUNT + 1);
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memset(&dmaMemSrc, 0x11, dmaMemSrc.getMemoryBlock().getSize());
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memset(&dmaMemDst, 0x55, dmaMemDst.getMemoryBlock().getSize());
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const uint32_t* dataSrc = &dmaMemSrc[DATA_OFFSET];
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const uint32_t* dataDst = &dmaMemDst[DATA_OFFSET];
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// connect DMA to Rtds2Gpu IP
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||||
// TODO: this should be done automatically
|
||||
cr_assert(axiSwitch->connect(6, 7));
|
||||
|
||||
|
||||
|
||||
cr_assert(rtds2gpu.startOnce(dmaMem0.getMemoryBlock(), SAMPLE_COUNT),
|
||||
cr_assert(rtds2gpu.startOnce(dmaMemDst.getMemoryBlock(), SAMPLE_COUNT, DATA_OFFSET*4, DOORBELL_OFFSET*4),
|
||||
"Preparing Rtds2Gpu IP failed");
|
||||
|
||||
cr_assert(dma->write(dmaMem1.getMemoryBlock(), FRAME_SIZE));
|
||||
cr_assert(dma->write(dmaMemSrc.getMemoryBlock(), FRAME_SIZE),
|
||||
"Starting DMA MM2S transfer failed");
|
||||
|
||||
// cr_assert(axiSwitch->connect(6, 6)); // loopback
|
||||
// cr_assert(dma->read(dmaMem1.getMemoryBlock(), FRAME_SIZE));
|
||||
// cr_assert(dma->readComplete());
|
||||
cr_assert(dma->writeComplete(),
|
||||
"DMA failed");
|
||||
|
||||
cr_assert(dma->writeComplete());
|
||||
while(not rtds2gpu.isFinished());
|
||||
|
||||
puts("After:");
|
||||
for(size_t i = 0; i < dmaMem0.getMemoryBlock().getSize(); i++) {
|
||||
printf("0x%02x ", dmaMem0[i]);
|
||||
}
|
||||
puts("");
|
||||
const uint32_t* doorbellDst = &dmaMemDst[DOORBELL_OFFSET];
|
||||
rtds2gpu.dump(spdlog::level::info);
|
||||
rtds2gpu.dumpDoorbell(*doorbellDst);
|
||||
|
||||
|
||||
rtds2gpu.dump();
|
||||
|
||||
cr_assert(rtds2gpu.isDone());
|
||||
cr_assert(memcmp(dataSrc, dataDst, FRAME_SIZE) == 0, "Memory not equal");
|
||||
|
||||
logger->info(TXT_GREEN("Passed"));
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue