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add register interface to dino bitstream and make the necessary changes

Browse source 
to jsons and hwh parser

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
This commit is contained in:
Niklas Eiling 2024-02-10 16:17:27 +01:00 • committed by Niklas Eiling
parent 535560d39d
commit 2a74f7e8c2
3 changed files with 1383 additions and 2 deletions
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2
fpga/etc/fpgas.json
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@ -4,7 +4,7 @@
"id": "10ee:7021", "id": "10ee:7021",
"slot": "0000:88:00.0", "slot": "0000:88:00.0",
"do_reset": true, "do_reset": true,
"ips": "vc707-xbar-pcie-dino/vc707-xbar-pcie-dino.json", "ips": "vc707-xbar-pcie-dino/vc707-xbar-pcie-dino-v2.json",
"polling": false, "polling": false,
"interface": "pcie" "interface": "pcie"
} }

1379
fpga/etc/vc707-xbar-pcie-dino/vc707-xbar-pcie-dino-v2.json Normal file
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4
fpga/scripts/hwdef-parse.py
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@ -47,6 +47,7 @@ whitelist = [
[ 'xilinx.com', 'module_ref', 'dinoif_fast' ], [ 'xilinx.com', 'module_ref', 'dinoif_fast' ],
[ 'xilinx.com', 'module_ref', 'dinoif_dac' ], [ 'xilinx.com', 'module_ref', 'dinoif_dac' ],
[ 'xilinx.com', 'module_ref', 'axi_pcie_intc' ], [ 'xilinx.com', 'module_ref', 'axi_pcie_intc' ],
[ 'xilinx.com', 'module_ref', 'registerif' ],
[ 'xilinx.com', 'hls', 'rtds2gpu' ], [ 'xilinx.com', 'hls', 'rtds2gpu' ],
[ 'xilinx.com', 'hls', 'mem' ], [ 'xilinx.com', 'hls', 'mem' ],
[ 'acs.eonerc.rwth-aachen.de', 'user', 'axi_pcie_intc' ], [ 'acs.eonerc.rwth-aachen.de', 'user', 'axi_pcie_intc' ],
@ -64,7 +65,8 @@ axi_converter_whitelist = [
[ 'xilinx.com', 'ip', 'axis_register_slice' ], [ 'xilinx.com', 'ip', 'axis_register_slice' ],
[ 'xilinx.com', 'ip', 'axis_dwidth_converter' ], [ 'xilinx.com', 'ip', 'axis_dwidth_converter' ],
[ 'xilinx.com', 'ip', 'axis_register_slice' ], [ 'xilinx.com', 'ip', 'axis_register_slice' ],
[ 'xilinx.com', 'ip', 'axis_data_fifo' ] [ 'xilinx.com', 'ip', 'axis_data_fifo' ],
[ 'xilinx.com', 'ip', 'floating_point' ]
] ]
opponent = { opponent = {