tests: move variables to global state and set criterion jobs to 1

fpga/tests/fifo.cpp

@@ -27,8 +27,8 @@
 #include <villas/fpga/card.hpp>
 #include <villas/fpga/ips/fifo.hpp>
 
+#include "global.hpp"
 
-extern villas::fpga::PCIeCard* fpga;
 
 Test(fpga, fifo, .description = "FIFO")
 {
@@ -37,7 +37,7 @@ Test(fpga, fifo, .description = "FIFO")
 
 	auto logger = loggerGetOrCreate("unittest:fifo");
 
-	for(auto& ip : fpga->ips) {
+	for(auto& ip : state.cards.front()->ips) {
 		// skip non-fifo IPs
 		if(*ip != villas::fpga::Vlnv("xilinx.com:ip:axi_fifo_mm_s:"))
 			continue;

fpga/tests/global.hpp

@@ -0,0 +1,21 @@
+#pragma once
+
+#include <cstdlib>
+
+#include <villas/fpga/card.hpp>
+
+class FpgaState {
+public:
+	FpgaState() {
+		// force criterion to only run one job at a time
+		setenv("CRITERION_JOBS", "1", 0);
+	}
+
+	// list of all available FPGA cards, only first will be tested at the moment
+	villas::fpga::CardList cards;
+};
+
+// global state to be shared by unittests
+extern FpgaState state;
+
+

fpga/tests/main.cpp

@@ -35,6 +35,8 @@
 
 #include <spdlog/spdlog.h>
 
+#include "global.hpp"
+
 #define FPGA_CARD	"vc707"
 #define TEST_CONFIG	"../etc/fpga.json"
 #define TEST_LEN	0x1000
@@ -42,13 +44,10 @@
 #define CPU_HZ		3392389000
 #define FPGA_AXI_HZ	125000000
 
-struct pci pci;
-struct vfio_container vc;
-villas::fpga::CardList fpgaCards;
-villas::fpga::PCIeCard* fpga;
+FpgaState state;
 
-// keep to make it compile with old C tests
-struct fpga_card* card;
+static struct pci pci;
+static struct vfio_container vc;
 
 static void init()
 {
@@ -88,22 +87,17 @@ static void init()
 	villas::fpga::PCIeCardFactory* fpgaCardPlugin = dynamic_cast<villas::fpga::PCIeCardFactory*>(plugin);
 
 	// create all FPGA card instances using the corresponding plugin
-	fpgaCards = fpgaCardPlugin->make(fpgas, &pci, &vc);
+	state.cards = fpgaCardPlugin->make(fpgas, &pci, &vc);
 
-	if(fpgaCards.size() == 0) {
-		logger->error("No FPGA cards found!");
-	} else {
-		fpga = fpgaCards.front().get();
-	}
-
-	cr_assert_not_null(fpga, "No FPGA card available");
+	cr_assert(state.cards.size() != 0, "No FPGA cards found!");
 
 	json_decref(json);
 }
 
 static void fini()
 {
-	fpgaCards.clear();
+	// release all cards
+	state.cards.clear();
 }
 
 TestSuite(fpga,

fpga/tests/timer.cpp

@@ -28,14 +28,13 @@
 #include <villas/fpga/ips/timer.hpp>
 
 #include "config.h"
-
-extern villas::fpga::PCIeCard* fpga;
+#include "global.hpp"
 
 Test(fpga, timer, .description = "Timer Counter")
 {
 	auto logger = loggerGetOrCreate("unittest:timer");
 
-	for(auto& ip : fpga->ips) {
+	for(auto& ip : state.cards.front()->ips) {
 		// skip non-timer IPs
 		if(*ip != villas::fpga::Vlnv("xilinx.com:ip:axi_timer:")) {
 			continue;