mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
fpga: removed all FPGA related code
This commit is contained in:
parent
db464e50ee
commit
3f74f036ea
5 changed files with 4 additions and 390 deletions
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@ -32,7 +32,7 @@ var global = require(__dirname + '/global.js')
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/* List of plugins
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*
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* Additional node-types, hooks or VILLASfpga IP cores
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* Additional node-types, hooks or formats
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* can be loaded by compiling them into a shared library and
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* adding them to this list
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*/
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@ -85,4 +85,4 @@ var json = JSON.stringify(global, null, 4);
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process.stderr.write('Configuration file successfully generated\n');
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// Print JSON to stdout
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process.stdout.write(json);
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process.stdout.write(json);
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@ -26,11 +26,11 @@
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############ List of plugins ############
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#
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# Additional node-types, hooks or VILLASfpga IP cores
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# Additional node-types, hooks or formats
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# can be loaded by compiling them into a shared library and
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# adding them to this list
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plugins = [
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"simple_circuit.so",
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"example_hook.so"
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]
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]
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@ -1,75 +0,0 @@
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/** Node type: VILLASfpga
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*
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* This file implements the fpga node-type.
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*
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* @file
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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*********************************************************************************/
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/**
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* @addtogroup fpga VILLASfpga
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* @ingroup node
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* @{
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*/
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#pragma once
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#include "kernel/vfio.h"
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#include "kernel/pci.h"
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#include "fpga/ips/dma.h"
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#include "node.h"
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#include "list.h"
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/* Forward declarations */
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struct fpga_ip;
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/** The node type */
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struct fpga {
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struct fpga_ip *ip;
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struct pci *pci;
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struct vfio_container *vfio_container;
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int use_irqs;
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struct dma_mem dma;
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};
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/** @see node_vtable::init */
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int fpga_init(struct super_node *sn);
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/** @see node_type::deinit */
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int fpga_deinit();
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/** @see node_type::parse */
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int fpga_parse(struct node *n, json_t *cfg);
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struct fpga_card * fpga_lookup_card(const char *name);
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/** @see node_type::print */
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char * fpga_print(struct node *n);
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/** @see node_type::open */
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int fpga_start(struct node *n);
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/** @see node_type::close */
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int fpga_stop(struct node *n);
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/** @see node_type::read */
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int fpga_read(struct node *n, struct sample *smps[], unsigned cnt);
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/** @see node_type::write */
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int fpga_write(struct node *n, struct sample *smps[], unsigned cnt);
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/** Get pointer to internal VILLASfpga datastructure */
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struct fpga * fpga_get();
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/** Reset VILLASfpga */
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int fpga_reset(struct fpga *f);
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/** Dump some details about the fpga card */
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void fpga_dump(struct fpga *f);
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/** @} */
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@ -71,14 +71,6 @@ ifeq ($(shell $(PKGCONFIG) --atleast-version=1.2.0 libiec61850; echo $$?),0)
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endif
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endif
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# Enable VILLASfpga support when libvillas-fpga is available
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ifeq ($(WITH_NODE_FPGA),1)
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ifeq ($(shell $(PKGCONFIG) libvillas-fpga; echo $$?),0)
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LIB_PKGS += libvillas-fpga
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LIB_NODES += fpga
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endif
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endif
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# Enable OPAL-RT Asynchronous Process support (will result in 32bit binary!!!)
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ifeq ($(WITH_NODE_OPAL),1)
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ifneq ($(wildcard $(SRCDIR)/thirdparty/libopal/include/opal/AsyncApi.h),)
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303
lib/nodes/fpga.c
303
lib/nodes/fpga.c
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@ -1,303 +0,0 @@
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/** Node type: VILLASfpga
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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*********************************************************************************/
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#include <stdio.h>
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#include <inttypes.h>
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#include "kernel/kernel.h"
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#include "kernel/pci.h"
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#include "nodes/fpga.h"
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#include "config.h"
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#include "utils.h"
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#include "timing.h"
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#include "plugin.h"
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#include "super_node.h"
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#include "fpga/card.h"
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static struct list cards;
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static struct pci pci;
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static struct vfio_container vc;
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void fpga_dump(struct fpga *f)
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{
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struct fpga_card *c = f->ip->card;
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fpga_card_dump(c);
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}
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int fpga_init(struct super_node *sn)
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{
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int ret;
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ret = pci_init(&pci);
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if (ret)
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error("Failed to initialize PCI sub-system");
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ret = vfio_init(&vc);
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if (ret)
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error("Failed to initiliaze VFIO sub-system");
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#if 0
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json_t *cfg, *json_fpgas;
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/* Parse FPGA configuration */
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cfg = config_root_setting(&sn->cfg);
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json_fpgas = config_setting_lookup(cfg, "fpgas");
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if (!json_fpgas)
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cerror(cfg, "Config file is missing 'fpgas' section");
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ret = fpga_card_parse_list(&cards, json_fpgas);
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if (ret)
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cerror(cfg, "Failed to parse VILLASfpga config");
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#endif
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return 0;
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}
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int fpga_deinit()
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{
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int ret;
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list_destroy(&cards, (dtor_cb_t) fpga_card_destroy, true);
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pci_destroy(&pci);
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ret = vfio_destroy(&vc);
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if (ret)
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error("Failed to deinitialize VFIO sub-system");
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ret = pci_destroy(&pci);
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if (ret)
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error("Failed to deinitialize PCI sub-system");
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return 0;
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}
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int fpga_parse(struct node *n, json_t *cfg)
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{
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struct fpga *f = (struct fpga *) n->_vd;
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struct fpga_card *card;
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struct fpga_ip *ip;
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char *cpy, *card_name, *ip_name;
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const char *dm;
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json_error_t err;
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int ret;
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/* Default values */
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f->use_irqs = false;
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ret = json_unpack_ex(cfg, &err, 0, "{ s: s, s?: b }",
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"datamover", &dm,
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"use_irqs", &f->use_irqs
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);
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if (ret)
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jerror(&err, "Failed to parse configuration of node %s", node_name(n));
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cpy = strdup(dm); /* strtok can not operate on type const char * */
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card_name = strtok(cpy, ":");
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ip_name = strtok(NULL, ":");
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card = list_lookup(&cards, card_name);
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if (!card)
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error("There is no FPGA card named '%s' used by node %s", card_name, node_name(n));
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ip = list_lookup(&card->ips, ip_name);
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if (!ip)
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error("There is no datamover named '%s' on the FPGA card '%s' used by node %s", ip_name, card_name, node_name(n));
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if (ip->_vt->type != FPGA_IP_TYPE_DM_DMA && ip->_vt->type != FPGA_IP_TYPE_DM_FIFO)
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error("The IP '%s' on FPGA card '%s' is not a datamover", ip_name, card_name);
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free(cpy);
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f->ip = ip;
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return 0;
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}
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char * fpga_print(struct node *n)
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{
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struct fpga *f = (struct fpga *) n->_vd;
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struct fpga_card *c = f->ip->card;
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if (f->ip)
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return strf("dm=%s (%s:%s:%s:%s) baseaddr=%#jx port=%u slot=%02"PRIx8":%02"PRIx8".%"PRIx8" id=%04"PRIx16":%04"PRIx16,
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f->ip->name, f->ip->vlnv.vendor, f->ip->vlnv.library, f->ip->vlnv.name, f->ip->vlnv.version,
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f->ip->baseaddr, f->ip->port,
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c->filter.slot.bus, c->filter.slot.device, c->filter.slot.function,
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c->filter.id.vendor, c->filter.id.device);
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else
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return strf("dm=%s", f->ip->name);
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}
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int fpga_start(struct node *n)
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{
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int ret;
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struct fpga *f = (struct fpga *) n->_vd;
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struct fpga_card *c = f->ip->card;
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fpga_card_init(c, f->pci, f->vfio_container);
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int flags = 0;
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if (!f->use_irqs)
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flags |= INTC_POLLING;
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switch (f->ip->_vt->type) {
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case FPGA_IP_TYPE_DM_DMA:
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/* Map DMA accessible memory */
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ret = dma_alloc(f->ip, &f->dma, 0x1000, 0);
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if (ret)
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return ret;
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intc_enable(c->intc, (1 << (f->ip->irq )), flags); /* MM2S */
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intc_enable(c->intc, (1 << (f->ip->irq + 1)), flags); /* S2MM */
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break;
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case FPGA_IP_TYPE_DM_FIFO:
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intc_enable(c->intc, (1 << f->ip->irq), flags); /* MM2S & S2MM */
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break;
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default: { }
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}
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return 0;
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}
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int fpga_stop(struct node *n)
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{
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int ret;
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struct fpga *f = (struct fpga *) n->_vd;
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struct fpga_card *c = f->ip->card;
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switch (f->ip->_vt->type) {
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case FPGA_IP_TYPE_DM_DMA:
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intc_disable(c->intc, f->ip->irq); /* MM2S */
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intc_disable(c->intc, f->ip->irq + 1); /* S2MM */
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ret = dma_free(f->ip, &f->dma);
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if (ret)
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return ret;
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case FPGA_IP_TYPE_DM_FIFO:
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if (f->use_irqs)
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intc_disable(c->intc, f->ip->irq); /* MM2S & S2MM */
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default: { }
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}
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return 0;
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}
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int fpga_read(struct node *n, struct sample *smps[], unsigned cnt)
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{
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int ret;
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struct fpga *f = (struct fpga *) n->_vd;
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struct sample *smp = smps[0];
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size_t recvlen;
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size_t len = SAMPLE_DATA_LEN(64);
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/* We dont get a sequence no from the FPGA. Lets fake it */
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smp->sequence = -1;
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smp->ts.origin = time_now();
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/* Read data from RTDS */
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switch (f->ip->_vt->type) {
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case FPGA_IP_TYPE_DM_DMA:
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ret = dma_read(f->ip, f->dma.base_phys + 0x800, len);
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if (ret)
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return ret;
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ret = dma_read_complete(f->ip, NULL, &recvlen);
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if (ret)
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return ret;
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memcpy(smp->data, f->dma.base_virt + 0x800, recvlen);
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smp->length = recvlen / 4;
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return 1;
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case FPGA_IP_TYPE_DM_FIFO:
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recvlen = fifo_read(f->ip, (char *) smp->data, len);
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smp->length = recvlen / 4;
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return 1;
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default: { }
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}
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return -1;
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}
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int fpga_write(struct node *n, struct sample *smps[], unsigned cnt)
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{
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int ret;
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struct fpga *f = (struct fpga *) n->_vd;
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struct sample *smp = smps[0];
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size_t sentlen;
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size_t len = smp->length * sizeof(smp->data[0]);
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/* Send data to RTDS */
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switch (f->ip->_vt->type) {
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case FPGA_IP_TYPE_DM_DMA:
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memcpy(f->dma.base_virt, smp->data, len);
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ret = dma_write(f->ip, f->dma.base_phys, len);
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if (ret)
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return ret;
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ret = dma_write_complete(f->ip, NULL, &sentlen);
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if (ret)
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return ret;
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//info("Sent %u bytes to FPGA", sentlen);
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return 1;
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case FPGA_IP_TYPE_DM_FIFO:
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sentlen = fifo_write(f->ip, (char *) smp->data, len);
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return sentlen / sizeof(smp->data[0]);
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break;
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default: { }
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}
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return -1;
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}
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struct fpga_card * fpga_lookup_card(const char *name)
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{
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return (struct fpga_card *) list_lookup(&cards, name);
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}
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static struct plugin p = {
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.name = "fpga",
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.description = "VILLASfpga PCIe card (libxil)",
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.type = PLUGIN_TYPE_NODE,
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.node = {
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.size = sizeof(struct fpga),
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.vectorize = 1,
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.parse = fpga_parse,
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.print = fpga_print,
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.start = fpga_start,
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.stop = fpga_stop,
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.read = fpga_read,
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.write = fpga_write,
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.init = fpga_init,
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.deinit = fpga_deinit
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}
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};
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REGISTER_PLUGIN(&p)
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LIST_INIT_STATIC(&p.node.instances)
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